Semiconductor device structure and forming method thereof

Abstract

Semiconductor device structures and methods of forming the same are described. The semiconductor device structure includes a first gate structure disposed over the substrate in the active device region, an insulating material disposed over the substrate in the passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, and a second conductive contact electrically connected to the first conductive contact. A second conductive contact disposed over the resistor structure; and a dielectric layer in contact with the second conductive contact and the resistor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor device structures and methods for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced new generations of ICs, each with smaller and more complex circuits than the previous one. During IC evolution, functional density (e.g., the number of interconnected devices per chip area) generally increases, while geometry size (e.g., the smallest component (or line) that can be created using a manufacturing process) decreases. This scaling-down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As devices shrink, manufacturers have begun using new and different materials and / or material combinations to facilitate device shrinkage. Shrinking size, either alone or in combination with new and different materials, also presents challenges that may not have been encountered with previous generations at larger geometries. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device structure is provided, including: a first gate structure, arranged above a substrate in an active device area; an insulating material, arranged above a substrate in a passive device area; a resistor structure, arranged above the insulating material in the passive device area; a first conductive contact, electrically connected to the resistor structure; a second conductive contact, arranged above the resistor structure; and a dielectric layer, contacting the second conductive contact and the resistor structure.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, including: an insulating material disposed above a substrate; a resistor structure disposed above the insulating material; a first spacer and a second spacer disposed above the insulating material, wherein the resistor structure is disposed between the first spacer and the second spacer; a first conductive contact electrically connected to the resistor structure; a second conductive contact extending into the resistor structure; and a first dielectric layer extending into the resistor structure, wherein the first dielectric layer is in contact with the second conductive contact and the resistor structure.

[0006] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device structure is provided, comprising: depositing a metal-containing layer over an active device region and a passive device region of a substrate; depositing a semiconductor material in the active device region and the passive device region; patterning the semiconductor material to form a sacrificial gate electrode in the active device region and a resistor structure in the passive device region; replacing the sacrificial gate electrode in the active device region with a gate structure; forming an interlayer dielectric layer over the gate structure and the resistor structure, wherein the interlayer dielectric layer comprises a first opening exposing the gate electrode of the gate structure, a second opening exposing the first portion of the resistor structure, and a third opening exposing the second portion of the resistor structure; depositing a dielectric layer in the first opening, the second opening, and the third opening; removing portions of the dielectric layer in the first opening and the second opening; and forming a first conductive contact, a second conductive contact, and a third conductive contact in the first opening, the second opening, and the third opening, respectively, wherein the dielectric layer is disposed between the third conductive contact and the resistor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1-Figure 18 Cross-sectional side views of various stages of fabrication of a semiconductor device structure are shown in accordance with some embodiments.

[0009] Figure 19-21 is a top view of a semiconductor device structure according to some embodiments.

[0010] Figure 22-Figure 25 Cross-sectional side views of various stages of fabrication of a semiconductor device structure are shown in accordance with an alternative embodiment.

[0011] Figure 26-Figure 28 Cross-sectional side views of various stages of fabrication of a semiconductor device structure are shown in accordance with an alternative embodiment.

[0012] Fig.29 According to some embodiments Fig. 27 A top view of a passive device region of a semiconductor device structure.

[0013] Figure 30-Figure 39 Cross-sectional side views of various stages of fabrication of a semiconductor device structure are shown in accordance with an alternative embodiment. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] The present invention relates to a resistor structure that can be integrated with an active device (such as a field effect transistor (FET)) in a front-end-of-line (FEOL) process. In some embodiments, the resistor structure includes a semiconductor material, and one or more conductive contacts are disposed on, in, or through the semiconductor material. The one or more conductive contacts can be used as tuning electrodes to provide a bias voltage to tune the resistance of the resistor structure.

[0017] Some variations of the example methods and structures are described. Those of ordinary skill in the art will readily appreciate other modifications that may be made within the scope of other embodiments. Although the method embodiments may be described in a particular order, various other method embodiments may also be performed in any logical order and may include fewer or more steps than described herein. In some figures, some reference numerals for components or features shown therein may be omitted to avoid obscuring other components or parts; this is for ease of depiction.

[0018] Figures 1 to 18 A cross-sectional side view of various stages of fabrication of a semiconductor device structure 100 according to some embodiments is shown. As described below, the semiconductor device structure 100 is used to implement a planar FET. Other device structures, such as FinFET, horizontal gate-all-around (HGAA) FET, vertical gate-all-around (VGAA) FET, nanosheet FET, nanowire FET, fork-sheet FET, complementary FET (CFET), can be implemented in other example embodiments.

[0019] like Figure 1 As shown, the semiconductor device structure 100 includes a substrate 102. The substrate 102 can be a semiconductor substrate. The substrate 102 can include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0020] The substrate 102 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0021] like Figure 1 As shown, an insulating material 104 is formed in the substrate 102. The insulating material 104 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 104 may be formed by any suitable method, such as low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), or flowable CVD (FCVD). In some embodiments, an opening is formed in the substrate 102, and the insulating material 104 is formed in the opening. A planarization process, such as a chemical mechanical polishing process, may be performed to remove portions of the insulating material 104 formed on the substrate 102. The insulating material 104 is an isolation region, such as a shallow trench isolation (STI) region.

[0022] like Figure 1 As shown, the semiconductor device structure 100 includes an active device region 101a and a passive device region 101p. Active devices (such as FETs) may be formed in the active device region 101a, and passive devices (such as resistors or capacitors) may be formed in the passive device region 101p.

[0023] like Figure 2As shown, a dielectric layer 106 is formed on the substrate 102 and the insulating material 104. The dielectric layer 106 may include any suitable dielectric material. In some embodiments, the dielectric layer 106 includes a high-K dielectric material. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiN, HfTaO, HfTiO, HbZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials and / or combinations thereof. The dielectric layer 106 can be formed by CVD, ALD or any suitable deposition technique. A metal-containing layer 108 is formed on the dielectric layer 106. In some embodiments, the metal-containing layer is a nitride, such as TiN or TaN. The metal-containing layer 108 can be formed by physical vapor deposition (PVD), CVD, ALD or any suitable deposition technique.

[0024] like Figure 3 As shown, the dielectric layer 106 and the metal-containing layer 108 are patterned. In some embodiments, portions of the dielectric layer 106 and the metal-containing layer 108 located in the passive device region 101p are removed. A patterned mask layer (not shown) may be formed over the metal-containing layer 108, and the pattern of the patterned mask layer may be transferred to the metal-containing layer 108 and the dielectric layer 106. The patterning of the dielectric layer 106 and the metal-containing layer 108 may include a photolithography process and one or more etching processes.

[0025] like Figure 4 As shown, semiconductor material 110 is deposited on substrate 102, metal-containing layer 108, and insulating material 104. In some embodiments, semiconductor material 110 covers the sidewalls of dielectric layer 106 and metal-containing layer 108. Semiconductor material 110 may include any suitable semiconductor material. In some embodiments, semiconductor material 110 includes doped or undoped polycrystalline silicon (polysilicon). Semiconductor material 110 may be formed by any suitable process, such as CVD (including LPCVD and PECVD), PVD, or ALD.

[0026] like Figure 5 As shown, the semiconductor material 110 is patterned to form a sacrificial gate electrode 112 and a resistor structure 114. A patterned mask layer (not shown) may be formed on the semiconductor material 110, and the pattern of the patterned mask layer may be transferred to the semiconductor material 110. The patterning of the semiconductor material 110 may include a photolithography process and one or more etching processes. As a result of the patterning process, the sacrificial gate electrode 112 is formed in the active device region 101a, and the resistor structure 114 is formed in the passive device region 101p. In some embodiments, as shown in FIG. Figure 5 As shown, the sidewalls of the sacrificial gate electrode 112 may be aligned with the sidewalls of the dielectric layer 106 and the metal-containing layer 108 .

[0027] like Figure 6 As shown, a spacer 116a is formed on the sidewalls of the sacrificial gate electrode 112, the metal-containing layer 108, and the dielectric layer 106 in the active device region 101a, and a spacer 116p is formed on the sidewalls of the resistor structure 114. The spacer 116a and the spacer 116p may include one or more dielectric layers. The material of the spacer 116a and the spacer 116p may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), any combination thereof, or any suitable dielectric material. In some embodiments, a conformal dielectric layer is formed on the exposed surface of the semiconductor device structure 100, and an anisotropic etching process is performed on the dielectric layer to remove a portion of the dielectric layer formed on the horizontal surface of the semiconductor device structure 100. The remaining portions of the dielectric layer formed on the vertical surfaces of the semiconductor device structure 100 become spacers 116 a and 116 p .

[0028] like Figure 7 As shown, a source / drain (S / D) region 118 is formed in the substrate 102, and an interlayer dielectric (ILD) layer 120 is formed on the S / D region 118. The S / D region 118 can be formed by doping the exposed portion of the substrate 102. The S / D region 118 can be formed using an N-type dopant such as phosphorus (P) or arsenic (As) or a P-type dopant such as boron (B). In some embodiments, n-type FETs and p-type FETs can be formed at different times, and a mask layer (not shown) can be used. In the present disclosure, source regions and drain regions can be used interchangeably, and their structures are basically the same. In addition, depending on the context, the source / drain regions can refer to the source or drain individually or collectively.

[0029] The ILD layer 120 may be formed over the S / D regions 118. The ILD layer 120 may include or be silicon dioxide, a low-k dielectric material (e.g., a material with a lower dielectric constant than silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphate silicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiO x C y, spin-on glass, spin-on polymer, silicon-carbon material, compounds thereof, composites thereof, etc., or combinations thereof. The ILD layer 120 may initially be formed to embed the sacrificial gate electrode 112 and the resistor structure 114, and a planarization process, such as a CMP process, may be performed to expose the sacrificial gate electrode 110 and the resistor structure 114. In some embodiments, a contact etch stop layer (CESL) (not shown) may be first formed on the S / D region 118, the spacers 116a, 116p, the sacrificial gate electrode 112, and the resistor structure 114, and the ILD layer 120 may be formed on the CESL. The planarization process may also remove portions of the CESL formed on the top surface of the sacrificial gate electrode 112 and the top surface of the resistor structure 114.

[0030] like Figure 8 As shown, a patterned mask layer 122 is formed on the ILD layer 120 and the resistor structure 114. An opening 124 is formed in the patterned mask layer 122, and the sacrificial gate electrode 112 is exposed in the opening 124. In some embodiments, the spacer 116a is also exposed in the opening 124, such as Figure 8 As shown. The sacrificial gate electrode 112 is then removed by any suitable process. In some embodiments, the sacrificial gate electrode 112 is removed by a dry etching process, a wet etching process, or a combination thereof. The etching process may be a selective etching process that does not substantially affect the spacer 116a. The patterned mask layer 122 is removed during or after the removal of the sacrificial gate electrode 112.

[0031] like Fig. 9As shown, a gate structure 126 is formed in the opening formed by removing the sacrificial gate electrode 112. The gate structure 126 includes one or more work function layers 128, 130 and a gate electrode 132. The work function layers 128, 130 may include metal materials, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu) or similar materials. The gate electrode 132 may include one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or any combination thereof. The work function layers 128, 130 and the gate electrode 132 may be formed by CVD, ALD, PVD, electroplating or other suitable deposition techniques. In some embodiments, the dielectric layer 106 and the metal-containing layer 108 are also part of the gate structure 126. The metal-containing layer 108 may be a work function layer of the gate structure 126, and the dielectric layer 106 may be a gate dielectric layer of the gate structure 126. In some embodiments, the metal-containing layer 108 may not be present. In some embodiments, a portion of the work function layers 128, 130 and the gate electrode 132 may be formed on the ILD layer 120 and the resistor structure 114, and a planarization process, such as a CMP process, may be performed to remove the portions of the work function layers 128, 130 and the gate electrode 132 formed on the ILD layer 120 and the resistor layer 114. In some embodiments, a top surface of the resistor structure 114 and a top surface of the gate electrode 132 are substantially coplanar.

[0032] like Fig.10 As shown, a second ILD layer 134 is deposited on the ILD layer 120, the gate structure 126, and the resistor structure 114, and a patterned photoresist layer 136 is formed on the second ILD layer 134. The second ILD layer 134 may include the same material as the ILD layer 120, and may be formed by the same process as the ILD layer 20. The patterned photoresist layer 136 may be a photoresist layer including a plurality of openings 137. In some embodiments, an etch stop layer (not shown) may be formed on the ILD layer 120, the gate structure 126, and the resistor structure 114, and the second ILD layer 134 is deposited on the etch stop layer.

[0033] like Fig.11As shown, the pattern of the patterned photoresist layer 136 is transferred to the second ILD layer 134, and the patterned photoresist layer 136 is removed. Openings 138a, 138p1, and 138p2 are formed in the second ILD layer 134. The opening 138a is formed in the active device region 101a, and the openings 138p1 and 138p2 are formed in the passive device region 101p. The gate electrode 132 is exposed in the opening 138a, and a portion of the resistor structure 114 is exposed in the openings 138p1 and 138p2. In some embodiments, two openings 138p1 are formed in the passive device region 101p for forming a conductive contact 150p1 ( Fig.18 ), and one or more openings 138p2 are formed in the passive device region 101p for forming therein a conductive contact 150p2 ( Fig.18 ).

[0034] like Fig.12 As shown, dielectric layer 140 is formed on second ILD layer 134, in openings 138a, 138p1, 138p2, and on portions of gate electrode 132 and resistor structure 114. Dielectric layer 140 may include any suitable dielectric material, such as an oxide, such as silicon oxide. Dielectric layer 140 may be formed by any suitable process. In some embodiments, dielectric layer 140 is a conformal layer and is formed by a conformal process such as ALD.

[0035] like Fig.13 As shown, a patterned photoresist layer 142 is formed on the dielectric layer 140. The patterned photoresist layer 142 fills the opening 138p2, while the openings 138a and 138p1 remain open. As a result, the portion of the dielectric layer 140 located in the openings 138a and 138p1 is exposed. Next, as shown in FIG. Fig.14 As shown, the exposed portion of the dielectric layer 140 in the openings 138a, 138p1 is removed. The exposed portion of the dielectric layer 140 can be removed by a selective etching process, which does not substantially affect the second ILD layer 134, the gate electrode 132, and the resistor structure 114. After removing the portion of the dielectric layer 140 located in the openings 138a, 138p1, the patterned photoresist layer 142 is removed, as shown. Fig.15 As a result, the dielectric layer 140 remains in the opening 138p2.

[0036] like Fig.16As shown, a seed layer 144 is formed in the openings 138a, 138p1, 138p2 and over the dielectric layer 140 over the second ILD layer 134. The seed layer 144 can be a metal, such as cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, or the like, or a combination thereof. The seed layer 144 can be deposited by CVD, ALD, PVD, or another deposition technique. In some embodiments, the seed layer 144 reacts with the semiconductor material of the resistor structure 114 to form a silicide layer 146. In some embodiments, the seed layer 144 contacts the gate electrode 132 and is in electrical contact with the resistor structure 114 through the silicide layer 146. As shown in FIG. Fig.16 As shown, the seed layer 144 is separated from one or more portions of the resistor structure 114 by the dielectric layer 140 in the opening 138 p 2 .

[0037] like Fig.17 As shown, a conductive material 148 is formed on the seed layer 144. The conductive material 148 may include a conductive material, such as cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, or a combination thereof. In some embodiments, the conductive material 148 includes the same material as the seed layer 144. The conductive material 148 fills the openings 138a, 138p1, and 138p2. In some embodiments, the seed layer 144 is not formed, and the conductive material 148 is directly deposited in the openings 138a, 138p1, and 138p2. For example, the conductive material 148 may be in direct contact with the second ILD layer 134 and the gate electrode 132 in the opening 138a. The conductive material 148 may be in direct contact with the second ILD layer 134 and the silicide layer 146 in the opening 138p1. The conductive material 148 may be in direct contact with the dielectric layer 140 in the opening 138p2.

[0038] like Fig.18As shown, portions of the conductive material 148, the seed layer 144, and the dielectric layer 140 located on the second ILD layer 134 are removed. In some embodiments, a planarization process, such as a CMP process, is performed to remove portions of the conductive material 148, the seed layer 144, and the dielectric layer 140. The conductive material 148 and the seed layer 144 located in the active device region 101a may be a conductive contact 150a of the gate electrode 132. The conductive material 148 and the seed layer 144 located above the silicide layer 146 in the passive device region 101p may be a conductive contact 150p1 of the resistor structure 114. The conductive material 148 and the seed layer 144 located on the dielectric layer 140 (i.e., the conductive contact 150p2) may be a tuning electrode of the resistor structure 114. The tuning electrode is electrically insulated from the resistor structure 114 by the dielectric layer 140. The tuning electrode may be used to provide a bias voltage that may change the resistance of the resistor structure 114. In some embodiments, the resistance of the resistor structure 114 may be tuned within a range of about 200 ohms to about 1000 ohms by the tuning electrode.

[0039] Figure 19-21 is a top view of a semiconductor device structure 100 according to some embodiments. For clarity, Figures 19 to 21 Some components are omitted, such as the second ILD layer 134, the seed layer 144, one or more work function layers 128, 130, the dielectric layer 140, and the spacers 116a, 116p. Fig.19 As shown, the gate electrode 132 extends through one or more active regions 152. In some embodiments, each active region 152 includes an active device, such as a FET, which includes a source region 118, a drain region 118, a gate structure 126 ( Fig.18 ) and a channel region located below the gate structure 126 and between the source region 118 and the drain region 118. The active regions 152 are separated by the insulating material 104 along the Y direction. The resistor structure 114 can be disposed on the insulating material 104, adjacent to one of the active regions 152, such as Fig.19 As shown. Conductive contact 150p1 is disposed above resistor structure 114 to provide current flowing through resistor structure 114. In some embodiments, conductive contact 150p1 is a conductive via. Conductive contact 150p2 is disposed above resistor structure 114 to serve as a bias electrode that can adjust the resistance of resistor structure 114. In some embodiments, conductive contact 150p2 is a conductive via, such as Fig.19 shown.

[0040] Fig. 20 is a top view of a semiconductor device structure 100 according to an alternative embodiment. Fig. 20As shown, the resistor structure 114 is disposed over the insulating material 104 along the Y direction, adjacent to the two active regions 152. A plurality of conductive contacts 150p1 may be formed over the resistor structure 114. In some embodiments, the conductive contacts 150p2 are conductive lines.

[0041] Fig.21 is a top view of a semiconductor device structure 100 according to an alternative embodiment. Fig.21 As shown, the resistor structure 114 is disposed over the insulating material 104 along the Y direction, adjacent to the three active regions 152. A plurality of conductive contacts 150p1 may be formed on the resistor structure 114, and a plurality of conductive contacts 150p2 (wires) may be formed over the resistor structure 114.

[0042] Figure 22-Figure 25 1 shows a cross-sectional side view of various stages of fabrication of a semiconductor device structure 100 according to an alternative embodiment. Fig. 22 As shown, in some embodiments, the opening 138p2 extends into the resistor structure 114. Additional masks may be used to form deeper openings 138p2. Fig.11 After the semiconductor device structure 100 is shown, an additional mask may be formed to cover the openings 138a, 138p1 while exposing the opening 138p2. An etching process, such as a dry etching process, a wet etching process, or a combination thereof, may be performed to extend the opening 138p2 into the resistor structure 114. The additional mask is then removed, resulting in a structure such as Fig. 22 Next, execute Figures 12 to 18 The process described in the above is used to form the dielectric layer 140 and the conductive contacts 150a, 150p1, 150p2, as shown in FIG. Fig.23 As shown. The dielectric layer 140 and the seed layer 144, the conductive material 148 of the conductive contact 150p2 can extend into the resistor structure 114. In some embodiments, the dielectric layer 140 and the conductive contact 150p2 extend to about half of the thickness along the Z direction of the resistor structure 114. As the conductive contact 150p2 extends into the resistor structure 114, the tuning range of the resistance of the resistor structure 114 is widened. For example, Fig.18 As shown, by providing a conductive contact 150p2 above the resistor structure 114, the resistance of the resistor structure 114 can be tuned within a range of about 550 ohms to about 650 ohms through the conductive contact 150p2. Fig.23 As shown, as the conductive contact 150p2 extends into the resistor structure 114, the resistance of the resistor structure 114 can be tuned within a range of about 400 ohms to about 800 ohms by the conductive contact 150p2.

[0043] In some embodiments, the opening 138p2 extends through the resistor structure 114, such as Fig.24 As shown. The insulating material 104 may be exposed in the opening 138p2. Fig. 22 The additional masks described in Fig. 22 The etching process described in the above is performed for a longer time to etch through the resistor structure 114 until the insulating material 104 is exposed. Next, Figures 12 to 18 The process described in the above is used to form the dielectric layer 140 and the conductive contacts 150a, 150p1, 150p2, as shown in FIG. Fig.25 As shown. The dielectric layer 140 and the seed layer 144, the conductive material 148 of the conductive contact 150p2 may extend through the resistor structure 114, and the dielectric layer 140 may contact the insulating material 104. As the conductive contact 150p2 extends through the resistor structure 114, the tuning range of the resistance of the resistor structure 114 is further widened. For example, Fig.25 As shown, the conductive contact 150p2 extends through the resistor structure 114, and the resistance of the resistor structure 114 can be tuned within a range of about 200 ohms to about 1000 ohms by the conductive contact 150p2.

[0044] Figure 26-Figure 28 1 shows a cross-sectional side view of various stages of fabrication of a semiconductor device structure 100 according to an alternative embodiment. In some embodiments, the resistor structure 114 is larger, such as Fig.21 The resistor structure 114 is shown. Therefore, the CMP process (such as Figure 7 and Fig. 9 In some embodiments, in order to reduce the recess defects, the gate structure 126 can be formed in the passive device region 101p. Fig.26 As shown, the patterned mask layer 122 includes openings 124 in the active device region 101a and the passive device region 101p. In some embodiments, the openings 124 in the passive device region 101p expose edge portions of the resistor structure 114, such as Fig.26 shown.

[0045] like Fig. 27 As shown, the sacrificial gate electrode 112 in the active device region 101a and the exposed portion of the resistor structure 114 in the passive device region 101p are removed and replaced with a gate structure 126. Fig. 27As shown, the work function layer 128 is deposited on the insulating material 104 in the passive device area 101p, while the work function layer 28 is deposited on the metal-containing layer 108 in the active device area 101a. The gate structure 126 formed in the passive device area 101p is not an active gate structure and does not function as a gate. Instead, the gate structure 126 formed in the passive device area 101p serves as a conductive component to provide current flowing through the resistor structure 114 because the materials of the work function layers 128, 130 and the gate electrode 132 are conductive. The gate structure 126 formed in the passive device area 101p also helps to reduce the recess defects after the CMP process. For example, a portion of the work function layers 128, 130 and the gate electrode 132 can be formed on the ILD layer 120 and the resistor structure 114. The CMP process can be performed to remove portions of the work function layers 128, 130, and the gate electrode 132 can be formed on the ILD layer 120 and the resistor structure 114. Since the gate structure 126 is located in the passive device region 101 p , recess defects are reduced.

[0046] like Fig.28 As shown, the second ILD layer 134 and the conductive contacts 150a, 150p1, 150p2 are formed on the first ILD layer 120, the gate structure 126, and the resistor structure 114. The conductive contact 150p1 contacts the gate electrode 132 located in the passive device region 101p, and the gate structure 126 located in the passive device region 101p provides a path for current to flow through the resistor structure 114. In some embodiments, the conductive contact 150p2 and the dielectric layer 140 are disposed on the resistor structure 114, as shown in FIG. Fig.28 In some embodiments, the conductive contact 150p2 and the dielectric layer 140 extend into the resistor structure 114, as shown in FIG. Fig.23 In some embodiments, the conductive contact 150p2 and the dielectric layer 140 extend through the resistor structure 114, as shown in FIG. Fig.25 As shown. Since the gate electrode 132 is exposed in the opening 138p1 ( Fig.11 ), so you don't need to use Fig. 22 The portion of the resistor structure 114 exposed in the opening 138p2 is removed by using a selective etching process ( Fig.11 ), the gate electrode 132 exposed in the openings 137a, 138p1 may not be substantially affected.

[0047] Fig.29 According to some embodiments Fig. 27 FIG. 1 is a top view of a passive device region 101p of a semiconductor device structure 100. Fig.29As shown, the resistor structure 114 is disposed between two gate structures 126. In some embodiments, the length of the gate structure 126 in the Y direction may be substantially the same as the length of the resistor structure 114 in the Y direction. In some embodiments, the length of the gate structure 126 in the Y direction may be substantially greater than the length of the resistor structure 114 in the Y direction. For example, the gate structure 126 may extend to another active device region to form a transistor. Therefore, in some embodiments, a first portion of the gate structure 126 is disposed above the channel region between the source region and the drain region, and a second portion of the gate structure 126 is disposed adjacent to the resistor structure (e.g., the resistor structure 114). In some embodiments, the length of the gate structure 126 in the Y direction may be substantially less than the length of the resistor structure 114 in the Y direction.

[0048] In some embodiments, the resistor structure 114 is a resistor device, such as Fig.18 In some embodiments, the resistor structure includes more than one resistor device. Figure 30-Figure 39 1 shows a cross-sectional side view of various stages of fabrication of a semiconductor device structure 100, including a resistor structure having two resistor devices. Fig.30 As shown, a dielectric layer 106 and a metal-containing layer 108 are deposited over the substrate 102 and the insulating material 104 .

[0049] like Fig.31 As shown, semiconductor material 110 is deposited on metal-containing layer 108. Before depositing semiconductor material 110, metal-containing layer 108 and dielectric layer 106 are not patterned. Fig.32 As shown, the semiconductor material 110, the metal-containing layer 108, and the dielectric layer 106 are patterned to form a sacrificial gate electrode 112 in the active device region 101a and a resistor structure 158 in the passive device region 101p. The sacrificial gate electrode 112 is disposed on the metal-containing layer 108, which is disposed on the dielectric layer 106 in the active device region 101a. The resistor structure 158 includes a first resistor layer 160 as the metal-containing layer 108 and a second resistor layer 162 as the semiconductor material 110. The resistor structure 158 can be disposed on the dielectric layer 106 in the passive device region 101p. Fig.32 As shown, the first resistor layer 160 may include sidewalls that are substantially aligned with sidewalls of the second resistor layer 162 .

[0050] like Fig.33 As shown, spacers 116a, 116p and an ILD layer 120 are formed. CESL (not shown) may be formed between the substrate 102 and the ILD layer 120 and between the spacers 116a, 116p and the ILD layer 20. Next, as shown in FIG. Fig.34As shown, the sacrificial gate electrode 112 is replaced by a gate structure 126 including work function layers 128, 130 and a gate electrode 132. In some embodiments, the gate structure 126 is also formed in the passive device region 101p, such as Fig.34 In some embodiments, the gate structure 126 is not formed in the passive device region 101p. Fig. 9 shown.

[0051] like Fig.35 As shown, the second ILD layer 134, the dielectric layer 140 and the conductive contacts 150a, 150p1, 150p2 are formed above the first ILD layer 120, the gate structure 126 and the second resistor layer 162. In some embodiments, the first resistor layer 160 is a first resistor device and the second resistor layer 162 is a second resistor device. The conductive contact 150p1 contacts the gate electrode 132 located in the passive device area 101p, and the gate structure 126 located in the passive device area 101p provides a path for current to flow through the first resistor layer 160 and the second resistor layer 162. Therefore, in some embodiments, the first resistor device (i.e., the first resistor layer 160) and the second resistor device (i.e., the second resistor layer 162) are connected in parallel. The conductive contact 150p2 can be used to adjust the resistance of the first resistor layer 160 and the second resistor layer 162. In some embodiments, the conductive contact 150p2 and the dielectric layer 140 are disposed on the second resistor layer 162, as shown in FIG. Fig.35 In some embodiments, the conductive contact 150p2 and the dielectric layer 140 extend into the second resistor layer 162, as shown in FIG. Fig.36 In some embodiments, the conductive contact 150p2 and the dielectric layer 140 extend through the second resistor layer 162, as shown in FIG. Fig.37 In some embodiments, the conductive contact 150p2 and the dielectric layer 140 extend through the first resistor layer 160, as shown in FIG. Fig.38 shown.

[0052] In some embodiments, in order to independently adjust the resistance of the first and second resistor layers 160, 162, the conductive contact 150p2 and the dielectric layer 140 may have different depths, such as Fig.39 In some embodiments, the first conductive contact 150p2 and the dielectric layer 140 are disposed on the second resistor layer 162 to adjust its resistance, and the second conductive contact 150p2 and the dielectric layer are disposed through the second resistor layer 162 to adjust the resistance of the first and second resistor layers 160, 162. In some embodiments, the first conductive contact 150p2 and the dielectric layer 140 may extend into the second resistor layer 162. In some embodiments, the second conductive contact 150p2 and the dielectric layer 140 may extend into or through the first resistor layer 160.

[0053] Embodiments of the present disclosure provide a semiconductor device structure 100 and a method for forming the same. In some embodiments, the semiconductor device structure 100 includes a passive device region 101p having a resistor structure 114 and one or more conductive contacts 150p2 to adjust the resistance of the resistor structure 114. The formation of the resistor structure 114 and the conductive contacts 150p2 can be integrated with the formation of the FET in the active device region 101a. Some embodiments can achieve advantages. For example, the resistance of the resistor structure 114 can have a wider range with the conductive contacts 150p2.

[0054] One embodiment is a semiconductor device structure. The semiconductor device structure includes a first gate structure disposed over a substrate in an active device region, an insulating material disposed over the substrate in a passive device region, a resistor structure disposed over the insulating material in the passive device region, a first conductive contact electrically connected to the resistor structure, a second conductive contact disposed over the resistor structure, and a dielectric layer in contact with the second conductive contact and the resistor structure.

[0055] In the above semiconductor device structure, a silicide layer in contact with the first conductive contact and the resistor structure is also included.

[0056] In the above semiconductor device structure, each of the first conductive contact and the second conductive contact includes a seed layer and a conductive material.

[0057] In the above semiconductor device structure, the resistor structure includes a semiconductor material.

[0058] In the above semiconductor device structure, the resistor structure includes a first resistor layer and a second resistor layer disposed on the first resistor layer.

[0059] In the above semiconductor device structure, the first resistor layer includes a first metal-containing layer, and the second resistor layer includes a semiconductor material.

[0060] In the above semiconductor device structure, a second metal-containing layer is further included and arranged between the first gate structure and the substrate in the active device region.

[0061] In the above-mentioned semiconductor device structure, it also includes: a first spacer, arranged above the substrate in the active device area, wherein the first gate structure is arranged between the first spacers; and a second spacer, arranged above the insulating material in the passive device area, wherein the resistor structure is arranged between the second spacers.

[0062] In the above semiconductor device structure, it also includes a second gate structure and a third gate structure arranged above the insulating material, wherein the resistor structure is arranged between the second gate structure and the third gate structure, and the second gate structure and the third gate structure are arranged between the second spacers.

[0063] Another embodiment is a semiconductor device structure. The semiconductor device structure includes an insulating material disposed above a substrate, a resistor structure disposed above the insulating material, and first and second spacers disposed above the insulating material. The resistor structure is disposed between the first and second spacers. The semiconductor device structure also includes a first conductive contact electrically connected to the resistor structure, a second conductive contact extending into the resistor structure, and a first dielectric layer extending into the resistor structure. The first dielectric layer contacts the second conductive contact and the resistor structure.

[0064] In the above semiconductor device structure, it also includes a first gate structure and a second gate structure arranged above the substrate, wherein the resistor structure is arranged between the first gate structure and the second gate structure.

[0065] In the above semiconductor device structure, the second conductive contact and the first dielectric layer extend through the resistor structure.

[0066] In the above semiconductor device structure, it also includes a third conductive contact extending into the resistor structure and a second dielectric layer.

[0067] In the above semiconductor device structure, the resistor structure includes a first resistor layer and a second resistor layer disposed on the first resistor layer.

[0068] In the above semiconductor device structure, the second conductive contact and the first dielectric layer extend into the resistor structure at a first depth, and the third conductive contact and the second dielectric layer extend into the resistor structure at a second depth substantially greater than the first depth.

[0069] In the above semiconductor device structure, the second conductive contact and the first dielectric layer extend into the second resistor layer, and the third conductive contact and the second dielectric layer extend through the second resistor layer.

[0070] Another embodiment is a method of forming a semiconductor device structure. The method includes: depositing a metal-containing layer over an active device region and a passive device region of a substrate; depositing a semiconductor material in the active device region and the passive device region; patterning the semiconductor material to form a sacrificial gate electrode in the active device region and a resistor structure in the passive device region; replacing the sacrificial gate electrode in the active device region with a gate structure; forming an interlayer dielectric layer over the gate structure and the resistor structure, wherein the interlayer dielectric layer includes a first opening exposing a gate electrode of the gate structure, a second opening exposing a first portion of the resistor structure, and a third opening exposing a second portion of the resistor structure; depositing a dielectric layer in the first opening, the second opening, and the third opening; removing portions of the dielectric layer in the first opening and the second opening; and forming a first conductive contact, a second conductive contact, and a third conductive contact in the first opening, the second opening, and the third opening, respectively, wherein the dielectric layer is disposed between the third conductive contact and the resistor structure.

[0071] In the above semiconductor device structure, a silicide layer is also formed between the second conductive contact and the resistor structure.

[0072] In the above semiconductor device structure, the method further includes removing a portion of the metal-containing layer disposed in the passive device region before depositing the semiconductor material.

[0073] In the above semiconductor device structure, the third opening is further extended into the resistor structure.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A first gate structure is disposed above the substrate in the active device region; an insulating material disposed over the substrate in the passive device region; a resistor structure disposed above the insulating material in the passive device region; a first conductive contact electrically connected to the resistor structure; a second conductive contact disposed above the resistor structure; as well as A dielectric layer contacts the second conductive contact and the resistor structure. 2 . The semiconductor device structure of claim 1 , further comprising a silicide layer in contact with the first conductive contact and the resistor structure.

3. The semiconductor device structure according to claim 1, wherein: The resistor structure includes a first resistor layer and a second resistor layer disposed on the first resistor layer.

4. The semiconductor device structure according to claim 3, wherein: The first resistor layer includes a first metal-containing layer, and the second resistor layer includes a semiconductor material.

5. The semiconductor device structure according to claim 1, further comprising: first spacers disposed above the substrate in the active device region, wherein the first gate structure is disposed between the first spacers; and Second spacers are disposed above the insulating material in the passive device region, wherein the resistor structure is disposed between the second spacers.

6. The semiconductor device structure according to claim 5, further comprising a second gate structure and a third gate structure disposed above the insulating material, wherein: The resistor structure is disposed between the second gate structure and the third gate structure, and the second gate structure and the third gate structure are disposed between the second spacers.

7. A semiconductor device structure, comprising: an insulating material disposed above the substrate; a resistor structure disposed above the insulating material; a first spacer and a second spacer disposed over the insulating material, wherein the resistor structure is disposed between the first spacer and the second spacer; a first conductive contact electrically connected to the resistor structure; a second conductive contact extending into the resistor structure; and A first dielectric layer extends into the resistor structure, wherein the first dielectric layer contacts the second conductive contact and the resistor structure. 8 . The semiconductor device structure of claim 7 , further comprising a third conductive contact extending into the resistor structure and a second dielectric layer.

9. The semiconductor device structure according to claim 8, wherein: The resistor structure includes a first resistor layer and a second resistor layer disposed on the first resistor layer.

10. A method for forming a semiconductor device structure, comprising: depositing a metal-containing layer over the active device region and the passive device region of the substrate; Depositing semiconductor material in the active device region and the passive device region; Patterning the semiconductor material to form a sacrificial gate electrode in the active device region and a resistor structure in the passive device region; replacing a sacrificial gate electrode in the active device region with a gate structure; forming an interlayer dielectric layer over the gate structure and the resistor structure, wherein the interlayer dielectric layer comprises a first opening exposing a gate electrode of the gate structure, a second opening exposing a first portion of the resistor structure, and a third opening exposing a second portion of the resistor structure; depositing a dielectric layer in the first opening, the second opening, and the third opening; removing portions of the dielectric layer in the first opening and the second opening; and A first conductive contact, a second conductive contact, and a third conductive contact are formed in the first opening, the second opening, and the third opening, respectively, wherein the dielectric layer is disposed between the third conductive contact and the resistor structure.

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