Semiconductor device and forming method thereof

Abstract

The device includes a substrate having a semiconductor fin; a semiconductor channel stack on the substrate and positioned over the fin; a gate structure wrapping the semiconductor channel; a source / drain adjacent to the semiconductor channel; an internal spacer positioned between the semiconductor channel stack and the fin; an undoped semiconductor layer vertically adjacent to the source / drain and laterally adjacent to the fin; and an isolation structure laterally surrounding the undoped semiconductor layer, the isolation structure between the source / drain and the internal spacer. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: a substrate having a semiconductor fin; a semiconductor channel stack located on the substrate and positioned above the fin; a gate structure wrapping the semiconductor channel; a source / drain adjacent to the semiconductor channel; an internal spacer positioned between the semiconductor channel stack and the fin; an undoped semiconductor layer vertically adjacent to the source / drain and laterally adjacent to the fin; and an isolation structure laterally surrounding the undoped semiconductor layer, the isolation structure being located between the source / drain and the internal spacer.

[0004] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a semiconductor nanostructure layer stack above a substrate; forming a semiconductor nanostructure stack by forming a source / drain opening through the semiconductor nanostructure layer stack; forming a dielectric layer on a surface exposed by the source / drain opening; forming a first semiconductor layer on the dielectric layer in the source / drain opening; forming an isolation structure by removing a portion of the dielectric layer exposed by the first semiconductor layer; and forming a source / drain adjacent to the semiconductor nanostructure stack on the first semiconductor layer.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure stack above a substrate by forming a source / drain opening; forming a first semiconductor layer in the source / drain opening; forming an isolation layer in the source / drain opening on the first semiconductor layer; forming an isolation layer by thinning the isolation layer, wherein the forming of the isolation layer exposes the upper surface of the first semiconductor layer; forming an injection region including a first dopant of a first type by directing the first dopant onto the upper surface of the first semiconductor layer; forming a second semiconductor layer on the injection region; forming an isolation structure by removing a portion of the isolation layer exposed by the second semiconductor layer; and forming a source / drain on the second semiconductor layer, wherein the source / drain is a second type different from the first type. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1A to 1C is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0008] Figures 2A to 24 are diagrams of various embodiments of an IC device at various stages of fabrication according to various aspects of the disclosed embodiments.

[0009] Fig.25 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about", "substantially", etc., should be interpreted as understood by one of ordinary skill in the art in view of the current technical specification.

[0013] The terms "first", "second", "third", etc. may be used herein to describe the order of events or the sequential order of elements, but may be interchangeable or varied in some contexts. For example, a second layer may be formed on a first layer (e.g., sequentially after the first layer), but in some contexts, the first layer may be referred to as the "second layer", "third layer", "fourth layer", etc., and the second layer may be referred to as the "first layer", "third layer", "fourth layer", etc.

[0014] The term "surrounding" may be used herein to describe a structure that completely or partially surrounds another element or structure, for example in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left, right, front, and back) without surrounding the second structure on two vertical sides (e.g., top and bottom). In other examples, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front, and back) while leaving other sides (e.g., left, right, and bottom) exposed.

[0015] The presently disclosed embodiments relate generally to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0016] GAA logic hybrid cell devices can include different nanosheet widths to provide different effective widths (Weff). However, large nanosheet widths increase the cell area, while small nanosheet widths may limit the internal spacer and source / drain epitaxy process windows. Multiple sheet number selection (e.g., by disabling some nanosheets) provides different Weff for logic hybrid cells, allowing the cell size to be reduced and the process window to be increased.

[0017] Bulk substrate leakage and well isolation leakage increase with semiconductor scaling. Bottom isolation dielectrics can be implemented by depositing a dielectric layer (e.g., SiN) between the source / drain epitaxial bottom and the undoped semiconductor to reduce the effective capacitance (Ceff). However, the direct current (DC) performance of p-type FETs is degraded due to p-type epitaxial strain losses.

[0018] Embodiments of the present disclosure effectively isolate the source / drain epitaxy and substrate for n-type and p-type FETs while maintaining an improved strain effect on pFETs. In an embodiment, a sidewall dielectric layer is positioned between the substrate / fin and the undoped semiconductor component to isolate the source / drain epitaxy and the semiconductor component from the surrounding substrate while maintaining the undoped semiconductor surface exposed for pFET source / drain epitaxy growth to improve strain behavior. Body leakage and well isolation leakage can be effectively suppressed by the sidewall dielectric. In some embodiments, Ceff can be further reduced by including a bottom implant region having an anti-dopant therein. In such an embodiment, the sidewall dielectric can extend adjacent to the disabled bottommost channel.

[0019] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, less than the spacing obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0020] Figure 1A , Figure 1B , Figure 1C 1 shows a schematic cross-sectional side view of a portion of a nanostructured device 10 according to various embodiments. Figure 1A Provide a description, Figure 1A A view in the XZ plane is shown, wherein an isolation structure 110B is positioned below the source / drain regions 82P, 82N, isolating the respective semiconductor component 110A from the substrate 110 or the fin 32. Figure 1A The nanostructured device 10 is provided to provide a method for understanding Figures 2A to 24 The context of the technical features and benefits of various embodiments described in the accompanying drawings. A source / drain region may refer to a source or a drain, either individually or collectively depending on the context.

[0021] refer to Figure 1A, the nanostructured devices 20A, 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). The nanostructured devices 20A, 20B are formed on and / or in the substrate 110 and generally include a plurality of transistors extending across and / or encapsulating the isolation structure 36 (see FIG. Figure 3B ) and is separated by isolation structures 36. The gate structure 200 controls the current flowing through the channels 22A, 22B, 22C (or "channels 22") (optionally referred to as "nanostructures") protruding above the semiconductor fins 32.

[0022] Nanostructured devices 20A, 20B are shown to include three channels 22A, 22B, 22C that are laterally adjacent to source / drain features 82N, 82P and are covered and surrounded by a gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more. The gate structure 200 controls the flow of current through the channels 22A, 22B, 22C to and from the source / drain features 82N, 82P based on voltages applied at the gate structure 200 and at the source / drain features 82N, 82P.

[0023] In some embodiments, the fin structure 32 comprises silicon. In some embodiments, the nanostructure device 20B comprises an NFET and its source / drain features 82N comprise silicon phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, combinations thereof, or the like. In some embodiments, the nanostructure device 20A comprises a PFET and its source / drain features 82P comprise undoped or doped silicon germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. In general, the source / drain features 82N, 82P may comprise any combination of suitable semiconductor materials and suitable dopants. Figure 1A In the embodiment depicted in , nanostructure device 20A comprises a PFET and nanostructure device 20B comprises an NFET.

[0024] Each of the channels 22A, 22B, 22C includes a semiconductor material, such as silicon or a silicon compound, such as silicon germanium, etc. The channels 22A, 22B, 22C are nanostructures (e.g., having a size in the range of several nanometers), and may also each have an elongated shape and extend in the X direction. In some embodiments, each of the channels 22A, 22B, 22C has a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of the channels 22A, 22B, 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0025] In some embodiments, the lengths of the channels 22A, 22B, 22C (eg, measured in the X direction) may be different from each other, for example due to tapering during a fin etching process (see Figure 3A , Figure 3B ). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. Each of channels 22A, 22B, and 22C may not have a uniform thickness (e.g., along the X-axis direction), for example due to a channel trimming process used to expand the spacing between channels 22A, 22B, and 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window. For example, the middle portion of each of channels 22A, 22B, and 22C may be thinner than the ends of each of channels 22A, 22B, and 22C. Such shapes may be collectively referred to as "dog bone" shapes.

[0026] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 8 nanometers (nm) and about 12 nm, but ranges above or below the range may also be advantageous. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 5 nm and about 8 nm, but ranges above or below the range may also be advantageous. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., measured in the Y direction, perpendicular to the XZ plane) is at least about 8 nm, but in some embodiments, the width may be less than 8 nm.

[0027] The gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, and 22C, and the channels 22A, 22B, and 22C are silicon channels for N-type devices or silicon germanium channels for P-type devices. In some embodiments, the gate structure 200 includes an interface layer (IL) 210, one or more gate dielectric layers 600 on the interface layer 210, and one or more optional work function adjustment layers 900 (see FIG. 1 ) on the gate dielectric layer 600. Fig.24 ) and a metal core layer 290 on the gate dielectric layer 600 and an optional work function adjustment layer 900.

[0028] An interface layer 210 (which may be an oxide of the material of the channels 22A, 22B, 22C) is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interface layer 210 promotes adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the interface layer 210 has a thickness of about 5 angstroms (A) to about 50 angstroms (A). In some embodiments, the interface layer 210 has a thickness of about 10 A. An interface layer 210 having too thin a thickness may exhibit voids or insufficient adhesion properties. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage adjustment and resistance. In some embodiments, the interface layer 210 is doped with a dipole such as lanthanum for threshold voltage adjustment.

[0029] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、 2 O 5 or a combination thereof. In some embodiments, the gate dielectric layer 600 has a thickness of about 5 Å to about 100 Å. The gate dielectric layer 600 may be a single layer or multiple layers.

[0030] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material such as Co, W, Ru, combinations thereof, etc. In some embodiments, the metal core layer 290 is or includes a Co-based, W-based, or Ru-based compound or alloy, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, etc. Between the channels 22A, 22B, 22C, the metal core layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, which are then circumferentially surrounded by a gate dielectric layer 600, which is circumferentially surrounded by an interface layer 210. The gate structure 200 may also include a glue layer formed between the one or more work function layers 900 and the metal core layer 290 to increase adhesion. For simplicity, the glue layer is not Figure 1A Specifically shown in .

[0031] Nanostructured devices 20A, 20B may also include source / drain contacts 120 formed above source / drain features 82N, 82P. Source / drain contacts 120 may include a core layer that is or includes a conductive material such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner (or "barrier") layers such as SiN or TiN, which helps prevent or reduce diffusion of material from and into source / drain contacts 120. In some embodiments, the height of source / drain contacts 120 may be in the range of about 1 nm to about 50 nm.

[0032] The silicide layer 118 is positioned between the source / drain components 82N, 82P and the source / drain contact 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The silicide layer 118 can have a thickness in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction in contact resistance. A thickness above about 10nm may cause an electrical short circuit with the nanostructure 22. In some embodiments, the silicide layer 118 is present below the etch stop layer 131 and is in contact with the etch stop layer 131 .

[0033] The nanostructured devices 20A, 20B may also include an interlayer dielectric (ILD) 130. Fig. 12B . The ILD 130 provides electrical isolation between the various components of the nanostructured devices 20A, 20B discussed above (e.g., between adjacent pairs of source / drain contacts 120). The etch stop layer 131 may be formed prior to forming the ILD 130 and may be positioned laterally between the ILD 130 and the gate spacers 41 and vertically between the ILD 130 and the source / drain features 82N, 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO 2 、ZrO 2 、ZrAlO x 、HfAlO x 、HfSiO x 、Al 2 O 3 Or other suitable materials. In some embodiments, the thickness of the etch stop layer is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of ILD 130 (e.g., completely removed before forming source / drain contacts 120), the etch stop layer 131 can contact the source / drain contacts 120. Before forming the source / drain contacts 120, the etch stop layer 131 can be trimmed, for example, in the X-axis direction to improve the filling quality of the source / drain contacts 120.

[0034] Nanostructured devices 20A, 20B include metal core layer 290 disposed above channel 22A, gate dielectric layer 600, and gate spacer 41 on the sidewalls of IL 210, and inner spacer 74 disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C. Inner spacer 74 is also positioned between channels 22A, 22B, 22C. Figure 1A In the embodiment depicted in , the gate spacer 41 includes a first spacer layer 41A and a second spacer layer 41B on the first spacer layer 41A. The first spacer layer 41A and the second spacer layer 41B may each include a dielectric material, for example, a low-k material such as SiOCN, SiON, SiN, SICN, SiOC, etc. In some embodiments, the second spacer layer 41B is not present. The materials of the first spacer layer 41A and the second spacer layer 41B may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer 41B (or the first spacer layer 41A, when the second spacer layer 41B is not present) may be partially or completely removed to increase the aspect ratio of the opening through which the source / drain regions 82N, 82P are formed. Figure 1AAn embodiment is depicted in which the upper portion of the second spacer layer 41B is not thinned.

[0035] The isolation feature 110B extends from the lower surface of the source / drain 82 to a level below the upper surface of the fin 32. In some embodiments, the semiconductor feature 110A is an undoped semiconductor, such as silicon, silicon germanium, etc., grown in the source / drain opening. The semiconductor feature 110A can provide an improved surface for growing the source / drain 82P. In a device including a bottom insulator or bottom isolation layer 800, such as the nanostructure device 20B, the semiconductor feature 110A can provide a flat surface approximately at the level of the lowermost internal spacer 74, which can facilitate positioning the bottom insulator 800 near the level of the bottommost channel 22A. The isolation feature 110B provides electrical isolation between the source / drain 82N, 82P and the underlying substrate 110 and / or fin 32, which can reduce leakage current from the source / drain 82N, 82P to the substrate 110 and / or fin 32. The isolation features 110B may be a vertical thin dielectric layer between each respective fin 32 and the sidewall of the semiconductor feature 110A. In some embodiments, the isolation features 110B are in direct contact with the sidewalls of the fin 32 and the semiconductor feature 110A. In some embodiments, the isolation features 110B are or include a dielectric material such as one or more of SiOC, SiOCN, SiCN, SiN, combinations thereof, and the like.

[0036] Figure 1B An embodiment is depicted in which one or more of the channels 22 are disabled, which reduces the Weff of the nanostructured devices 20A, 20B. Figure 1B The device 10 depicted in FIG. 1 is similar in many respects to the reference Figure 1A The device 10 is described in detail and like reference numerals refer to like elements. Figure 1B In the embodiment, the nanostructured devices 20A, 20B include a trench isolation structure 110D and a trench isolation layer 110E extending from a level of about the upper surface of the fin 32 to a level above one or more trenches 22 of the nanostructured devices 20A, 20B. Figure 1B As depicted in , trench isolation structure 110D and trench isolation layer 110E extend to a level above bottommost channel 22A, such that channels 22B, 22C are active and may conduct current, while bottommost channel 22A is inactive / disabled and may not conduct current.

[0037] Figure 1C An embodiment is depicted in which one or more of the channels 22 are disabled, which reduces the Weff of the nanostructured devices 20A, 20B. Figure 1C The device 10 depicted in FIG. 1 is similar in many respects to the reference Figure 1B and Figure 1CThe device 10 described above is similar to the device 10 described above, and like reference numerals refer to like elements. In addition to or in place of the trench isolation structure 110D and the trench isolation layer 110E, such as Figure 1C As depicted in , the nanostructured devices 20A, 20B include an implanted region 110C, which can increase electrical isolation to the substrate 110 and / or the fin 32. The implanted region 110C may include an anti-dopant, which may be a dopant of the opposite type to the source / drain 82N, 82P above. For example, the source / drain 82N may include dopant ions of P, As, Sb, Bi, etc., and the implanted region 110C below the source / drain region 82N may include dopant ions of B, Al, Ga, In, Zn, etc. In another example, the source / drain 82P includes dopant ions of B, Al, Ga, In, Zn, etc., and the implanted region 110C below the source / drain region 82N may include dopant ions of P, As, Sb, Bi, etc.

[0038] Fig.25 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of an embodiment of the present disclosure is depicted. The method 1000 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 1000. Additional steps may be provided before, during, and after the method 1000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2A to 24 The method 1000 is described with reference to partial perspective views and / or cross-sectional views of a workpiece shown in FIG. 1 at different stages of manufacture according to an embodiment of the method 1000. For the avoidance of doubt, throughout the drawings, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that because the workpiece can be manufactured into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0039] Figures 2A to 24 is a diagram of an intermediate stage in the fabrication of a FET, such as a nanostructure FET, according to some embodiments.

[0040] exist Figure 2A and Figure 2BIn the embodiment, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0041] In addition, Figure 2A and Figure 2B In the embodiment of the present invention, a multilayer stack 25 or "lattice" is formed over a substrate 110 of alternating layers of first semiconductor layers 21A, 21B, 21C (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23. In some embodiments, the first semiconductor layer 21 can be formed of a first semiconductor material suitable for n-type nanoFETs, such as silicon, silicon carbide, etc., and the second semiconductor layer 23 can be formed of a second semiconductor material suitable for p-type nanoFETs, such as silicon germanium, etc. Each of the layers 21, 23 of the multilayer stack 25 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc.

[0042] Three layers of each of the first semiconductor layer 21 and the second semiconductor layer 23 are shown. In some embodiments, the multilayer stack 25 may include fewer or additional pairs of the first semiconductor layer 21 and the second semiconductor layer 23. Although the multilayer stack 25 is shown as including the second semiconductor layer 23 as the bottom layer, in some embodiments, the bottom layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0043] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of a nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of a nanoFET.

[0044] exist Figure 3A and Figure 3B In the embodiment, fins 32 are formed in substrate 110, and nanostructures 22, 24 are formed in multilayer stack 25, corresponding to Fig.25Step 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 may be formed by etching grooves in the multilayer stack 25 and the substrate 110. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching may be anisotropic. The first nanostructures 22A, 22B, 22C (hereinafter also referred to as "channels 22") are formed by the first semiconductor layer 21, and the second nanostructure 24 is formed by the second semiconductor layer 23. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 may be from about 18 nm to about 100 nm. To simplify the description, in Figure 3A and Figure 3B A portion of device 10 including two fins 32 is shown in FIG. Fig.25 The process 1000 shown in FIG. 1 can be extended to any number of fins and is not limited to FIG. 3A to FIG. 24 Two fins 32 are shown in FIG.

[0045] The fin 32 and the nanostructures 22, 24 can be patterned by any suitable method. For example, the fin 32 and the nanostructures 22, 24 can be formed using one or more photolithography processes including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a spacing smaller than that obtainable using a single, direct photolithography process. As an example of a multiple patterning process, a sacrificial layer can be formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 32.

[0046] Figure 3A and Figure 3B The fin 32 is shown with tapered sidewalls, such that the width of the fin 32 and / or each of the nanostructures 22, 24 increases continuously in a direction toward the substrate 110. In such embodiments, each of the nanostructures 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered), such that the widths of the fin 32 and nanostructures 22, 24 are substantially similar, and each of the nanostructures 22, 24 is rectangular in shape.

[0047] exist Figure 3A and Figure 3BIn the embodiment of the present invention, an isolation region or feature 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region or feature. The isolation region 36 may be formed by depositing an insulating material over the substrate 110, the fin 32 and the nanostructures 22, 24 and between adjacent fins 32 and nanostructures 22, 24. The insulating material may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32 and the nanostructures 22, 24. Thereafter, a core material, such as those discussed above, may be formed over the liner.

[0048] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material over the nanostructures 22, 24. After the removal process is completed, the top surfaces of the nanostructures 22, 24 may be exposed and flush with the insulating material.

[0049] The insulating material is then recessed to form isolation regions 36. After recessing, upper portions of nanostructures 22, 24 and fins 32 may protrude from between adjacent isolation regions 36. Isolation regions 36 may have top surfaces that are flat (as shown), convex, concave, or a combination thereof. In some embodiments, isolation regions 36 are recessed by an acceptable etching process, such as oxide removal using, for example, dilute hydrofluoric acid (dHF), which is selective to insulating materials and leaves fins 32 and nanostructures 22, 24 substantially unchanged.

[0050] FIG. 2A to FIG. 3B One embodiment of forming the fin 32 and nanostructures 22, 24 is shown (e.g., etched later). In some embodiments, the fin 32 and / or nanostructures 22, 24 are epitaxially grown in trenches in the dielectric layer (e.g., etched first). The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material.

[0051] exist Figure 3A and Figure 3BIn the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. Using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 110. Exemplary n-type impurities may include phosphorus, arsenic, antimony, etc. Exemplary p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implantation damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, but in-situ doping and implantation doping may be used together.

[0052] exist FIG. 4A to FIG. 4C In the embodiment, a dummy or sacrificial gate structure 40 is formed over the fin 32 and / or the nanostructures 22, 24, corresponding to Fig.25 Step 1200. A dummy or sacrificial gate layer 45 is formed over the fin 32 and / or nanostructures 22, 24. The dummy gate layer 45 may be or include a material having a high etch selectivity relative to the isolation region 36. The dummy gate layer 45 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polycrystalline silicon (poly-silicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 45 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing selected materials. A mask layer 47, which may include, for example, silicon nitride, silicon oxynitride, etc., is formed over the dummy gate layer 45. In some embodiments, before the dummy gate layer 45, a gate dielectric layer 43 is formed between the dummy gate layer 45 and the fin 32 and / or nanostructures 22, 24. In some embodiments, mask layer 47 includes a first mask layer 47A contacting dummy gate layer 45 and a second mask layer 47B located on and contacting first mask layer 47A. First mask layer 47A may be or include a material that is the same as or different from that of second mask layer 47B.

[0053] A spacer layer 41 is formed over the sidewalls of the mask layer 47 and the dummy gate layer 45. According to some embodiments, the spacer layer 41 is or includes an insulating material such as SiOCN, SiOC, SICN, etc. (or reference numerals). Figure 1A The spacer layer 41 may be formed by depositing a spacer material layer (not shown) over the mask layer 47 and the dummy gate layer 45. According to some embodiments, the portion of the spacer material layer located between the dummy gate structures 40 is removed using an anisotropic etching process. In some embodiments, as shown in FIG. Figure 4B , Figure 4CAs shown in detail in FIG. 4 , the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructure 22C, the gate dielectric layer 43, the dummy gate layer 45, and the first mask layer 47A and the second mask layer 47B. The second spacer layer 41B of the spacer layer 41 may be in contact with the first spacer layer 41A. The first spacer layer 41A may be or include a material that is the same as or different from that of the second spacer layer 41B.

[0054] exist Figure 5A and Figure 5B In the embodiment, a source / drain opening 59 is formed by performing an etching process to etch the protruding fin 32 and / or the portion of the nanostructures 22, 24 not covered by the dummy gate structure 40, corresponding to Fig.25 The recess may be anisotropic, so that the portion of the fin 32 directly below the dummy gate structure 40 and the spacer layer 41 is protected and substantially unetched. According to some embodiments, the top surface of the recessed fin 32 may be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, the top surface of the recessed fin 32 may be lower than the top surface of the isolation region 36, such as Figure 5B For simplicity, Figure 5A Three vertical stacks of nanostructures 22, 24 after the etching process are depicted. In general, the etching process may be used to form fewer or additional vertical stacks of nanostructures 22, 24 over the fins 32. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5B Fin spacers 41F are depicted, which are portions of the first spacer layer 41A and / or the second spacer layer 41B that are located over the isolation regions 36 adjacent to respective fins 32 .

[0055] FIG. 6A to FIG. 10B The formation of inner spacers and isolation structures 110B in the source / drain openings 59 is depicted.

[0056] exist Fig. 6A , Figure 6B In the process, a selective etching process is performed to recess the end portions of the nanostructure 24 exposed by the openings in the spacer layer 41 without substantially corroding the nanostructure 22. After the selective etching process, a groove is formed at the location where the removed end portion was once located in the nanostructure 24. Then, after the groove is formed, an inner spacer layer 74L is formed to fill (partially or completely) the groove formed in the nanostructure 22 by the previous selective etching process. The inner spacer layer 74L can be a suitable dielectric material such as silicon carbon nitride (SICN), silicon carbon oxynitride (SiOCN), etc. formed by a suitable deposition method such as PVD, CVD, ALD, etc.

[0057] exist Fig. 7A and Figure 7B In the embodiment, after forming the inner spacer layer 74L, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer 74 disposed outside the recess (e.g., on the sidewalls of the nanostructure 22 and the fin 32). The remaining portion of the inner spacer layer 74L (e.g., the portion disposed inside the recess in the nanostructure 24) forms the inner spacer 74. During the formation of the inner spacer 74 by the etching process, after penetrating the portion of the inner spacer layer 74L located on the upper surface of the fin 32, the etching process may continue to form an extended source / drain opening 79 having a depth exceeding the depth of the source / drain opening 59. The resulting structure is Fig. 7A Shown in.

[0058] The extended source / drain opening 79 may extend to a first depth D1 below the upper surface of the fin 32. The first depth D1 may be measured from the bottom surface of the lowermost internal spacer 74, as depicted. In some embodiments, the first depth D1 may be in the range of about 10 nm to about 30 nm. In subsequent operations, an isolation structure 110B is formed in the extended source / drain opening 79 to isolate the source / drain 82 from the substrate 110 or the fin 32. A first depth D1 less than about 10 nm may produce insufficient isolation (physical and / or electrical) between the source / drain 82 and the substrate 110 or the fin 32. A first depth D1 exceeding about 30 nm may make it difficult to form a layer in the extended source / drain opening 79 due to its increased aspect ratio (depth / width).

[0059] FIG. 8A to FIG. 10B Depicts the formation of an isolation structure 110B and a semiconductor layer 110A or “second semiconductor layer 110A” according to various embodiments, corresponding to Fig.25 Steps 1400 and 1500. Some parts of step 1500 may be performed before completing step 1400.

[0060] exist Fig. 8A , Figure 8BIn the extended source / drain openings 79, a first material layer 110BL is formed. The first material layer 110BL may be or include a dielectric material and have an etching selectivity different from that of the substrate 110 and the fin 32. For example, the substrate 110 and the fin 32 may be silicon, and the first material layer 110BL may be SiN, SiOC, SiOCN, SICN, etc. The first material layer 110BL may be deposited in the extended source / drain openings 79. The deposition may include one or more operations, such as CVD, ALD, etc. The first material layer 110BL may be deposited to a thickness in a range of about 1 nm to about 3 nm. In some embodiments, after the first material layer 110BL is deposited, the etching may be performed, for example, by a suitable etching operation, such as a gas source (including CF 4 , CH 3 F. CHF 3 , CH 4 The first material layer 110BL may be in direct contact with the side or sidewalls of the spacer layer 41, the fin spacer 41F, the channel 22, the inner spacer 74, the fin 32, and the isolation region 36.

[0061] exist Fig. 9A , Fig. 9B In the embodiment, a first semiconductor layer 110A or a “first semiconductor component 110A” is formed on the first material layer 110BL, corresponding to Fig.25 Step 1500. The first semiconductor layer 110A may be or include a semiconductor material, which may be an undoped semiconductor material, such as undoped silicon or undoped silicon germanium. The first semiconductor layer 110A may be formed by a suitable growth process, such as chemical vapor deposition (CVD), molecular beam epitaxy (MPE), etc. The first semiconductor layer 110A is a different material from the first material layer 110BL, which facilitates removing the exposed portion of the first material layer 110BL without substantially removing the first semiconductor layer 110A. The first semiconductor layer 110A is a semiconductor material, which facilitates forming a pFET source / drain in a subsequent operation with improved strain, which improves DC performance. The first semiconductor layer 110A may have a substantially flat top surface, which facilitates forming an epitaxial layer thereon, such as the source / drain 82.

[0062] In some embodiments, the first semiconductor layer 110A has an upper surface located above the upper surface of the fin 32 and optionally below the lower surface of the bottommost channel 22A and / or the top surface of the bottommost inner spacer 74. The first semiconductor layer 110A may have a height in the range of about 10 nm to about 25 nm. The first semiconductor layer 110A may be in direct contact with the upper surface of the fin 32 in the extended source / drain opening 79 and the side or sidewall of the first material layer 110BL.

[0063] exist Fig. 10A , Fig. 10B In the embodiment, the portion of the first material layer 110BL exposed by the first semiconductor layer 110A is removed to form an isolation structure 110B, and the isolation structure 110B is completed. Fig.25 Step 1400. After removal, the isolation structure 110B may have an upper surface substantially coplanar with an upper surface of the first semiconductor layer 110A. Removing the exposed portion of the first material layer 110BL exposes the gate spacer 41, the channel 22, the inner spacer 74, and the upper portion of the fin spacer 41F.

[0064] Remove Fig. 10A , Fig. 10B The exposed portion of the first material layer 110BL depicted in FIG. 1 may be implemented via an isotropic etching process, such as wet etching including a dilute HF or sulfur peroxide mixture (SPM) solution. In some embodiments, the upper surface of the first material layer 110BL may be slightly recessed to a level below the upper surface of the first semiconductor layer 110A. In some embodiments, the upper surface of the isolation structure 110B extends to a level slightly above the upper surface of the first semiconductor layer 110A.

[0065] exist Fig.11A , Fig. 11B , Fig. 11C , Fig.11D , Fig.11E In the embodiment, source / drain regions 82N and 82P are formed, corresponding to Fig.25Step 2000. In the illustrated embodiment, the source / drain region 82P is epitaxially grown by epitaxial material. In some embodiments, the source / drain region 82P applies stress in the corresponding channel 22A, 22B, 22C, thereby improving performance. The source / drain region 82P is formed so that each dummy gate structure 40 is disposed between corresponding adjacent pairs of the source / drain region 82P. In some embodiments, the spacer layer 41 separates the source / drain region 82P from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device. The source / drain region 82P may be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, etc. The source / drain region 82P may apply compressive strain in the channel region. The source / drain regions 82N, 82P may have a surface protruding from the corresponding surface of the first semiconductor layer 110A, and may have a small plane. In some embodiments, adjacent source / drain regions 82P may be merged to form a single source / drain region 82P adjacent to two adjacent fins 32 .

[0066] In the illustrated embodiment, after forming the source / drain regions 82P, an optional bottom insulator 800 may be formed corresponding to Fig.25 Step 1900. The formation of the bottom insulator 800 may include a suitable deposition operation, such as LPCVD, PECVD, ALD, etc. The bottom insulator 800 may be or include SiN or another suitable dielectric material. The thickness of the bottom insulator 800 may be in the range of about 2nm to about 4nm. During the formation of the bottom insulator 800, a dielectric layer having the same composition and thickness as the bottom insulator 800 may be formed on the upper surface of the source / drain region 82P. The dielectric layer may be removed from the upper surface of the source / drain region 82P, as shown. In some embodiments, the bottom insulator 800 is not formed, so that the source / drain region 82N formed in a subsequent operation is directly formed on the first semiconductor layer 110A.

[0067] After forming the bottom insulator 800, the source / drain region 82N is epitaxially grown by the epitaxial material. In an embodiment including the optional bottom insulator 800, the source / drain region 82N can grow from the channel 22 without growing from the first semiconductor layer 110A. In some embodiments, the source / drain region 82N applies stress in the corresponding channels 22A, 22B, 22C, thereby improving performance. The source / drain region 82N is formed so that each dummy gate structure 40 is disposed between corresponding adjacent pairs of the source / drain region 82N. In some embodiments, the spacer layer 41 separates the source / drain region 82N from the dummy gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the subsequently formed gate of the resulting device. The source / drain region 82N can be or include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, etc. Due to the presence of the bottom insulator 800, the source / drain region 82N can apply tensile strain in the channel region. The source / drain regions 82N may have surfaces that are raised from corresponding surfaces of the fins 32 and may have facets. In some embodiments, adjacent source / drain regions 82N may merge to form a single source / drain region 82N adjacent to two adjacent fins 32 .

[0068] like Fig.11A , the isolation structure 110B may extend to a second depth D2 below the bottom surface of the source / drain region 82P. That is, the second depth D2 is the distance between the bottommost point of the bottom surface of the source / drain region 82P to the bottommost point of the bottom surface of the isolation structure 110B. In some embodiments, the second depth D2 is in a range of about 5 nm to about 20 nm. A second depth D2 less than about 5 nm may result in insufficient isolation between the source / drain 82 and the substrate 110 and / or the fin 32.

[0069] In some embodiments, Fig. 11C , the isolation structure 110B is formed in the PFET and not in the NFET. For example, under the p-type source / drain 82P, the isolation structure 110B is positioned between the first semiconductor layer 110A and the adjacent substrate 110 and / or the fin 32, and under the n-type source / drain 82N, the isolation structure 110B is omitted, so that the first semiconductor layer 110A is in direct contact with the upper surface and the side or sidewall of the substrate 110 and / or the fin 32. In such an embodiment, the bottom insulator 800 is present between the source / drain 82N and the first semiconductor layer 110A.

[0070] Fig.11D The device 10 is depicted along the XY plane. Fig. 11B. The isolation structure 110B completely surrounds the first semiconductor layer 110A along at least four sides (such as the front side, the back side, the left side, and the right side). "Completely surrounding" includes meanings surrounding less than all sides of the first semiconductor layer 110A. For example, the top surface and the bottom surface of the first semiconductor layer 110A may not be surrounded by the isolation structure 110B.

[0071] like Fig.11E , in some embodiments, the first semiconductor layer 110A may directly adjoin the isolation region 36, and the isolation structure 110B may be omitted on one or more sides of the first semiconductor layer 110A adjoining the isolation region 36. That is, because the isolation region 36 is an electrical insulator, the formation of the isolation structure 110B between the first semiconductor layer and the isolation region 36 may be omitted.

[0072] exist Fig. 12A , Fig. 12B In the embodiment, after forming the source / drain regions 82N, 82P, an ILD 130 covering the source / drain regions 82N, 82P and adjacent to the spacer layer 41 may be formed (see FIG. Fig. 12B In some embodiments, ESL 131 is formed before forming ILD 130. ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from that of ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO 2 、ZrO 2 、ZrAlO x 、HfAlO x 、HfSiO x 、Al 2 O 3 or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD can be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition process.

[0073] Then, an active gate structure 200 may be formed. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed on the ILD 130 and the ESL 131. In the planarization process, portions of the hard masks 47A, 47B and the gate spacers 41 are also removed. After the planarization process, the dummy gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the dummy gate layer 45 and the gate spacers 41.

[0074] Next, the dummy gate layer 45 is removed in an etching process to form a groove. In some embodiments, the dummy gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate layer 45 without etching the spacer layer 41. The dummy gate dielectric 43 (when present) can be used as an etch stop layer when etching the dummy gate layer 45. Then, after removing the dummy gate layer 45, the dummy gate dielectric 43 can be removed.

[0075] Nanostructure 24 is removed to release nanostructure 22. After nanostructure 24 is removed, nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of substrate 110). In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant that is selective to the material of nanostructure 24, so that nanostructure 24 is removed without substantially attacking nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F 2 and HF, and the carrier gas can be an inert gas such as Ar, He, N 2 , their combinations, etc.

[0076] In some embodiments, nanostructure 24 is removed, and nanostructure 22 is patterned to form the channel region of the PFET and NFET. However, in some embodiments, nanostructure 24 may be removed, and nanostructure 22 may be patterned to form the channel region of the NFET, and nanostructure 22 may be removed, and nanostructure 24 may be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of the NFET, and nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of the PFET. In some embodiments, nanostructure 22 may be removed, and nanostructure 24 may be patterned to form the channel region of the PFET and NFET.

[0077] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction.

[0078] Then, a replacement gate 200 is formed. The gate structure 200 may be formed by a series of deposition operations, such as ALD cycles, of the various layers of the gate structure 200 in the opening, as shown in FIG. Fig.24 Describe in more detail.

[0079] Fig.24 is a detailed view of a portion of a gate structure 200. The gate structure 200 generally includes an interfacial layer (IL or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0080] refer to Fig.24 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, for example, silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The first IL 210 has a thickness ranging between about 5 angstroms and about 50 angstroms.

[0081] Still reference Fig.24 , a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed at a temperature in a range between about 200 degrees Celsius and about 300 degrees Celsius using between about 40 and 80 deposition cycles. In some embodiments, the ALD process uses HfCl 4 and / or H 2 O as a precursor. Such an ALD process may form the first gate dielectric layer 220 to have a thickness ranging between about 10 angstroms and about 100 angstroms.

[0082] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than that of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、 2 O5 or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of which includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructured device 20A, 20B.

[0083] Further references Fig.24 , a second IL 240 is formed on the gate dielectric layer 600, and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 further provides improved thermal stability for the gate structure 200, and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function barrier layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is accomplished by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following materials: HfSiON, HfTaO, HfTiO, HfTaO, HfAlON, HfZrO or other suitable materials. In a specific embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by using about 40 to about 100 cycles of ALD at a temperature of about 400 degrees Celsius to about 450 degrees Celsius. In some embodiments, thermal annealing is then performed to form the second IL 240, which can be or include TiSiNO. After the second IL 240 is formed by thermal annealing, atomic layer etching (ALE) with artificial intelligence (AI) control can be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 240. Each cycle can include WCl 5 The first pulse of , followed by an Ar purge, followed by O 2 A second pulse of , followed by another Ar purge, is performed. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage tuning by metal gate patterning.

[0084] In addition, Fig.24In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function barrier layer 700 is optionally formed on the gate structure 200. The work function barrier layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function barrier layer 700 is TiN. The work function barrier layer 700 may have a thickness ranging from about 5 Å to about 20 Å. The inclusion of the work function barrier layer 700 provides additional threshold voltage adjustment flexibility. Generally, the work function barrier layer 700 increases the threshold voltage for NFET transistor devices and reduces the threshold voltage (magnitude) for PFET transistor devices.

[0085] In some embodiments, the work function metal layer 900 is formed on the work function barrier layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal layer, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating and / or other suitable methods, and has a thickness between about 10A and 20A. The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN or another suitable material, and has a thickness between about 10A and 20A. The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer, which will cause an undesirable drift in the threshold voltage. The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer, and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness between about 10 Å and about 20 Å.

[0086] Fig.24A metal core layer 290 is also shown. In some embodiments, a glue layer (not shown separately) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance the adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride using ALD, such as TiN, TaN, MoN, WN, or another suitable material. In some embodiments, the thickness of the glue layer is between about 10A and about 25A. The metal core layer 290 can be formed on the glue layer and can include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 can be deposited using processes such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510 is formed in the metal core layer 290 vertically located between the channels 22A, 22B, and 22C, and the seam 510 can be an air gap. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. Due to merging of the sidewall deposited films during conformal deposition, seams 510 may form. In some embodiments, seams 510 do not exist between adjacent channels 22A, 22B, 22C.

[0087] After forming the gate structure 200, source / drain openings may be formed in the ILD 130, and source / drain contacts 120 may be formed in the source / drain openings. Fig. 12A , Fig. 12B Shown in.

[0088] Silicide regions 118 and source / drain contacts 120 may be formed on source / drain regions 82N, 82P. In some embodiments, silicide layer 118 is formed before forming source / drain contacts 120. For example, an N-type or P-type metal layer may be formed as a conformal thin layer over the exposed portions of source / drain regions 82N, 82P. The metal layer may be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, silicide layer 118 may be formed by annealing device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the region below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Above about 10 nm, the silicide layer 118 may be short-circuited with the channel 22B.

[0089] After forming the silicide layer 118, the source / drain contacts 120 are formed by filling the openings above the source / drain regions 82N, 82P with, for example, a liner layer and a filling layer. In some embodiments, the source / drain contacts 120 are formed by depositing a material that is or includes a conductive material such as Co, W, Ru, combinations thereof, etc. In some embodiments, the source / drain contacts 120 are or include a Co-based, W-based, or Ru-based compound or alloy, including one or more elements such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, etc. The source / drain contacts 120 are bonded to the silicide layer 118 and contact the ESL 131. The description of the device 10 and its illustration in many of the figures are given with reference to a GAAFET including a vertical stack of nanostructures 22. In some embodiments, a silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain regions 82N, 82P of the FinFET device.

[0090] Additional processing may be performed to complete the fabrication of the nanostructure device 20. For example, a gate contact (or gate via) may be formed to electrically couple to the gate structure 200. An interconnect structure may then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structure may include a plurality of dielectric layers (including, for example, a second ILD) surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices on the substrate 110 (such as the nanostructure device 20) and to IC devices external to the IC device 10.

[0091] Figures 13 to 23B 1 is a cross-sectional side view depicting the formation of an implanted region 110C having an anti-dopant therein according to various embodiments. Like reference numerals refer to like elements. Reference is made to a configuration in which the isolation structure 110B is not formed. Figures 13 to 22 In some embodiments, the formation of the isolation structure 110B may be combined with the formation of the implant region 110C. Fig.23A and Fig. 23B It should be understood that “incorporating” includes meaning that the isolation structure 110B is formed in an operation before or after the implant region 110C is formed.

[0092] exist Fig.13 In the embodiment, after forming a first semiconductor layer or mesa 110A in direct contact with the adjacent fin 32 and / or substrate 110, an isolation layer 110EL is formed in the source / drain openings 89 in the first device region 10A, the second device region 10B, the third device region 10C, and the fourth device region 10D, corresponding to Fig.25 Step 1600. The first device region 10A and the second device region 10B may be regions where three of the channels 22 are active, and the third device region 10C and the fourth device region 10D may be regions where two of the channels 22 are active and one of the channels 22 is disabled. The first device region 10A and the third device region 10C may be regions where NFETs are formed, and the second device region 10B and the fourth device region 10D may be regions where PFETs are formed.

[0093] The isolation layer 110EL may be a dielectric material layer, which may be or include one or more of SiOC, SiOCN, SICN, SiN, etc. The isolation layer 110EL may be deposited as a conformal thin layer on the exposed surfaces of the spacer 41, the channel 22, the inner spacer 74, and the first semiconductor layer 110A. The isolation layer 110EL may be deposited by a suitable deposition operation, such as PVD, CVD, ALD, etc. The isolation layer 110EL may have a first thickness in the range of about 1 nm to about 10 nm.

[0094] exist Fig.14 and Fig.15 In the embodiment, after forming the isolation layer 110EL, a mask layer 400 is formed, which covers the isolation layer 110EL in the first device region 10A and the second device region 10B, while exposing the isolation layer 110EL in the third device region 10C and the fourth device region 10D. The mask layer 400 can be blanket coated on the device regions 10A-10D and then patterned to expose the third device region 10C and the fourth device region 10D. Then, the portions of the device regions 10A-10D exposed by the mask layer 400 are etched by a suitable etching process. For example, the isolation layer 110EL in the third device region 10C and the fourth device region 10D is etched in the etching process, which penetrates (or removes) the bottom portion of the isolation layer 110EL to expose the first semiconductor layer 110A below. In some embodiments, the upper surface of the first semiconductor layer 110A is slightly etched by the etching process, which may cause the upper surface to be concave after the etching process. The thickness of the isolation layer 110EL' remaining on the side or sidewall of the spacer 41, the inner spacer 74, and the channel 22 may be reduced by an etching process. In some embodiments, after the etching process, the thickness of the isolation layer 110EL' is in a range of about 1 nm to about 3 nm. In some embodiments, the etching process may be a wet etch that is selective to the material of the isolation layer 110EL'.

[0095] After removing the bottom portion of the isolation layer 110EL to expose the first semiconductor layer 110A, as shown in FIG. Fig.14 As depicted in FIG. 1 , an implantation process may be performed to form implantation regions 110C in the first semiconductor layer 110A in the third device region 10C and the fourth device region 10D, corresponding to Fig.25 In some embodiments, the implant process implants an "anti-dopant" into the implant region 110C, which may be a dopant of a different or opposite type than the source / drain 82 to be formed above the implant region 110C. For example, the third device region 10C may include a P-type nanostructure device 20A ( Fig.23A ), and the implantation regions 110C in the third device region 10C and the fourth device region 10D may include N-type ion dopant substances, such as P, As, Sb, Bi, etc. In another example, the third device region 10C and the fourth device region 10D may include an N-type nanostructure device having an N-type source / drain 82N, and the implantation regions 110C may include P-type ion dopant substances, such as B, Al, Ga, In, etc.

[0096] In some embodiments, Fig.15, the third device region 10C will include a P-type nanostructure device, and the fourth device region 10D will include an N-type nanostructure device. In such an embodiment, the implantation region 110CN located below the P-type nanostructure device in the third device region 10C may include an N-type ion dopant material, such as P, As, Sb, Bi, etc., and the implantation region 110CP located below the N-type nanostructure device in the fourth device region 10D may include a P-type ion dopant material, such as B, Al, Ga, In, etc. For example, the third device region 10C may be masked when the first implantation process implants P-type ions in the fourth device region 10D, and then the fourth device region 10D may be masked when the second implantation process implants N-type ions in the third device region 10C.

[0097] In some embodiments, the third device region 10C including the P-type nanostructure device is implanted with N-type ions to form an implant region 110CN, and the fourth device region 10D including the N-type nanostructure device is not implanted. For example, the implant region 110CN can be formed in the P-type device region, and the implant region 110CP is omitted in the N-type device region. When the implant region 110C or 110CP is omitted, the first semiconductor layer 110A can be a single, continuous layer that is always undoped and is in direct contact with the source / drain 82N formed thereon, or in direct contact with the bottom insulator 800 located between the first semiconductor layer 110A and the source / drain 82N formed thereon.

[0098] The implantation process may include a first cleaning process, wherein the exposed area is cleaned to remove surface contaminants, which may include immersing the wafer in one or more chemicals and rinsing the wafer with deionized water. Then, a thin oxide layer may be optionally grown on the trench wall and bottom to improve dopant diffusion and prevent channeling. An implantation operation may be performed, wherein the selected dopant material (e.g., phosphorus for n-type, boron for p-type) is ionized and accelerated to high energy (e.g., 10-100 keV). The ion beam is directed at the exposed area, and parameters that are conducive to achieving conformal doping in high aspect ratio trenches are selected. In some embodiments, the wafer is tilted and / or multiple ion beams are directed at the wafer. The dose and energy of the ion beam may be selected to achieve the selected dopant concentration and distribution in the trench. The implanted wafer may then be annealed at high temperature (e.g., 800-1000° C.) to activate the dopant and remove implant damage. The annealing process may also affect dopant diffusion and activation distribution. Then, a post-implantation cleaning to remove post-implantation residues may be performed.

[0099] The implant region 110C may extend from a first side of the isolation layer 110EL' to an opposite second side of the isolation layer 110EL'. The implant region 110C may extend to a depth below a lower surface of the bottommost inner spacer 74 and above a bottom surface of the first semiconductor layer 110A.

[0100] The inclusion of implanted regions 110C, 110CP, 110CN including counter-dopants may be beneficial in reducing leakage current and, thereby, reducing effective capacitance Ceff.

[0101] Although the implantation regions 110C, 110CP, and 110CN are Fig.14 and Fig.15 10D, but it should be understood that in some embodiments, the implanted regions 110C, 110CP, and 110CN may be formed in all four device regions 10A-10D. That is, after forming the layer 110EL, the mask layer 400 may not be formed, and the layer 110EL may be thinned in all device regions 10A-10D, so that the three devices in the first device region 10A and the second device region 10B and the two devices in the third device region 10C and the fourth device region 10D may each include the implanted regions 110C, 110CP, and 110CN.

[0102] exist Fig.16 In the embodiment, the mask layer 400 may be removed, and then a second semiconductor layer 110D may be formed on the implantation region 110C, which may be an undoped semiconductor layer, such as an undoped silicon layer, corresponding to Fig.25 Step 1800. The undoped silicon layer may be formed by a suitable epitaxial operation, such as reduced pressure CVD (RPCVD), ultra-high vacuum CVD (UHVCVD), MBE, selective epitaxial growth (SEG), etc. The second semiconductor layer 110D is formed to a level high enough to isolate one or more of the channels 22. For example, Fig.16 , the second semiconductor layer 110D is formed to a level above the upper surface of the bottommost channel 22A. This will be used to deactivate or disable channel 22A while allowing channels 22B, 22C to remain active. In some embodiments, the second semiconductor layer 110D is formed to a level above the upper surface of another channel 22 (such as channel 22B), so that channels 22A and 22B can be disabled. Typically, this level can be located between the upper and lower surfaces of one of the internal spacers 74, such as the internal spacer 74 between channels 22A and 22B or between channels 22B and 22C.

[0103] exist Fig.17In the embodiment, after forming the second semiconductor layer 110D, the exposed portions of the isolation layers 110EL and 110EL' are removed, thereby exposing the first semiconductor layer 110A in the first device region 10A and the second device region 10B and the second semiconductor layer 110D in the third device region 10C and the fourth device region 10D. The removal can be performed by a suitable etching operation, such as wet etching that is selective to the material of the isolation layers 110EL and 110EL'. In the third device region 10C and the fourth device region 10D, the remaining portion of the isolation layer 110EL' is the isolation structure 110E, corresponding to Fig.25 Step 1600. The isolation structure 110E is positioned between the channel 22A and the second semiconductor layer 110D. Fig.17 , the isolation structure 110E may extend to a level slightly above or at the upper surface of the second semiconductor layer 110D. In some embodiments, the isolation structure 110E may extend to a level slightly below the upper surface of the second semiconductor layer 110D. For example, an etching operation to remove the exposed area of ​​the isolation layer 110EL' may cause an over-etch that removes a portion of the isolation layer 110EL' that is laterally located between the second semiconductor layer 110D and the adjacent internal spacer and / or channel 22A. This is particularly useful in Fig.17 10D and the lower surface of the inner spacer 74 between the channels 22A, 22B. In some embodiments, the isolation structure 110E extends to the level L1, rather than to a level above or at the upper surface of the second semiconductor layer 110D.

[0104] exist Fig.18 In the embodiment of the present invention, a second mask layer 850 is formed, and the second mask layer 850 covers the regions 10A and 10C where the N-type nanostructure devices are to be formed, while exposing the regions 10B and 10D where the P-type nanostructure devices are to be formed. Then, a P-type source / drain 82P is formed in the second device region 10B and the fourth device region 10D, corresponding to Fig.25Step 2000. The source / drain 82P is formed on the first semiconductor layer 110A in the second device region 10B and on the second semiconductor layer 110D in the fourth device region 10D. The formation of the source / drain 82P can be implemented by a suitable epitaxial growth process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In the second device region 10B, the source / drain 82P is in contact with the channels 22A, 22B, 22C. In the fourth device region 10D, the source / drain 82P is in contact with the channels 22B, 22C and is isolated from the channel 22A, for example, by the isolation structure 110E. The source / drain 82P in the fourth device region 10D is isolated from the substrate 110 and / or the fin 32 by the implantation region 110C. The source / drain 82P in the second device region 10B is in direct contact with the first semiconductor layer 110A and is not isolated from the substrate 110 and / or the fin 32 by the implantation region because the implantation region 110C is not formed in the second device region 10B.

[0105] exist Fig.19 In the embodiment, after forming the source / drain 82P, the second mask layer 850 is removed, and then the bottom isolation layer 800 is formed, which also forms a dielectric layer 820 on the source / drain 82P, corresponding to Fig.25 Step 1900. The bottom isolation layer 800 and the dielectric layer 820 can be formed by: depositing a single material layer (such as a dielectric layer including SiOC, SiOCN, SiCN, SiN, etc.) as a blanket conformal layer above the device regions 10A-10D; and then removing the excess portion of the material layer located above the gate spacer 41 and the sacrificial gate 45, leaving a horizontal portion covering the upper surface of the first semiconductor layer 110A, the source / drain 82P, and the second semiconductor layer 110D and the isolation structure 110E. In some embodiments, the bottom isolation layer 800 and the isolation structure 110E include different materials. In some embodiments, there is a visible interface between the bottom isolation layer 800 and the isolation structure 110E. The interface can be located at a reference Fig.17 At the level L1 described. The bottom isolation layer 800 may be advantageous in the first device region 10A and the third device region 10C where the NFET nanostructure device will be formed to restrict the growth of the N-type source / drain 82N to grow laterally outward from the channel 22, and not substantially upward from the substrate 110 (e.g., from the first semiconductor layer 110A or the second semiconductor layer 110D). This can improve the strain in the channel 22, which is advantageous for N-type devices (such as N-type GAAFETs, etc.). In some embodiments, the bottom isolation layer 800 and / or the dielectric layer 820 are omitted, or are not formed and do not exist between the source / drain 82N and the first semiconductor layer 110A and / or the second semiconductor layer 110D.

[0106] exist Fig. 20 In the embodiment, after forming the optional bottom isolation layer 800, an N-type source / drain 82N is formed. The source / drain 82N is formed on the first semiconductor layer 110A in the first device region 10A (e.g., with or without the bottom isolation layer 800 therebetween) and on the second semiconductor layer 110D in the third device region 10C (e.g., with or without the bottom isolation layer 800 therebetween), corresponding to Fig.25 Step 2000. The formation of the source / drain 82N can be implemented by a suitable epitaxial growth process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. In the first device region 10A, the source / drain 82N is in contact with the channels 22A, 22B, 22C. In the third device region 10C, the source / drain 82N is in contact with the channels 22B, 22C, and is isolated from the channel 22A, for example, by the isolation structure 110E. The source / drain 82N in the third device region 10C is isolated from the substrate 110 and / or the fin 32 by the implantation region 110C. The source / drain 82N in the first device region 10A is in direct contact with the first semiconductor layer 110A or the bottom isolation layer 800, and is not isolated from the substrate 110 and / or the fin 32 by the implantation region because the implantation region 110C is not formed in the first device region 10A.

[0107] Fig.21 and Fig. 22 The formation of N-type source / drain 82N is depicted in accordance with an embodiment wherein implant regions 110CN, 110CP are formed to have different dopant species from one another, rather than implant region 110C having the same dopant species from one another.

[0108] exist Fig.21 In the example, after forming the source / drain 82P, the bottom isolation layer 800 and the dielectric layer 820 are as shown in FIG. Fig.19 However, in Fig.21 In the embodiment, the bottom isolation layer 800 is removed from the second semiconductor layer 110D in the third device region 10C or is not formed on the second semiconductor layer 110D in the third device region 10C. For example, the bottom isolation layer 800 may be formed above the second semiconductor layer 110D and then may be removed by a suitable etching process. In another example, the third device region 10C may be masked during the formation of the bottom isolation layer 800 so that the bottom isolation layer 800 is not formed on the second semiconductor layer 110D.

[0109] In the third device region 10C, due to the presence of the implantation region 110CP having a different dopant type (e.g., P-type) from the source / drain 82N to be formed (e.g., N-type), the isolation between the source / drain 82N to be formed and the substrate 110 and / or the fin 32 can be high enough so that the bottom isolation layer 800 can be omitted in the third device region 10C. Another reason for not forming the bottom isolation layer 800 in the third device region 10C may be the difference in strain adjustment selection between the 3-piece device in the first device region 10A and the 2-piece device in the third device region 10C. In some embodiments, when the implantation region 110CP exists in the third device region 10C, the bottom isolation layer 800 can be formed in the third device region 10C on the second semiconductor layer 110D, which can increase the isolation between the source / drain 82N to be formed and the substrate 110 and / or the fin 32.

[0110] exist Fig. 22 In the embodiment, after forming the bottom isolation layer 800, an N-type source / drain 82N is formed, which may be similar to the reference in most aspects. Fig. 20 The described embodiment is similar except that the Fig. 22 The source / drain 82N in the third device region 10C in FIG. 10A may be formed to directly contact the second semiconductor layer 110D and to be formed outside over the implantation region 110CP.

[0111] In the formation of Fig. 22 After the N-type source / drain 82N depicted in FIG. 1 , reference Fig. 12A and Fig. 12B The operations are described to form source / drain contacts 120 and replacement gate 200 .

[0112] Fig.23A and Fig. 23B The device 10 having the isolation structure 110B, the isolation structure 110E, the second semiconductor layer 110D and the implantation region 110C is depicted. For example, reference may be implemented 7A to 8B The operations described above are performed to form layer 110BL. Then, reference Fig. 9A , Fig. 9B and Fig.14 or Fig.15 The operations described above are performed to form the first semiconductor layer 110A and the implantation region 110C. Then, the second semiconductor layer 110D may be formed as described in reference Fig.16 Then, the layer 110BL can be patterned to form isolation structures 110B, 110E, similar to reference Fig.17As described above. Since they are formed from the same layer 110BL, the isolation structures 110B and 110E may be a single, continuous structure. In such an embodiment, the isolation structure including the isolation structures 110B and 110E may extend to a depth below the implant region 110C, so that the side of the implant region 110C is in direct contact with the side of the isolation structure 110B and / or the side of the isolation structure 110E. Fig. 23B As depicted in , the side surfaces of the isolation structures 110B, 110E may be in direct contact with the first semiconductor layer 110A, the implantation region 110C, the second semiconductor layer 110D, the fin spacer 41F, and the isolation region 36 .

[0113] Embodiments may provide advantages. For n-type and p-type FETs, the source / drain 82N, 82P may be effectively isolated from the substrate 110 and / or the fin 32 while maintaining an improved strain effect on the PFET. Isolation structures 110B, 110E are positioned between the substrate 110 and / or the fin 32 and the undoped semiconductor layer 110A to isolate the source / drain 82N, 82P and the semiconductor layer 110A from the adjacent substrate 110 while maintaining the surface of the undoped semiconductor layer 110A exposed for PFET source / drain epitaxial growth to improve strain behavior. Body leakage and well isolation leakage may be effectively suppressed by the isolation structures 110B, 110E. The effective capacitance Ceff may be further reduced by including bottom implant regions 110C, 110CN, 110CP having anti-dopants therein.

[0114] According to at least one embodiment, a device includes: a substrate having a semiconductor fin; a semiconductor channel stack located on the substrate and positioned above the fin; a gate structure wrapping the semiconductor channel; a source / drain adjacent to the semiconductor channel; an internal spacer positioned between the semiconductor channel stack and the fin; an undoped semiconductor layer vertically adjacent to the source / drain and laterally adjacent to the fin; and an isolation structure laterally surrounding the undoped semiconductor layer, the isolation structure being located between the source / drain and the internal spacer.

[0115] According to at least one embodiment, the method includes: forming a semiconductor nanostructure layer stack above a substrate; forming a semiconductor nanostructure stack by forming a source / drain opening through the semiconductor nanostructure layer stack; forming a dielectric layer on a surface exposed by the source / drain opening; forming a first semiconductor layer on the dielectric layer in the source / drain opening; forming an isolation structure by removing a portion of the dielectric layer exposed by the first semiconductor layer; and forming a source / drain adjacent to the semiconductor nanostructure stack on the first semiconductor layer.

[0116] According to at least one embodiment, the method includes: forming a nanostructure stack above a substrate by forming a source / drain opening; forming a first semiconductor layer in the source / drain opening; forming an isolation layer in the source / drain opening on the first semiconductor layer; forming the isolation layer by thinning the isolation layer, the isolation layer exposing the upper surface of the first semiconductor layer; forming an injection region including a first dopant of a first type by directing the first dopant onto the upper surface of the first semiconductor layer; forming a second semiconductor layer on the injection region; forming an isolation structure by removing a portion of the isolation layer exposed by the second semiconductor layer; and forming a source / drain on the second semiconductor layer, the source / drain being a second type different from the first type.

[0117] Some embodiments of the present application provide a semiconductor device, including: a substrate having a semiconductor fin; a semiconductor channel stack located on the substrate and positioned above the fin; a gate structure wrapping the semiconductor channel; a source / drain adjacent to the semiconductor channel; an internal spacer positioned between the semiconductor channel stack and the fin; an undoped semiconductor layer vertically adjacent to the source / drain and laterally adjacent to the fin; and an isolation structure laterally surrounding the undoped semiconductor layer, the isolation structure being located between the source / drain and the internal spacer.

[0118] In some embodiments, the isolation structure has a thickness in the range of about 1 nanometer to about 3 nanometers. In some embodiments, the isolation structure is in direct contact with the source / drain. In some embodiments, the semiconductor device further comprises: a bottom isolation layer, the isolation structure being separated from the source / drain by the bottom isolation layer. In some embodiments, the semiconductor device further comprises: an implantation region between the undoped semiconductor layer and the source / drain, the first type of dopant substance in the implantation region being opposite to the second type of the source / drain. In some embodiments, the semiconductor device further comprises: a second semiconductor layer between the implantation region and the source / drain. In some embodiments, the semiconductor device further comprises: a bottom isolation layer between the source / drain and the second semiconductor layer. In some embodiments, the semiconductor device further comprises: a second semiconductor channel stack offset relative to the semiconductor channel stack; a second source / drain adjacent to the second semiconductor channel stack; and a second implantation region below the second source / drain, the third type of dopant substance in the second implantation region being opposite to the first type of dopant substance in the implantation region. In some embodiments, the semiconductor device further comprises: a third semiconductor layer between the second implantation region and the second source / drain. In some embodiments, the second source / drain is in direct contact with the third semiconductor layer, and the source / drain is isolated from the second semiconductor layer by a bottom isolation layer.

[0119] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a semiconductor nanostructure layer stack above a substrate; forming a semiconductor nanostructure stack by forming a source / drain opening through the semiconductor nanostructure layer stack; forming a dielectric layer on a surface exposed by the source / drain opening; forming a first semiconductor layer on the dielectric layer in the source / drain opening; forming an isolation structure by removing a portion of the dielectric layer exposed by the first semiconductor layer; and forming a source / drain adjacent to the semiconductor nanostructure stack on the first semiconductor layer.

[0120] In some embodiments, the method further comprises forming an exposed portion of the substrate by removing a horizontal portion of the dielectric layer, wherein forming the semiconductor layer comprises growing the semiconductor layer on the exposed portion. In some embodiments, forming a source / drain comprises growing the source / drain directly on the first semiconductor layer. In some embodiments, the method further comprises forming a bottom insulator on the first semiconductor layer, wherein forming the source / drain comprises growing the source / drain from the semiconductor nanostructure stack without substantially growing the source / drain from the first semiconductor layer. In some embodiments, the method further comprises: forming a second semiconductor nanostructure stack offset relative to the first semiconductor nanostructure stack by forming a second source / drain opening in the nanostructure layer stack; and during the formation of the first semiconductor layer, forming a second semiconductor layer having a side directly in contact with a fin over which the second semiconductor nanostructure stack is positioned.

[0121] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a nanostructure stack above a substrate by forming a source / drain opening; forming a first semiconductor layer in the source / drain opening; forming an isolation layer in the source / drain opening on the first semiconductor layer; forming an isolation layer by thinning the isolation layer, wherein the forming of the isolation layer exposes the upper surface of the first semiconductor layer; forming an injection region including a first dopant of a first type by directing the first dopant onto the upper surface of the first semiconductor layer; forming a second semiconductor layer on the injection region; forming an isolation structure by removing a portion of the isolation layer exposed by the second semiconductor layer; and forming a source / drain on the second semiconductor layer, wherein the source / drain is a second type different from the first type.

[0122] In some embodiments, the forming of the second semiconductor layer includes forming the second semiconductor layer to a level above at least one nanostructure of the nanostructure stack. In some embodiments, the forming of the source / drain includes growing the source / drain directly from the second semiconductor layer. In some embodiments, the method further includes: forming a second nanostructure stack by forming a second source / drain opening; forming a second implantation region in the second source / drain opening, the second implantation region including the first dopant of the first type; forming a third semiconductor layer on the second implantation region; forming a bottom insulator on the third semiconductor layer; and forming a second source / drain on the bottom insulator, the second source / drain being of the first type. In some embodiments, the method further includes: forming a second nanostructure stack by forming a second source / drain opening; forming a second implantation region in the second source / drain opening, the second implantation region including the second dopant of the second type; forming a third semiconductor layer on the second implantation region; and forming a second source / drain directly from the third semiconductor layer, the second source / drain being of the first type.

[0123] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate having semiconductor fins; a semiconductor channel stack on the substrate and positioned above the fin; A gate structure wrapping the semiconductor channel; a source / drain adjacent to the semiconductor channel; an internal spacer positioned between the semiconductor channel stack and the fin; an undoped semiconductor layer vertically adjacent to the source / drain and laterally adjacent to the fin; as well as An isolation structure laterally surrounds the undoped semiconductor layer, and the isolation structure is located between the source / drain and the inner spacer.

2. The semiconductor device according to claim 1, wherein The isolation structure has a thickness in a range from about 1 nanometer to about 3 nanometers.

3. The semiconductor device according to claim 1, wherein The isolation structure is in direct contact with the source / drain.

4. The semiconductor device according to claim 1, further comprising: A bottom isolation layer, wherein the isolation structure is separated from the source / drain by the bottom isolation layer.

5. The semiconductor device according to claim 1, further comprising: An implantation region is located between the undoped semiconductor layer and the source / drain, wherein a first type of dopant material in the implantation region is opposite to a second type of dopant material in the source / drain.

6. The semiconductor device according to claim 5, further comprising: The second semiconductor layer is located between the implantation region and the source / drain.

7. The semiconductor device according to claim 6, further comprising: A bottom isolation layer is located between the source / drain and the second semiconductor layer.

8. The semiconductor device according to claim 1, further comprising: a second semiconductor channel stack offset relative to the semiconductor channel stack; a second source / drain adjacent to the second semiconductor channel stack; as well as A second implantation region is located below the second source / drain, and a third type of dopant material in the second implantation region is opposite to the first type of dopant material in the implantation region.

9. A method of forming a semiconductor device, comprising: forming a semiconductor nanostructure layer stack over a substrate; forming a semiconductor nanostructure stack by forming source / drain openings through the semiconductor nanostructure layer stack; forming a dielectric layer on the surface exposed by the source / drain openings; forming a first semiconductor layer on the dielectric layer in the source / drain openings; forming an isolation structure by removing a portion of the dielectric layer exposed by the first semiconductor layer; as well as A source / drain is formed on the first semiconductor layer adjacent to the semiconductor nanostructure stack.

10. A method of forming a semiconductor device, comprising: forming a nanostructure stack over the substrate by forming source / drain openings; forming a first semiconductor layer in the source / drain opening; forming an isolation layer in the source / drain opening on the first semiconductor layer; forming an isolation layer by thinning the isolation layer, wherein the forming of the isolation layer exposes an upper surface of the first semiconductor layer; forming an implant region including a first dopant of a first type by directing the first dopant onto the upper surface of the first semiconductor layer; forming a second semiconductor layer on the implantation region; forming an isolation structure by removing a portion of the isolation layer exposed by the second semiconductor layer; as well as A source / drain is formed on the second semiconductor layer, the source / drain being of a second type different from the first type.

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