Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. An example semiconductor device includes a substrate including an active pattern; a channel pattern including a semiconductor pattern; a source / drain pattern connected to the semiconductor pattern; an inner gate electrode between two adjacent semiconductor patterns; an inner gate dielectric layer; and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer includes an upper dielectric layer, a lower dielectric layer, and an inner spacer. A first thickness of the inner spacer is greater than a second thickness of the upper dielectric layer or the lower dielectric layer. The first thickness is greater than a third thickness of the inner high-k dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, including semiconductor devices having improved reliability and improved electrical characteristics, and methods of manufacturing the same. Background Art

[0002] Semiconductor devices include integrated circuits, which include metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices gradually decrease, the size of MOSFETs is increasingly scaled down. The scaled down of MOSFETs may degrade the operating characteristics of semiconductor devices. Therefore, various studies have been conducted to develop methods for manufacturing semiconductor devices with excellent performance while overcoming the limitations caused by the high integration of semiconductor devices. Summary of the invention

[0003] In some implementations, a semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns stacked vertically and spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; an inner gate electrode between adjacent first and second semiconductor patterns in the plurality of semiconductor patterns; an inner gate dielectric layer between the inner gate electrode and the plurality of semiconductor patterns; and an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer. The inner gate dielectric layer may include: an upper dielectric layer between the inner gate electrode and the second semiconductor pattern; a lower dielectric layer between the inner gate electrode and the first semiconductor pattern; and an inner spacer between the inner gate electrode and the source / drain pattern. The first thickness of the inner spacer may be greater than the second thickness of the upper dielectric layer or the lower dielectric layer. The first thickness may be greater than the third thickness of the inner high-k dielectric layer.

[0004] In some implementations, a semiconductor device includes: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns stacked vertically and spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode on the plurality of semiconductor patterns, wherein the gate electrode includes an inner gate electrode between adjacent semiconductor patterns in the plurality of semiconductor patterns and an outer gate electrode on the uppermost one of the plurality of semiconductor patterns; and an inner spacer between the inner gate electrode and the source / drain pattern. Each of the plurality of semiconductor patterns may have a first lattice constant. The source / drain pattern may have a second lattice constant. The inner spacer may have a third lattice constant. The second lattice constant may be the same as the first lattice constant and greater than the third lattice constant.

[0005] In some implementations, a semiconductor device includes: a substrate including a first region, a second region, a third region, and a fourth region; a plurality of first semiconductor patterns vertically stacked and spaced apart from each other on the first region; a plurality of second semiconductor patterns vertically stacked and spaced apart from each other on the second region; a plurality of third semiconductor patterns vertically stacked and spaced apart from each other on the third region; a plurality of fourth semiconductor patterns vertically stacked and spaced apart from each other on the fourth region; a first inner electrode between the first semiconductor patterns; a second inner electrode between the second semiconductor patterns; a third inner electrode between the third semiconductor patterns; a fourth inner electrode between the fourth semiconductor patterns; a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a fourth high-k dielectric layer, respectively on the first inner electrode, the second inner electrode, the third inner electrode, and the fourth inner electrode; and a first inner spacer on a sidewall of at least one of the first high-k dielectric layer, the second high-k dielectric layer, the third high-k dielectric layer, and the fourth high-k dielectric layer. The first width of the first semiconductor pattern may be less than the second width of the second semiconductor pattern. The thickness of the first high-k dielectric layer may be less than the thickness of the third high-k dielectric layer.

[0006] In some implementations, a method for manufacturing a semiconductor device includes: forming a stack pattern on a substrate, the stack pattern including an active layer and a sacrificial layer alternately stacked; forming a sacrificial pattern extending in a first direction on the stack pattern; etching the stack pattern using the sacrificial pattern as a mask to form a recess in the stack pattern, wherein the active layer includes a plurality of semiconductor patterns exposed by the recess; forming a source / drain pattern in the recess; removing the sacrificial pattern and the sacrificial layer to expose the plurality of semiconductor patterns; forming a gate dielectric layer on the exposed plurality of semiconductor patterns; and forming a gate electrode on the gate dielectric layer. The gate dielectric layer may include an inner gate dielectric layer adjacent to an inner gate electrode of the gate electrode and an outer gate dielectric layer adjacent to an outer gate electrode of the gate electrode. The inner gate dielectric layer may include: an upper dielectric layer between the inner gate electrode and a second one of the plurality of semiconductor patterns; a lower dielectric layer between the inner gate electrode and a first one of the plurality of semiconductor patterns; and an inner spacer between the inner gate electrode and the source / drain pattern. The first thickness of the inner spacer may be greater than the second thickness of the upper dielectric layer or the lower dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 , Figure 2 and Figure 3 A conceptual diagram of a logic unit showing an example of a semiconductor device is shown.

[0008] Figure 4 A plan view showing an example of a semiconductor device is shown.

[0009] Figure 5A , Figure 5B , Figure 5C and Figure 5D Shown along Figure 4 Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'.

[0010] Fig. 6A Show Display Figure 5A An example enlarged view of portion M.

[0011] Figure 6B Show Display Fig. 6A An example enlarged view of section N.

[0012] Fig. 7A and Fig. 8A A simplified plan view partially showing an example of a semiconductor device is shown.

[0013] Figure 7B Shown along Fig. 7A Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'.

[0014] Figure 7C Shown along Fig. 7A Example cross-sectional views taken along lines EE', F-F', G-G' and H-H'.

[0015] Figure 8B Shown along Fig. 8A Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'.

[0016] Figure 8C Shown along Fig. 8A Example cross-sectional views taken along lines EE', F-F', G-G' and H-H'.

[0017] 9A to 14D A cross-sectional view showing an example of a method of manufacturing a semiconductor device is shown.

[0018] Fig.15 , Fig.16 , Fig.17 and Fig.18 Shown display formation Fig.13A An enlarged view of an example of the method of section M.

[0019] Fig.19 , Fig. 20 , Fig.21 and Fig. 22 Shown display formation Fig.13A An enlarged view of another example of the method of portion M. DETAILED DESCRIPTION

[0020] Figure 1 , Figure 2 and Figure 3 A conceptual diagram of a logic unit showing an example of a semiconductor device is shown.

[0021] Reference Figure 1 , providing a single height cell SHC. For example, the substrate 100 is provided with a first power line M1_R1 and a second power line M1_R2 thereon. The first power line M1_R1 is a path for providing a source voltage (VSS) (e.g., a ground voltage). The second power line M1_R2 is a path for providing a drain voltage (VDD) (e.g., a power supply voltage).

[0022] The single height cell SHC may be defined between the first power line M1_R1 and the second power line M1_R2. The single height cell SHC may include a first active area AR1 and a second active area AR2. One of the first active area AR1 and the second active area AR2 may be a PMOSFET area, and the other of the first active area AR1 and the second active area AR2 may be an NMOSFET area. For example, the single height cell SHC may have a complementary metal oxide semiconductor (CMOS) structure provided between the first power line M1_R1 and the second power line M1_R2. For example, the first active area AR1 may be an NMOSFET area, and the second active area AR2 may be a PMOSFET area.

[0023] Each of the first active area AR1 and the second active area AR2 may have a single width W_SHC in the first direction D1. The first height HE1 may be defined as a length of the single height unit SHC in the first direction D1. The first height HE1 may be substantially the same as a distance (eg, a pitch) between the first power line M1_R1 and the second power line M1_R2.

[0024] The single height cell SHC may constitute a logic unit. In this specification, a logic unit may refer to a logic element that performs a specific function, such as AND, OR, XOR, XNOR, and an inverter. For example, a logic unit may include transistors for constituting a logic element, and may also include wiring lines that connect the transistors to each other.

[0025] Reference Figure 2 , providing a double height cell DHC. For example, the substrate 100 is provided with a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 thereon. The first power line M1_R1 is disposed between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 is a path for providing a source voltage (VSS).

[0026] The double height cell DHC may be defined between the second power line M1_R2 and the third power line M1_R3 The double height cell DHC may include two first active regions AR1 and two second active regions AR2.

[0027] One of the two second active regions AR2 may be adjacent to the second power line M1_R2. The other of the two second active regions AR2 may be adjacent to the third power line M1_R3. The two first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be disposed between the two first active regions AR1.

[0028] The second height HE2 may be defined as the length of the double height unit DHC in the first direction D1. The second height HE2 may be Figure 1 The two first active regions AR1 of the double height cell DHC may be commonly connected to serve as one active region.

[0029] In this concept, Figure 2 The double height cell DHC shown may be defined as a multi-height cell. Although not shown, the multi-height cell may include a triple height cell, the cell height of which is approximately three times the height of the single height cell SHC.

[0030] Reference Figure 3 , the substrate 100 is provided with a first single height cell SHC1, a second single height cell SHC2, and a double height cell DHC arranged in two dimensions thereon. The first single height cell SHC1 is arranged between the first power line M1_R1 and the second power line M1_R2. The second single height cell SHC2 is arranged between the first power line M1_R1 and the third power line M1_R3. The second single height cell SHC2 is adjacent to the first single height cell SHC1 in the first direction D1.

[0031] The double height cell DHC may be disposed between the second power line M1_R2 and the third power line M1_R3 . The double height cell DHC may be adjacent to the first and second single height cells SHC1 and SHC2 in the second direction D2 .

[0032] A partition structure DB may be provided between the first single height cell SHC1 and the double height cell DHC and between the second single height cell SHC2 and the double height cell DHC. The partition structure DB may electrically separate an active region of the double height cell DHC from an active region of each of the first and second single height cells SHC1 and SHC2.

[0033] Figure 4 A plan view showing an example of a semiconductor device is shown. Figure 5A , Figure 5B, Figure 5C and Figure 5D Shown along Figure 4 Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'. Fig. 6A Show Display Figure 5A An example enlarged view of portion M. Figure 6B Show Display Fig. 6A An example enlarged view of part N. Figure 4 and FIG. 5A to FIG. 5D The semiconductor device shown is Figure 1 A specific example of a single height unit SHC is shown.

[0034] Reference Figure 4 and FIG. 5A to FIG. 5D , a single height cell SHC is provided on a substrate 100. The single height cell SHC is provided thereon with a logic transistor included in a logic circuit. The substrate 100 is a compound semiconductor substrate or a semiconductor substrate including silicon, germanium or silicon germanium. For example, the substrate 100 is a silicon substrate.

[0035] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. In some implementations, the first active region AR1 may be an NMOSFET region, and the second active region AR2 may be a PMOSFET region.

[0036] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on an upper portion of the substrate 100. The first active pattern AP1 may be provided on the first active region AR1, and the second active pattern AP2 may be provided on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100.

[0037] A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover any of the first channel pattern CH1 and the second channel pattern CH2 to be discussed below.

[0038] The first channel pattern CH1 may be provided on the first active pattern AP1. The second channel pattern CH2 may be provided on the second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in sequence. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the vertical direction (or the third direction D3).

[0039] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon. In some implementations, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be stacked nanosheets.

[0040] A plurality of first source / drain patterns SD1 may be provided on the first active pattern AP1. A plurality of first recesses RS1 may be formed on the upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be provided in the first recess RS1 accordingly. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. For example, the pair of first source / drain patterns SD1 may be connected by stacking a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. In the implementation shown here, the phrase source / drain pattern may be understood to mean a source terminal pattern or a drain terminal pattern of a transistor.

[0041] A plurality of second source / drain patterns SD2 may be provided on the second active pattern AP2. A plurality of second recesses RS2 may be formed at an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be provided in the second recess RS2 accordingly. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be interposed between a pair of second source / drain patterns SD2. For example, the pair of second source / drain patterns SD2 may be connected by stacking the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0042] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. For example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface higher than a top surface of the third semiconductor pattern SP3. For another example, at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface at substantially the same level as that of the top surface of the third semiconductor pattern SP3.

[0043] In some implementations, the first source / drain pattern SD1 may include a semiconductor element (e.g., Si) that is the same as that of the substrate 100. The second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element (e.g., Si) of the substrate 100. Therefore, the pair of second source / drain patterns SD2 may provide compressive stress to the second channel pattern CH2.

[0044] Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have an uneven embossed shape at a sidewall thereof. For example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile at a sidewall thereof. A sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude toward a first inner gate electrode IGE1, a second inner gate electrode IGE2, and a third inner gate electrode IGE3 of a gate electrode GE to be discussed below. Fig. 6A and Figure 6B , the first source / drain pattern SD1 according to the present concept will be discussed in detail below.

[0045] The gate electrodes GE may be provided on the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may extend in the first direction D1 while crossing the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may vertically overlap the first channel pattern CH1 and the second channel pattern CH2. The gate electrodes GE may be arranged at a first pitch in the second direction D2.

[0046] The gate electrode GE may include a first inner gate electrode IGE1 interposed between the first semiconductor pattern SP1 and the active pattern AP1 or AP2, a second inner gate electrode IGE2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third inner gate electrode IGE3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and an outer gate electrode OGE on the third semiconductor pattern SP3.

[0047] Reference Figure 5DThe gate electrode GE is provided on the top surface TS, the bottom surface BS and the opposite sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the third semiconductor pattern SP3. For example, the transistor is a three-dimensional field effect transistor (e.g., MBCFET or GAAFET), in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0048] On the first active area AR1, an inner spacer may be formed between the first source / drain pattern SD1 and the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE. On the second active area AR2, an inner spacer may be formed between the second source / drain pattern SD2 and the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE. Each of the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE may be spaced apart from the first source / drain pattern SD1 or the second source / drain pattern SD2 via the inner spacer. The inner spacer may prevent leakage current from the gate electrode GE. Referring to FIG. Fig. 6A , the inner spacer according to the present concept will be discussed in detail below.

[0049] Return to reference Figure 4 and FIG. 5A to FIG. 5D , a pair of gate spacers GS are disposed on opposite side walls of the outer gate electrode OGE of the gate electrode GE. The gate spacer GS extends along the gate electrode GE in the first direction D1. The gate spacer GS has a top surface that is higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS is coplanar with the top surface of the first interlayer dielectric layer 110 to be discussed below. In some implementations, the gate spacer GS includes at least one selected from SiCN, SiCON, and SiN. In some implementations, the gate spacer GS includes a multilayer formed of at least two selected from SiCN, SiCON, and SiN.

[0050] Refer again Figure 4 and FIG. 5A to FIG. 5D , a gate capping pattern GP is provided on the gate electrode GE. The gate capping pattern GP extends along the gate electrode GE in the first direction D1. The gate capping pattern GP includes a material having an etching selectivity with respect to a first interlayer dielectric layer 110 and a second interlayer dielectric layer 120 to be discussed below. For example, the gate capping pattern GP includes at least one selected from SiON, SiCN, SiCON, and SiN.

[0051] The gate dielectric layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI may cover the top surface TS, the bottom surface BS, and the opposite sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric layer GI may cover the top surface of the device isolation layer ST under the gate electrode GE. The gate dielectric layer GI may include an inner gate dielectric layer IIL between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3, and may further include an outer gate dielectric layer OIL between the third semiconductor pattern SP3 and the outer gate electrode OGE.

[0052] In some implementations, the gate dielectric layer GI may include a silicon oxide layer or a silicon oxynitride layer. Fig. 6A , a high-k dielectric layer HK is interposed between the gate electrode GE and the gate dielectric layer GI. The high-k dielectric layer HK has a uniform thickness of the inner gate electrodes IGE1, IGE2, and IGE3 surrounding the gate electrode GE. The high-k dielectric layer HK extends from the bottom of the outer gate electrode OGE to the side surface. For example, the gate dielectric layer GI has a stacked structure on the high-k dielectric layer HK.

[0053] The high-k dielectric layer HK may include a high-k dielectric material whose dielectric constant is greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0054] In some implementations, the gate dielectric layer GI may have a structure in which a silicon oxide layer and a high-k dielectric layer HK are stacked. In some implementations, a semiconductor device according to the present concept may include a negative capacitance field effect transistor using a negative capacitor. For example, the gate dielectric layer GI may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0055] The ferroelectric material layer may have a negative capacitance and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series, and when each capacitor has a positive capacitance, the total capacitance may be reduced to be less than the capacitance of each capacitor. Conversely, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance may have a positive capacitance value that increases to be greater than the absolute value of the capacitance of each capacitor.

[0056] When a ferroelectric material layer having negative capacitance is connected in series with a paraelectric material layer having positive capacitance, the total capacitance of the series-connected ferroelectric material layer and the paraelectric material layer can be increased. The increase in total capacitance can be used to allow a transistor including the ferroelectric material layer to have a subthreshold swing of less than about 60 mV / decade at room temperature.

[0057] The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, one or more of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and lead zirconium titanium oxide. For example, the hafnium zirconium oxide may be a material in which the hafnium oxide is doped with zirconium (Zr). For another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0058] The ferroelectric material layer may further include impurities doped therein. For example, the impurities may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of impurities included in the ferroelectric material layer may vary depending on which ferroelectric material is included in the ferroelectric material layer.

[0059] When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include at least one of impurities such as gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0060] When the impurity is aluminum (Al), the ferroelectric material layer may include about 3 to 8 atomic % of aluminum. In the present specification, the ratio of the impurity may be a ratio of the impurity to the sum of hafnium and the impurity.

[0061] When the impurity is silicon (Si), the ferroelectric material layer may include about 2 to about 10 atomic percent of silicon. When the impurity is yttrium (Y), the ferroelectric material layer may include about 2 to about 10 atomic percent of yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may include about 1 to about 7 atomic percent of gadolinium. When the impurity is zirconium (Zr), the ferroelectric material layer may include about 50 to about 80 atomic percent of zirconium.

[0062] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one selected from silicon oxide and high-k metal oxide. The metal oxide included in the paraelectric material layer may include, for example, one or more of hafnium oxide, zirconium oxide, and aluminum oxide, but the present concept is not limited thereto.

[0063] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the hafnium oxide included in the ferroelectric material layer may have a crystal structure different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0064] The ferroelectric material layer may have a thickness that has ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, in a range from about 0.5 nm to about 10 nm, but the present concept is not limited thereto. Since the ferroelectric material has its own critical thickness for exhibiting ferroelectric properties, the thickness of the ferroelectric material layer may depend on the ferroelectric material.

[0065] For example, the gate dielectric layer GI may include a single ferroelectric material layer. For another example, the gate dielectric layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate dielectric layer GI may have a stacked structure in which a plurality of ferroelectric material layers are alternately stacked with a plurality of paraelectric material layers.

[0066] Return to reference Figure 4 and FIG. 5A to FIG. 5D , the gate electrode GE includes a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern is provided on the gate dielectric layer GI and is adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern includes a work function metal that controls the threshold voltage of the transistor. The thickness and composition of the first metal pattern are adjusted to achieve the desired threshold voltage of the transistor. For example, the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3 of the gate electrode GE are formed by the first metal pattern or the work function metal.

[0067] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0068] The second metal pattern may include a metal having a resistance less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer gate electrode OGE of the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern.

[0069] A first interlayer dielectric layer 110 may be provided on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer 110 may be provided thereon with a second interlayer dielectric layer 120 covering the gate capping pattern GP. A third interlayer dielectric layer 130 may be provided on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be provided on the third interlayer dielectric layer 130. For example, the first to fourth interlayer dielectric layers 110 to 140 may include silicon oxide layers.

[0070] The single height cell SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. The first boundary BD1 and the second boundary BD2 may extend in the first direction D1. The single height cell SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2.

[0071] The single height cell SHC may be provided with a pair of partition structures DB on opposite sides thereof, the pair of partition structures being opposite to each other in the second direction D2. For example, the pair of partition structures DB may be provided on the first boundary BD1 and the second boundary BD2 of the single height cell SHC, respectively. The partition structure DB may extend in the first direction D1 parallel to the gate electrode GE. The pitch between the partition structure DB and its adjacent gate electrode GE may be the same as the first pitch.

[0072] The separation structure DB may penetrate the first interlayer dielectric layer 110 to extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB may pass through an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The separation structure DB may electrically separate the active region of the single height cell SHC from the active region of another adjacent cell.

[0073] The active contact AC may be provided to penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A pair of active contacts AC may be provided on opposite sides of the gate electrode GE. When viewed in a plan view, the active contact AC may have a bar shape extending in the first direction D1.

[0074] The active contact AC may be a self-aligned contact. For example, the gate capping pattern GP and the gate spacer GS may be used to form the active contact AC in a self-aligned manner. The active contact AC may cover, for example, at least a portion of the sidewall of the gate spacer GS. Although not shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

[0075] A metal semiconductor compound layer SC (such as a silicide layer) may be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern SD2 through the metal semiconductor compound layer SC. For example, the metal semiconductor compound layer SC may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0076] The gate contact GC may be provided to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE. When viewed in a plan view, the gate contact GC may be disposed to overlap the first active area AR1 and the second active area AR2, respectively. For example, the gate contact GC may be provided on the second active pattern AP2 (see FIG. Figure 5B ).

[0077] In some implementations, reference Figure 5B , the active contact AC has an upper portion adjacent to the gate contact GC, and the upper dielectric pattern UIP fills the upper portion of the active contact AC. The upper dielectric pattern UIP has a bottom surface lower than the bottom surface of the gate contact GC. For example, the upper dielectric pattern UIP makes the active contact AC adjacent to the gate contact GC have a top surface lower than the bottom surface of the gate contact GC. Therefore, a short circuit caused by contact between the gate contact GC and its adjacent active contact AC can be prevented.

[0078] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

[0079] The first metal layer M1 may be provided in the third interlayer dielectric layer 130. For example, the first metal layer M1 may include a first power line M1_R1, a second power line M1_R2, and a first wiring line M1_I. The lines M1_R1, M1_R2, and M1_I of the first metal layer M1 may extend in parallel in the second direction D2.

[0080] For example, the first power line M1_R1 and the second power line M1_R2 may be provided on the third boundary BD3 and the fourth boundary BD4 of the single height cell SHC, respectively. The first power line M1_R1 may extend in the second direction D2 along the third boundary BD3. The second power line M1_R2 may extend in the second direction D2 along the fourth boundary BD4.

[0081] The first wiring lines M1_I of the first metal layer M1 may be disposed between the first power line M1_R1 and the second power line M1_R2. The first wiring lines M1_I of the first metal layer M1 may be arranged at a second pitch along the first direction D1. The second pitch may be smaller than the first pitch. Each of the first wiring lines M1_I may have a line width smaller than that of each of the first power line M1_R1 and the second power line M1_R2.

[0082] The first metal layer M1 may further include a first via VI1. The first via VI1 may be provided under the wires M1_R1, M1_R2, and M1_I of the first metal layer M1, respectively. The first via VI1 may electrically connect the active contact AC to the wiring line of the first metal layer M1. The first via VI1 may electrically connect the gate contact GC to the wiring line of the first metal layer M1.

[0083] The specific line of the first metal layer M1 and the first via VI1 thereunder can be formed by respective processes. For example, the specific line of the first metal layer M1 and the first via VI1 thereunder can each be formed by a single damascene process. According to some implementations, a sub-20nm process can be used to manufacture semiconductor devices.

[0084] The second metal layer M2 may be provided in the fourth interlayer dielectric layer 140. The second metal layer M2 may include a plurality of second wiring lines M2_I. The second wiring lines M2_I of the second metal layer M2 may each have a line shape or a bar shape extending in the first direction D1. For example, the second wiring lines M2_I may extend in parallel in the first direction D1.

[0085] The second metal layer M2 may further include a second via VI2, which is provided below the second wiring line M2_I. A specific line of the first metal layer M1 may be electrically connected to a corresponding line of the second metal layer M2 through the second via VI2. For example, the wiring line of the second metal layer M2 and the second via VI2 thereunder may be formed simultaneously in a dual damascene process.

[0086] The first metal layer M1 and the second metal layer M2 may have their wiring lines include the same or different conductive materials. For example, the wiring lines of the first metal layer M1 and the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium and cobalt. Although not shown, other metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer dielectric layer 140. Each stacked metal layer may include a wiring line for wiring between cells.

[0087] Fig. 6A Show Display Figure 5A An example enlarged view of portion M. Figure 6B Show Display Fig. 6A Example enlarged view of section N. Fig. 6A The gate electrode GE, the gate dielectric layer GI, the inner spacer ISP, the high-k dielectric layer HK and the first source / drain pattern SD1 will be discussed in detail below. The gate electrode GE includes a first inner gate electrode IGE1, a second inner gate electrode IGE2, a third inner gate electrode IGE3 and an outer gate electrode OGE.

[0088] The gate dielectric layer GI may include a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a combination thereof. The gate dielectric layer GI may include an inner gate dielectric layer IIL on each of the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3, and may also include an outer gate dielectric layer OIL on the outer gate electrode OGE. The outer gate dielectric layer OIL may be provided on the bottom surface and the side surface of the outer gate electrode OGE. The outer gate dielectric layer OIL may extend to the gate cover pattern (see FIG. 1 ) covering the top surface of the outer gate electrode OGE. Figure 5A GP).

[0089] The inner gate dielectric layer IIL may be provided between the first, second, and third semiconductor patterns SP1, SP2, and SP3 and the first, second, and third inner gate electrodes IGE1, IGE2, and IGE3. For example, the inner gate dielectric layer IIL may surround the first, second, and third inner gate electrodes IGE1, IGE2, and IGE3.

[0090] The inner gate dielectric layer IIL may include an upper dielectric layer IILT between the first inner gate electrode IGE1 and the first semiconductor pattern SP1 , a lower dielectric layer IILB between the first inner gate electrode IGE1 and the first active pattern AP1 , and an inner spacer ISP between the first inner gate electrode IGE1 and the first source / drain pattern SD1 .

[0091] The inner gate dielectric layer IIL may include an upper dielectric layer IILT between the second inner gate electrode IGE2 and the second semiconductor pattern SP2 , a lower dielectric layer IILB between the second inner gate electrode IGE2 and the first semiconductor pattern SP1 , and an inner spacer ISP between the second inner gate electrode IGE2 and the first source / drain pattern SD1 .

[0092] The inner gate dielectric layer IIL may include an upper dielectric layer IILT between the third inner gate electrode IGE3 and the third semiconductor pattern SP3 , a lower dielectric layer IILB between the third inner gate electrode IGE3 and the second semiconductor pattern SP2 , and an inner spacer ISP between the third inner gate electrode IGE3 and the first source / drain pattern SD1 .

[0093] The width WGI of the inner gate dielectric layer IIL in the second direction D2 may be smaller than the width WCH of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the second direction D2. The width WCH of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the second direction D2 may be the same as the width WGI of the first channel pattern (see FIG. Figure 5A The width of CH1) in the second direction D2 is the same.

[0094] The high-k dielectric layer HK may be interposed between the inner gate dielectric layer IIL and the inner gate electrodes IGE1, IGE2, and IGE3 or between the outer gate electrode OGE and the outer gate dielectric layer OIL. The high-k dielectric layer HK may be provided on the inner gate electrodes IGE1, IGE2, and IGE3, and the inner gate dielectric layer IIL may be provided on the high-k dielectric layer HK. The high-k dielectric layer HK may be conformally formed.

[0095] Return to reference Fig. 6A , the inner spacer ISP has a first thickness TH1. The first thickness TH1 is defined as representing a minimum distance between one side surface of the high-k dielectric layer HK and one side surface of the first source / drain pattern SD1. The first thickness TH1 is a distance in the second direction D2.

[0096] The upper dielectric layer IILT or the lower dielectric layer IILB may have a second thickness TH2. The second thickness TH2 may be defined as representing the minimum distance between the top surface of the high-k dielectric layer HK and the bottom surface of one (e.g., SP2) of the upper portion of the adjacent semiconductor patterns (e.g., SP1 and SP2). The high-k dielectric layer HK may have a third thickness TH3. The third thickness TH3 may be defined as representing the minimum distance between the top surface of the lower dielectric layer IILB on the bottom surface of the inner gate electrode (e.g., IGE2) and one (e.g., SP1) of the lower portion of the adjacent semiconductor patterns (e.g., SP1 and SP2). The second thickness TH2 and the third thickness TH3 may each be a distance in the third direction D3.

[0097] The first thickness TH1 may be greater than the second thickness TH2. The first thickness TH1 may be greater than the third thickness TH3. The first thickness TH1 may be greater than the sum of the second thickness TH2 and the third thickness TH3. The third thickness TH3 may be greater than the second thickness TH2. Optionally, the third thickness TH3 may be the same as the second thickness TH2. For example, the first thickness TH1 may be greater than about to about The second thickness TH2 may be in the range of about to about The third thickness TH3 may be in the range of about to about within the range.

[0098] The first source / drain pattern SD1 may include a protrusion, and the protrusion may protrude toward the first, second, and third inner gate electrodes IGE1, IGE2, and IGE3 between the adjacent semiconductor patterns SP1, SP2, and SP3.

[0099] The first source / drain pattern SD1 may have an uneven embossing shape at its sidewall SSF. The sidewall SSF may have a wavy profile. For example, the sidewall SSF of the first source / drain pattern SD1 may protrude toward the first inner gate electrode IGE1, the second inner gate electrode IGE2, and the third inner gate electrode IGE3, and thus may have a wavy profile. The sidewall SSF of the first source / drain pattern SD1 may include a concave portion CCP and a convex portion CVP. The concave portion CCP and the convex portion CVP may be alternately disposed with each other.

[0100] The concave portion CCP may be a portion where a sidewall of one of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 contacts a portion of the sidewall SSF of the first source / drain pattern SD1. The convex portion CVP may be a portion where a sidewall of the inner spacer ISP contacts a portion of the sidewall SSF of the first source / drain pattern SD1. The convex portion CVP may have a curvature smaller than that of the concave portion CCP. Alternatively, the concave portion CCP may have the same curvature as that of the convex portion CVP.

[0101] Reference Fig. 6A and Figure 6B , the inner spacer ISP of the inner gate dielectric layer IIL includes a junction surface BF in contact with the first source / drain pattern SD1. The second semiconductor pattern SP2 includes a junction surface BF in contact with the first source / drain pattern SD1. For example, the junction surface BF is a boundary surface between the inner spacer ISP and the first source / drain pattern SD1 and between the second semiconductor pattern SP2 and the first source / drain pattern SD1.

[0102] like Figure 6B As shown, silicon (Si) atoms in the second semiconductor pattern SP2 are arranged in a specific lattice structure (eg, FCC). The second semiconductor pattern SP2 has a first lattice constant LC1. The first lattice constant LC1 is defined to represent a minimum distance between atoms included in the second semiconductor pattern SP2.

[0103] Silicon (Si) atoms in the first source / drain pattern SD1 may be arranged in a specific lattice structure (eg, FCC). The first source / drain pattern SD1 may have a second lattice constant LC2. The second lattice constant LC2 may be defined to represent a minimum distance between atoms included in the first source / drain pattern SD1.

[0104] Silicon (Si) atoms and oxygen (O) atoms in the interspacer ISP may be arranged in a specific lattice structure. The interspacer ISP may have a third lattice constant LC3. The third lattice constant LC3 may be defined to represent a minimum distance between atoms included in the interspacer ISP.

[0105] Return to reference Fig. 6A and Figure 6B , silicon atoms in the first active pattern AP1 are arranged in a specific lattice structure. The first active pattern AP1 has a fourth lattice constant. The fourth lattice constant is defined to represent a minimum distance between atoms included in the first active pattern AP1.

[0106] The second lattice constant LC2 may be the same as the first lattice constant LC1. The second lattice constant LC2 may be greater than the third lattice constant LC3. The second lattice constant LC2 may be the same as the fourth lattice constant.

[0107] According to the method of manufacturing a semiconductor device described later, the first source / drain pattern SD1 may be formed in the first recess (see FIG. Fig.11A For example, the first recess RS1 may be formed to have a wavy profile, and then the first, second, and third semiconductor patterns SP1, SP2, and SP3 and the first active pattern AP1 may be used as seeds to form the first source / drain pattern SD1.

[0108] When a selective epitaxial growth (SEG) process is performed on the recessed region between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, the first source / drain pattern SD1 may not be grown in a polycrystalline or amorphous form but in a single crystal form. This may be caused by the fact that the first source / drain pattern SD1 is formed according to the lattice structure of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the first active pattern AP1. For example, the first source / drain pattern SD1 may be single crystalline.

[0109] Various implementations will be described below. In the following implementations, references to the above references will be omitted. Figure 4 and FIG. 5A to FIG. 5D , Fig. 6A and Figure 6B The detailed description of the technical features discussed are repeated, and their differences will be discussed in detail. Fig. 7A and Fig. 8A A simplified plan view partially showing an example of a semiconductor device is shown. Figure 7B Shown along Fig. 7A Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'. Figure 7C Shown along Fig. 7A Example cross-sectional views taken along lines EE', F-F', G-G' and H-H'. Figure 8B Shown along Fig. 8A Example cross-sectional views taken along lines A-A', B-B', CC' and D-D'. Figure 8C Shown along Fig. 8A Example cross-sectional views taken along lines EE', F-F', G-G' and H-H'.

[0110] Reference 7A to 7CThe semiconductor device includes first to fourth active patterns NAP1, NAP2, NAP3 and PUP, first to fourth semiconductor pattern structures, first to fourth gate electrodes GE1, GE2, GE3 and GE4, first to fourth gate dielectric layers GI1, GI2, GI3 and GI4, first to fourth high-k dielectric layers HKL1, HKL2, HKL3 and HKL4, and a first source / drain pattern SD1.

[0111] The substrate may include a first region 10, a second region 20, a third region 30, and a fourth region 40. The first to fourth regions 10, 20, 30, and 40 may be NMOSFET regions. N-type three-dimensional field effect transistors (eg, MBCFETs or GAAFETs) may be provided on the first to fourth regions 10, 20, 30, and 40.

[0112] Different elements may be provided on the first to fourth regions 10, 20, 30, and 40. For example, an NMOSFET region of a standard gate short channel element (SG SC) may be formed on the first region 10. An NMOSFET region of a standard gate long channel element (SG LC) may be formed on the second region 20. An NMOSFET region of a thick oxide gate element (EG) may be formed on the third region 30. An NMOSFET region of an SRAM element (SRAM) may be formed on the fourth region 40. For example, a pull-up transistor of the SRAM element (SRAM) may be formed on the fourth region 40.

[0113] The first to fourth active patterns NAP1, NAP2, NAP3, and PUP may protrude from the substrate in the third direction D3. The first to fourth active patterns NAP1, NAP2, NAP3, and PUP may correspond to the first active pattern (see Figure 5A The first to fourth semiconductor pattern structures may be on the first to fourth active patterns NAP1, NAP2, NAP3, and PUP, respectively, and each of the first to fourth semiconductor pattern structures may include a plurality of semiconductor patterns vertically stacked and spaced apart from each other, and the semiconductor pattern may be a nanosheet.

[0114] For example, the first semiconductor pattern structure may include a first nanosheet SP1, a second nanosheet SP2, and a third nanosheet SP3. The second semiconductor pattern structure may include a fourth nanosheet SP4, a fifth nanosheet SP5, and a sixth nanosheet SP6. The third semiconductor pattern structure may include a seventh nanosheet SP7, an eighth nanosheet SP8, and a ninth nanosheet SP9. The fourth semiconductor pattern structure may include a tenth nanosheet SP10, an eleventh nanosheet SP11, and a twelfth nanosheet SP12.

[0115] The first semiconductor pattern structure may have a first width W1. The second semiconductor pattern structure may have a second width W2. The third semiconductor pattern structure may have a third width W3. The fourth semiconductor pattern structure may have a fourth width W4. The first to fourth widths W1, W2, W3, and W4 may each be defined as representing a horizontal distance in the second direction D2. The first width W1, the third width W3, and the fourth width W4 may be the same as each other. The first width W1 may be smaller than the second width W2. For example, the first width W1 may be in a range from about 5 nm to about 20 nm, and the second width W2 may be in a range from about 30 nm to about 300 nm.

[0116] The first gate electrode GE1 may include a first internal electrode IE1, a second internal electrode IE2, and a third internal electrode IE3 interposed between the first active pattern NAP1 and the first nanosheet SP1 and between the first to third nanosheets SP1 to SP3, and may further include a first external electrode OE1 on the third nanosheet SP3. The second gate electrode GE2 may include a fourth internal electrode IE4, a fifth internal electrode IE5, and a sixth internal electrode IE6 interposed between the second active pattern NAP2 and the fourth nanosheet SP4 and between the fourth to sixth nanosheets SP4 to SP6, and may further include a second external electrode OE2 on the sixth nanosheet SP6. The third gate electrode GE3 may include a seventh internal electrode IE7, an eighth internal electrode IE8, and a ninth internal electrode IE9 interposed between the third active pattern NAP3 and the seventh nanosheet SP7 and between the seventh to ninth nanosheets SP9, and may further include a third external electrode OE3 on the ninth nanosheet SP9. The fourth gate electrode GE4 may include tenth, eleventh, and twelfth internal electrodes IE10, IE11, and IE12 interposed between the fourth active pattern PUP and the tenth nanosheet SP10 and between the tenth to twelfth nanosheets SP10 to SP12, and may further include a fourth external electrode OE4 on the twelfth nanosheet SP12.

[0117] The first high-k dielectric layer HKL1 may be provided on the first internal electrode IE1, the second internal electrode IE2, and the third internal electrode IE3, and on the bottom surface and the side surface of the first external electrode OE1. The second high-k dielectric layer HKL2 may be provided on the fourth internal electrode IE4, the fifth internal electrode IE5, and the sixth internal electrode IE6, and on the bottom surface and the side surface of the second external electrode OE2. The third high-k dielectric layer HKL3 may be provided on the seventh internal electrode IE7, the eighth internal electrode IE8, and the ninth internal electrode IE9, and on the bottom surface and the side surface of the third external electrode OE3. The fourth high-k dielectric layer HKL4 may be provided on the tenth internal electrode IE10, the eleventh internal electrode IE11, and the twelfth internal electrode IE12, and on the bottom surface and the side surface of the fourth external electrode OE4.

[0118] The first high-k dielectric layer HKL1 may have a thickness L1 less than a thickness L2 of the third high-k dielectric layer HKL3. For example, the first high-k dielectric layer HKL1 may have a thickness of about 0.2 nm to about 20 nm, and the third high-k dielectric layer HKL3 may have a thickness of about 2.5 nm to about 4.5 nm.

[0119] The first gate dielectric layer GI1, the second gate dielectric layer GI2, the third gate dielectric layer GI3, and the fourth gate dielectric layer GI4 may be provided on the first high-k dielectric layer HKL1, the second high-k dielectric layer HKL2, the third high-k dielectric layer HKL3, and the fourth high-k dielectric layer HKL4, respectively. The first gate dielectric layer GI1 may include a first inner gate dielectric layer IL1 on the first inner electrode IE1, the second inner electrode IE2, and the third inner electrode IE3, and may also include a first outer gate dielectric layer OL1 on the first outer electrode OE1. The second gate dielectric layer GI2 may include a second inner gate dielectric layer IL2 on the fourth inner electrode IE4, the fifth inner electrode IE5, and the sixth inner electrode IE6, and may also include a second outer gate dielectric layer OL2 on the second outer electrode OE2. The third gate dielectric layer GI3 may include a third inner gate dielectric layer IL3 on the seventh inner electrode IE7, the eighth inner electrode IE8, and the ninth inner electrode IE9, and may also include a third outer gate dielectric layer OL3 on the third outer electrode OE3. The fourth gate dielectric layer GI4 may include a fourth inner gate dielectric layer IL4 on the tenth, eleventh, and twelfth internal electrodes IE10, IE11, and IE12, and may further include a fourth outer gate dielectric layer OL4 on the fourth outer electrode OE4.

[0120] For example, the first inner gate dielectric layer IL1 may include a first upper dielectric layer ILT1, a first lower dielectric layer ILB1, and a first inner spacer IP1. The first inner spacer IP1 may be disposed on the sidewall of the first high-k dielectric layer HKL1. The description of the first inner gate dielectric layer IL1 may be similarly applied to the second to fourth inner gate dielectric layers IL2 to IL4.

[0121] Reference FIG. 8A to FIG. 8C The semiconductor device includes fifth to eighth active patterns PAP1, PAP2, PAP3 and PDP, fifth to eighth semiconductor pattern structures, fifth to eighth gate electrodes GE5, GE6, GE7 and GE8, fifth to eighth gate dielectric layers GI5, GI6, GI7 and GI8, fifth to eighth high-k dielectric layers HKL5, HKL6, HKL7 and HKL8, and a second source / drain pattern SD2.

[0122] The substrate may include a fifth region 50, a sixth region 60, a seventh region 70, and an eighth region 80. The fifth to eighth regions 50, 60, 70, and 80 may be PMOSFET regions. A p-type three-dimensional field effect transistor (eg, MBCFET or GAAFET) may be provided on the fifth to eighth regions 50, 60, 70, and 80.

[0123] Different elements may be provided on the fifth to eighth regions 50, 60, 70, and 80. For example, a PMOSFET region of a standard gate short channel element (SG SC) may be formed on the fifth region 50. A PMOSFET region of a standard gate long channel element (SG LC) may be formed on the sixth region 60. A PMOSFET region of a thick oxide gate element (EG) may be formed on the seventh region 70. A PMOSFET region of an SRAM element (SRAM) may be formed on the eighth region 80. For example, a transfer gate transistor or a pull-down transistor of the SRAM element (SRAM) may be formed on the eighth region 80.

[0124] The fifth to eighth active patterns PAP1, PAP2, PAP3, and PDP may protrude from the substrate in the third direction D3. The fifth to eighth active patterns PAP1, PAP2, PAP3, and PDP may correspond to the second active patterns (see Figure 5B The fifth to eighth semiconductor pattern structures may be on the fifth to eighth active patterns PAP1, PAP2, PAP3 and PDP, respectively, each of the fifth to eighth semiconductor pattern structures may include a plurality of semiconductor patterns vertically stacked and spaced apart from each other, and the semiconductor pattern may be a nanosheet.

[0125] For example, the fifth semiconductor pattern structure may include a thirteenth nanosheet SP13, a fourteenth nanosheet SP14, and a fifteenth nanosheet SP15. The sixth semiconductor pattern structure may include a sixteenth nanosheet SP16, a seventeenth nanosheet SP17, and an eighteenth nanosheet SP18. The seventh semiconductor pattern structure may include a nineteenth nanosheet SP19, a twentieth nanosheet SP20, and a twenty-first nanosheet SP21. The eighth semiconductor pattern structure may include a twenty-second nanosheet SP22, a twenty-third nanosheet SP23, and a twenty-fourth nanosheet SP24.

[0126] The fifth semiconductor pattern structure may have a fifth width W5. The sixth semiconductor pattern structure may have a sixth width W6. The seventh semiconductor pattern structure may have a seventh width W7. The eighth semiconductor pattern structure may have an eighth width W8. The fifth to eighth widths W5, W6, W7, and W8 may each be defined to represent a horizontal distance in the second direction D2. The fifth width W5, the seventh width W7, and the eighth width W8 may be substantially the same as each other. The fifth width W5 may be smaller than the sixth width W6. For example, the fifth width W5 may be in a range from about 5 nm to about 20 nm, and the sixth width W6 may be in a range from about 30 nm to about 300 nm.

[0127] The fifth gate electrode GE5 may include a thirteenth internal electrode IE13, a fourteenth internal electrode IE14, and a fifteenth internal electrode IE15 interposed between the fifth active pattern PAP1 and the thirteenth nanosheet SP13 and between the thirteenth to fifteenth nanosheets SP15, and may further include a fifth external electrode OE5 on the fifteenth nanosheet SP15. The sixth gate electrode GE6 may include a sixteenth internal electrode IE16, a seventeenth internal electrode IE17, and an eighteenth internal electrode IE18 interposed between the sixth active pattern PAP2 and the sixteenth nanosheet SP16 and between the sixteenth to eighteenth nanosheets SP16 SP18, and may further include a sixth external electrode OE6 on the eighteenth nanosheet SP18. The seventh gate electrode GE7 may include a nineteenth internal electrode IE19, a twentieth internal electrode IE20, and a twenty-first internal electrode IE21 interposed between the seventh active pattern PAP3 and the nineteenth nanosheet SP19 and between the nineteenth to twenty-first nanosheets SP19 and SP21, and may further include a seventh external electrode OE7 on the twenty-first nanosheet SP21. The eighth gate electrode GE8 may include a twenty-second internal electrode IE22, a twenty-third internal electrode IE23, and a twenty-fourth internal electrode IE24 interposed between the eighth active pattern PDP and the twenty-second nanosheet SP22 and between the twenty-second to twenty-fourth nanosheets SP24, and may further include an eighth external electrode OE8 on the twenty-fourth nanosheet SP24.

[0128] A fifth high-k dielectric layer HKL5 may be provided on the thirteenth internal electrode IE13, the fourteenth internal electrode IE14, and the fifteenth internal electrode IE15, and on the bottom surface and the side surface of the fifth external electrode OE5. A sixth high-k dielectric layer HKL6 may be provided on the sixteenth internal electrode IE16, the seventeenth internal electrode IE17, and the eighteenth internal electrode IE18, and on the bottom surface and the side surface of the sixth external electrode OE6. A seventh high-k dielectric layer HKL7 may be provided on the nineteenth internal electrode IE19, the twentieth internal electrode IE20, and the twenty-first internal electrode IE21, and on the bottom surface and the side surface of the seventh external electrode OE7. An eighth high-k dielectric layer HKL8 may be provided on the twenty-second internal electrode IE22, the twenty-third internal electrode IE23, and the twenty-fourth internal electrode IE24, and on the bottom surface and the side surface of the eighth external electrode OE8.

[0129] The fifth high-k dielectric layer HKL5 may have a thickness L3 less than a thickness L4 of the seventh high-k dielectric layer HKL7. For example, the fifth high-k dielectric layer HKL5 may have a thickness of about 0.2 nm to about 20 nm, and the seventh high-k dielectric layer HKL7 may have a thickness of about 2.5 nm to about 4.5 nm.

[0130] The fifth to eighth gate dielectric layers GI5, GI6, GI7, and GI8 may be provided on the fifth to eighth high-k dielectric layers HKL5, HKL6, HKL7, and HKL8, respectively. The fifth gate dielectric layer GI5 may include a fifth inner gate dielectric layer IL5 on the thirteenth inner electrode IE13, the fourteenth inner electrode IE14, and the fifteenth inner electrode IE15, and may also include a fifth outer gate dielectric layer OL5 on the fifth outer electrode OE5. The sixth gate dielectric layer GI6 may include a sixth inner gate dielectric layer IL6 on the sixteenth inner electrode IE16, the seventeenth inner electrode IE17, and the eighteenth inner electrode IE18, and may also include a sixth outer gate dielectric layer OL6 on the sixth outer electrode OE6. The seventh gate dielectric layer GI7 may include a seventh inner gate dielectric layer IL7 on the nineteenth inner electrode IE19, the twentieth inner electrode IE20, and the twenty-first inner electrode IE21, and may also include a seventh outer gate dielectric layer OL7 on the seventh outer electrode OE7. The eighth gate dielectric layer GI8 may include an eighth inner gate dielectric layer IL8 on the twenty-second, twenty-third, and twenty-fourth internal electrodes IE22, IE23, and IE24, and may further include an eighth outer gate dielectric layer OL8 on the eighth outer electrode OE8.

[0131] For example, the fifth inner gate dielectric layer IL5 may include a second upper dielectric layer ILT3, a second lower dielectric layer ILB3, and a second inner spacer IP3. The second inner spacer IP3 may be disposed on the sidewall of the fifth high-k dielectric layer HKL5. The description of the fifth inner gate dielectric layer IL5 may be similarly applied to the sixth to eighth inner gate dielectric layers IL6 to IL8.

[0132] The first to eighth high-k dielectric layers HKL1 to HKL8 may include, for example, at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0133] With reference to Tables 1 and 2 below, semiconductor devices according to some implementations will be described below. Table 1 lists the presence or absence of inner spacers on NMOSFET regions in each of a standard gate short channel component (SG SC), a standard gate long channel component (SG LC), a thick oxide gate component (EG), and an SRAM component (SRAM). Table 2 lists the presence or absence of inner spacers on PMOSFET regions in each of a standard gate short channel component (SGSC), a standard gate long channel component (SG LC), a thick oxide gate component (EG), and an SRAM component (SRAM).

[0134] For example, the SRAM element (SRAM) may be a pull-up transistor on the NMOSFET region of Table 1, and may be a pull-down transistor or a transmission gate transistor on the PMOSFET region of Table 2. In Tables 1 and 2, the symbol "○" may indicate that an inner spacer is formed, and the symbol "X" may indicate that an inner spacer is not formed.

[0135] [Table 1]

[0136]

[0137] [Table 2]

[0138]

[0139]

[0140] On the NMOSFET region and the PMOSFET region, by combining the implementation of Table 1 with the implementation of Table 2, an inner spacer may be formed or not formed for each element. For example, 7A to 7C and FIG. 8A to FIG. 8CThe implementation method may be a combination of implementation method 7 in Table 1 and implementation method 23 in Table 2.

[0141] In each of the plurality of elements, the presence or absence of an inner spacer can be implemented to effectively control the capacitance of each of the plurality of elements. For example, based on the presence or absence of an inner spacer in the plurality of elements, a target value of capacitance can be set for each element. Therefore, according to some implementations, the operation of the semiconductor device can be optimized, and the semiconductor device can be improved in electrical characteristics.

[0142] 9A to 14D A cross-sectional view showing an example of a method for manufacturing a semiconductor device is shown. In detail, Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A Shown along Figure 4 A cross-sectional view taken along line AA'. Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B Shown along Figure 4 A cross-sectional view taken along line BB'. Fig. 11C , Fig. 12C , Fig. 13C and Fig. 14C Shown along Figure 4 A cross-sectional view taken along line CC'. Fig. 9B , Fig. 10B , Fig.13D and Fig.14D Shown along Figure 4 A cross-sectional view taken along line D-D'.

[0143] Reference Fig. 9A and Fig. 9B A substrate 100 including a first active region AR1 and a second active region AR2 is provided. Active layers ACL and sacrificial layers SAL are alternately formed on the substrate 100. The active layer ACL includes one of silicon (Si), germanium (Ge) and silicon germanium (SiGe), and the sacrificial layer SAL may include another of silicon (Si), germanium (Ge) and silicon germanium (SiGe).

[0144] The sacrificial layer SAL may include a material having an etching selectivity with respect to the active layer ACL. For example, the active layer ACL may include silicon (Si), and the sacrificial layer SAL may include silicon germanium (SiGe). Each sacrificial layer SAL may have a germanium concentration of about 10 at % to about 30 at %.

[0145] A mask pattern may be formed on each of the first active area AR1 and the second active area AR2 of the substrate 100. The mask pattern may have a line shape or a bar shape extending in the second direction D2.

[0146] A patterning process may be performed in which the mask pattern is used as an etching mask to form trenches TR defining first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the first active region AR1. The second active pattern AP2 may be formed on the second active region AR2.

[0147] The stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. The stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2 during a patterning process.

[0148] A device isolation layer ST may be formed to fill the trench TR. For example, a dielectric layer may be formed on the front surface of the substrate 100 to cover the stack pattern STP and the first and second active patterns AP1 and AP2. The dielectric layer may be recessed until the stack pattern STP is exposed, and thus a device isolation layer ST may be formed.

[0149] The device isolation layer ST may include a dielectric material such as a silicon oxide layer. The stack pattern STP may be exposed upward from the device isolation layer ST. For example, the stack pattern STP may protrude vertically upward from the device isolation layer ST.

[0150] Reference Fig. 10A and Fig. 10B The sacrificial patterns PP are formed on the substrate 100 to cross the stacked patterns STP. Each of the sacrificial patterns PP is formed to have a line shape or a bar shape extending in the first direction D1. The sacrificial patterns PP are arranged at a first pitch along the second direction D2.

[0151] For example, the formation of the sacrificial pattern PP may include forming a sacrificial layer on the front surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask. The sacrificial layer may include polysilicon.

[0152] A pair of gate spacers GS may be formed on opposite sidewalls of each sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer on the front surface of the substrate 100 and anisotropically etching the gate spacer layer. In some implementations, the gate spacer GS may be a multilayer including at least two layers.

[0153] Reference FIG. 11A to FIG. 11C, the first recess RS1 is formed in the stacked pattern STP on the first active pattern AP1. The second recess RS2 is formed in the stacked pattern STP on the second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST is further recessed on the opposite side of each of the first active pattern AP1 and the second active pattern AP2 (see FIG. Fig. 11C ).

[0154] For example, the hard mask pattern MP and the gate spacer GS may be used as an etching mask so that the stack pattern STP on the first active pattern AP1 may be etched to form a first recess RS1. The first recess RS1 may be formed between a pair of sacrificial patterns PP. The sacrificial layer SAL exposed by the first recess RS1 may undergo a selective etching process to form a retracted region IDE on the first active pattern AP1. The retracted region IDE may allow the first recess RS1 to have a wavy inner sidewall.

[0155] The active layer ACL may be formed of first, second, and third semiconductor patterns SP1, SP2, and SP3 sequentially stacked between adjacent first recesses RS1. The first channel pattern CH1 may be composed of first, second, and third semiconductor patterns SP1, SP2, and SP3 between adjacent first recesses RS1.

[0156] Return to reference FIG. 11A to FIG. 11C , the second recess RS2 in the stacked pattern STP on the second active pattern AP2 is formed by a method similar to the method for forming the first recess RS1. The sacrificial layer SAL exposed by the second recess RS2 undergoes a selective etching process to form an indentation area IDE also on the second active pattern AP2. The indentation area IDE enables the second recess RS2 to have a wavy inner sidewall. The second channel pattern CH2 is composed of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between adjacent second recesses RS2.

[0157] Reference FIG. 12A to FIG. 12C , the first source / drain pattern SD1 is correspondingly formed in the first recess RS1. For example, a selective epitaxial growth (SEG) process is performed, in which the inner sidewall of the first recess RS1 is used as a seed layer to form an epitaxial layer filling the first recess RS1. The epitaxial layer grows from the seed crystal or substrate 100 exposed by the first recess RS1 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, the SEG process includes chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0158] In some implementations, the first source / drain pattern SD1 may include the same semiconductor element (e.g., Si) as that of the substrate 100. When forming the first source / drain pattern SD1, impurities (e.g., phosphorus, arsenic, or antimony) may be in-situ implanted to allow the first source / drain pattern SD1 to have n-type conductivity. Alternatively, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1.

[0159] The second source / drain pattern SD2 may be formed in the second recess RS2 accordingly. For example, a selective epitaxial growth (SEG) process may be performed so that the inner sidewall of the second recess RS2 serves as a seed to form the second source / drain pattern SD2.

[0160] In some implementations, the second source / drain pattern SD2 may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. When the second source / drain pattern SD2 is formed, impurities (e.g., boron, gallium, or indium) may be in-situ implanted to allow the second source / drain pattern SD2 to have p-type conductivity. Alternatively, after the second source / drain pattern SD2 is formed, impurities may be implanted into the second source / drain pattern SD2.

[0161] Reference FIG. 13A to FIG. 13D A first interlayer dielectric layer 110 is formed to cover the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer dielectric layer 110 includes a silicon oxide layer.

[0162] The first interlayer dielectric layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer dielectric layer 110 may be planarized using an etch-back or chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP may be completely removed. As a result, the first interlayer dielectric layer 110 may have a top surface coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0163] The exposed sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may form an outer region ORG (see FIG. 1 ) exposing the first channel pattern CH1 and the second channel pattern CH2. Fig.13D ). Removing the sacrificial pattern PP may include performing a wet etching process using an etchant that selectively etches polysilicon.

[0164] The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG (see Fig.13D). For example, an etching process of selectively etching the sacrificial layer SAL may be performed so that only the sacrificial layer SAL may be removed, leaving the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The etching process may have a high etching rate relative to silicon germanium having a relatively high germanium concentration. For example, the etching process may have a high etching rate relative to silicon germanium having a germanium concentration greater than about 10 at %.

[0165] The etching process may remove the sacrificial layer SAL on the first active region AR1 and the second active region AR2. The etching process may be a wet etching process. The etching material used in the etching process may quickly etch the sacrificial layer SAL having a relatively high germanium concentration.

[0166] Return to reference Fig.13D The first inner region IRG1 is formed between the first semiconductor pattern SP1 and one of the first and second active patterns AP1 and AP2, the second inner region IRG2 is formed between the first and second semiconductor patterns SP1 and SP2, and the third inner region IRG3 is formed between the second and third semiconductor patterns SP2 and SP3.

[0167] Return to reference FIG. 13A to FIG. 13D , a gate dielectric layer GI is formed on the exposed first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate dielectric layer GI is formed to surround each of the first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3. The gate dielectric layer GI is formed in each of the first inner region IRG1, second inner region IRG2, and third inner region IRG3. The gate dielectric layer GI is formed in the outer region ORG.

[0168] For example, the gate dielectric layer GI formed in each of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 may correspond to an inner gate dielectric layer (see Fig. 6A The gate dielectric layer GI formed in the outer region ORG may correspond to an outer gate dielectric layer (see Fig. 6A of OIL).

[0169] Figures 15 to 18 Shown display formation Fig.13A An enlarged view of an example of the method of part M. Fig.15 , a selective wet etching process is performed through the outer region ORG formed between the gate spacers GS, thereby removing the sacrificial layer SAL.

[0170] The first inner region IRG1 may be formed between the substrate 100 and the first semiconductor pattern SP1. The second inner region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third inner region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 may each have a width in the second direction D2 that is smaller than a width of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the second direction D2. The outer region ORG may have a width in the second direction D2 that is smaller than a width of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the second direction D2.

[0171] A portion of the first source / drain pattern SD1 may protrude toward each of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3. For example, a portion of the first source / drain pattern SD1 may protrude between the substrate 100 and the first semiconductor pattern SP1, between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and between the second semiconductor pattern SP2 and the third semiconductor pattern SP3. The first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 may each have a concave portion at a side surface thereof. For example, a side surface of each of the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 may have a curved surface having a curvature.

[0172] Reference Fig.16 , a bulk silicon oxide layer is formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 and the outer region ORG. The bulk silicon oxide layer is formed on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The bulk silicon oxide layer includes a first bulk layer BOX1, a second bulk layer BOX2, a third bulk layer BOX3, and a fourth bulk layer BOX4. The first bulk layer BOX1 to the fourth bulk layer BOX4 are formed by performing an atomic layer deposition (ALD) process. The first bulk layer BOX1 to the fourth bulk layer BOX4 include silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, or a combination thereof. For example, the first bulk layer BOX1 to the fourth bulk layer BOX4 are silicon oxide (SiOx) layers.

[0173] The first bulk layer BOX1 may be formed in the first inner region IRG1, the second bulk layer BOX2 may be formed in the second inner region IRG2, the third bulk layer BOX3 may be formed in the third inner region IRG3, and the fourth bulk layer BOX4 may be formed on the outer region ORG.

[0174] Each of the first to fourth bulk layers BOX1 to BOX4 may be conformally formed to have a uniform thickness. Therefore, the first bulk layer BOX1, the second bulk layer BOX2, the third bulk layer BOX3, and the fourth bulk layer BOX4 may include a first seam region IBR1, a second seam region IBR2, a third seam region IBR3, and a fourth seam region OBR, respectively.

[0175] For example, the second bulk layer BOX2 may be conformally formed in the second inner region IRG2 and may include a second seam region IBR2. The second bulk layer BOX2 may have a first length T1 in the second direction D2 and a second length T2 in the third direction D3. The first length T1 may be defined as representing the minimum distance between the side wall of the first source / drain pattern SD1 and the side surface of the second seam region IBR2. The second length T2 may be defined as representing the minimum distance between the top surface of the second seam region IBR2 and the bottom surface of the second semiconductor pattern SP2. The first length T1 and the second length T2 may be the same or different from each other.

[0176] Reference Fig.17 , an etching process is performed on the first bulk layer BOX1 to the fourth bulk layer BOX4. The etching process is a composite process in which a dry etching process and a wet etching process are combined with each other. For example, the etching process is performed in a manner of performing a dry etching process under specific conditions and then completing a wet etching process. Therefore, the etching process partially removes the bulk silicon oxide layer or the first bulk layer BOX1 to the fourth bulk layer BOX4.

[0177] For example, the first bulk layer BOX1, the second bulk layer BOX2, and the third bulk layer BOX3 may undergo an etching process to form an inner gate dielectric layer IIL. The inner gate dielectric layer IIL may include an inner spacer ISP, an upper dielectric layer IILT, and a lower dielectric layer IILB. In the etching process, the inner spacer ISP may be formed to have a first thickness TH1, and the upper dielectric layer IILT or the lower dielectric layer IILB may be formed to have a second thickness TH2. The first thickness TH1 may be greater than the second thickness TH2.

[0178] The fourth bulk layer BOX4 may undergo an etching process to form an outer gate dielectric layer OIL. The outer gate dielectric layer OIL may be formed to have a uniform thickness. For example, an etching process may be performed to form a gate dielectric layer GI including an inner gate dielectric layer IIL and an outer gate dielectric layer OIL.

[0179] Reference Fig.18 , a high-k dielectric layer HK is formed on each of the inner gate dielectric layer IIL and the outer gate dielectric layer OIL. As discussed above, the high-k dielectric layer HK includes a high-k dielectric material whose dielectric constant is greater than the dielectric constant of the silicon oxide layer. For example, the high-k dielectric material includes at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0180] For example, the high-k dielectric layer HK may be formed by performing an atomic layer deposition (ALD) process. The high-k dielectric layer HK may be conformally formed to have a uniform thickness. The high-k dielectric layer HK may be formed to have a third thickness TH3. The first thickness TH1 may be greater than the third thickness TH3. The first thickness TH1 may be greater than the sum of the second thickness TH2 and the third thickness TH3.

[0181] Fig.15 , Fig.18 and Figures 19 to 22 Shown display formation Fig.13A FIG. 1 is an enlarged view of an example of the method of part M depicted in FIG. Figures 19 to 22 Show Fig.16 and Fig.17 An enlarged view of another example showing the formation of Fig.13A Another example of the method of the portion M depicted in FIG. In the following implementation, the above reference will be omitted. Figures 15 to 18 A detailed description of the technical features discussed is repeated, and their differences will be explained in detail.

[0182] Reference Fig.15 , a selective wet etching process is performed through the outer region ORG formed between the gate spacers GS, thereby removing the sacrificial layer SAL. The first inner region IRG1 is formed between the substrate 100 and the first semiconductor pattern SP1. The second inner region IRG2 is formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The third inner region IRG3 is formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3.

[0183] Reference Fig.19, a bulk silicon oxide layer is formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3 and the outer region ORG. The bulk silicon oxide layer is formed on the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The bulk silicon oxide layer includes a first bulk layer BOX1, a second bulk layer BOX2, a third bulk layer BOX3, and a fourth bulk layer BOX4. The first bulk layer BOX1 to the fourth bulk layer BOX4 are formed by performing an atomic layer deposition (ALD) process. The first bulk layer BOX1 to the fourth bulk layer BOX4 include silicon oxide, silicon oxynitride, silicon oxycarbide, silicon nitride, silicon carbon nitride, or a combination thereof. For example, the first bulk layer BOX1 to the fourth bulk layer BOX4 may be a silicon oxide (SiOx) layer.

[0184] The first block layer BOX1 may be formed in the first inner region IRG1, and the second block layer BOX2 may be formed in the second inner region IRG2. The third block layer BOX3 may be formed in the third inner region IRG3, and the fourth block layer BOX4 may be formed on the outer region ORG. The first block layer BOX1, the second block layer BOX2, the third block layer BOX3, and the fourth block layer BOX4 may include a first seam region IBR1, a second seam region IBR2, a third seam region IBR3, and a fourth seam region OBR, respectively.

[0185] Reference Fig. 20 , an etching process is performed on the first bulk layer BOX1 to the fourth bulk layer BOX4. The etching process is a composite process in which a dry etching process and a wet etching process are combined with each other. The etching process partially removes the bulk silicon oxide layer or the first bulk layer BOX1 to the fourth bulk layer BOX4. For example, the etching process is performed until the surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are exposed.

[0186] The first to fourth bulk layers BOX1 to BOX4 may be subjected to an etching process to completely remove portions of the first to fourth bulk layers BOX1 to BOX4 adjacent to the substrate 100 and the first to third semiconductor patterns SP1 to SP3. For example, portions of the first to fourth bulk layers BOX1 to BOX4 adjacent to the first source / drain pattern SD1 may remain without being removed.

[0187] After the etching process, the inner spacer ISP may be composed of the first to third bulk layers BOX1 to BOX3 remaining on the surface of the first source / drain pattern SD1. The fourth bulk layer BOX4 remaining on the gate spacer GS may be a residual dielectric layer RBOX having a tail on the third semiconductor pattern SP3. The tail may be a portion extending on the exposed third semiconductor pattern SP3.

[0188] After the etching process, the first seam region IBR1, the second seam region IBR2, the third seam region IBR3, and the fourth seam region OBR may be extended near the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Therefore, the extended first seam region IBR1 may be the fifth seam region IBR1'. The extended second seam region IBR2 may be the sixth seam region IBR2'. The extended third seam region IBR3 may be the seventh seam region IBR3'. The extended fourth seam region OBR may be the eighth seam region OBR'.

[0189] Reference Fig.21 , the fifth to eighth seam regions IBR1', IBR2', IBR3' and OBR' undergo the above-mentioned deposition process. An initial outer dielectric layer POIL and an initial inner dielectric layer PIIL are additionally deposited in the fifth to eighth seam regions IBR1', IBR2', IBR3' and OBR'. The initial outer dielectric layer POIL extends from the exposed third semiconductor pattern SP3 to the residual dielectric layer RBOX. The initial inner dielectric layer PIIL covers the substrate 100 and the first semiconductor pattern SP1, the second semiconductor pattern SP2 and the third semiconductor pattern SP3 and the inner spacer ISP.

[0190] Reference Fig. 22 , the initial outer dielectric layer POIL and the initial inner dielectric layer PIIL are subjected to the above-mentioned etching process. The etching process is a composite process in which a dry etching process and a wet etching process are combined with each other. The etching process is performed to partially remove the initial outer dielectric layer POIL and the initial inner dielectric layer PIIL. After partially removing the initial outer dielectric layer POIL and the initial inner dielectric layer PIIL, the remaining layers are the upper dielectric layer IILT, the lower dielectric layer IILB, the inner spacer ISP and the outer gate dielectric layer OIL.

[0191] For example, the upper dielectric layer IILT and the lower dielectric layer IILB may be formed on the substrate 100 and the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 in the fifth seam region IBR1', the sixth seam region IBR2', and the seventh seam region IBR3'. The upper dielectric layer IILT and the lower dielectric layer IILB may include silicon oxide, silicon oxynitride, silicon oxycarbide, silicon nitride, silicon carbon nitride, or a combination thereof. For example, the inner spacer ISP, the upper dielectric layer IILT, and the lower dielectric layer IILB may include the same material. For another example, the inner spacer ISP, the upper dielectric layer IILT, and the lower dielectric layer IILB may include materials different from each other.

[0192] According to this implementation, Fig.16and Fig.17 Depending on the implementation manner, the inner spacer ISP, the upper dielectric layer IILT, and the lower dielectric layer IILB may not be formed at the same time.

[0193] The deposition process and the etching process may constitute a cyclic process. According to some embodiments, as described above with reference to Fig.15 and Figures 19 to 22 As described above, the cycle process may be performed at least twice. The cycle process may be repeatedly performed to allow the inner spacer ISP to have a target thickness.

[0194] The inner gate dielectric layer IIL may be composed of an inner spacer ISP, an upper dielectric layer IILT, and a lower dielectric layer IILB. In the etching process, the inner spacer ISP may be formed to have a first thickness TH1, and the upper dielectric layer IILT or the lower dielectric layer IILB may be formed to have a second thickness TH2. The first thickness TH1 may be greater than the second thickness TH2.

[0195] The outer gate dielectric layer OIL may be composed of a residual dielectric layer RBOX and an initial outer dielectric layer POIL. The outer gate dielectric layer OIL may be formed to have a uniform thickness. For example, an etching process may be performed to form a gate dielectric layer GI including an inner gate dielectric layer IIL and an outer gate dielectric layer OIL.

[0196] Although not shown, according to some implementations, the outer gate dielectric layer OIL may be composed only of the remaining initial outer dielectric layer POIL. For example, the outer gate dielectric layer OIL may be formed only on the exposed third semiconductor pattern SP3. The outer gate dielectric layer OIL may be formed only on the third semiconductor pattern SP3 and may not extend onto the gate spacer GS.

[0197] Reference Fig.18 , a high-k dielectric layer HK is formed on each of the inner gate dielectric layer IIL and the outer gate dielectric layer OIL. As described above, the high-k dielectric layer HK includes a high-k dielectric material whose dielectric constant is greater than the dielectric constant of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0198] For example, the high-k dielectric layer HK may be formed by performing an atomic layer deposition (ALD) process. The high-k dielectric layer HK may be conformally formed to have a uniform thickness. The high-k dielectric layer HK may be formed to have a third thickness TH3. The first thickness TH1 may be greater than the third thickness TH3. The first thickness TH1 may be greater than the sum of the second thickness TH2 and the third thickness TH3.

[0199] Reference FIG. 14A to FIG. 14D , a gate electrode GE is formed on the gate dielectric layer GI. For example, the gate electrode GE is formed on the high-k dielectric layer (see Fig. 6A HK). For example, a high-k dielectric layer HK is formed on the gate dielectric layer GI, and a gate electrode GE is formed on the high-k dielectric layer HK. The gate electrode GE includes a first inner gate electrode IGE1, a second inner gate electrode IGE2, and a third inner gate electrode IGE3 formed in the first inner region IRG1, the second inner region IRG2, and the third inner region IRG3, respectively, and also includes an outer gate electrode OGE formed in the outer region ORG. The gate electrode GE is recessed to have a reduced height. The gate capping pattern GP is formed on the recessed gate electrode GE.

[0200] Return to reference FIG. 5A to FIG. 5D , a second interlayer dielectric layer 120 is formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 includes a silicon oxide layer. An active contact AC is formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 to be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC is formed to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP to be electrically connected to the gate electrode GE.

[0201] The formation of each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed to include a metal layer and a metal nitride layer. The conductive pattern FM may include a metal whose resistance is low.

[0202] The separation structure DB may be formed on the first and second boundaries BD1 and BD2 of the single height cell SHC, respectively. The separation structure DB may extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2. The separation structure DB may include a dielectric material such as a silicon oxide layer or a silicon nitride layer.

[0203] A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. A second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

[0204] In a three-dimensional field effect transistor according to the present concept, the gate dielectric on the side surface of the gate electrode can be used as an inner spacer, so the distance between the source / drain pattern and the inner gate electrode of the gate electrode can be increased. The increase in the distance between the source / drain pattern and the inner gate electrode can reduce the capacitor / gate leakage current. In addition, the stress applied to the channel from the source / drain pattern can be effectively adjusted to increase the mobility of the carriers. For example, since the inner spacer is formed after the source / drain pattern is formed, the semiconductor can be improved in reliability and electrical characteristics.

[0205] In a three-dimensional field effect transistor according to the present concept, in each of the plurality of elements, the presence or absence of an inner spacer can be realized to effectively control the capacitance of each of the plurality of elements. For example, based on the presence or absence of the inner spacer in the plurality of elements, a target value of capacitance can be set for each element to optimize the operation of the semiconductor device. The semiconductor device according to the present concept can therefore be improved in electrical characteristics.

[0206] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented separately in multiple implementations or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations, and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0207] Although the concepts described herein have been described in conjunction with the implementations of the present disclosure shown in the accompanying drawings, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and essential features of the present disclosure. Therefore, the implementations disclosed above should be considered illustrative rather than restrictive.

[0208] This application claims the priority of Korean Patent Application No. 10-2023-0087768 filed on July 6, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns vertically stacked and spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; an inner gate electrode between a first semiconductor pattern and a second semiconductor pattern, wherein the first semiconductor pattern and the second semiconductor pattern are two adjacent semiconductor patterns among the plurality of semiconductor patterns; an inner gate dielectric layer; as well as an inner high-k dielectric layer between the inner gate electrode and the inner gate dielectric layer, The inner gate dielectric layer comprises: an upper dielectric layer between the inner gate electrode and the second semiconductor pattern; a lower dielectric layer between the inner gate electrode and the first semiconductor pattern; and an inner spacer between the inner gate electrode and the source / drain pattern, wherein a first thickness of the inner spacer is greater than a second thickness of the upper dielectric layer or the lower dielectric layer, and The first thickness is greater than a third thickness of the inner high-k dielectric layer. 2 . The semiconductor device according to claim 1 , wherein the first thickness is greater than a sum of the second thickness and the third thickness.

3. The semiconductor device according to claim 1, wherein the first thickness is to within the range.

4. The semiconductor device according to claim 1, wherein The second thickness is to within the scope of The third thickness is to within the range. The semiconductor device according to claim 4 , wherein the third thickness is greater than the second thickness. The semiconductor device according to claim 4 , wherein the second thickness and the third thickness are equal.

7. The semiconductor device according to claim 1 , wherein the sidewall of the source / drain pattern comprises a concave portion and a convex portion, wherein the concave portions and the convex portions are arranged alternately with each other, and The side wall has a wavy profile. 8 . The semiconductor device according to claim 7 , wherein the convex portion is a portion where a sidewall of the inner spacer contacts the sidewall of the source / drain pattern. 9 . The semiconductor device of claim 7 , wherein the concave portion is a portion where a sidewall of each of the plurality of semiconductor patterns contacts the sidewall of the source / drain pattern. 10 . The semiconductor device according to claim 7 , wherein a curvature of the convex portion is equal to or smaller than a curvature of the concave portion. 11 . The semiconductor device according to claim 1 , wherein the inner spacer comprises a silicon oxide layer or a silicon oxynitride layer. 12 . The semiconductor device according to claim 1 , wherein a width of the channel pattern in a first direction is greater than a width of the inner gate dielectric layer in the first direction.

13. The semiconductor device according to claim 1, comprising: an outer gate electrode on an uppermost semiconductor pattern among the plurality of semiconductor patterns; as well as an outer gate dielectric layer, adjacent to the outer gate electrode, The outer gate dielectric layer has a uniform thickness. 14 . The semiconductor device of claim 13 , comprising an outer high-k dielectric layer between the outer gate electrode and the outer gate dielectric layer.

15. A semiconductor device comprising: a substrate including an active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns vertically stacked and spaced apart from each other; a source / drain pattern connected to the plurality of semiconductor patterns; a gate electrode, wherein the gate electrode includes an inner gate electrode between two adjacent semiconductor patterns among the plurality of semiconductor patterns, and includes an outer gate electrode on an uppermost semiconductor pattern among the plurality of semiconductor patterns; as well as an inner spacer, between the inner gate electrode and the source / drain pattern, wherein each of the plurality of semiconductor patterns has a first lattice constant, wherein the source / drain pattern has a second lattice constant, wherein the inner spacer has a third lattice constant, and The second lattice constant is equal to the first lattice constant and greater than the third lattice constant.

16. The semiconductor device according to claim 15, wherein The active pattern has a fourth lattice constant, and The second lattice constant is equal to the fourth lattice constant.

17. The semiconductor device according to claim 15, wherein the source / drain pattern is single crystalline.

18. A semiconductor device comprising: A substrate, comprising a first region, a second region, a third region and a fourth region; a plurality of first semiconductor patterns vertically stacked on the first region and spaced apart from each other; a plurality of second semiconductor patterns vertically stacked on the second region and spaced apart from each other; a plurality of third semiconductor patterns vertically stacked on the third region and spaced apart from each other; a plurality of fourth semiconductor patterns vertically stacked on the fourth region and spaced apart from each other; a first inner electrode between two first semiconductor patterns among the plurality of first semiconductor patterns; a second inner electrode between two second semiconductor patterns among the plurality of second semiconductor patterns; a third inner electrode between two third semiconductor patterns among the plurality of third semiconductor patterns; a fourth inner electrode between two fourth semiconductor patterns among the plurality of fourth semiconductor patterns; a first high-k dielectric layer, a second high-k dielectric layer, a third high-k dielectric layer, and a fourth high-k dielectric layer on the first internal electrode, the second internal electrode, the third internal electrode, and the fourth internal electrode, respectively; and a first inner spacer on a sidewall of at least one of the first high-k dielectric layer, the second high-k dielectric layer, the third high-k dielectric layer, and the fourth high-k dielectric layer, wherein a first width of the first semiconductor pattern is smaller than a second width of the second semiconductor pattern, and The thickness of the first high-k dielectric layer is less than the thickness of the third high-k dielectric layer. 19 . The semiconductor device according to claim 18 , wherein each of the first region, the second region, the third region, and the fourth region is an NMOSFET region.

20. The semiconductor device according to claim 18, wherein the substrate comprises a fifth region, a sixth region, a seventh region, and an eighth region, The semiconductor device comprises: a plurality of fifth semiconductor patterns vertically stacked on the fifth region and spaced apart from each other; a plurality of sixth semiconductor patterns vertically stacked on the sixth region and spaced apart from each other; a plurality of seventh semiconductor patterns vertically stacked on the seventh region and spaced apart from each other; a plurality of eighth semiconductor patterns vertically stacked on the eighth region and spaced apart from each other; a fifth inner electrode between two fifth semiconductor patterns among the plurality of fifth semiconductor patterns; a sixth inner electrode between two sixth semiconductor patterns among the plurality of sixth semiconductor patterns; a seventh inner electrode between two seventh semiconductor patterns among the plurality of seventh semiconductor patterns; an eighth inner electrode between two eighth semiconductor patterns among the plurality of eighth semiconductor patterns; a fifth high-k dielectric layer, a sixth high-k dielectric layer, a seventh high-k dielectric layer, and an eighth high-k dielectric layer on the fifth inner electrode, the sixth inner electrode, the seventh inner electrode, and the eighth inner electrode, respectively; and a second inner spacer on a sidewall of at least one of the fifth high-k dielectric layer, the sixth high-k dielectric layer, the seventh high-k dielectric layer, and the eighth high-k dielectric layer, wherein the third width of the fifth semiconductor pattern is smaller than the fourth width of the sixth semiconductor pattern, and The thickness of the fifth high-k dielectric layer is less than the thickness of the seventh high-k dielectric layer.

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