Protective device with low capacitance and high ESD (Electro-Static Discharge) protection capability and manufacturing method thereof

Abstract

The invention relates to an ESD (Electro-Static Discharge) protection device and a manufacturing method thereof, in particular to a low-capacitance high-ESD protection capability protection device and a manufacturing method thereof, comprising a P-type substrate, an N-epitaxy and a dielectric layer which are sequentially connected from bottom to top; an N + buried layer of which the top is connected with the N-epitaxy is arranged in the middle of the upper surface of the P-type substrate; the middle part of the upper surface of the N-epitaxy is provided with a first P + expansion region, and a first N + expansion region group, a second P + expansion region group and a second N + expansion region which are sequentially distributed from inside to outside; the first N + expansion region group comprises a plurality of first N + expansion regions which are circumferentially and uniformly distributed; the second P + expansion region group comprises a plurality of second P + expansion regions which are uniformly distributed along the circumference; the N-epitaxy is provided with an annular isolation groove penetrating into the P-type substrate; the second N + expansion region is provided with an annular electric connection layer which goes deep into the P-type substrate. An anode and a cathode are arranged on the dielectric layer, the bottom of the anode is connected with the first P + expansion region and the first N + expansion region, and the bottom of the cathode is connected with the second N + expansion region and the second P + expansion region. According to the invention, the ultra-low capacitance value can be realized and the high electrostatic protection capability can be ensured.

Description

Technical Field

[0001] The invention relates to an ESD protection device and a manufacturing method thereof, and in particular to a low-capacitance and high-ESD protection capability protection device and a manufacturing method thereof. Background Art

[0002] With the rapid development of electronic technology, especially the commercial application of USB4.0 technology, the requirements for electrostatic protection products are increasing. Electrostatic discharge (ESD) protection is one of the key technologies to protect electronic devices from electrostatic damage. Traditionally, in order to achieve low capacitance, a lateral silicon-controlled rectifier (SCR) process is usually used.

[0003] However, this process has an obvious trade-off relationship between capacitance and electrostatic protection capability: reducing capacitance is often accompanied by a decrease in electrostatic protection capability; although this conflict can be alleviated to a certain extent through a series of process optimization innovations, the improvement of the electrostatic capability of the lateral SCR structure is still limited due to the limitations of the process itself. Summary of the invention

[0004] The purpose of the present invention is to solve the technical problem that the electrostatic protection capability of the existing silicon-controlled rectifier is often reduced when the capacitance is reduced, and to provide a protection device with low capacitance and high ESD protection capability and a manufacturing method thereof.

[0005] To solve the above technical problems, the technical solutions provided by the present invention are as follows:

[0006] A low capacitance and high ESD protection capability protection device, comprising a P-type substrate, an N-epitaxial layer and a dielectric layer connected sequentially from bottom to top;

[0007] An N+ buried layer whose top is connected to the N- epitaxial layer is provided in the middle of the upper surface of the P-type substrate;

[0008] A first P+ expansion area is provided in the middle of the upper surface of the N- epitaxial portion, and a first N+ expansion area group, a second P+ expansion area group and a second N+ expansion area are sequentially distributed from the inside to the outside; the first N+ expansion area group includes a plurality of first N+ expansion areas uniformly distributed around the circumference; the second P+ expansion area group includes a plurality of second P+ expansion areas uniformly distributed around the circumference;

[0009] The second N+ expansion area, the P-type substrate and the N+ buried layer form a low trigger NPN tube; the first P+ expansion area, the N-epitaxial, the N+ buried layer and the P-type substrate form a low capacitance PNP tube; the first N+ expansion area, the N-epitaxial and the second P+ expansion area form a guide diode;

[0010] The N-epitaxial structure is provided with an annular isolation groove extending deep into the P-type substrate, for electrically isolating the low-capacitance PNP tube and the low-trigger NPN tube;

[0011] A ring-shaped electrical connection layer extending deep into the P-type substrate is provided on the second N+ expansion area;

[0012] An anode and a cathode are arranged on the dielectric layer. The bottom of the anode is connected to the first P+ expansion area and the first N+ expansion area, and the bottom of the cathode is connected to the second N+ expansion area and the second P+ expansion area.

[0013] Furthermore, a first trench region penetrating into the P-type substrate is opened on the N-epitaxial portion, and polysilicon is filled in the first trench region to form an annular isolation groove for electrically isolating the low-capacitance PNP tube and the low-trigger NPN tube.

[0014] Furthermore, the first trench region is filled with silicon dioxide to form an annular isolation trench.

[0015] Furthermore, a second trench region penetrating into the P-type substrate is provided on the second N+ expansion region, and the second trench region is filled with P-type silicon to form an annular electrical connection layer.

[0016] Furthermore, the annular isolation groove includes a first annular isolation groove, a second annular isolation groove, a third annular isolation groove and a fourth annular isolation groove which are co-centered and sequentially distributed from the inside to the outside, wherein:

[0017] The inner sidewall of the first annular isolation groove is connected to the N+ buried layer, and the outer sidewall is connected to the first N+ expansion area;

[0018] The inner sidewall of the second annular isolation groove is connected to the second P+ expansion area, and there is a gap between the outer sidewall and the second N+ expansion area;

[0019] There is a gap between the inner side wall of the third annular isolation groove and the second N+ expansion region;

[0020] There is a gap between the inner side wall of the fourth annular isolation groove and the inner and outer side walls of the third annular isolation groove.

[0021] Furthermore, the annular electrical connection layer includes a first annular electrical connection layer, a second annular electrical connection layer, a third annular electrical connection layer and a fourth annular electrical connection layer which are co-centered and arranged in sequence from the inside to the outside.

[0022] Furthermore, the thickness of the N-epitaxial layer is 5um-12um, and the resistivity thereof is greater than 100Ω·cm.

[0023] Further, the doping material of the second N+ expansion region and the first N+ expansion region is phosphorus;

[0024] The doping material of the first P+ extension region and the second P+ extension region is boron;

[0025] The material of the anode and cathode is aluminum.

[0026] The present invention also provides a method for preparing a protection device with low capacitance and high ESD protection capability, comprising the following steps:

[0027] S1, implanting N-type doping elements into the middle of the upper surface of the P-type substrate to form an N+ buried layer;

[0028] S2, growing a layer of N- epitaxial on the P-type substrate and the N+ buried layer by epitaxial growth technology;

[0029] S3, implanting phosphorus on the N-epitaxial layer to form a second N+ expansion region, the second N+ expansion region, the P-type substrate, and the N+ buried layer form a low trigger NPN transistor;

[0030] S4, implanting boron into the N-epitaxial and annealing at 1000-1150° C. to form a first P+ expansion region and a second P+ expansion region, implanting phosphorus into the N-epitaxial and annealing at 1000-1150° C. to form a first N+ expansion region;

[0031] The first P+ expansion area, N-epitaxial area, N+ buried layer and P-type substrate form a low capacitance PNP tube;

[0032] The first N+ extension region, the N- epitaxial region and the second P+ extension region form a guiding diode;

[0033] S5, forming an annular isolation groove and an annular electrical connection layer on the N-epitaxial layer by deep trench etching and filling;

[0034] S6. Form the anode and cathode of the circuit on the dielectric layer by sputtering aluminum and etching, and complete the preparation of the protection device with low capacitance and high ESD protection capability.

[0035] Furthermore, step S5 is specifically as follows:

[0036] A first trench region is formed on the N-epitaxial by deep trench etching, and polysilicon or silicon dioxide is filled in the first trench region to form an annular isolation groove to electrically isolate the low-capacitance PNP tube and the low-trigger NPN tube;

[0037] A second trench region is formed on the N-epitaxial layer by deep trench etching, and P-type silicon is filled in the second trench region to form an annular electrical connection layer.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The low-capacitance and high-ESD protection capability protection device and the preparation method thereof provided by the present invention adopt a P-type substrate, an N+ buried layer, an N-epitaxial layer and a dielectric layer distributed in sequence from bottom to top to form a vertical SCR structure, reduce the channel dynamic impedance through the structure, and improve the current discharge capability; and in the present application, the first P+ expansion area and the N-epitaxial layer, the N+ buried layer, and the P-type substrate form a low-capacitance PNP tube, and the capacitance of the protection device can be adjusted by adjusting the concentration of the N-epitaxial layer; it further helps to achieve ultra-low capacitance while ensuring the high electrostatic protection capability of the protection device; and by setting an annular isolation groove and an annular electrical connection layer, a double Trench structure is formed, and the electrical isolation between the low-capacitance PNP tube and the low-trigger NPN tube, as well as the electrical connection between the devices are achieved, effectively solving the disadvantages of the vertical table structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic cross-sectional structural diagram of an embodiment of the present invention;

[0041] Figure 2 A top view of an embodiment of the present invention;

[0042] Figure 3 2 is an equivalent circuit diagram of an embodiment of the present invention.

[0043] Explanation of the accompanying drawings: 1 is a P-type substrate, 2 is an N-epitaxial, 3 is a dielectric layer, 4 is an N+ buried layer, 5 is a first P+ expansion zone, 6 is a first N+ expansion zone, 7 is a second P+ expansion zone, 8 is a second N+ expansion zone, 9 is an annular isolation groove, 91 is a first annular isolation groove, 92 is a second annular isolation groove, 93 is a third annular isolation groove, 94 is a fourth annular isolation groove, 10 is an annular electrical connection layer, 101 is a first annular electrical connection layer, 102 is a second annular electrical connection layer, 103 is a third annular electrical connection layer, 104 is a fourth annular electrical connection layer, 11 is an anode, and 12 is a cathode. DETAILED DESCRIPTION

[0044] The technical solutions in the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] like Figure 1 As shown, a low capacitance and high ESD protection capability protection device comprises a P-type substrate 1, an N-epitaxial layer 2 and a dielectric layer 3 connected sequentially from bottom to top;

[0046] An N+ buried layer 4 is provided in the middle of the upper surface of the P-type substrate 1, the top of which is connected to the N- epitaxial 2;

[0047] like Figure 2 As shown, a first P+ expansion area 5 is provided in the middle of the upper surface of the N-epitaxial 2, and a first N+ expansion area group, a second P+ expansion area group and a second N+ expansion area 8 are sequentially distributed from the inside to the outside; the first N+ expansion area group includes a plurality of first N+ expansion areas 6 uniformly distributed around the circumference; the second P+ expansion area group includes a plurality of second P+ expansion areas 7 uniformly distributed around the circumference;

[0048] Among them, the thickness of the N-epitaxial 2 is 5um-12um, and its resistivity is 210Ω·cm; the doping material of the first P+ extension region 5 and the second P+ extension region 7 is boron; the doping material of the first N+ extension region 6 and the second N+ extension region 8 is phosphorus;

[0049] The second N+ expansion area 8, the P-type substrate 1 and the N+ buried layer 4 form a low trigger NPN tube, and the minimum trigger voltage of the low trigger NPN tube is 5V; the first P+ expansion area 5, the N- epitaxial, the N+ buried layer 4, and the P-type substrate 1 form a low capacitance PNP tube, and the capacitance of the low capacitance PNP tube is 0.15pF; the first N+ expansion area 6, the N- epitaxial 2 and the second P+ expansion area 7 form a guide diode;

[0050] In order to electrically isolate the low-capacitance PNP tube and the low-trigger NPN tube, a first groove area deep into the P-type substrate 1 is opened on the N-epitaxial 2, and polysilicon is filled in the first groove area to form an annular isolation groove 9, and the annular isolation groove 9 includes a first annular isolation groove 91, a second annular isolation groove 92, a third annular isolation groove 93 and a fourth annular isolation groove 94 which are co-centered and sequentially distributed from the inside to the outside, wherein: the inner side wall of the first annular isolation groove 91 is connected to the N+ buried layer 4, and the outer side wall is connected to the first N+ expansion area 6; the inner side wall of the second annular isolation groove 92 is connected to the second P+ expansion area 7, and there is a gap between the outer side wall and the second N+ expansion area 8; there is a gap between the inner side wall of the third annular isolation groove 93 and the second N+ expansion area 8; there is a gap between the inner side wall of the fourth annular isolation groove 94 and the inner and outer side walls of the third annular isolation groove 93;

[0051] A second groove region extending deep into the P-type substrate 1 is formed on the second N+ expansion region 8, and the second groove region is filled with P-type silicon to form an annular electrical connection layer 10. The annular electrical connection layer 10 includes a first annular electrical connection layer 101, a second annular electrical connection layer 102, a third annular electrical connection layer 103 and a fourth annular electrical connection layer 104 which are co-centered and arranged in sequence from the inside to the outside.

[0052] An anode 11 and a cathode 12 are provided on the dielectric layer 3. The materials of the anode 11 and the cathode 12 are aluminum. The bottom of the anode 11 is connected to the first P+ expansion area 5 and the first N+ expansion area 6. The bottom of the cathode 12 is connected to the second N+ expansion area 8 and the second P+ expansion area 7.

[0053] In this embodiment, the forward pulse current discharge path passes through the anode 11 of the low-capacitance and high-ESD protection capability protection device, the first P+ expansion region 5, the N-epitaxial 2, the N+ buried layer 4, the P+ substrate 1, the annular electrical connection layer 9 and the second N+ expansion region 8 to the cathode 12.

[0054] The second N+ expansion area 8, the P-type substrate 1 and the N+ buried layer 4 form a low trigger NPN tube, the first P+ expansion area 5, the N-epitaxial, the N+ buried layer 4 and the P-type substrate 1 form a low capacitance PNP tube, the first N+ expansion area 6, the N-epitaxial 2 and the second P+ expansion area 7 form a guide diode D1; the circuit composed of the low trigger NPN tube, the low capacitance PNP tube and the guide diode is shown in FIG. Figure 3 shown.

[0055] The preparation method of the low capacitance and high ESD protection capability protection device is specifically as follows:

[0056] S1, implanting N-type doping elements into the middle of the upper surface of the P-type substrate 1 to form an N+ buried layer 4;

[0057] S2, growing a layer of N- epitaxial 2 on the P-type substrate 1 and the N+ buried layer 4 by epitaxial growth technology;

[0058] S3, implanting phosphorus into the N- epitaxial layer 2 and annealing at 1000-1150° C. to form a second N+ expansion region 8, the second N+ expansion region 8, the P-type substrate 1, and the N+ buried layer 4 form a low trigger NPN transistor;

[0059] S4, implanting boron into the N-epitaxial 2 and annealing at 1000-1150° C. to form a first P+ expansion region 5 and a second P+ expansion region 7, implanting phosphorus into the N-epitaxial 2 and annealing at 1000-1150° C. to form a first N+ expansion region 6;

[0060] Among them, the first P+ expansion region 5, N-epitaxial, N+ buried layer 4, and P-type substrate 1 form a low-capacitance PNP tube;

[0061] The first N+ extension region 6, the N- epitaxial region 2 and the second P+ extension region 7 form a guiding diode;

[0062] S5, forming a first trench region on the N-epitaxial 2 by deep trench etching, filling the first trench region with polysilicon or silicon dioxide to form an annular isolation groove 9, and electrically isolating the low-capacitance PNP tube and the low-trigger NPN tube;

[0063] A second trench region is formed on the N-epitaxial 2 by deep trench etching, and P-type silicon is filled in the second trench region to form an annular electrical connection layer 10;

[0064] S6. Anode 11 and cathode 12 of the circuit are formed on dielectric layer 3 by sputtering aluminum and etching, thereby completing the preparation of a protection device with low capacitance and high ESD protection capability.

[0065] In other embodiments of the present invention, the first trench region is filled with silicon dioxide to form the annular isolation trench 9 .

[0066] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A low capacitance and high ESD protection capability protection device, characterized in that: It comprises a P-type substrate (1), an N-epitaxial layer (2) and a dielectric layer (3) which are connected in sequence from bottom to top; An N+ buried layer (4) whose top is connected to the N- epitaxial layer (2) is provided in the middle of the upper surface of the P-type substrate (1); A first P+ expansion area (5) is provided in the middle of the upper surface of the N-epitaxial (2), and a first N+ expansion area group, a second P+ expansion area group and a second N+ expansion area (8) are sequentially distributed from the inside to the outside; the first N+ expansion area group includes a plurality of first N+ expansion areas (6) uniformly distributed around the circumference; the second P+ expansion area group includes a plurality of second P+ expansion areas (7) uniformly distributed around the circumference; The second N+ expansion region (8), the P-type substrate (1) and the N+ buried layer (4) form a low-trigger NPN transistor; the first P+ expansion region (5), the N-epitaxial region, the N+ buried layer (4) and the P-type substrate (1) form a low-capacitance PNP transistor; the first N+ expansion region (6), the N-epitaxial region (2) and the second P+ expansion region (7) form a guide diode; The N-epitaxial (2) is provided with an annular isolation groove (9) extending deep into the P-type substrate (1) for electrically isolating the low-capacitance PNP tube and the low-trigger NPN tube; The second N+ expansion region (8) is provided with a ring-shaped electrical connection layer (10) extending deep into the P-type substrate (1); An anode (11) and a cathode (12) are provided on the dielectric layer (3); the bottom of the anode (11) is connected to the first P+ expansion area (5) and the first N+ expansion area (6); and the bottom of the cathode (12) is connected to the second N+ expansion area (8) and the second P+ expansion area (7).

2. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: The N-epitaxial (2) is provided with a first groove region penetrating into the P-type substrate (1), and the first groove region is filled with polysilicon to form an annular isolation groove (9) for electrically isolating the low-capacitance PNP tube and the low-trigger NPN tube.

3. The low capacitance and high ESD protection capability protection device according to claim 2, characterized in that: The first trench region is filled with silicon dioxide to form an annular isolation trench (9).

4. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: A second trench region extending deep into the P-type substrate (1) is provided on the second N+ expansion region (8), and the second trench region is filled with P-type silicon to form an annular electrical connection layer (10).

5. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: The annular isolation groove (9) comprises a first annular isolation groove (91), a second annular isolation groove (92), a third annular isolation groove (93) and a fourth annular isolation groove (94) which are co-centered and are sequentially distributed from the inside to the outside, wherein: The inner side wall of the first annular isolation groove (91) is connected to the N+ buried layer (4), and the outer side wall is connected to the first N+ expansion region (6); The inner side wall of the second annular isolation groove (92) is connected to the second P+ expansion region (7), and there is a gap between the outer side wall and the second N+ expansion region (8); There is a gap between the inner side wall of the third annular isolation groove (93) and the second N+ expansion region (8); There is a gap between the inner side wall of the fourth annular isolation groove (94) and the inner and outer side walls of the third annular isolation groove (93).

6. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: The annular electrical connection layer (10) comprises a first annular electrical connection layer (101), a second annular electrical connection layer (102), a third annular electrical connection layer (103) and a fourth annular electrical connection layer (104) which are co-centered and arranged in sequence from the inside to the outside.

7. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: The thickness of the N-epitaxial (2) is 5um-12um, and its resistivity is greater than 8. The low capacitance and high ESD protection capability protection device according to claim 1, characterized in that: The doping material of the second N+ expansion region (8) and the first N+ expansion region (6) is phosphorus; The doping material of the first P+ expansion region (5) and the second P+ expansion region (7) is boron; The material of the anode (11) and the cathode (12) is aluminum.

9. A method for preparing a low capacitance and high ESD protection capability protection device, characterized in that: The steps include: S1, implanting an N-type doping element into the middle of the upper surface of a P-type substrate (1) to form an N+ buried layer (4); S2, growing a layer of N-epitaxial (2) on the P-type substrate (1) and the N+ buried layer (4) by epitaxial growth technology; S3, implanting phosphorus on the N-epitaxial (2) and annealing at 1000-1150° C. to form a second N+ expansion region (8), the second N+ expansion region (8) and the P-type substrate (1) and the N+ buried layer (4) form a low trigger NPN transistor; S4, implanting boron into the N-epitaxial (2) and annealing at 1000-1150° C. to form a first P+ expansion region (5) and a second P+ expansion region (7), implanting phosphorus into the N-epitaxial (2) and annealing at 1000-1150° C. to form a first N+ expansion region (6); The first P+ expansion region (5), the N-epitaxial region, the N+ buried layer (4), and the P-type substrate (1) form a low-capacitance PNP transistor; The first N+ expansion region (6), the N- epitaxial region (2) and the second P+ expansion region (7) form a guiding diode; S5, forming an annular isolation groove (9) and an annular electrical connection layer (10) on the N-epitaxial layer (2) by deep trench etching and filling; S6. Forming the anode (11) and cathode (12) of the circuit on the dielectric layer (3) by sputtering aluminum and etching, thereby completing the preparation of a low-capacitance and high-ESD protection capability protection device.

10. The method for preparing a protection device with low capacitance and high ESD protection capability according to claim 9, characterized in that: Step S5 is specifically as follows: A first groove region is formed on the N-epitaxial (2) by deep trench etching, and polysilicon or silicon dioxide is filled in the first groove region to form an annular isolation groove (9) to electrically isolate the low-capacitance PNP tube and the low-trigger NPN tube; A second trench region is formed on the N-epitaxial (2) by deep trench etching, and P-type silicon is filled in the second trench region to form an annular electrical connection layer (10).

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