Preparation Method of SOT-MRAM Device and SOT-MRAM Device

Abstract

The present invention discloses a method for fabricating a SOT-MRAM device and a SOT-MRAM device, belonging to the technical field of magnetic memories. First, an interlayer and a hard mask layer are sequentially deposited on the surface of the MTJ thin film along the thickness direction; then a dielectric layer is deposited and the hard mask layer is exposed; then a chemical reaction occurs in the hard mask layer. Under this chemical reaction, the selectivity between the hard mask layer and other layers is relatively large, so the hard mask layer can be accurately removed. Therefore, compared with the traditional CMP method, the process window has more obvious advantages; at the same time, during the process of removing the hard mask layer, the presence of the interlayer can prevent the oxidation of the MTJ thin film, and the interlayer can adopt a specific material, thereby further enhancing the SOT efficiency. This process flow is simple to implement, and compared with the top-pinned SOT-MRAM device, the electrical and magnetic properties of the bottom-pinned SOT-MRAM device are more excellent.

Description

Technical Field

[0001] The present invention relates to the technical field of magnetic memories, and particularly to a method for manufacturing a SOT-MRAM device and a SOT-MRAM device. Background Art

[0002] SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory) has the advantages of fast writing speed, unlimited erasing and writing, and read-write separation compared with STT (Spin Transfer Torque)-MRAM. The SOT-MTJ (Magnetic Tunnel Junction) is its core structure, and its obvious structural feature is the SOT orbit layer with a thickness of only a few nanometers. The SOT orbit layer provides an independent channel for the write current, realizing read-write separation.

[0003] Currently, in the manufacture of SOT-MRAM, the MTJ usually adopts a Top Pinning (TP) structure. In this structure, the free layer of the MTJ is at the bottom, and the SOT orbit layer is below the free layer. The etching of the MTJ stops on the SOT orbit layer, which is difficult to precisely control, resulting in too small an etching window for the MTJ and increasing the manufacturing process difficulty of the SOT-MRAM. At the same time, the electrical properties, magnetic properties, and annealing stability of the magnetic tunnel junction based on top pinning are inferior to those of the MTJ based on bottom pinning (BP). Therefore, it is very important to realize the process integration and preparation of SOT-MRAM with the structure of the MTJ based on bottom pinning.

[0004] However, in the manufacture of current bottom-pinned SOT-MRAM devices, usually, after the surface dielectric layer is polished flat by CMP (Chemical Mechanical Polishing) to expose the MTJ, the SOT orbit layer is deposited. The problem is that the free layer is only a few nanometers, and due to the loading effect of the CMP process, it is difficult to precisely stop on the free layer, resulting in too small a process window. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for manufacturing a SOT-MRAM device and a SOT-MRAM device, thereby improving the process window for manufacturing the SOT-MRAM device.

[0006] To achieve the above purpose, the present invention provides a method for manufacturing a SOT-MRAM device, including:

[0007] A columnar structure is formed on the surface of a substrate; the columnar structure includes an MTJ thin film, an interlayer, and a hard mask layer sequentially arranged in a direction away from the substrate; the MTJ thin film at least includes a reference layer, a barrier layer, and a free layer sequentially arranged in a direction away from the substrate;

[0008] At least one dielectric layer is deposited on the surface of the substrate having the columnar structure, and the surface of the hard mask layer is exposed;

[0009] After the surface of the hard mask layer is exposed, the hard mask layer is removed by causing a chemical reaction in the hard mask layer to form a region for depositing an orbit layer on the surface of the substrate;

[0010] An orbit layer is deposited in the region for depositing an orbit layer to obtain the SOT-MRAM device.

[0011] Optionally, the depositing at least one dielectric layer on the surface of the substrate having the columnar structure includes:

[0012] A first dielectric layer is deposited on the surface of the substrate having the columnar structure;

[0013] Correspondingly, the removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a region for depositing an orbit layer on the surface of the substrate includes:

[0014] The hard mask layer is removed by causing a chemical reaction in the hard mask layer, and the surface of the interlayer is exposed to form a groove, so as to form the region for depositing an orbit layer on the surface of the substrate; the interlayer is the bottom surface of the groove.

[0015] Optionally, the depositing at least one dielectric layer on the surface of the substrate having the columnar structure includes:

[0016] A first dielectric layer and a second dielectric layer are sequentially deposited in a thickness direction on the surface of the substrate having the columnar structure;

[0017] Correspondingly, the removing the hard mask layer by causing a chemical reaction in the hard mask layer to form a region for depositing an orbit layer on the surface of the substrate includes:

[0018] The hard mask layer is removed by causing a chemical reaction in the hard mask layer, and the second dielectric layer is removed by causing a chemical reaction in the second dielectric layer, and the surface of the interlayer is exposed to form a groove; the interlayer serves as the bottom surface of the groove;

[0019] The side walls of the groove are removed to form the region for depositing an orbit layer on the surface of the substrate.

[0020] Optionally, removing the sidewalls of the groove includes:

[0021] Removing the sidewalls of the groove by means of grazing incidence etching.

[0022] Optionally, the deposition height of the first dielectric layer is flush with the height of the interlayer or exceeds the height of the interlayer.

[0023] Optionally, the material of the second dielectric layer is amorphous carbon, doped amorphous carbon, germanium, or phosphosilicate glass;

[0024] Correspondingly, removing the second dielectric layer by causing a chemical reaction in the hard mask layer includes:

[0025] Introducing a reaction gas or liquid to cause a chemical reaction with the second dielectric layer to remove the second dielectric layer.

[0026] Optionally, the material of the hard mask layer is amorphous carbon, doped amorphous carbon, germanium, or phosphosilicate glass;

[0027] Correspondingly, removing the hard mask layer by causing a chemical reaction in the hard mask layer includes:

[0028] Introducing a reaction gas or liquid to cause a chemical reaction with the second dielectric layer to remove the second dielectric layer.

[0029] Optionally, after depositing the track layer in the area of the track layer to be deposited, it further includes:

[0030] Depositing a third dielectric layer on the surface of the track layer, and the track layer and the third dielectric layer form a second stacked structure;

[0031] Performing patterning on the second stacked structure;

[0032] After patterning, depositing a fourth dielectric layer on the surface of the substrate;

[0033] Preparing a top interconnect structure in the fourth dielectric layer by using a dual damascene process; the top interconnect structure penetrates through the third dielectric layer and is connected to the track layer.

[0034] Optionally, exposing the surface of the hard mask layer includes:

[0035] By means of chemical mechanical polishing, polishing until the surface of the hard mask layer is exposed.

[0036] Optionally, the material of the track layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, or a topological insulator;

[0037] The intercalated material is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, a topological insulator, or NiO.

[0038] Optionally, the shape of the track layer is rectangular or L-shaped.

[0039] Optionally, the surface of the MTJ film is circular, elliptical, or rectangular, forming a perpendicularly magnetized MTJ;

[0040] Alternatively, the surface of the MTJ film is elliptical or rectangular, forming an in-plane magnetized MTJ.

[0041] Optionally, the material of the first dielectric layer is SiN or SiO2.

[0042] To achieve the above object, the present invention also provides a SOT-MRAM device, including: a SOT-MRAM device prepared by the above-described SOT-MRAM device preparation method.

[0043] Obviously, for the SOT-MRAM device preparation method provided by the present invention, an intercalated layer and a hard mask layer are sequentially deposited on the surface of the MTJ film along the thickness direction; then a dielectric layer is deposited, and the hard mask layer is exposed; then a chemical reaction occurs to the hard mask layer. Under this chemical reaction, the selectivity between the hard mask layer and other layers is relatively large, so the hard mask layer can be accurately removed. Therefore, compared with the traditional CMP method, the process window has more obvious advantages; at the same time, during the process of removing the hard mask layer, the presence of the intercalated layer can prevent the MTJ film from being oxidized, and this intercalated layer can adopt specific materials, thereby further enhancing the SOT efficiency. This process flow is simple to implement, and compared with the top-pinned SOT-MRAM device, the electrical and magnetic properties of the bottom-pinned SOT-MRAM device are more excellent. The present invention also provides a SOT-MRAM device prepared by the above SOT-MRAM device preparation method, so it also has the above beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0045] Figure 1 It is a flowchart of a SOT-MRAM device preparation method provided by an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of the shape of the first track layer provided by an embodiment of the present invention;

[0047] Figure 3 Schematic diagram of the shape of the second track layer provided by an embodiment of the present invention;

[0048] Figures 4 to 10 Schematic flow chart of the first method for fabricating a SOT-MRAM device provided by an embodiment of the present invention;

[0049] Figures 11 to 20 Schematic flow chart of the second method for fabricating a SOT-MRAM device provided by an embodiment of the present invention.

[0050] Explanation of reference numerals is as follows:

[0051] 101 - First bottom dielectric layer; 102 - Bottom electrode; 103 - Second bottom dielectric layer; 104 - Bottom via; 105 - Bottom conductive layer; 106 - MTJ thin film; 107 - Interlayer; 108 - Hard mask layer; 103a - First dielectric layer of the first layer; 101a - First dielectric layer of the second layer; 109 - Track layer; 103b - Third dielectric layer; 110 - Top via; 111 - Top conductive layer; 112 - Second dielectric layer. Detailed implementation manners

[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] Please refer to Figure 1 , Figure 1 which is a flowchart of a method for fabricating a SOT-MRAM device provided by an embodiment of the present invention. The method may include:

[0054] S101: Form a columnar structure on the surface of the substrate; the columnar structure includes an MTJ thin film, an interlayer, and a hard mask layer sequentially arranged in a direction away from the substrate; the MTJ thin film at least includes a reference layer, a barrier layer, and a free layer sequentially arranged in a direction away from the substrate.

[0055] In this embodiment, the process of forming the columnar structure may specifically include:

[0056] Deposit an MTJ thin film, an interlayer, and a hard mask layer sequentially in the thickness direction on the surface of the substrate to form a first stacked structure;

[0057] The first stack structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode.

[0058] It should be noted that in this embodiment, the substrate includes a bottom electrode, the bottom electrode is formed in the first bottom dielectric layer, the first bottom dielectric layer functions as insulation, and the first bottom dielectric layer and the bottom electrode constitute the substrate. This embodiment does not limit the specific type of the first bottom dielectric layer. For example, the material of the first bottom dielectric layer can be SiO or SiN, or other insulating materials.

[0059] In this embodiment, the columnar structure needs to be electrically connected to the bottom electrode, that is, the MTJ thin film needs to be connected to the bottom electrode. This embodiment does not limit the specific manner of connecting the MTJ thin film and the bottom electrode, as long as it is ensured that the MTJ thin film and the bottom electrode can form an electrical connection. For example, the substrate can further include a bottom interconnect structure; the bottom interconnect structure is formed in the first bottom dielectric layer; one end of the bottom interconnect structure is connected to the bottom electrode, and the other end is connected to the MTJ thin film. Correspondingly, after patterning, one end of the bottom interconnect structure is connected to the bottom electrode, and the other end is connected to the columnar structure.

[0060] This embodiment does not limit the specific type of the bottom interconnect structure. For example, the material of the bottom interconnect structure can be metal, or other conductive materials. This embodiment does not limit the specific structure of the bottom interconnect structure. For example, the bottom interconnect structure can include a bottom via; or, the bottom interconnect structure can include a bottom via and a bottom conductive layer connected in sequence along the thickness direction.

[0061] Furthermore, the substrate in this embodiment can further include a second bottom dielectric layer, the second bottom dielectric layer is located inside the first bottom dielectric layer, covers the surface of the bottom electrode, and surrounds the bottom interconnect structure to function as insulation. This embodiment does not limit the specific type of the second bottom dielectric layer. For example, the material of the second bottom dielectric layer can be SiO or SiN, or other insulating materials.

[0062] This embodiment does not limit the specific manner of depositing the MTJ thin film, the interlayer, and the hard mask layer. For example, physical vapor deposition or chemical vapor deposition can be used to deposit the MTJ thin film, the interlayer, and the hard mask layer in sequence along the thickness direction on the surface of the substrate to form the first stack structure.

[0063] The MTJ thin film in this embodiment is not limited to including a reference layer, a barrier layer, and a free layer, and other film layers can also be added according to actual needs. Among them, the magnetization direction of the free layer can be changed by means of current or magnetic field.

[0064] This embodiment does not limit the specific type of the interlayer. For example, the interlayer can be made of the same material as the orbit layer. For example, the material of the interlayer can be W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, topological insulator. When using such materials, the MTJ film can be electrically connected to the orbit layer through the interlayer; or the interlayer can be made of a material different from the orbit layer. For example, the material of the interlayer can be NiO or other materials that can improve the spin transfer efficiency, so as to improve the spin transfer efficiency through the interlayer. It should be noted that when the material of the interlayer is NiO, since only a relatively thin layer of NiO is needed to improve the spin transfer efficiency, it will not affect the electrical connection between the MTJ film and the orbit layer either.

[0065] This embodiment does not limit the specific type of the hard mask layer. For example, the material of the hard mask layer can be amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass, or other materials that can be removed by chemical etching.

[0066] In this embodiment, the first stacked structure remaining after patterning should cover the bottom electrode to ensure that the columnar structure can be connected to the bottom electrode.

[0067] This embodiment does not limit the specific method of patterning, as long as the desired pattern can be obtained. For example, the hard mask layer can be etched to define the pattern of the hard mask layer; after the etching is completed, the interlayer and the MTJ film are etched to define the patterns of the interlayer and the MTJ film.

[0068] This embodiment does not limit the specific pattern of the MTJ film after patterning. Different patterns of the MTJ film result in different types of MTJs. For example, the surface of the MTJ film can be circular, elliptical or rectangular, forming a perpendicularly magnetized MTJ; or the surface of the MTJ film is elliptical or rectangular, forming an in-plane magnetized MTJ. Among them, in the perpendicularly magnetized MTJ, the magnetic moments of the reference layer and the free layer are both arranged in the direction perpendicular to the film plane; in the in-plane magnetized MTJ, the magnetic moments of the reference layer and the free layer are both arranged in the direction within the film plane. In addition, the side wall of the MTJ film after patterning in this embodiment can be perpendicular to the substrate, or can form a preset angle with the surface of the substrate.

[0069] S102: Deposit at least one dielectric layer on the surface of the substrate with columnar structures and expose the surface of the hard mask layer.

[0070] This embodiment does not limit the specific method of exposing the surface of the hard mask layer, as long as it can ensure the removal of the dielectric layer covering the surface of the hard mask layer. For example, chemical mechanical polishing can be used to polish until the surface of the hard mask layer is exposed.

[0071] This embodiment does not limit the specific number and type of the deposited dielectric layers. For details, please refer to the following specific embodiments.

[0072] S103: After exposing the surface of the hard mask layer, remove the hard mask layer by causing a chemical reaction in the hard mask layer to form a region for depositing the track layer on the surface of the substrate.

[0073] This embodiment does not limit the specific method for removing the hard mask layer, as long as it can ensure that the hard mask layer can be chemically etched. For example, reaction gas or liquid can be introduced to react with the hard mask layer to remove it. Further, according to the specific type of the hard mask layer, the corresponding reaction gas or liquid can be selected. For example, when the material of the hard mask layer is amorphous carbon, the reaction gas can be oxygen; when the material of the hard mask layer is germanium, the reaction gas can be H2O2.

[0074] This embodiment does not limit the specific method for forming the region for depositing the track layer. For details, please refer to the following specific embodiments.

[0075] S104: Deposit a track layer in the region for depositing the track layer to fabricate an SOT-MRAM device.

[0076] This embodiment does not limit the specific type of the track layer. For example, the material of the track layer can be W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, or a topological insulator.

[0077] Further, after depositing the track layer in the region for depositing the track layer in this embodiment, it may further include:

[0078] Deposit a third dielectric layer on the surface of the track layer, and the track layer and the third dielectric layer form a second stacked structure;

[0079] Perform patterning on the second stacked structure;

[0080] After patterning, deposit a fourth dielectric layer on the surface of the substrate;

[0081] Fabricate a top interconnect structure in the fourth dielectric layer using a dual damascene process; the top interconnect structure penetrates through the third dielectric layer and is connected to the track layer.

[0082] This embodiment does not limit the specific pattern of the track layer after patterning. For example, as Figure 2 and Figure 3As shown, the shape of the track layer can be rectangular or L-shaped. It should be noted that in this embodiment, since the track layer and the MTJ pattern are defined separately, field-free switching can be achieved. The top interconnect structure formed in this embodiment can be used for interconnection with other devices. When vias are used in the top interconnect structure, due to the height difference between the MRAM region and the logic region, the drilling depths of the two regions are different. The third dielectric layer deposited on the surface of the track layer in this embodiment can play a role in compensating for the height difference between the MRAM region and the logic region.

[0083] This embodiment does not limit the specific type of the top interconnect structure. For example, the material of the top interconnect structure can be metal or other conductive materials. This embodiment does not limit the specific structure of the top interconnect structure. For example, the top interconnect structure can include top vias; or, the top interconnect structure can include a top via and a top conductive layer connected in sequence along the thickness direction.

[0084] Based on the above embodiments, the present invention first deposits an interlayer and a hard mask layer in sequence along the thickness direction on the surface of the MTJ thin film; then deposits a dielectric layer and exposes the hard mask layer; then makes the hard mask layer undergo a chemical reaction. Under this chemical reaction, the difference between the hard mask layer and other layers is relatively large, so the hard mask layer can be accurately removed. Therefore, compared with the traditional CMP method, the process window has more obvious advantages; at the same time, during the process of removing the hard mask layer, due to the presence of the interlayer, the MTJ thin film can be prevented from being oxidized, and the interlayer can be made of a specific material, so that the SOT efficiency can be further enhanced. This process flow is simple to implement, and compared with the top-pinned SOT-MRAM device, the electrical and magnetic properties of the bottom-pinned SOT-MRAM device are more excellent.

[0085] Please refer to Figures 4 to 10 , Figures 4 to 10 which is a schematic flow chart of the first method for fabricating an SOT-MRAM device provided by an embodiment of the present invention. Different from the embodiment of the first method for fabricating an SOT-MRAM device, this embodiment further specifically defines steps S102 and S103 on the basis of the embodiment of the first method for fabricating an SOT-MRAM device. The rest of the content has been introduced in detail in the embodiment of the first method for fabricating an SOT-MRAM device, and will not be elaborated here.

[0086] The method for fabricating an SOT-MRAM device in this embodiment may include:

[0087] As Figure 4 shown, an MTJ thin film 106, an interlayer 107, and a hard mask layer 108 are sequentially deposited along the thickness direction on the surface of the substrate to form a first stacked structure; the substrate includes a bottom electrode 102; the MTJ thin film 106 at least includes a reference layer, a barrier layer, and a free layer sequentially arranged in a direction away from the substrate.

[0088] The substrate in this embodiment may be composed of a first bottom dielectric layer 101, a second bottom dielectric layer 103, a bottom interconnect structure, and a bottom electrode 102; the bottom interconnect structure may include a bottom via 104 and a bottom conductive layer 105 connected in sequence along the thickness direction.

[0089] As Figure 5 shown, the first stacked structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode 102.

[0090] As Figure 6 shown, a first dielectric layer is deposited on the surface of the substrate having the columnar structure, and the surface of the hard mask layer 108 is exposed.

[0091] The first dielectric layer in this embodiment serves as a protective layer and will not be corroded during the chemical etching of the hard mask layer 108. The specific type of the first dielectric layer is not limited in this embodiment. For example, the material of the first dielectric layer may be SiN or SiO2. The specific number of the first dielectric layers is not limited in this embodiment. For example, a first dielectric layer may be deposited on the surface of the substrate along the thickness direction; or a first first dielectric layer 103a and a second first dielectric layer 101a may be sequentially deposited on the surface of the substrate along the thickness direction, and the materials of the two first dielectric layers may be different.

[0092] As Figure 7 shown, after the surface of the hard mask layer 108 is exposed, the hard mask layer 108 is removed by causing a chemical reaction on the hard mask layer 108, and the surface of the interlayer 107 is exposed to form a groove, so as to form a region for depositing the track layer 109 on the surface of the substrate; the interlayer 107 is the bottom surface of the groove.

[0093] As Figure 8 shown, the track layer 109 is deposited in the region for depositing the track layer 109, and an SOT-MRAM device is prepared; the track layer 109 is connected to the interlayer 107.

[0094] Further, after depositing the track layer 109 in the region for depositing the track layer 109 in this embodiment, it may further include:

[0095] As Figure 8 and Figure 9 shown, a third dielectric layer 103b is deposited on the surface of the track layer 109, and the track layer 109 and the third dielectric layer 103b form a second stacked structure; the second stacked structure is patterned; after the patterning, a fourth dielectric layer is deposited on the surface of the substrate.

[0096] As Figure 10As shown, a top interconnect structure is fabricated in the fourth dielectric layer using a dual damascene process to obtain an SOT-MRAM device; the top interconnect structure penetrates through the third dielectric layer 103b and is connected to the track layer 109.

[0097] In this embodiment, the top interconnect structure may include a top via 110 and a top conductive layer 111 connected in sequence along the thickness direction.

[0098] Please refer to Figures 11 to 20 , Figures 11 to 20 which is a schematic flow chart of the second method for fabricating an SOT-MRAM device provided by an embodiment of the present invention. Different from the embodiment of the first method for fabricating an SOT-MRAM device, this embodiment further specifically defines steps S102 and S103 on the basis of the embodiment of the first method for fabricating an SOT-MRAM device. The remaining content has been introduced in detail in the embodiment of the first method for fabricating an SOT-MRAM device and will not be elaborated here.

[0099] The method for fabricating an SOT-MRAM device in this embodiment may include:

[0100] As Figure 11 shown, an MTJ thin film 106, an interlayer 107, and a hard mask layer 108 are sequentially deposited along the thickness direction on the surface of the substrate to form a first stacked structure; the substrate includes a bottom electrode 102; the MTJ thin film 106 at least includes a reference layer, a barrier layer, and a free layer sequentially arranged in a direction away from the substrate.

[0101] The substrate in this embodiment may be composed of a first bottom dielectric layer 101, a second bottom dielectric layer 103, a bottom interconnect structure, and a bottom electrode 102; the bottom interconnect structure may include a bottom via 104 and a bottom conductive layer 105 connected in sequence along the thickness direction.

[0102] As Figure 12 shown, the first stacked structure is patterned to form a columnar structure; the columnar structure is connected to the bottom electrode 102.

[0103] As Figures 13 to 15 shown, a first dielectric layer and a second dielectric layer 112 are sequentially deposited along the thickness direction on the surface of the substrate having the columnar structure, and the surface of the hard mask layer 108 is exposed.

[0104] In this embodiment, the first dielectric layer serves as a protective layer and will not be etched away during the chemical etching of the hard mask layer 108. This embodiment does not limit the specific type of the first dielectric layer. For example, the material of the first dielectric layer can be SiN or SiO2. This embodiment does not limit the specific number of the first dielectric layers. For example, a first dielectric layer can be deposited on the surface of the substrate in the thickness direction; or a first first dielectric layer 103a and a second first dielectric layer 101a can be sequentially deposited on the surface of the substrate in the thickness direction, and the materials of the two first dielectric layers can be different.

[0105] Further, in this embodiment, the deposition height of the first dielectric layer can be flush with the height of the interlayer 107 or exceed the height of the interlayer 107 to avoid damaging the interlayer 107 during the process of removing the sidewalls of the groove by means of grazing incidence etching.

[0106] This embodiment does not limit the specific type of the second dielectric layer 112. For example, the material of the second dielectric layer 112 can be amorphous carbon, doped amorphous carbon, germanium, or phosphosilicate glass, or other materials that can be removed by chemical etching.

[0107] As Figure 16 shown, by causing a chemical reaction in the hard mask layer 108, the hard mask layer 108 is removed, and by causing a chemical reaction in the second dielectric layer 112, the second dielectric layer 112 is removed, exposing the surface of the interlayer 107 to form a groove; the interlayer 107 serves as the bottom surface of the groove.

[0108] This embodiment does not limit the specific method of removing the second dielectric layer 112, as long as it can ensure that the second dielectric layer 112 can be chemically etched away. For example, a reaction gas or liquid can be introduced to react chemically with the second dielectric layer 112 to remove the second dielectric layer 112. Further, according to the specific type of the second dielectric layer 112, the corresponding reaction gas or liquid can be selected. For example, when the material of the second dielectric layer 112 is amorphous carbon, the reaction gas can be oxygen; when the material of the second dielectric layer 112 is germanium, the reaction gas can be H2O2.

[0109] It should be noted that when the second dielectric layer 112 and the hard mask layer 108 in this embodiment use the same material, the same reaction gas or liquid can be introduced to react chemically with both the second dielectric layer 112 and the hard mask layer 108 to remove the second dielectric layer 112 and the hard mask layer 108 simultaneously; when the second dielectric layer 112 and the hard mask layer 108 in this embodiment use different materials, different reaction gases or liquids can be introduced to remove the second dielectric layer 112 and the hard mask layer 108 step by step.

[0110] As Figure 17 shown, the sidewalls of the groove are removed to form a region for depositing the track layer 109 on the surface of the substrate.

[0111] It should be noted that the sidewall of the groove in this embodiment refers to the remaining first dielectric layer above the plane where the interlayer 107 is located after being processed by chemical etching.

[0112] This embodiment does not limit the specific method for removing the sidewall of the groove, as long as it can ensure the removal of the sidewall of the groove. For example, the sidewall of the groove can be removed by grazing incidence etching. It should be noted that grazing incidence etching etches the side faster and the bottom slower, thus generating a certain selectivity ratio, so the interlayer 107 can be damaged as little as possible.

[0113] As Figure 18 shown, the track layer 109 is deposited in the area where the track layer 109 is to be deposited, and an SOT-MRAM device is prepared; the track layer 109 is connected to the interlayer 107.

[0114] Furthermore, after depositing the track layer 109 in the area where the track layer 109 is to be deposited in this embodiment, it may further include:

[0115] As Figure 18 and Figure 19 shown, a third dielectric layer 103b is deposited on the surface of the track layer 109, and the track layer 109 and the third dielectric layer 103b form a second stacked structure; the second stacked structure is patterned; after patterning, a fourth dielectric layer is deposited on the surface of the substrate.

[0116] As Figure 20 shown, a top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process, and an SOT-MRAM device is prepared; the top interconnect structure penetrates through the third dielectric layer 103b and is connected to the track layer 109.

[0117] In this embodiment, the top interconnect structure may include a top via 110 and a top conductive layer 111 connected in sequence along the thickness direction.

[0118] An embodiment of the present invention also provides an SOT-MRAM device, which may include: an SOT-MRAM device prepared by the above SOT-MRAM device preparation method.

[0119] Based on the above embodiment, the SOT-MRAM device of the present invention is prepared by the above SOT-MRAM device preparation method, so it also has the above beneficial effects.

[0120] In this article, specific examples are used to illustrate the principles and implementation manners of the present invention, and the various embodiments are in a progressive relationship. The key point of each embodiment is to explain the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. For those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

[0121] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

Claims

1. A method for preparing a SOT-MRAM device, characterized in that: include: Forming a columnar structure on the surface of the substrate; the columnar structure includes an MTJ film, an intercalation layer, and a hard mask layer sequentially arranged in a direction away from the substrate; The MTJ film at least includes a reference layer, a barrier layer and a free layer arranged in sequence in a direction away from the substrate; Depositing a first dielectric layer and a second dielectric layer in sequence along a thickness direction on the surface of the substrate having the columnar structure, and exposing the surface of the hard mask layer; After the surface of the hard mask layer is exposed, the hard mask layer is removed by causing a chemical reaction in the hard mask layer, and the second dielectric layer is removed by causing a chemical reaction in the second dielectric layer, thereby exposing the surface of the intercalation layer to form a groove; the intercalation layer serves as the bottom surface of the groove; Under the chemical reaction, the hard mask layer has a large selectivity with other layers; The sidewalls of the groove are removed by grazing incidence etching to form a track layer region to be deposited on the surface of the substrate; in the process of removing the sidewalls of the groove by grazing incidence etching, the deposition height of the first dielectric layer is flush with the height of the intercalation layer or exceeds the height of the intercalation layer; The track layer is deposited in the area where the track layer is to be deposited, so as to prepare the SOT-MRAM device.

2. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the second dielectric layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass; Accordingly, removing the second dielectric layer by causing a chemical reaction in the hard mask layer includes: A reaction gas or liquid is introduced to chemically react with the second dielectric layer, thereby removing the second dielectric layer.

3. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the hard mask layer is amorphous carbon, doped amorphous carbon, germanium or phosphosilicate glass; Accordingly, removing the hard mask layer by causing a chemical reaction in the hard mask layer includes: A reaction gas or liquid is introduced to chemically react with the hard mask layer to remove the hard mask layer.

4. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: After the track layer is deposited in the area where the track layer is to be deposited, the method further comprises: Depositing a third dielectric layer on the surface of the track layer, wherein the track layer and the third dielectric layer constitute a second stacked structure; performing a patterning process on the second stacked structure; After the patterning process, a fourth dielectric layer is deposited on the surface of the substrate; A top interconnect structure is prepared in the fourth dielectric layer by using a dual damascene process; the top interconnect structure penetrates through the third dielectric layer and is connected to the track layer.

5. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The exposing the surface of the hard mask layer comprises: The chemical mechanical polishing method is adopted to polish until the surface of the hard mask layer is exposed.

6. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the track layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe or a topological insulator; The material of the intercalation layer is W, Ta, Pt, WTax, PtCoO, PtMgO, AuPt, PtCr, PtHf, PtTi, BiSb, BiSe, topological insulator or NiO.

7. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The shape of the track layer is rectangular or L-shaped.

8. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The surface of the MTJ film is circular, elliptical or rectangular, forming a perpendicularly magnetized MTJ; Alternatively, the surface of the MTJ film is elliptical or rectangular, forming an MTJ with in-plane magnetization.

9. The method for preparing a SOT-MRAM device according to claim 1, characterized in that: The material of the first dielectric layer is SiN or SiO2.

10. A SOT-MRAM device, characterized in that: include: A SOT-MRAM device prepared by the SOT-MRAM device preparation method according to any one of claims 1 to 9.

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