Novel memory unit and preparation method and application thereof

Abstract

The invention relates to a novel memory unit and a preparation method and application thereof, a gate tube S and a resistor R form a 1S1R memory unit, the 1S1R memory unit comprises a bottom electrode, an isolation layer, a resistive layer, a gate layer and a top electrode which are sequentially stacked on a substrate, the isolation layer comprises a thick groove and a thin groove which are connected up and down, the thick groove is located above the thin groove, and the top electrode is located above the thin groove. The thick groove is filled with a gate layer material to form a gate layer, the thin groove is filled with a resistance change layer material to form a resistance change layer, and the bottom surface area of the thick groove is larger than the top surface area of the thin groove; during preparation, thick and thin grooves are formed through two times of photoetching and etching, the effective growth region areas of the gating layer and the resistive layer are designed, the gating tubes with different current driving capacities are prepared, performance matching of the resistive layer and the gating layer is facilitated, the intermediate connecting layer is introduced between the gating layer and the resistive layer, and the problem of mutual diffusion of material components of the gating layer and the resistive layer is solved; the 1S1R unit and the transistor are connected in series to form the 1T1S1R unit, and the actual electrical performance of the nanoscale gate tube is accurately measured through the control of the transistor on the current.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuit, and in particular relates to a novel memory unit and a preparation method and application thereof. Background Art

[0002] In the era of big data, emerging technologies such as smart cities and autonomous driving have put forward higher requirements for data storage, hoping that the memory has faster speed, lower power consumption and higher capacity. However, existing memory faces many challenges: the read and write speed of traditional memory is difficult to match the data processing speed of the processor; the power consumption of traditional memory (especially dynamic random access memory, DRAM) is difficult to further reduce; as the process node shrinks, the manufacturing cost and complexity of memory increase, making it difficult to achieve higher storage density.

[0003] The demands and challenges faced by traditional memory have promoted the development of new memory technologies. Selector is a new type of memory, a nonlinear threshold switching device. The resistance state of the device changes between high resistance state and low resistance state according to the applied electrical signal, thereby determining whether the information is selected. It has many advantages such as simple structure, low power consumption, high integration, and flexible design. The selector and resistive random access memory (RRAM) can be connected in series to form a 1S1R unit, which is suitable for fields such as storage and neuromorphic computing systems and is the most promising integrated architecture.

[0004] When the size of the gate tube device is miniaturized to hundreds of nanometers, a single gate tube is easily affected by the outside world and easily breaks down. The external current limiting mechanism of the conventional test system cannot protect the gate tube from breakdown, so the actual electrical characteristics of the nano-sized gate tube cannot be measured, which limits the research progress of the miniaturization of the gate tube size. At present, there is a performance mismatch problem between the gate device and the resistive switching device, that is, the conduction current density provided by the gate tube is limited and cannot drive the resistive switching device to operate normally; and this problem is more serious at the nano node, limiting its application in large-scale integration. Summary of the invention

[0005] In view of the problems existing in the above-mentioned prior art, the present invention proposes a new type of memory unit (One Selector and One Resistance, 1S1R) and its preparation method and application, which solves the problems that the actual electrical characteristics of the nano-sized gate tube cannot be measured, the current driving capability of the gate tube is insufficient, and the performance mismatch between the resistance layer and the gate layer.

[0006] The technical solution of the present invention is as follows:

[0007] A novel memory cell is a 1S1R memory cell formed by a gate tube S and a resistor R connected in series. The 1S1R memory cell comprises a bottom electrode, an isolation layer, a resistive switching layer, a gate layer and a top electrode stacked in sequence on a substrate. The isolation layer comprises a coarse trench and a fine trench connected up and down. The coarse trench is located above the fine trench. The coarse trench is filled with a gate layer material to form a gate layer. The fine trench is filled with a resistive switching layer material to form a resistive switching layer. The bottom surface area of ​​the coarse trench is larger than the top surface area of ​​the fine trench.

[0008] Furthermore, an intermediate connection layer is inserted between the resistive layer and the gate layer, and the intermediate connection layer material is vanadium V, niobium Nb, ruthenium Ru, tungsten W, tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN, titanium tungsten TiW, aluminum Al, titanium aluminum tungsten TiAlW, yttrium Ir yttrium oxide IrO2, indium tin oxide ITO, aluminum titanium nitride TiAlN, aluminum nitride AlN x , aluminum titanium nitride TiAlN or AlTiN, hafnium Hf, iridium Ir, manganese Mn, zinc Zn, platinum Pt, palladium Pd, copper Cu or one or more of the alloys of the above materials; or carbon nanotubes CNTs, graphene G, graphite Graphite, silicon carbide SiC, tellurium carbide TeC, tellurium carbon sulfide TeCS any one or more; or selected from molybdenum sulfide MoS2, tungsten sulfide WS2, molybdenum telluride MoTe, indium gallium zinc oxide IGZO, indium aluminum zinc oxide IAZO, tin-doped indium oxide ITO, manganese telluride MnTe, tungsten telluride WTe, zinc-doped indium oxide IZO at least one; the thickness of the intermediate connecting layer is between 1 and 50 nm.

[0009] Furthermore, the intermediate connection layer is located at the bottom of the rough trench, and the top surface area thereof is equal to the bottom surface area of ​​the gate layer.

[0010] Furthermore, the intermediate connection layer is located at the top of the fine groove, and the bottom surface area thereof is equal to the top surface area of ​​the resistive switching layer.

[0011] Furthermore, the resistive layer material is tantalum oxide TaO x 、TiO x 、HfO x 、ZrO x 、Silicon oxide SiO x , magnesium oxide MgO, aluminum nitride AlN x 、GeTe x , scandium antimony telluride ScSbTe, indium silver antimony telluride InAgSbTe, germanium antimonide GeSb, germanium telluride GeTe, antimony telluride SbTe, copper sulfide CuS x 、GeS x , Germanium selenide GeSe x, zinc sulfide ZnS, aluminum borate AlBO; or the material of the resistive layer is selected from strontium titanate SrTiO x 、Zirconium titanate ZrTiO x , barium titanate BaTiO x , at least one of hafnium zirconium oxide HfZrO, and hafnium aluminum oxide HfAlO; the resistive layer is a single-layer structure composed of one material or a multi-layer structure of multiple materials; if the resistive layer is replaced by an ordinary resistor, the material is polysilicon, or polysilicon doped with phosphorus P, arsenic As or boron B, or one or more of aluminum Al, hafnium Hf, manganese Mn, zinc Zn, copper Cu or alloys of the above materials, and the thickness of the resistive layer is between 5 and 100 nm.

[0012] Furthermore, the gating layer material is a metal oxide or a semiconductor oxide material, including niobium oxide NbO x 、Vanadium oxide VO x , titanium oxide TiO x 、Silicon oxide SiO x 、ZrO x , Yttrium oxide YO x 、GeTe x , Germanium selenide GeSe x 、Iron Oxide FeO x 、NdNiO x 、SmNiO x 、LaCoO x , GdCoO x materials, and one or more of their alloys; the thickness of the gating layer is between 5 and 100 nm.

[0013] Furthermore, the materials of the bottom electrode and the top electrode are vanadium V, niobium Nb, ruthenium Ru, tungsten W, tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN, titanium tungsten TiW, aluminum Al, titanium aluminum tungsten TiAlW, yttrium Ir yttrium oxide IrO2, indium tin oxide ITO, aluminum titanium nitride TiAlN, aluminum nitride AlN x , aluminum titanium nitride TiAlN or AlTiN, hafnium Hf, iridium Ir, manganese Mn, zinc Zn, platinum Pt, palladium Pd, copper Cu or one or more of the alloys of the above materials; or any one or more of carbon nanotubes CNTs, graphene G, graphite Graphite, silicon carbide SiC, tellurium carbide TeC, and tellurium carbon sulfide TeCS; or at least one selected from molybdenum sulfide MoS2, tungsten sulfide WS2, molybdenum telluride MoTe, indium gallium zinc oxide IGZO, indium aluminum zinc oxide IAZO, tin-doped indium oxide ITO, manganese telluride MnTe, tungsten telluride WTe, and zinc-doped indium oxide IZO.

[0014] A method for preparing the novel memory cell comprises the following steps:

[0015] 1) preparing a bottom electrode on a substrate;

[0016] 2) preparing an isolation layer on the bottom electrode;

[0017] 3) Spin-coat a layer of photoresist on the isolation layer;

[0018] 4) Exposure to achieve patterning and form a first photolithography pattern on the photoresist;

[0019] 5) performing reactive ion etching on the isolation layer to etch the area not covered by the photoresist and remove the photoresist;

[0020] 6) Spin-coat a layer of photoresist on the isolation layer;

[0021] 7) Exposure to achieve patterning and form a second photolithography pattern on the photoresist;

[0022] 8) performing reactive ion etching on the isolation layer to etch the area not covered by the photoresist and remove the photoresist; after this step, a coarse groove and a fine groove connected up and down are formed in the isolation layer;

[0023] 9) Fill the fine grooves with resistive switching layer material, and grind away excess resistive switching layer material on the surface to make the surface smooth;

[0024] 10) Filling the rough groove with a gate layer material, and grinding and removing the excess gate layer material on the surface to make the surface flat;

[0025] 11) A top electrode TiN is prepared on the gating layer and the isolation layer to complete the device preparation.

[0026] A 1T1S1R unit is provided. The R terminal of the 1S1R memory unit is connected to the drain or source of a transistor T. The transistor T is a standardized transistor, so as to form a memory 1T1S1R unit.

[0027] A memory array is formed by using the 1T1S1R unit, wherein the gates of transistors in the 1T1S1R in the same row of the array are connected by a word line, the sources of transistors in the 1T1S1R in the same column are connected by a source line, and the gate terminals of transistors in the 1T1S1R in the same column are connected by a bit line.

[0028] The technical effects of the present invention are as follows:

[0029] The present invention discloses a novel memory cell and a preparation method thereof. In the preparation of a 1S1R memory cell, when the resistor is RRAM, the effective growth area of ​​the gate layer material and the RRAM resistive switching layer material is designed, that is, two coarse and fine grooves connected up and down are formed by two times of photolithography and etching, the coarse groove is located above the fine groove, and the bottom surface area of ​​the coarse groove is larger than the top surface area of ​​the fine groove, so that the effective contact area of ​​the gate tube and the resistive switching memory is different, and gate tubes with different current driving capabilities are prepared, ensuring that the gate tube can provide sufficient current density, which is beneficial to the resistive switching layer and the gate layer. When the resistor is a common resistor, the ideal window matching of the gate tube and the RRAM in different resistance states is simulated by setting different resistance values; the introduction of an intermediate connection layer between the gate layer and the resistive switching layer can solve the problem of mutual diffusion of the gate layer material and the resistive switching layer material components, improve the performance consistency between different devices, and facilitate large-scale integrated applications; the 1S1R memory unit is connected in series with the transistor to form a memory 1T1S1R unit, and the actual electrical performance of the nano-sized gate tube can be accurately measured through the control of the current by the transistor T. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic diagram of the longitudinal cross-section structure of a 1S1R memory cell in a specific embodiment 1 of the present invention;

[0031] Figure 2 This is a process flow chart of preparing a 1S1R memory unit in a specific embodiment 1 of the present invention;

[0032] Figure 3 It is a schematic diagram of the longitudinal cross-section structure of a 1S1R memory cell in a second specific embodiment of the present invention;

[0033] Figure 4 This is a process flow chart of preparing a 1S1R memory unit in the second specific embodiment of the present invention;

[0034] Figure 5 It is a schematic diagram of the longitudinal cross-section structure of a 1S1R memory cell in a third specific embodiment of the present invention;

[0035] Figure 6 This is a process flow chart of preparing a 1S1R memory unit in the third specific embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of a 1T1S1R unit in a specific embodiment of the present invention;

[0037] Figure 8 Schematic diagram of a 1T1S1R array in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0039] The novel memory unit of the present invention comprises a gate tube S and a resistor R, the gate tube S and the resistor R are connected in series to form a 1S1R memory unit, the resistor R performs current limiting protection on the gate tube S, and the resistor R is a common resistor or a resistive random access memory RRAM. The 1S1R memory unit comprises a bottom electrode, an isolation layer, a resistive random access layer, a gate layer and a top electrode stacked in sequence on a substrate, wherein the isolation layer comprises a coarse groove and a fine groove connected up and down, the coarse groove is located above the fine groove, the gate layer material is filled in the coarse groove to form a gate layer, and the resistive random access layer material is filled in the fine groove to form a resistive random access layer, and the bottom surface area of ​​the coarse groove is larger than the top surface area of ​​the fine groove.

[0040] Three specific embodiments of the novel memory cell and the method for manufacturing the same are given below.

[0041] Embodiment 1

[0042] Figure 1 and Figure 2 A specific embodiment of the novel memory cell and its preparation method of the present invention is given, wherein the bottom electrode material is W and the gate layer material is NbO x , the resistive layer material is TaO x , the top electrode material is TiN, and the isolation layer material is Si3N4. The longitudinal cross-sectional structure diagram of the 1S1R memory cell is shown in Figure 1 As shown, on the substrate, the bottom electrode, the isolation layer, the resistive layer, the gating layer and the top electrode are stacked in sequence, and the isolation layer includes two grooves of different sizes connected up and down: a coarse groove and a fine groove, the coarse groove is located above the fine groove, the fine groove is filled with the resistive layer, and the coarse groove is filled with the gating layer, and on the contact surface between the resistive layer and the gating layer, the bottom surface area of ​​the gating layer is larger than the top surface area of ​​the resistive layer. The gating layer has a larger effective area than the resistive layer, so that the gating tube can provide a greater driving capability. By designing the effective growth area of ​​the gating layer and the resistive layer, a gating tube with different current driving capabilities can be prepared, which is beneficial to the performance matching of the resistive layer and the gating layer.

[0043] The manufacturing process of 1S1R memory cell is as follows: Figure 2 The specific description is as follows:

[0044] 1) A bottom electrode W with a thickness of 50 nm is prepared on the substrate by physical vapor deposition (PVD).

[0045] 2) A 100 nm thick isolation layer Si3N4 was prepared on the bottom electrode by plasma enhanced chemical vapor deposition (PECVD).

[0046] 3) Spin-coat a layer of photoresist on the isolation layer.

[0047] 4) Exposure to achieve patterning and form a first photolithography pattern on the photoresist.

[0048] 5) Reactive ion etching is performed on the isolation layer, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50 nm.

[0049] 6) Spin-coat a layer of photoresist on the isolation layer.

[0050] 7) Exposure to achieve patterning and form a second photolithography pattern on the photoresist.

[0051] 8) The isolation layer is subjected to reactive ion etching, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50nm. After this step, two coarse and fine grooves of different areas are formed in the isolation layer, with a cross-sectional diameter of 500nm. The fine groove is the growth area of ​​the resistive layer, and the coarse groove is the growth area of ​​the gating layer.

[0052] 9) Use PVD to deposit a 50nm thick resistive layer material TaO x , fill the fine grooves. And use chemical mechanical polishing (CMP) to remove excess TaO on the surface x , make the surface smooth.

[0053] 10) Depositing a gate layer material NbO with a thickness of 50 nm on the resistive layer by PVD x , fill the rough grooves. And use CMP grinding to remove the excess NbO on the surface x , make the surface smooth.

[0054] 11) A top electrode TiN with a thickness of 50 nm is deposited on the gating layer and the isolation layer by PVD to complete the device preparation.

[0055] Embodiment 2

[0056] Figure 3 and Figure 4 Another specific embodiment of the novel memory cell and its preparation method of the present invention is given, wherein the bottom electrode material is W and the gate layer material is NbO x , the middle connection layer material is Graphite, the resistive layer material is TaO x , the top electrode material is TiN, the isolation layer material is Si3N4, and the longitudinal cross-sectional structure diagram of the 1S1R memory unit is shown in FIG. Figure 3 As shown, compared Figure 1, an intermediate connection layer is added between the gating layer and the resistive switching layer, and the intermediate connection layer is at the bottom of the rough trench, and its top surface area is equal to the bottom surface area of ​​the gating layer. Based on the same inventive concept, this embodiment provides a 1S1R, which can solve the problem of mutual diffusion of the gating layer material and the resistive switching layer material components, improve the performance consistency between different devices, and is conducive to large-scale integrated applications.

[0057] The manufacturing process of 1S1R memory cell is as follows: Figure 4 The specific description is as follows:

[0058] 1) A bottom electrode W with a thickness of 50 nm is prepared on the substrate by physical vapor deposition (PVD).

[0059] 2) A 100 nm thick isolation layer Si3N4 was prepared on the bottom electrode by plasma enhanced chemical vapor deposition (PECVD).

[0060] 3) Spin-coat a layer of photoresist on the isolation layer.

[0061] 4) Exposure to achieve patterning and form a first photolithography pattern on the photoresist.

[0062] 5) Reactive ion etching is performed on the isolation layer, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50 nm.

[0063] 6) Spin-coat a layer of photoresist on the isolation layer.

[0064] 7) Exposure to achieve patterning and form a second photolithography pattern on the photoresist.

[0065] 8) The isolation layer is subjected to reactive ion etching, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50nm. After this step, two coarse and fine grooves of different areas are formed in the isolation layer, with a cross-sectional diameter of 500nm. The fine groove is the growth area of ​​the resistive layer, and the coarse groove is the growth area of ​​the gating layer.

[0066] 9) Use PVD to deposit a 50nm thick resistive layer material TaO x , fill the fine grooves. And use chemical mechanical polishing (CMP) to remove excess TaO on the surface x , make the surface smooth.

[0067] 10) Depositing a 10 nm intermediate connection layer of Graphite on the resistive layer by chemical vapor deposition (CVD) to fill the bottom of the rough groove, and performing CMP polishing to remove excess Graphite on the surface to make the surface flat.

[0068] 11) Deposit a gate layer material NbO with a thickness of 40 nm on the intermediate connection layer by PVD. x , fill the rest of the rough trench. And use CMP grinding to remove the excess NbO on the surface x , make the surface smooth.

[0069] 12) A top electrode TiN with a thickness of 50 nm is deposited on the gating layer and the isolation layer by PVD to complete the device preparation.

[0070] Embodiment 3

[0071] Figure 5 and Figure 6 Another specific embodiment of the novel memory cell and its preparation method of the present invention is given, in which the bottom electrode material is W and the gate layer material is NbO x , the middle connection layer material is Graphite, the resistive layer material is TaO x , the top electrode material is TiN, the isolation layer material is Si3N4, and the longitudinal cross-sectional structure diagram of the 1S1R memory unit is shown in FIG. Figure 5 As shown, compared Figure 1 , an intermediate connection layer is added between the gating layer and the resistive switching layer, and the intermediate connection layer is at the top of the fine groove, and its bottom surface area is equal to the top surface area of ​​the resistive switching layer. Based on the same inventive concept of the second embodiment, this embodiment provides a 1S1R, which can solve the problem of mutual diffusion of the gating layer material and the resistive switching layer material components compared with the first embodiment, improve the performance consistency between different devices, and is conducive to large-scale integrated applications.

[0072] The manufacturing process of 1S1R memory cell is as follows: Figure 6 The specific description is as follows:

[0073] 1) A bottom electrode W with a thickness of 50 nm is prepared on the substrate by physical vapor deposition (PVD).

[0074] 2) A 100 nm thick isolation layer Si3N4 was prepared on the bottom electrode by plasma enhanced chemical vapor deposition (PECVD).

[0075] 3) Spin-coat a layer of photoresist on the isolation layer.

[0076] 4) Exposure to achieve patterning and form a first photolithography pattern on the photoresist.

[0077] 5) Reactive ion etching is performed on the isolation layer, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50 nm.

[0078] 6) Spin-coat a layer of photoresist on the isolation layer.

[0079] 7) Exposure to achieve patterning and form a second photolithography pattern on the photoresist.

[0080] 8) The isolation layer is subjected to reactive ion etching, using CF4 to etch the area not covered by the photoresist, with an etching depth of 50nm. After this step, two coarse and fine grooves of different areas are formed in the isolation layer, with a cross-sectional diameter of 500nm. The fine groove is the growth area of ​​the resistive layer, and the coarse groove is the growth area of ​​the gating layer.

[0081] 9) Using PVD to deposit a 40nm thick resistive layer material TaO x , fill the bottom of the fine groove. And use chemical mechanical polishing (CMP) to remove excess TaO on the surface x , make the surface smooth.

[0082] 10) Depositing a 10 nm intermediate connection layer of Graphite on the resistive layer by chemical vapor deposition (CVD) to fill the rest of the fine grooves, and performing CMP polishing to remove excess Graphite on the surface to make the surface smooth.

[0083] 11) Deposit a gating layer material NbO with a thickness of 50 nm on the intermediate connection layer by PVD. x , fill the rough grooves. And use CMP grinding to remove the excess NbO on the surface x , make the surface smooth.

[0084] 12) A top electrode TiN with a thickness of 50 nm is deposited on the gating layer and the isolation layer by PVD to complete the device preparation.

[0085] The cross-sectional diameter of the fine groove is between 50nm and 10um.

[0086] The isolation layer material is a low dielectric material, which may be selected from silicon nitride Si3N4, silicon oxide SiO2, silicon fluoride oxide FSG, polyimide, interstitial silicon oxide, silicon oxide nanopile, silicon carbide SiC, etc.

[0087] The preparation process of the bottom electrode, top electrode, gating layer, resistive layer and intermediate connection layer can adopt physical vapor deposition PVD, atomic layer deposition ALD, or chemical vapor deposition process CVD, including atmospheric pressure chemical vapor deposition, APCVD, plasma enhanced chemical vapor deposition PECVD or low pressure chemical vapor deposition LPCVD.

[0088] The R end of the 1S1R unit of the present invention is connected to the drain or source of the transistor T to form a memory 1T1S1R unit. At this time, the transistor T is connected in series with the gate tube S. The electrical characteristics of the nano-sized gate tube are measured by controlling the current of the transistor T, such as Figure 7As shown, a gate tube (S), a resistor (R) and a transistor (T) are connected in series, and the transistor T is a standardized transistor. The three are connected in series to form a memory 1T1S1R unit.

[0089] The array structure composed of 1T1S1R units is as follows Figure 8 As shown, the gates of transistors in the same row of 1T1S1R in the array are connected by a word line, the sources of transistors in the same column of 1T1S1R are connected by a source line, and the gate terminals of transistors in the same column of 1T1S1R are connected by a bit line.

[0090] The operation method of the array composed of 1T1S1R units is as follows, taking the operation of the unit in row 0 and column 0 as an example:

[0091] Reading: Set the word line voltage of row 0 to a specific value for reading, turn on the transistor, and apply a read voltage to the bit line of column 0; turn off the word lines of other rows; set the bit lines of other columns to zero level; and set all source lines to zero level. Subtract the voltage division of the transistor and the resistor from the read voltage to get the actual voltage division of the strobe of row 0 and column 0. The bit lines of multiple columns can be selected at the same time, that is, the read voltage is applied to the bit lines of the selected columns to achieve parallel reading.

[0092] Writing: Turn on the transistor in row 0 and apply a write voltage to the bit line in column 0; turn off the word lines in other rows and set the bit lines in other columns to zero level; set all source lines to zero level. During the writing process, the current of the strobe in row 0 and column 0 is controlled by changing the gate voltage of the transistor in row 0, and the voltage at both ends of the strobe is controlled by changing the bit line voltage in column 0, so that a more accurate resistance value can be written while limiting the current.

[0093] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A 1S1R memory cell, comprising a bottom electrode, an isolation layer, a resistive switching layer, a gate layer and a top electrode stacked in sequence on a substrate, characterized in that: The isolation layer includes a coarse groove and a fine groove connected vertically. The coarse groove is located above the fine groove. The coarse groove is filled with a gating layer material to form a gating layer. The fine groove is filled with a resistive layer material to form a resistive layer. The bottom surface area of ​​the coarse groove is larger than the top surface area of ​​the fine groove.

2. The 1S1R memory cell according to claim 1, wherein: An intermediate connection layer is inserted between the resistive layer and the gate layer, and the intermediate connection layer material is vanadium V, niobium Nb, ruthenium Ru, tungsten W, tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN, titanium tungsten TiW, aluminum Al, titanium aluminum tungsten TiAlW, yttrium Ir yttrium oxide IrO2, indium tin oxide ITO, aluminum titanium nitride TiAlN, aluminum nitride AlN x , aluminum titanium nitride TiAlN or AlTiN, hafnium Hf, iridium Ir, manganese Mn, zinc Zn, platinum Pt, palladium Pd, copper Cu or one or more of the alloys of the above materials; or carbon nanotubes CNTs, graphene G, graphite Graphite, silicon carbide SiC, tellurium carbide TeC, tellurium carbon sulfide TeCS any one or more; or selected from molybdenum sulfide MoS2, tungsten sulfide WS2, molybdenum telluride MoTe, indium gallium zinc oxide IGZO, indium aluminum zinc oxide IAZO, tin-doped indium oxide ITO, manganese telluride MnTe, tungsten telluride WTe, zinc-doped indium oxide IZO at least one; the thickness of the intermediate connecting layer is between 1 and 50 nm.

3. The 1S1R memory cell according to claim 2, characterized in that The intermediate connection layer is located at the bottom of the rough trench, and the top surface area of ​​the intermediate connection layer is equal to the bottom surface area of ​​the gate layer.

4. The 1S1R memory cell according to claim 2, characterized in that The intermediate connection layer is located at the top of the fine groove, and the bottom surface area thereof is equal to the top surface area of ​​the resistive switching layer.

5. The 1S1R memory cell according to claim 1, wherein: The resistive layer material is tantalum oxide TaO x , titanium oxide TiO x 、HfO x 、ZrO x 、Silicon oxide SiO x , magnesium oxide MgO, aluminum nitride AlN x 、GeTe x , scandium antimony telluride ScSbTe, indium silver antimony telluride InAgSbTe, germanium antimonide GeSb, germanium telluride GeTe, antimony telluride SbTe, copper sulfide CuS x 、GeS x , Germanium selenide GeSe x , zinc sulfide ZnS, aluminum borate AlBO; or the material of the resistive layer is selected from strontium titanate SrTiO x 、Zirconium titanate ZrTiO x , barium titanate BaTiO x , at least one of hafnium zirconium oxide HfZrO, and hafnium aluminum oxide HfAlO; the resistive layer is a single-layer structure composed of one material or a multi-layer structure of multiple materials; if the resistive layer is replaced by an ordinary resistor, the material is polysilicon, or polysilicon doped with phosphorus P, arsenic As or boron B, or one or more of aluminum Al, hafnium Hf, manganese Mn, zinc Zn, copper Cu or alloys of the above materials, and the thickness of the resistive layer is between 5 and 100 nm.

6. The 1S1R memory cell according to claim 1, wherein: The gating layer material is a metal oxide or a semiconductor oxide material, including niobium oxide NbO x 、Vanadium oxide VO x , titanium oxide TiO x 、Silicon oxide SiO x 、ZrO x , Yttrium oxide YO x 、GeTe x , Germanium selenide GeSe x 、Iron Oxide FeO x 、NdNiO x 、SmNiO x 、LaCoO x , GdCoO x materials, and one or more of their alloys; the thickness of the gating layer is between 5 and 100 nm.

7. The 1S1R memory cell according to claim 1, wherein: The materials of the bottom electrode and the top electrode are vanadium V, niobium Nb, ruthenium Ru, tungsten W, tantalum Ta, tantalum nitride TaN, titanium Ti, titanium nitride TiN, titanium tungsten TiW, aluminum Al, titanium aluminum tungsten TiAlW, yttrium Ir yttrium oxide IrO2, indium tin oxide ITO, aluminum titanium nitride TiAlN, aluminum nitride AlN x , aluminum titanium nitride TiAlN or AlTiN, hafnium Hf, iridium Ir, manganese Mn, zinc Zn, platinum Pt, palladium Pd, copper Cu or one or more of the alloys of the above materials; or any one or more of carbon nanotubes CNTs, graphene G, graphite Graphite, silicon carbide SiC, tellurium carbide TeC, and tellurium carbon sulfide TeCS; or at least one selected from molybdenum sulfide MoS2, tungsten sulfide WS2, molybdenum telluride MoTe, indium gallium zinc oxide IGZO, indium aluminum zinc oxide IAZO, tin-doped indium oxide ITO, manganese telluride MnTe, tungsten telluride WTe, and zinc-doped indium oxide IZO.

8. A method for preparing a 1S1R memory cell as claimed in claim 1, characterized in that: Here are the steps: 1) preparing a bottom electrode on a substrate; 2) preparing an isolation layer on the bottom electrode; 3) Spin-coat a layer of photoresist on the isolation layer; 4) Exposure to achieve patterning and form a first photolithography pattern on the photoresist; 5) performing reactive ion etching on the isolation layer to etch the area not covered by the photoresist and remove the photoresist; 6) Spin-coat a layer of photoresist on the isolation layer; 7) Exposure to achieve patterning and form a second photolithography pattern on the photoresist; 8) performing reactive ion etching on the isolation layer to etch the area not covered by the photoresist and remove the photoresist; after this step, a coarse groove and a fine groove connected up and down are formed in the isolation layer; 9) Fill the fine grooves with resistive switching layer material, and grind away excess resistive switching layer material on the surface to make the surface smooth; 10) Filling the rough groove with a gate layer material, and grinding and removing the excess gate layer material on the surface to make the surface flat; 11) A top electrode TiN is prepared on the gating layer and the isolation layer to complete the device preparation.

9. A 1T1S1R unit, characterized in that: The R terminal of the 1S1R memory cell as claimed in claim 1 is connected to the drain or source of a transistor T, wherein the transistor T is a standardized transistor, to form a memory 1T1S1R cell.

10. A memory array, characterized in that: The 1T1S1R unit as claimed in claim 9 is used to form an array, wherein the gates of transistors in the 1T1S1R in the same row of the array are connected by word lines, the sources of transistors in the same column of 1T1S1R are connected by source lines, and the gate terminals of transistors in the same column of 1T1S1R are connected by bit lines.

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