A memory system and its operation method, and a computer-readable storage medium

Abstract

The present disclosure provides a memory system, an operating method thereof, and a computer-readable storage medium. The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; each non-volatile memory device includes multiple memory blocks, and at least one memory block in at least one non-volatile memory device forms a super block; the controller is configured to: determine an order of the multiple super blocks based on the number of erase times of each super block and the number of bad blocks in each super block; the number of erase times of any two adjacent super blocks in the order meets a preset requirement; a first super block in the order is set at an interval, and the number of bad blocks in the first super block is greater than a preset value; and a priority for performing write operations on the multiple super blocks is determined based on the order of the multiple super blocks.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory system and its operation method, and a computer-readable storage medium. Background Technology

[0002] Memory systems, such as solid-state drives (SSDs), can use flash memory, dynamic random access memory (DRAM), or 3D magnetic storage (3D XPoint) as storage media. The Flash Translation Layer (FTL) maps the logical block addresses (LBAs) of the host computer to the physical block addresses (PBAs) of the flash memory. In other words, the FTL requires a mapping table from LBAs to PBAs. This mapping table needs to be looked up and updated in real time throughout the SSD's read and write processes to ensure correct data reading and writing. Therefore, the quality of the FTL algorithm directly determines the performance, reliability, and endurance of the memory system (e.g., SSD).

[0003] Proper planning and use of storage devices in a memory system can optimize the FTL algorithm, which is crucial for achieving high performance and low power consumption in memory systems (e.g., SSDs). Inadequate management of storage devices in a memory system can lead to significant performance fluctuations. Summary of the Invention

[0004] This disclosure provides a memory system and its operation method, as well as a computer-readable storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a memory system, the memory system including at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device forms a superblock; the controller is configured to:

[0006] The order of multiple superblocks is determined based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblocks in the order are set at intervals, and the number of bad blocks within the first superblocks is greater than a preset value;

[0007] The priority of write operations on the multiple superblocks is determined based on their order.

[0008] In some embodiments, the controller is specifically configured to:

[0009] In the sorting process, the higher the ranking of the superblock, the higher the priority of the write operation on that superblock; wherein, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is less than or equal to the erase count of the superblock ranking later in the sorting process; or, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is greater than the erase count of the superblock ranking later in the sorting process, and the difference between the erase counts of the two superblocks is less than a preset difference; or...

[0010] The higher the superblock is in the sorting, the lower the priority of writing to the superblock; wherein, in the sorting, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, in the sorting, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

[0011] In some embodiments, the controller is specifically configured to:

[0012] Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, the multiple superblocks are arranged in ascending or descending order of the number of erases.

[0013] In some embodiments, the controller is specifically configured to:

[0014] Based on the pre-sorting of the multiple superblocks, at least two adjacent first superblocks are determined;

[0015] Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine a first sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets a preset requirement; and the first superblocks in the first sub-sorting are not set adjacent to each other.

[0016] In some embodiments, the plurality of superblocks further includes a second superblock and a third superblock; wherein the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third superblock is equal to 0.

[0017] In the first sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the first sub-sorting, the first superblock and the third superblock are arranged adjacently.

[0018] In some embodiments, the controller is specifically configured to:

[0019] Based on the first sub-sorting of the multiple superblocks, the first superblock and the second superblock that are set up adjacently are determined;

[0020] Based on the number of bad blocks in the first superblock and the second superblock, the order or position of the first superblock and the second superblock is adjusted to determine a second sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first superblock and the second superblock are not set adjacent to each other in the second sub-sorting.

[0021] In some embodiments, the two second superblocks in the second sub-sorting are arranged adjacently; or, the first superblock and the third superblock in the second sub-sorting are arranged adjacently; or, the second superblock and the third superblock in the second sub-sorting are arranged adjacently.

[0022] In some embodiments, the controller is specifically configured to:

[0023] Based on the second sub-sorting of the multiple superblocks, at least two adjacent second superblocks are determined;

[0024] Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of the multiple superblocks; wherein, the second superblocks are not arranged adjacently in the sorting.

[0025] In some embodiments, the second superblock and the third superblock are arranged adjacently in the sorting.

[0026] In some embodiments, the superblock includes a free block.

[0027] Secondly, embodiments of this disclosure provide an operation method for a memory system, the memory system including at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device forms a superblock; the operation method includes:

[0028] The order of multiple superblocks is determined based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblocks in the order are set at intervals, and the number of bad blocks within the first superblocks is greater than a preset value;

[0029] The priority of write operations on the multiple superblocks is determined based on their order.

[0030] In some embodiments, determining the priority of write operations on the plurality of superblocks based on their order includes:

[0031] In the sorting process, the higher the ranking of the superblock, the higher the priority of the write operation on that superblock; wherein, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is less than or equal to the erase count of the superblock ranking later in the sorting process; or, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is greater than the erase count of the superblock ranking later in the sorting process, and the difference between the erase counts of the two superblocks is less than a preset difference; or...

[0032] The higher the superblock is in the sorting, the lower the priority of writing to the superblock; wherein, in the sorting, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, in the sorting, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

[0033] In some embodiments, before determining the order of the multiple superblocks based on the number of erases per superblock and the number of bad blocks within each superblock, the operation method further includes:

[0034] Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, the multiple superblocks are arranged in ascending or descending order of the number of erases.

[0035] In some embodiments, after determining the pre-sorting of the multiple superblocks based on the number of erases for each superblock, the operation method further includes:

[0036] Based on the pre-sorting of the multiple superblocks, at least two adjacent first superblocks are determined;

[0037] Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine a first sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets a preset requirement; and the first superblocks in the first sub-sorting are not set adjacent to each other.

[0038] In some embodiments, the plurality of superblocks further includes a second superblock and a third superblock; wherein the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third superblock is equal to 0.

[0039] In the first sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the first sub-sorting, the first superblock and the third superblock are arranged adjacently.

[0040] In some embodiments, after adjusting the order or position of the first superblock according to the number of bad blocks within the first superblock to determine the first sub-sorting of the multiple superblocks, the operation method further includes:

[0041] Based on the first sub-sorting of the multiple superblocks, the first superblock and the second superblock that are set up adjacently are determined;

[0042] Based on the number of bad blocks in the first superblock and the second superblock, the order or position of the first superblock and the second superblock is adjusted to determine a second sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first superblock and the second superblock are not set adjacent to each other in the second sub-sorting.

[0043] In some embodiments, the two second superblocks in the second sub-sorting are arranged adjacently; or, the first superblock and the third superblock in the second sub-sorting are arranged adjacently; or, the second superblock and the third superblock in the second sub-sorting are arranged adjacently.

[0044] In some embodiments, after adjusting the order or position of the first superblock and the second superblock according to the number of bad blocks in the first superblock and the second superblock to determine a second sub-sorting of the multiple superblocks, the operation method further includes:

[0045] Based on the second sub-sorting of the multiple superblocks, at least two adjacent second superblocks are determined;

[0046] Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of the multiple superblocks; wherein, the second superblocks are not arranged adjacently in the sorting.

[0047] In some embodiments, the second superblock and the third superblock are arranged adjacently in the sorting.

[0048] In some embodiments, the superblock includes a free block.

[0049] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed, can implement the operation method of the memory system as described in the above technical solutions.

[0050] This disclosure provides a memory system and its operation method, as well as a computer-readable storage medium. In this disclosure, by simultaneously considering the number of erases on the superblock and the number of bad blocks within the superblock, the priority of write operations on the superblock is determined, which can effectively smooth write performance and enhance the performance stability of the memory system. Attached Figure Description

[0051] Figure 1 This is a block diagram of a system having a non-volatile storage device as shown in an embodiment of the present disclosure;

[0052] Figure 2A This is a schematic diagram of a memory card having a non-volatile storage device, as shown in an embodiment of this disclosure;

[0053] Figure 2B This is a schematic diagram of a solid-state drive with a non-volatile storage device shown in an embodiment of this disclosure;

[0054] Figure 3 This is a schematic diagram of a non-volatile memory device including peripheral circuitry, as shown in an embodiment of this disclosure;

[0055] Figure 4 This is a schematic cross-sectional view of a storage cell array including storage strings, as shown in an embodiment of this disclosure.

[0056] Figure 5 This is a block diagram of a non-volatile memory device including peripheral circuitry, as shown in an embodiment of this disclosure.

[0057] Figure 6 A flowchart illustrating the operation method of the memory system provided in this embodiment of the disclosure;

[0058] Figure 7 A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0059] Figure 8 A schematic diagram of a superblock provided in an embodiment of this disclosure;

[0060] Figure 9 The ordering of superblocks provided for a specific example;

[0061] Figure 10 The ordering of superblocks provided for another specific example;

[0062] Figure 11 This is a graph showing the write rate of each superblock in the sorting process. Detailed Implementation

[0063] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0064] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0065] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0066] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0067] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0068] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0069] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0070] The non-volatile storage devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type non-volatile storage devices. For ease of understanding, a three-dimensional NAND type non-volatile storage device will be used as an example for explanation.

[0071] refer to Figure 1 , Figure 1 This is a block diagram of a system having a non-volatile storage device, as shown in an embodiment of this disclosure. Figure 1 As shown, system 100 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having non-volatile storage.

[0072] like Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more non-volatile storage devices 104 and a controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the non-volatile storage device 104.

[0073] In some embodiments, controller 106 is coupled to nonvolatile storage device 104 and host 108, and is configured to control nonvolatile storage device 104. Controller 106 can manage data stored in nonvolatile storage device 104 and communicate with host 108.

[0074] In some embodiments, the controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0075] In some embodiments, the controller 106 is designed to operate in a high duty cycle environment in an SSD or embedded Multi-Media Card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0076] Controller 106 can be configured to control the operation of non-volatile storage device 104, such as read, erase, and program operations. Controller 106 can also be configured to manage various functions relating to data stored or to be stored in non-volatile storage device 104, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 106 is also configured to process error correcting codes (ECCs) relating to data read from or written to non-volatile storage device 104.

[0077] Controller 106 may also perform any other suitable functions, such as formatting non-volatile storage device 104. Controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0078] The controller 106 and one or more non-volatile storage devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0079] refer to Figure 2A , Figure 2A This is a schematic diagram of a memory card with a non-volatile storage device, as shown in an embodiment of this disclosure. Figure 2A As shown, controller 106 and a single non-volatile storage device 104 can be integrated into memory card 202. Memory card 202 may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., MMC, Reduced-Size MMC (RS-MMC), Micro MMC (MMCmicro)), SD cards (e.g., SD, MiniSD, MicroSD, Secure Digital High Capacity (SDHC)), UFS, etc. Memory card 202 may also include a connection between memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0080] refer to Figure 2B , Figure 2B This is a schematic diagram of a solid-state drive with a non-volatile storage device, as shown in an embodiment of this disclosure. Figure 2B As shown, controller 106 and multiple non-volatile storage devices 104 can be integrated into solid-state drive 206. Solid-state drive 206 may also include a connection between solid-state drive 206 and a host (e.g., Figure 1 The solid-state drive connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0081] refer to Figure 3 , Figure 3 This is a schematic diagram illustrating a non-volatile memory device including peripheral circuitry, as shown in an embodiment of this disclosure. The non-volatile memory device 300 may be... Figure 1An example of a non-volatile memory device 104 is provided. A non-volatile memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0082] In some embodiments, each memory cell 306 may be a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, an SLC may have a first memory state "1" and a second memory state "0", where the threshold voltage distribution of the first memory state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second memory state "0" may correspond to a second voltage range. The first memory state is an erase state, and the second memory state is a programmable state. In some embodiments, each memory cell 306 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0083] like Figure 3As shown, each memory string 308 may include a source-selective transistor (SST) 310 at its source end and a drain-selective transistor (DST) 312 at its drain end. The source-selective transistor 310 and drain-selective transistor 312 may be configured to activate a selected memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via the same source line (SL) 314 (e.g., common SL). In other words, in some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). In some embodiments, the drain of the drain-selective transistor 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the drain select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding drain select transistor 312 via one or more drain selective lines (DSL) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the source select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding source select transistor 310 via one or more source selective lines (SSL) 315.

[0084] like Figure 3As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a source line 314 (e.g., a common SL coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase a memory cell 306 in a selected memory block, an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a memory page 320 of a memory cell 306. Each word line 318 may include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320 and gate lines coupling the control gates.

[0085] It should be noted that, Figure 3 The illustrated storage page is a physical page, referring to a storage unit at the physical layer. The basic data unit for programming and reading operations is the logical page. For SLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 1 logical page. For MLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 2 logical pages. For TLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 3 logical pages. For QLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 4 logical pages.

[0086] refer to Figure 4 , Figure 4 This is a schematic cross-sectional view of a storage cell array including storage strings, as shown in an embodiment of this disclosure. Figure 4As shown, the memory string 308 may extend vertically through the memory stack layer 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0087] The memory stack 404 may include alternating gate conductive layers 406 and gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the memory cell 306 and may extend laterally at the top of the memory stack 404 as a drain select gate line 313, laterally at the bottom of the memory stack 404 as a source select gate line 315, or laterally between the drain select gate line 313 and the source select gate line 315 as a word line 318.

[0088] like Figure 4 As shown, the memory string 308 includes a channel structure extending vertically through the memory stack layer 404. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trap / memory layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0089] According to some embodiments, a well (e.g., a P-well and / or an N-well) may be formed in the substrate 402, and the source terminal of the memory string 308 may be in contact with the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string may also include a channel plug at the drain terminal of the memory string 308. It should be understood that, although in Figure 4 Additional components, not shown, but which may form the memory cell array 301, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0090] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, source-select-gate line 315, and drain-select-gate line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, source-select-gate line 315, and drain-select-gate line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0091] refer to Figure 5 , Figure 5 This is a block diagram of a non-volatile memory device including peripheral circuitry, as shown in an embodiment of this disclosure. Figure 5 As shown, the peripheral circuitry includes a page buffer / sensor amplifier 504, a column driver / bit line driver 506, a row driver / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface (I / F) 516, and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 5 Additional peripheral circuitry not shown.

[0092] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column driver / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0093] The row driver / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row driver / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row driver / word line driver 508 can also select / deselect and drive source select gate line 315 and drain select gate line 313. As described in detail below, the row driver / word line driver 508 is configured to perform an erase operation on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0094] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer slave devices (…). Figure 5The interface 516 receives control commands (not shown) and relays them to the control logic unit 512, and buffers status information received from the control logic unit 512 and relays it to the host. The interface 516 can also be coupled to the column driver / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer to buffer data and relay it to or from the memory cell array 301.

[0095] Proper planning and utilization of storage devices in a memory system, which optimizes the FTL (Fulfilled Time Tracking) algorithm, is crucial for achieving high performance and low power consumption in SSDs. Inadequate management of storage devices in a memory system can lead to significant performance fluctuations. Currently, inadequate management of storage devices in memory systems is a common problem in the industry. This is mainly due to the complexity of the management process; the classification and sorting of storage devices in a memory system require integration with FTL to maximize benefits. Proper planning and utilization of storage devices in a memory system can be achieved by managing them at the superblock level.

[0096] In view of the above, embodiments of the present disclosure provide a memory system and its operation method, as well as a computer-readable storage medium.

[0097] refer to Figure 6 , Figure 6 This is a flowchart illustrating an operation method of a memory system provided in an embodiment of this disclosure. (See also...) Figure 7 , Figure 7 A schematic diagram of a memory system provided for an embodiment of this disclosure. (See diagram below.) Figure 6 and Figure 7 As shown, this disclosure provides an operation method for a memory system 102, which includes at least one non-volatile memory device 104 and a controller 106 coupled to the non-volatile memory device 104; wherein the non-volatile memory device 104 includes a plurality of memory blocks, and at least one memory block within the at least one non-volatile memory device 104 forms a superblock; the operation method includes:

[0098] S601: Determine the order of multiple superblocks based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein, the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblock interval is set in the order, and the number of bad blocks within the first superblock is greater than a preset value;

[0099] S602: Determine the priority of write operations on multiple superblocks based on their order.

[0100] like Figure 7 As shown, the controller 106 can be connected to multiple non-volatile memory devices 104 via the first channel CH1 and the second channel CH2, respectively. Exemplarily, the non-volatile memory devices 104 can be dies. Specifically, non-volatile memory devices Die_11, Die_12 to Die_1n can be jointly connected to the first channel CH1, and can communicate with the controller 106 via the first channel CH1; non-volatile memory devices Die_21, Die_22 to Die_2n can be jointly connected to the second channel CH2, and can communicate with the controller 106 via the second channel CH2; where n is an integer greater than or equal to 1. This embodiment of the present disclosure does not impose any special limitations on the number of channels or the number of non-volatile memory devices connected to each channel.

[0101] For example, controller 106 can send commands to non-volatile storage device Die_11 via the first channel CH1; wherein the command includes operation type, target data and target address.

[0102] refer to Figure 8 , Figure 8 This is a schematic diagram of a superblock provided in an embodiment of this disclosure. The following will be combined with... Figure 8 The concepts of superblock and the number of bad blocks within a superblock in the embodiments of this disclosure are explained in detail.

[0103] like Figure 8 As shown, in the non-volatile storage devices Die_0 to Die_N, each non-volatile storage device may include one or more storage planes, each storage plane may include multiple storage blocks, and each storage block may include multiple storage pages. Figure 8 The illustration shows that each non-volatile memory device may include two memory planes (i.e., Plane0 and Plane1), and each memory plane may include memory blocks BLK0 to BLKm; where m is an integer greater than or equal to 0. This disclosure does not impose any special limitations on the number of memory planes included in each non-volatile memory device, the number of memory blocks included in each memory plane, or the number of memory pages included in each memory block.

[0104] In some embodiments, the controller may use superblocks to manage non-volatile storage devices Die_0 to Die_N. The controller manages in units of superblocks, and a superblock may include at least one storage block within at least one non-volatile storage device. For example, a superblock may include storage blocks with the same sequence number across all storage planes within all non-volatile storage devices.

[0105] Still Figure 8 As shown, the storage blocks BLK0 included in each storage plane of each of the non-volatile storage devices Die_0 to Die_N can collectively constitute a superblock Super BLK0; the storage blocks BLK1 included in each storage plane of each of the non-volatile storage devices Die_0 to Die_N can collectively constitute a superblock Super BLK1; and the storage blocks BLKm included in each storage plane of each of the non-volatile storage devices Die_0 to Die_N can collectively constitute a superblock Super BLKm. In this way, the non-volatile storage devices Die_0 to Die_N can include superblocks Super BLK0 to Superblock Super BLKm. Of course, the embodiments of this disclosure do not impose a special limitation on the number of storage blocks included in the superblock. For example, a superblock may include storage blocks with the same sequence number in each storage plane of each non-volatile storage device. For example, a superblock may include 2n storage blocks. A superblock may also include storage blocks with the same sequence number in some storage planes of some non-volatile storage devices. For example, a superblock may include 1 storage block, 2 storage blocks, or 4 storage blocks.

[0106] This disclosure does not impose any special limitations on the method of partitioning superblocks. For example, a superblock may include memory blocks with the same sequence number in each memory plane of at least a portion of the non-volatile memory devices coupled to the same channel. For instance, a superblock may include... Figure 7 A superblock may contain memory blocks with the same sequence number in each memory plane of each of the non-volatile memory devices Die_11 to Die_1L (L ≤ n) coupled to the first channel CH1; a superblock may also include Figure 7 The superblock comprises memory blocks with the same index in each storage plane of each of the non-volatile memory devices Die_21 to Die_2L (L less than or equal to n) coupled to the second channel CH2. Exemplarily, the superblock may also include memory blocks with the same index in each storage plane of each non-volatile memory device coupled to different channels; for example, a superblock may include... Figure 7 The non-volatile memory devices Die_11 coupled to the first channel CH1 and Die_21 coupled to the second channel CH2 have memory blocks with the same sequence number in each memory plane of each non-volatile memory device.

[0107] It should be noted that, Figure 8Any storage block shown in the diagram may be a physical bad block, also known as a bad block. In other words, both physical bad blocks and bad blocks belong to the storage block level. For example, BLK1 of the storage plane Plane1 of the non-volatile storage device Die_0 is a physical bad block. The sources of these physical bad blocks mainly include: factory bad blocks and growing bad blocks; factory bad blocks refer to blocks that have some bad blocks from the moment they leave the factory; growing bad blocks refer to blocks that may wear down and become physical bad blocks as the number of erase cycles increases.

[0108] There are two strategies for managing physical bad blocks: the first is the skip strategy, and the second is the replace strategy. The skip strategy means that when a user encounters a physical bad block during a write operation, they skip it and proceed to the next storage block. For example, when writing to the superblock Super BLK0, the more physical bad blocks Super BLK0 contains, the less space Super BLK0 has available for writing, and the lower the write speed for writing to Super BLK0.

[0109] The replacement strategy refers to replacing a physical bad block with a spare storage block when a user encounters a physical bad block during a write operation on a storage block. For example, when writing to the superblock Super BLK0, if Super BLK0 has a physical bad block, a spare storage block is used to replace the physical bad block, and the space available for writing in Super BLK0 remains unchanged.

[0110] In this embodiment, the number of bad blocks within a superblock is the same as the number of physically bad blocks within the superblock, also known as the number of bad storage planes within the superblock. This is because a superblock can include multiple storage blocks. For example, a superblock can include storage blocks with the same sequence number as the storage planes of a non-volatile storage device. For instance, a superblock Super BLK1 can include 2n storage blocks BLK1. If BLK1 of the storage plane Plane1 of the non-volatile storage device Die_0 can be physically bad blocks, then the number of physically bad blocks within the superblock is 1. In other words, for a superblock SuperBLK1, if the storage plane Plane1 of the non-volatile storage device Die_0 can be a bad storage plane, then the number of bad storage planes within the superblock is 1.

[0111] It should be noted that when FTL manages the superblock, it can divide the superblock into free blocks, closed blocks, garbage blocks, and bad blocks. In other words, free blocks, closed blocks, garbage blocks, and bad blocks are all part of the superblock, and each can include multiple storage blocks. The concepts of free blocks, closed blocks, garbage blocks, and bad blocks will be briefly explained below.

[0112] A free block refers to a superblock that can be used for write operations. In this embodiment, when a write operation is required, the superblock with the highest priority for write operations is selected from the superblock ranking as the target superblock, and the target data is written to the target superblock. A closed block refers to a superblock with no remaining storage space or very little remaining storage space. That is, a closed block can only be programmed after the closed block has been erased to free up storage space. A garbage block refers to a superblock that will undergo garbage collection (GC). During garbage collection, valid data in the garbage block needs to be moved to the target superblock, and all data in the garbage block is erased to obtain a new usable superblock, i.e., a free block; or, during garbage collection, valid data in the garbage block is moved to the target superblock, and the garbage block can be marked as a free block. When writing data to such a free block, an erase operation is performed on such a free block first, and then the data is written. An unusable block refers to a superblock that cannot be used normally. A certain number of storage blocks included in an unusable block are considered bad blocks.

[0113] In this embodiment of the disclosure, in S601, sorting the superblocks requires considering two factors simultaneously: the first factor is the number of erases in the superblock, and the second factor is the number of bad blocks within the superblock. Based on the number of erases and the number of bad blocks in the superblock, the order of the multiple superblocks is determined. Regarding the first factor, the number of erases between any two adjacent superblocks in the sorting meets a preset requirement. Regarding the second factor, the first superblock interval is set in the sorting, and the number of bad blocks within the first superblock is greater than a preset value.

[0114] Regarding the first factor, it's important to note that a superblock comprises multiple memory blocks. Each memory block, as the basic data unit for erase operations, causes wear and tear. Therefore, each memory block has a limited lifespan, which can be measured by the number of erase cycles. When a memory block exceeds its lifespan limit, it may develop defects and lose its ability to store electrical charge. Therefore, data should not be written to a few memory blocks in a concentrated manner; otherwise, these blocks will quickly lose their ability to store electrical charge because they have exceeded their lifespan limit. Typically, we expect all memory blocks to distribute data writes evenly, meaning that the wear and tear on each memory block should be roughly the same, thus ensuring the memory system has the maximum data write capacity. Similarly, we expect all superblocks to distribute data writes evenly, meaning that the wear and tear on each superblock should be roughly the same, thus ensuring the memory system has the maximum data write capacity.

[0115] In this embodiment, the number of erases of the superblock is considered as the first factor in the sorting of superblocks. The number of erases between any two adjacent superblocks in the sorting of multiple superblocks must meet a preset requirement. This ensures that the wear level of each superblock is substantially the same, thereby guaranteeing the memory system has the maximum data write capacity. The method for ensuring the number of erases of the superblock meets the preset requirement will be explained in further detail later.

[0116] Regarding the second factor, it should be noted that the more bad blocks there are in a superblock, the less space there is for writing data. When performing a write operation on the superblock, the amount of data that can be written in the same amount of time is less, resulting in a lower write rate and a deterioration in the performance of the memory system.

[0117] In this embodiment, based on the number of bad blocks within a superblock, a preset value is set to divide the superblock into a first superblock, a second superblock, and a third superblock. The number of bad blocks in the first superblock is greater than the preset value; the number of bad blocks in the second superblock is greater than 0 and less than or equal to the preset value; and the number of bad blocks in the third superblock is 0. In short, the first superblock has the most bad blocks, the second superblock has the next most, and the third superblock has no bad blocks. During the sorting process, for two adjacent superblocks, there are five possible scenarios: First, two first superblocks are adjacent; second, the first and second superblocks are adjacent; third, the first and third superblocks are adjacent; fourth, two second superblocks are adjacent; and fifth, the second and third superblocks are adjacent.

[0118] As mentioned above, the write speed for writing to the third superblock is normal, the write speed for writing to the second superblock is next, and the write speed for writing to the first superblock is the worst. Let's set the write speed for writing to the first superblock as the first write speed, the write speed for writing to the second superblock as the second write speed, and the write speed for writing to the third superblock as the third write speed; where the first write speed is less than the second write speed, and the second write speed is less than the third write speed. If two first superblocks are placed adjacent to each other, when writing to the first first superblock, the write speed drops to the first write speed, and when writing to the second first superblock, the write speed remains at the first write speed. This causes the memory system's write speed to suddenly drop to the first write speed and remain there for a considerable period, resulting in significant performance fluctuations in the memory system. More specifically, the impact on memory system performance is most severe when two first superblocks are placed adjacent to each other during write operations.

[0119] It is important to emphasize that, in this embodiment, a preset value can be set to classify superblocks into different types based on the number of bad blocks within them. The purpose of setting a preset value to classify superblocks into different types is to determine the write rate of a superblock based on the number of bad blocks within it. Here, the preset value is not a fixed value; different preset values ​​can be set for different actual situations. The preset value is only used to distinguish the different write rates of different superblocks. For example, the write rate when writing to the first superblock is lower than the write rate when writing to the second superblock.

[0120] For example, the number of superblocks in the sorting process can even reach several hundred, resulting in a very long sorted list of superblocks. Different preset values ​​can be determined for the number of bad blocks within each superblock in the sorting process. For instance, if the number of bad blocks in the first to tenth superblocks ranges from 0 to 5, then a preset value of 3 can be set. In this case, the number of bad blocks in the first superblock > 3, 0 < the number of bad blocks in the second superblock ≤ 3, and the number of bad blocks in the third superblock = 0. As another example, if the number of bad blocks in the 50th to 60th superblocks ranges from 0 to 20, then a preset value of 10 can be set. In this case, the number of bad blocks in the first superblock > 10, 0 < the number of bad blocks in the second superblock ≤ 10, and the number of bad blocks in the third superblock = 0. In this embodiment, the specific preset values ​​are for illustrative purposes only and do not constitute a limitation on the preset values ​​of this disclosure.

[0121] In some embodiments, a first preset value and a second preset value can be set to divide the superblock into four different types based on the number of bad blocks within it; wherein the first preset value is less than the second preset value. Multiple superblocks may include a first superblock, a second superblock, a third superblock, and a fourth superblock; wherein the number of bad blocks in the first superblock is greater than the second preset value; the number of bad blocks in the second superblock is greater than the first preset value and less than or equal to the second preset value; the number of bad blocks in the third superblock is greater than 0 and less than or equal to the first preset value; and the number of bad blocks in the fourth superblock is equal to 0. Of course, more preset values ​​can be set to divide the superblock into more types, thus allowing for more granular operation of the memory system and increasing the complexity of superblock management.

[0122] Another example is setting the first preset value to 5 and the second preset value to 10. In this case, the number of bad blocks in the first superblock is greater than 10, 5 < the number of bad blocks in the second superblock ≤ 10, 0 < the number of bad blocks in the third superblock ≤ 5, and the number of bad blocks in the fourth superblock is 0.

[0123] For ease of explanation, this disclosure describes the case where a superblock is divided into a first superblock, a second superblock, and a third superblock.

[0124] In this embodiment, the number of bad blocks within a superblock is considered as the second factor in the superblock sorting. As mentioned earlier, when two first superblocks are placed adjacently, the impact on memory system performance during write operations is most severe. By spacing the first superblocks in the superblock sorting, a sudden drop in the memory system's write rate will not last for a long time, thus reducing performance fluctuations. Specifically, spacing the first superblocks in the sorting refers to avoiding the situation where two first superblocks are placed adjacently; that is, the first and second superblocks or the first and third superblocks are placed adjacently. The following sections will explain in more detail how to determine the sorting of multiple superblocks based on the number of bad blocks within each superblock.

[0125] In this embodiment of the disclosure, the correspondence between the order of multiple superblocks and the priority of write operations on the multiple superblocks in S602 includes two cases. The priority of write operations on the multiple superblocks refers to the order in which the write operations are performed. In the first case, the earlier a superblock is in the order, the higher the priority of the write operation. In other words, when performing a write operation on a superblock, the superblocks with earlier order are used first, and the write operations are performed sequentially from front to back according to the order of the multiple superblocks. In the second case, the earlier a superblock is in the order, the lower the priority of the write operation. In other words, when performing a write operation on a superblock, the superblocks with later order are used first, and the write operations are performed sequentially from back to front according to the order of the multiple superblocks.

[0126] In this embodiment of the disclosure, the priority of writing operations to the superblock is determined by simultaneously considering the number of erases of the superblock and the number of bad blocks in the memory, which can effectively smooth write performance and enhance the performance stability of the memory system.

[0127] In this embodiment of the disclosure, it can be achieved by improving the FW algorithm in the controller within the memory system without incurring additional costs.

[0128] It should be noted that if multiple superblocks in the sorting process have the same or similar number of erases, and the number of bad blocks within each superblock is large, then when writing to these superblocks sequentially, the write rate will suddenly drop and remain so for a long time, causing significant performance fluctuations in the memory system. In this embodiment, when sorting multiple superblocks, while ensuring the number of erases meets preset requirements, both the number of erases for each superblock and the number of bad blocks within each superblock are considered. This effectively prevents large and prolonged performance fluctuations in the memory system, smooths write performance, and enhances the performance stability of the memory system.

[0129] In some embodiments, determining the priority of write operations on multiple superblocks based on their order includes:

[0130] In the sorting process, the earlier a superblock appears in the order, the higher the priority of write operations on that superblock; specifically, the erase count of the superblock that appears earlier in the sorting is less than or equal to the erase count of the superblock that appears later in the sorting; or, the erase count of the superblock that appears earlier in the sorting is greater than the erase count of the superblock that appears later in the sorting, and the difference in the erase counts between the two superblocks is less than a preset difference; or...

[0131] The higher the superblock is in the sorting, the lower the priority of writing to the superblock; specifically, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

[0132] In this embodiment of the disclosure, in the first case, the higher the superblock's ranking in the sorting, the higher the priority of writing to that superblock. The erase counts of the superblocks in the sorting can be arranged in ascending order, that is, the erase count of the superblock ranked earlier in any two adjacent superblocks is less than or equal to the erase count of the superblock ranked later; or, the erase count of the superblock ranked earlier in any two adjacent superblocks is greater than the erase count of the superblock ranked later, and the difference between the erase counts of the two superblocks is less than a preset difference. In this way, when writing to a superblock, superblocks with fewer erase counts are used as much as possible from front to back, so that the wear level among superblocks is basically the same. Even considering the number of bad blocks within a superblock, when writing to a superblock, superblocks with larger erase counts are used first, followed by superblocks with smaller erase counts, and the difference between the erase counts of these two superblocks is less than a preset difference. This smooths the write performance of the memory system while also ensuring that the wear level among superblocks is basically the same as much as possible.

[0133] In this embodiment of the disclosure, in the second case, the higher the superblock's ranking in the sorting, the lower the priority of writing to that superblock. The erase counts of the superblocks in the sorting can be arranged in descending order, that is, the erase count of the superblock ranked earlier in any two adjacent superblocks is greater than or equal to the erase count of the superblock ranked later; or, the erase count of the superblock ranked earlier in any two adjacent superblocks is less than the erase count of the superblock ranked later, and the difference between the erase counts of the two superblocks is less than a preset difference. In this way, when writing to a superblock, superblocks with fewer erase counts are used as much as possible from back to front, so that the wear level among superblocks is basically the same. Even considering the number of bad blocks within a superblock, when writing to a superblock, superblocks with larger erase counts are used first, followed by superblocks with smaller erase counts, and the difference between the erase counts of these two superblocks is less than a preset difference. This smooths the write performance of the memory system while also ensuring that the wear level among superblocks is basically the same as much as possible.

[0134] In this embodiment of the disclosure, a preset difference can be set based on performance test data of the memory system. For example, the preset difference can be 5. When performing a write operation, a superblock with a larger number of erase cycles (e.g., 10 erase cycles) can be used first, followed by a superblock with a smaller number of erase cycles (e.g., 6 erase cycles), and the difference between the erase cycles of adjacent superblocks is less than the preset difference. If, during a write operation, a superblock with a larger number of erase cycles (e.g., 18 erase cycles) is used first, followed by a superblock with a smaller number of erase cycles (e.g., 6 erase cycles), and the difference between the erase cycles of adjacent superblocks is greater than the preset difference, this may also cause performance fluctuations in the memory system.

[0135] In this embodiment of the disclosure, the order of write operations on the superblocks can be determined based on their priority, i.e., the sequential order of write operations. Furthermore, the number of erases and the number of bad blocks within each superblock can be obtained, and combined with the aforementioned order of the superblocks, a pattern for sorting the multiple superblocks can be derived.

[0136] This disclosure provides a memory system including at least one non-volatile memory device and a controller coupled to the non-volatile memory device. The controller includes a first interface coupled to a host and a second interface coupled to the non-volatile memory device. The controller can be configured to perform the following operations:

[0137] A write command is sent to the non-volatile storage device via a second interface. The amount of data included in the write command is greater than the storage capacity of two superblocks. The write command includes physical addresses mapped to multiple target superblocks, which appear in the write command in priority order. The order of the multiple superblocks is determined based on the number of erases and the number of bad blocks within each superblock. The number of erases between any two adjacent superblocks in the order meets a preset requirement. The first superblock interval is set in the order, and the number of bad blocks within the first superblock is greater than a preset value. The priority of write operations on the multiple superblocks is determined based on their order.

[0138] In response to a write command sent by the second interface, the non-volatile storage device writes data sequentially into the corresponding superblocks according to the order of their physical addresses.

[0139] In the above embodiments, the write command can be a write command from the receiving host, a write command during the garbage collection process, a write command during the dynamic wear leveling process, or a write command during the static wear leveling process.

[0140] For example, the timing of sorting multiple superblocks in the operation method provided in this disclosure embodiment may be, for example, after garbage collection, after marking a superblock as a closed block, or after marking a storage block in a superblock as a bad block (or, a physical bad block).

[0141] Here, the timing for sorting multiple superblocks in the operation method provided in this embodiment can be after garbage collection, using the operation method provided in this embodiment to sort the free blocks obtained during garbage collection. The timing for sorting multiple superblocks in the operation method provided in this embodiment can also be after a superblock is marked as a closed block, because once a superblock is marked as a closed block, it no longer participates in the sorting process. The timing for sorting multiple superblocks in the operation method provided in this embodiment can also be after a superblock is marked as a closed block or after a storage block within a superblock is marked as a bad block (or, a physically bad block), because when the number of bad blocks within a superblock changes, that is, the factors affecting the sorting of superblocks change, it is necessary to use the operation method provided in this embodiment to adjust the order or position of the superblock.

[0142] In some embodiments, the write operation includes at least one of the following: a write operation corresponding to a write operation command received by the controller from the host, a write operation during garbage collection, a write operation during dynamic wear leveling, and a write operation during static wear leveling.

[0143] In this embodiment, the number of erases and the number of bad blocks within a superblock are considered simultaneously to determine the order of multiple superblocks; based on the order of the multiple superblocks, the priority of write operations on the superblocks is determined. The order of the multiple superblocks is determined before any write operation is performed. In this embodiment, the application scenarios for writing operations on superblocks are not specifically limited. Application scenarios for writing operations on superblocks include, but are not limited to, performing write operations upon receiving write commands from the host, performing write operations during garbage collection, and performing write operations during wear leveling (including dynamic wear leveling and static wear leveling). These three application scenarios will be explained in detail below.

[0144] In a specific example, the above write operation includes: Host Write.

[0145] Here, the operation method provided in this disclosure is applied to receive a write operation command from a host to perform a write operation. Considering that the memory system includes multiple superblocks, this disclosure provides a method for selecting a target superblock from among these superblocks. In this disclosure, the erase count and the number of bad blocks within each superblock are considered simultaneously to determine the order of the multiple superblocks; the erase count of any two adjacent superblocks in the order meets a preset requirement; the first superblock interval is set in the order, and the number of bad blocks within the first superblock is greater than a preset value; based on the order of the multiple superblocks, the priority for writing operations on the multiple superblocks is determined; the superblock with the highest priority for writing operations can be determined as the target superblock. In this way, the write rate can be smoothed, preventing significant performance fluctuations in the memory system.

[0146] In a specific example, the above write operation includes writing the target data to the target superblock during garbage collection.

[0147] Here, the operation method provided in this disclosure is applied to the write operation during garbage collection. Specifically, the garbage collection process consists of the following three steps: First, selecting a source superblock (i.e., a garbage block); wherein, the source superblock stores valid data and invalid data, and the superblock with the least valid data is usually selected as the source superblock; Second, finding valid data from the source superblock; Third, writing the valid data to the target superblock. In this way, all data in the source superblock can be erased, resulting in a new usable superblock (i.e., a free block). The valid data moved from the source superblock to the target superblock is the target data. Considering that the memory system includes multiple superblocks, this disclosure provides an operation method for selecting a target superblock from multiple superblocks. In this embodiment, the erase count of each superblock and the number of bad blocks within each superblock are considered simultaneously to determine the order of multiple superblocks. The erase counts of any two adjacent superblocks in the order meet a preset requirement. The first superblocks are spaced at intervals, and the number of bad blocks within each first superblock is greater than a preset value. Based on the order of the multiple superblocks, the priority of write operations on the multiple superblocks is determined. The superblock with the highest priority for write operations can be identified as the target superblock. This smooths the write rate and prevents significant performance fluctuations in the memory system.

[0148] It should be noted that after erasing all data in the source superblock to obtain a new available superblock, the new available superblock (i.e., free block) can also be added to the sorting according to the operation method provided in the embodiments of this disclosure, thereby determining the priority of writing operations to the superblock.

[0149] In a specific example, the above write operation includes: writing the first target data into the first target superblock during dynamic wear leveling and writing the second target data into the second target superblock during static wear leveling.

[0150] Here, the operation method provided in this disclosure is applied to the write operation during the wear leveling process. Specifically, wear leveling includes dynamic wear leveling and static wear leveling. Dynamic wear leveling refers to writing hot data to superblocks with fewer erase cycles; that is, when selecting superblocks for writing operations, superblocks with fewer erase cycles are selected first. In this case, the hot data is the first target data, and the superblock with fewer erase cycles is the first target superblock.

[0151] Static wear leveling refers to writing cold data to a superblock with a high number of erase cycles. In this case, the cold data is the second target data, and the superblock with the high number of erase cycles is the second target superblock. Considering that the memory system includes multiple superblocks, this disclosure provides a method for selecting a first target superblock and a second target superblock from among multiple superblocks. This method considers both the number of erase cycles and the number of bad blocks within each superblock to determine the order of the multiple superblocks. During the ordering, the number of erase cycles between any two adjacent superblocks must meet a preset requirement. The first superblocks are spaced at intervals, and the number of bad blocks within each first superblock is greater than a preset value. Based on the order of the multiple superblocks, the priority of writing operations to the multiple superblocks is determined. The superblock with the highest priority for writing operations can be determined as the first target superblock, and the superblock with the lowest priority for writing operations can be determined as the second target superblock. This smooths the write rate and prevents significant performance fluctuations in the memory system.

[0152] In some embodiments, prior to S601, the above-described operation method further includes:

[0153] Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, multiple superblocks are arranged in ascending or descending order of the number of erases.

[0154] In this embodiment of the disclosure, the pre-sorting of multiple superblocks can be determined based on the number of erases for each superblock. The correspondence between the number of erases for a superblock and its pre-sorting includes two cases. In the first case, the smaller the number of erases for a superblock in the pre-sorting, the higher its position in the pre-sorting; that is, multiple superblocks in the pre-sorting are arranged in ascending order of the number of erases. In the second case, the larger the number of erases for a superblock in the pre-sorting, the higher its position in the pre-sorting; that is, multiple superblocks in the pre-sorting are arranged in descending order of the number of erases.

[0155] It should be noted that after determining the pre-sorting of multiple superblocks, the number of bad blocks within each superblock needs to be considered simultaneously. The order and position of the superblocks need to be adjusted. During the adjustment process, the number of erases between any two adjacent superblocks must meet a preset requirement as a constraint. This ensures that both the number of erases and the number of bad blocks in the memory are considered simultaneously, and the priority of write operations on the superblocks is determined. This not only effectively smooths write performance and enhances the performance stability of the memory system, but also ensures that the wear level of each superblock is basically the same, thereby guaranteeing that the memory system has the maximum data write capacity.

[0156] As mentioned earlier, based on the number of bad blocks within a superblock, a preset value is set to divide the superblock into a first superblock, a second superblock, and a third superblock. The number of bad blocks in the first superblock is greater than the preset value; the number of bad blocks in the second superblock is greater than 0 and less than or equal to the preset value; and the number of bad blocks in the third superblock is equal to 0. If two first superblocks are set adjacent to each other, the write rate will suddenly decrease and remain so for a long time when writing to these two superblocks, which will cause significant performance fluctuations in the memory system.

[0157] In some embodiments, after determining the pre-sorting of multiple superblocks based on the number of erases for each superblock, the above operation method further includes:

[0158] Based on the pre-sorting of multiple superblocks, determine the first superblock with at least two adjacent settings;

[0159] Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine the first sub-sorting of multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets the preset requirements; the first superblocks in the first sub-sorting are not set to be adjacent.

[0160] In this embodiment, at least two adjacent first superblocks are determined based on the pre-sorting of multiple superblocks. Since the number of bad blocks within a first superblock exceeds a preset value, the write rate will suddenly decrease and remain so for a prolonged period when writing to at least two adjacent first superblocks, causing significant performance fluctuations in the memory system. Therefore, when adjusting the pre-sorting of superblocks, the order or position of adjacent first superblocks is adjusted firstly to obtain a first sub-sorting; this ensures that the first superblocks in the first sub-sorting are not adjacent, or that the first superblocks in the first sub-sorting are spaced apart, i.e., there is another superblock (i.e., a second or third superblock) between two first superblocks.

[0161] It should be noted that during the process of adjusting the order or position of the adjacent first superblocks, the number of erases of any two adjacent superblocks must meet a preset requirement as a constraint, so that the number of erases of any two adjacent superblocks in the first sub-sorting meets the preset requirement.

[0162] It is important to emphasize that, based on the pre-sorting of multiple superblocks, at least two adjacent first superblocks are identified. Here, the number of adjacent first superblocks in the pre-sorting of multiple superblocks is greater than or equal to two. For example, three first superblocks may be consecutively placed in the pre-sorting. Furthermore, there may be multiple instances in the pre-sorting of multiple superblocks where at least two adjacent first superblocks are present. As mentioned earlier, the linked list of superblocks is very long, and there may be more than one instance where at least two adjacent first superblocks exist.

[0163] In some embodiments, the first superblock and the second superblock are arranged adjacent to each other in the first sub-sorting; or, the first superblock and the third superblock are arranged adjacent to each other in the first sub-sorting.

[0164] In this embodiment of the disclosure, after adjusting the order or position of at least two adjacent first superblocks, a first sub-sorting is obtained; in the first sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the first sub-sorting, the first superblock and the third superblock are arranged adjacently.

[0165] It should be noted that if two first superblocks are placed adjacent to each other, when writing to both first superblocks, the write rate of the memory system will suddenly drop to the first write rate and remain there for a relatively long time (i.e., the duration of the write operation at the first write rate covers the time it takes to write to both first superblocks), causing significant performance fluctuations in the memory system. If a second or third superblock is placed between the two first superblocks, when writing to the first, second (or third), and then first superblocks sequentially, the write rate of the memory system will show a trend of first decreasing to the first write rate, then increasing to the second (or third) write rate, and finally decreasing back to the first write rate; that is, the duration of the write operation at the first write rate covers the time it takes to write to one first superblock. Compared to the case where two first superblocks are placed adjacent to each other, this effectively avoids the prolonged decrease in the write rate of the memory system, reducing performance fluctuations.

[0166] In this embodiment, after adjusting the order or position of the first superblock, a first sub-sorting is obtained. Within the first sub-sorting, there are still instances where the first and second superblocks are adjacent. Since the number of bad blocks in the first superblock is greater than a preset value, and the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value, when writing to the adjacent first and second superblocks sequentially, the write rate will suddenly decrease and remain so for a certain period. This will cause certain performance fluctuations in the memory system. Therefore, it is necessary to adjust the order or position of the adjacent first and second superblocks to further optimize the operation method of the memory system.

[0167] In some embodiments, after adjusting the order or position of the first superblock according to the number of bad blocks within the first superblock to determine the first sub-sorting of multiple superblocks, the above operation method further includes:

[0168] Based on the first sub-sorting of multiple superblocks, determine the first and second superblocks that are set up adjacently;

[0169] Based on the number of bad blocks in the first and second superblocks, the order or position of the first and second superblocks is adjusted to determine the second sub-sorting of multiple superblocks; wherein, the number of erases for any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first and second superblocks in the second sub-sorting are not set to be adjacent.

[0170] In this embodiment, it is considered that when writing operations are performed sequentially on adjacent first and second superblocks, the write rate will suddenly decrease and last for a certain period of time, which will cause certain performance fluctuations in the memory system. Therefore, the order or position of the adjacent first and second superblocks is adjusted to obtain a second sub-sorting; such that the first and second superblocks in the second sub-sorting are not adjacent, or that the first and second superblocks in the second sub-sorting are spaced apart, that is, other superblocks (i.e., the second superblock or the third superblock) are placed between the first and second superblocks.

[0171] It should be noted that during the process of adjusting the order or position of the adjacent first and second superblocks, the number of erases of any two adjacent superblocks must meet a preset requirement as a constraint, so that the number of erases of any two adjacent superblocks in the second sub-sorting meets the preset requirement.

[0172] In some embodiments, two second superblocks are arranged adjacently in the second sub-sorting; or, a first superblock and a third superblock are arranged adjacently in the second sub-sorting; or, a second superblock and a third superblock are arranged adjacently in the second sub-sorting.

[0173] In this embodiment of the disclosure, after adjusting the order or position of the adjacent first superblock and second superblock, a second sub-sorting is obtained; in the second sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the second sub-sorting, the first superblock and the third superblock are arranged adjacently.

[0174] It should be noted that if the first and second superblocks are adjacent, then when write operations are performed sequentially on the first and second superblocks, the write rate of the memory system will exhibit a trend of first decreasing to the first write rate and then increasing to the second write rate. The write rate will also suddenly decrease and remain so for a certain period, causing some performance fluctuations in the memory system. If a second or third superblock is placed between the first and second superblocks, then when write operations are performed sequentially on the first, second (or third), and second superblocks, the write rate of the memory system will exhibit a trend of first decreasing to the first write rate and then increasing to the second write rate (or first decreasing to the first write rate, then increasing to the third write rate, and finally decreasing back to the second write rate). Compared to the case where the first and second superblocks are adjacent, this effectively avoids the prolonged decrease in the write rate of the memory system, reducing performance fluctuations.

[0175] In this embodiment, after adjusting the order or position of the first and second superblocks, a second sub-sorting is obtained. However, the second sub-sorting still contains adjacent second superblocks. Since the number of bad blocks within each second superblock is greater than 0 and less than or equal to a preset value, the write rate will decrease for a certain period when writing to adjacent second superblocks sequentially. This will cause performance fluctuations in the memory system. Therefore, it is necessary to adjust the order or position of adjacent second superblocks to further optimize the memory system's operation method.

[0176] In some embodiments, after adjusting the order or position of the first superblock and the second superblock according to the number of bad blocks in the first superblock and the second superblock to determine the second sub-sorting of multiple superblocks, the above operation method further includes:

[0177] Based on the second sub-sorting of multiple superblocks, determine at least two adjacent second superblocks;

[0178] Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of multiple superblocks; wherein, the second superblocks are not set adjacently in the sorting.

[0179] In this embodiment, it is considered that when writing to adjacent second superblocks sequentially, the write rate will decrease for a certain period of time, which will cause certain performance fluctuations in the memory system. Therefore, the order or position of the adjacent second superblocks is adjusted to obtain a sort; such that the second superblocks in the sort are not adjacent, or that the second superblocks in the sort are spaced apart, that is, other superblocks (i.e., third superblocks) are placed between the second superblocks and the second superblock.

[0180] It should be noted that during the process of adjusting the order or position of adjacent second superblocks, the number of erases of any two adjacent superblocks must meet a preset requirement as a constraint, so that the number of erases of any two adjacent superblocks in the sorting meets the preset requirement.

[0181] In some embodiments, the second superblock and the third superblock are arranged adjacently in the sorting.

[0182] In this embodiment of the disclosure, the order or position of the adjacent second superblocks is adjusted to obtain a sort; in the sort, the second superblock and the third superblock are arranged adjacently.

[0183] It should be noted that if two second superblocks are placed adjacent to each other, the write rate of the memory system will decrease for a certain period of time when write operations are performed on both second superblocks (i.e., the write rate is equal to the duration of the second write rate for writing operations on both second superblocks). This will cause some performance fluctuations in the memory system. If a third superblock is placed between the two second superblocks, then when write operations are performed sequentially on the second, third, and second superblocks, the write rate of the memory system will show a trend of first decreasing to the second write rate, then increasing to the third write rate, and finally decreasing back to the second write rate. That is, the write rate is equal to the duration of the second write rate for writing operations on one second superblock. Compared with the case where two second superblocks are placed adjacent to each other, this effectively avoids the continuous decrease in the write rate of the memory system, reducing performance fluctuations in the memory system.

[0184] refer to Figure 9 , Figure 9 The sorting of superblocks provided for a specific example. Figure 9 The diagram illustrates the order of superblocks Super BLK1 to Super BLK10, as well as the number of erases EC and the number of bad storage planes BP (i.e., the number of bad blocks within each superblock) for each superblock. Figure 9The illustrated superblocks Super BLK1 to Super BLK10 are sorted in ascending order of their erase count. However, this sorting does not take into account the number of bad blocks within each superblock, meaning that two adjacent superblocks may both contain a large number of bad blocks. For example, superblocks Super BLK6 and Super BLK7 may be adjacent; Super BLK6 may contain 6 bad blocks, while Super BLK7 may contain 8.

[0185] refer to Figure 10 , Figure 10 The sorting of superblocks provided for another specific example. Figure 10 It also illustrates the order of superblocks SuperBLK1 to SuperBLK10, as well as the number of erases (EC) and bad storage planes (BP) for each superblock (i.e., the number of bad blocks within each superblock). However, Figure 10 The illustrated superblock order and Figure 9 The illustrated superblock ordering shows a clear difference. Based on Figure 9 The illustrated superblock arrangement swaps the order (or position) of superblocks Super BLK5 and Super BLK6, and swaps the order (or position) of superblocks Super BLK7 and Super BLK8. Thus, Figure 10 The diagram shows that the superblock with the sequence number (5) is Super BLK6, the superblock with the sequence number (6) is Super BLK5, the superblock with the sequence number (7) is Super BLK8, and the superblock with the sequence number (8) is Super BLK7.

[0186] First, considering that the difference in erase counts between any two adjacent superblocks (Super BLK4 to Super BLK9) is less than 5, meaning the erase counts of any two adjacent superblocks meet the preset requirements, the order or position of superblocks Super BLK5 and Super BLK6, and superblocks Super BLK7 and Super BLK8, can be adjusted. Second, considering the large number of bad blocks in superblocks Super BLK6 and Super BLK7, their order or position can be adjusted so that they are not set adjacently.

[0187] refer to Figure 11 , Figure 11This is a graph showing the write rate of each superblock in the sorting process. Figure 11 The horizontal axis represents the sequence number of each superblock in the sorting, and the vertical axis represents the write rate. Figure 11 Figure (a) shows Figure 9 The write rate of each superblock in the sorting. Figure 11 Figure (b) shows Figure 10 The write rate of each superblock in the sorting.

[0188] like Figure 11 As shown in Figure (a), when writing to the sorted superblocks in sequence, the write rate suddenly drops when writing to Superblock SuperBLK6 because both Superblock SuperBLK6 and Superblock SuperBLK7 contain a large number of bad blocks. This drop continues until the write operation to Superblock SuperBLK7 is completed. The long duration of the write rate drop causes significant performance fluctuations in the memory system.

[0189] like Figure 11 As shown in Figure (b), after adjusting the sorting of superblocks, the superblock with sequence number (5) is now Super BLK6, and the superblock with sequence number (8) is now Super BLK7. When writing to the superblocks in the sorting sequentially, the write rate will decrease when writing to superblock (5) because both superblocks with sequence number (5) and superblocks with sequence number (8) contain a large number of bad blocks. Subsequently, the write rate will increase when writing to superblocks with sequence numbers (6) and (7), and decrease when writing to superblock (8). In this way, the write rate decrease will not last for a long time, which can reduce the performance fluctuation of the memory system and effectively smooth the write performance of the memory system.

[0190] In some embodiments, the order of multiple superblocks is provided as a superblock list. Here, by querying the superblock list, the target superblock to be written to can be obtained.

[0191] In other embodiments, the sorting of multiple superblocks is provided using a red-black tree. Here, considering the increasing length of the linked list, adjusting the linked list to a red-black tree can improve query efficiency and save query time.

[0192] In some embodiments, a data superblock refers to a superblock containing both valid and invalid data portions, which are distributed across different locations within the superblock. Here, "valid data portions" and "invalid data portions" relate to wear leveling and are not the same as the "valid data" and "invalid data" in the garbage collection process described earlier. More specifically, valid data portions typically include cold data, i.e., data accessed infrequently; invalid data portions typically include hot data, i.e., data accessed frequently.

[0193] As mentioned earlier, static wear leveling refers to writing cold data to superblocks with higher erase counts. In this case, the cold data becomes the secondary target data, and the superblocks with higher erase counts become the secondary target superblocks. The Valid Transport Unit Count can be used to characterize the valid data portion within a superblock. Considering the static wear leveling process, some superblocks are used to store system data, which is considered cold data. These superblocks storing system data have lower erase counts. This system data can be moved out and written to superblocks with higher erase counts, thus freeing up the superblocks originally used for storing system data and allowing these superblocks with lower erase counts to be fully utilized.

[0194] Still referencing Figure 7 and Figure 8 This disclosure provides a memory system 102, which includes at least one non-volatile memory device 104 and a controller 106 coupled to the non-volatile memory device 104; wherein each non-volatile memory device 104 includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device 104 forms a superblock; the controller 106 is configured to:

[0195] The order of multiple superblocks is determined based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein, the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblock in the order is set with an interval, and the number of bad blocks within the first superblock is greater than a preset value;

[0196] The priority of write operations on multiple superblocks is determined based on their order.

[0197] In some embodiments, the controller 106 is specifically configured to:

[0198] In the sorting process, the earlier a superblock appears in the order, the higher the priority of write operations on that superblock; specifically, the erase count of the superblock that appears earlier in the sorting is less than or equal to the erase count of the superblock that appears later in the sorting; or, the erase count of the superblock that appears earlier in the sorting is greater than the erase count of the superblock that appears later in the sorting, and the difference in the erase counts between the two superblocks is less than a preset difference; or...

[0199] The higher the superblock is in the sorting, the lower the priority of writing to the superblock; specifically, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

[0200] In some embodiments, the controller 106 is specifically configured to:

[0201] Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, multiple superblocks are arranged in ascending or descending order of the number of erases.

[0202] In some embodiments, the controller 106 is specifically configured to:

[0203] Based on the pre-sorting of multiple superblocks, determine the first superblock with at least two adjacent settings;

[0204] Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine the first sub-sorting of multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets the preset requirements; the first superblocks in the first sub-sorting are not set to be adjacent.

[0205] In some embodiments, the multiple superblocks further include a second superblock and a third superblock; wherein the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value; and the number of bad blocks in the third superblock is equal to 0.

[0206] In the first sub-sorting, the first superblock and the second superblock are set adjacent to each other; or, in the first sub-sorting, the first superblock and the third superblock are set adjacent to each other.

[0207] In some embodiments, the controller 106 is specifically configured to:

[0208] Based on the first sub-sorting of multiple superblocks, determine the first and second superblocks that are set up adjacently;

[0209] Based on the number of bad blocks in the first and second superblocks, the order or position of the first and second superblocks is adjusted to determine the second sub-sorting of multiple superblocks; wherein, the number of erases for any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first and second superblocks in the second sub-sorting are not set to be adjacent.

[0210] In some embodiments, two second superblocks are arranged adjacently in the second sub-sorting; or, a first superblock and a third superblock are arranged adjacently in the second sub-sorting; or, a second superblock and a third superblock are arranged adjacently in the second sub-sorting.

[0211] In some embodiments, the controller 106 is specifically configured to:

[0212] Based on the second sub-sorting of multiple superblocks, determine at least two adjacent second superblocks;

[0213] Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of multiple superblocks; wherein, the second superblocks are not set adjacently in the sorting.

[0214] In some embodiments, the second superblock and the third superblock are arranged adjacently in the sorting.

[0215] In some embodiments, the superblock includes a free block.

[0216] This disclosure provides a computer-readable storage medium storing a computer program. When executed, the computer program can implement the operation method of the memory system as described in the above technical solution. The operation method includes: determining an order of multiple superblocks based on the number of erases per superblock and the number of bad blocks within each superblock; wherein the number of erases between any two adjacent superblocks in the order satisfies a preset requirement; the first superblocks in the order are spaced at intervals, and the number of bad blocks within each first superblock is greater than a preset value; and determining the priority of write operations on the multiple superblocks based on their order.

[0217] In this disclosure, the computer-readable storage medium may include: random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, register, hard disk, removable disk, read-only optical disk (CD-ROM), or any other form of program code medium known in the art.

[0218] In this embodiment of the disclosure, the operation method of the memory system in the above technical solution can be implemented by running firmware.

[0219] This disclosure also provides an electronic device, which includes the memory system described in the above technical solutions. Here, the electronic device may include a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device, or power bank, etc.

[0220] This disclosure provides a memory system and its operation method, as well as a computer-readable storage medium. In this disclosure, by simultaneously considering the number of erases on the superblock and the number of bad blocks within the superblock, the priority of write operations on the superblock is determined, which can effectively smooth write performance and enhance the performance stability of the memory system.

[0221] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0222] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory system, characterized in that, The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device includes a plurality of memory blocks, and at least one memory block within at least one non-volatile memory device forms a superblock; the controller is configured to: The order of multiple superblocks is determined based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblocks in the order are set at intervals, and the number of bad blocks within the first superblocks is greater than a preset value; The priority of write operations on the multiple superblocks is determined based on their order.

2. The memory system according to claim 1, characterized in that, The controller is specifically configured as follows: In the sorting process, the higher the ranking of the superblock, the higher the priority of the write operation on that superblock; wherein, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is less than or equal to the erase count of the superblock ranking later in the sorting process; or, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is greater than the erase count of the superblock ranking later in the sorting process, and the difference between the erase counts of the two superblocks is less than a preset difference; or... The higher the superblock is in the sorting, the lower the priority of writing to the superblock; wherein, in the sorting, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, in the sorting, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

3. The memory system according to claim 1, characterized in that, The controller is specifically configured as follows: Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, the multiple superblocks are arranged in ascending or descending order of the number of erases.

4. The memory system according to claim 3, characterized in that, The controller is specifically configured as follows: Based on the pre-sorting of the multiple superblocks, at least two adjacent first superblocks are determined; Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine a first sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets a preset requirement; and the first superblocks in the first sub-sorting are not set adjacent to each other.

5. The memory system according to claim 4, characterized in that, The multiple superblocks also include a second superblock and a third superblock; wherein, the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value; the number of bad blocks in the third superblock is equal to 0; In the first sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the first sub-sorting, the first superblock and the third superblock are arranged adjacently.

6. The memory system according to claim 5, characterized in that, The controller is specifically configured as follows: Based on the first sub-sorting of the multiple superblocks, the first superblock and the second superblock that are set up adjacently are determined; Based on the number of bad blocks in the first superblock and the second superblock, the order or position of the first superblock and the second superblock is adjusted to determine a second sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first superblock and the second superblock are not set adjacent to each other in the second sub-sorting.

7. The memory system according to claim 6, characterized in that, In the second sub-sorting, the two second superblocks are set adjacent to each other; or, in the second sub-sorting, the first superblock and the third superblock are set adjacent to each other; or, in the second sub-sorting, the second superblock and the third superblock are set adjacent to each other.

8. The memory system according to claim 7, characterized in that, The controller is specifically configured as follows: Based on the second sub-sorting of the multiple superblocks, at least two adjacent second superblocks are determined; Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of the multiple superblocks; wherein, the second superblocks are not arranged adjacently in the sorting.

9. The memory system according to claim 8, characterized in that, In the sorting, the second superblock and the third superblock are arranged adjacent to each other.

10. The memory system according to claim 1, characterized in that, The superblock includes free blocks.

11. A method for operating a memory system, characterized in that, The memory system includes at least one non-volatile memory device and a controller coupled to the non-volatile memory device; wherein each non-volatile memory device includes multiple memory blocks, and at least one memory block within at least one non-volatile memory device forms a superblock; the operation method includes: The order of multiple superblocks is determined based on the number of erases for each superblock and the number of bad blocks within each superblock; wherein the number of erases for any two adjacent superblocks in the order meets a preset requirement; the first superblocks in the order are set at intervals, and the number of bad blocks within the first superblocks is greater than a preset value; The priority of write operations on the multiple superblocks is determined based on their order.

12. The method of operating the memory system according to claim 11, characterized in that, The step of determining the priority of write operations on the multiple superblocks based on their order includes: In the sorting process, the higher the ranking of the superblock, the higher the priority of the write operation on that superblock; wherein, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is less than or equal to the erase count of the superblock ranking later in the sorting process; or, in the sorting process, the erase count of the superblock ranking earlier in any two adjacent superblocks is greater than the erase count of the superblock ranking later in the sorting process, and the difference between the erase counts of the two superblocks is less than a preset difference; or... The higher the superblock is in the sorting, the lower the priority of writing to the superblock; wherein, in the sorting, the number of erases of the superblock that is higher in the sorting is greater than or equal to the number of erases of the superblock that is lower in the sorting; or, in the sorting, the number of erases of the superblock that is higher in the sorting is less than the number of erases of the superblock that is lower in the sorting, and the difference between the number of erases of the two superblocks is less than a preset difference.

13. The method of operating the memory system according to claim 11, characterized in that, Before determining the order of multiple superblocks based on the number of erases and the number of bad blocks within each superblock, the operation method further includes: Based on the number of erases for each superblock, a pre-sorting of multiple superblocks is determined; wherein, in the pre-sorting, the multiple superblocks are arranged in ascending or descending order of the number of erases.

14. The method of operating the memory system according to claim 13, characterized in that, After determining the pre-sorting of multiple superblocks based on the number of erases for each superblock, the operation method further includes: Based on the pre-sorting of the multiple superblocks, at least two adjacent first superblocks are determined; Based on the number of bad blocks in the first superblock, the order or position of the first superblock is adjusted to determine a first sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the first sub-sorting meets a preset requirement; and the first superblocks in the first sub-sorting are not set adjacent to each other.

15. The method of operating the memory system according to claim 14, characterized in that, The multiple superblocks also include a second superblock and a third superblock; wherein, the number of bad blocks in the second superblock is greater than 0 and less than or equal to a preset value; the number of bad blocks in the third superblock is equal to 0; In the first sub-sorting, the first superblock and the second superblock are arranged adjacently; or, in the first sub-sorting, the first superblock and the third superblock are arranged adjacently.

16. The method of operating the memory system according to claim 15, characterized in that, After adjusting the order or position of the first superblock based on the number of bad blocks within the first superblock to determine the first sub-sorting of the multiple superblocks, the operation method further includes: Based on the first sub-sorting of the multiple superblocks, the first superblock and the second superblock that are set up adjacently are determined; Based on the number of bad blocks in the first superblock and the second superblock, the order or position of the first superblock and the second superblock is adjusted to determine a second sub-sorting of the multiple superblocks; wherein, the number of erases of any two adjacent superblocks in the second sub-sorting meets a preset requirement; the first superblock and the second superblock are not set adjacent to each other in the second sub-sorting.

17. The method of operating a memory system according to claim 16, characterized in that, In the second sub-sorting, the two second superblocks are set adjacent to each other; or, in the second sub-sorting, the first superblock and the third superblock are set adjacent to each other; or, in the second sub-sorting, the second superblock and the third superblock are set adjacent to each other.

18. The method of operating the memory system according to claim 17, characterized in that, After adjusting the order or position of the first superblock and the second superblock based on the number of bad blocks in the first superblock and the second superblock to determine the second sub-sorting of the multiple superblocks, the operation method further includes: Based on the second sub-sorting of the multiple superblocks, at least two adjacent second superblocks are determined; Based on the number of bad blocks within the second superblock, the order or position of the second superblock is adjusted to determine the sorting of the multiple superblocks; wherein, the second superblocks are not arranged adjacently in the sorting.

19. The method of operating the memory system according to claim 18, characterized in that, In the sorting, the second superblock and the third superblock are arranged adjacent to each other.

20. The method of operating the memory system according to claim 11, characterized in that, The superblock includes free blocks.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, can implement the method of operating the memory system as described in any one of claims 11 to 20.

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