Voltage calibration method and device, memory and memory system

Abstract

The invention discloses a voltage calibration method and device, a memory and a memory system. The method comprises the following steps: detecting the current target temperature of a memory cell array; respectively carrying out reading operation on the memory cell array at a plurality of candidate times by using a standard reading voltage, and obtaining a corresponding target reading failure bit number; and determining a target read voltage offset parameter according to the target temperature, the target read failure bit number, the candidate time and a stored target offset function, and calibrating the read voltage.

Description

Voltage calibration method and device, memory and memory system

Technical field

[0001] The present application relates to the field of semiconductor technology, and in particular to a voltage calibration method and device thereof, a memory, and a memory system. [Background Technology]

[0002] With the advancement of storage technology, the application of three-dimensional memory (such as 3D NAND flash memory chips) is becoming more and more widespread. For example, three-dimensional memory can be applied to mobile phones, computers and other devices.

[0003] In a three-dimensional memory, when reading data from any memory cell, different read voltages can be applied to the control gate of the memory cell in sequence, and then the data reading result of the memory cell is determined based on the conduction state of the corresponding bit line after applying the different read voltages.

[0004] However, as the usage time and the number of read and write times affect the memory performance, the read voltage of the memory cell will shift. The shifted read voltage will cause errors in the read data, so a read voltage calibration solution is needed.

[0005] [Summary of the invention]

[0006] The present application provides a voltage calibration method and device thereof, a memory and a memory system, which can better realize the calibration of the read voltage and improve the accuracy of the data reading operation.

[0007] In one aspect, an embodiment of the present application provides a voltage calibration method, comprising:

[0008] Detecting the current target temperature of the memory cell array;

[0009] Performing a read operation on the memory cell array at a plurality of candidate times with a standard read voltage, and obtaining a corresponding target number of read failure bits, wherein each candidate time corresponds to one target number of read failure bits;

[0010] determining a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and a stored target offset function;

[0011] A read voltage of the memory cell array during a read operation is calibrated using the target read voltage offset parameter.

[0012] On the other hand, an embodiment of the present application further provides a voltage calibration device, comprising:

[0013] a temperature sensor configured to detect a target temperature currently located at the memory cell array;

[0014] a first processing unit, the first processing unit being electrically connected to the memory cell array and the temperature sensor, and being configured to perform a read operation on the memory cell array at a plurality of candidate times with a standard read voltage, and obtain a corresponding target number of read failures, wherein each candidate time corresponds to one target number of read failures; determine a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and a stored target offset function; and calibrate the read voltage of the memory cell array in the read operation with the target read voltage offset parameter.

[0015] On the other hand, an embodiment of the present application further provides a voltage calibration device, including a second processing unit, the second processing unit being electrically connected to a memory, the memory including a memory cell array, and the second processing unit being configured to:

[0016] placing the memory cell array at a reference temperature and a preset temperature respectively, performing a read operation on the memory cell array at a standard read voltage and any one of a plurality of preset read times, and obtaining corresponding first and second read failure bit numbers;

[0017] placing the memory cell array at the reference temperature and the preset temperature respectively, performing a read operation on the memory cell array at any one of a plurality of preset read voltages and a standard read time, and obtaining a corresponding third read failure bit number and a fourth read failure bit number;

[0018] determining the target offset function according to the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, the fourth number of read failure bits, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time;

[0019] The target offset function is stored in the memory.

[0020] On the other hand, an embodiment of the present application further provides a memory, comprising a memory cell array and a peripheral circuit structure coupled to the memory cell array, wherein the peripheral circuit structure comprises any one of the above-mentioned voltage calibration devices.

[0021] On the other hand, an embodiment of the present application further provides a memory system, comprising at least one memory as described above, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

[0022] The voltage calibration method and device, memory, and memory system provided in the embodiments of the present application, during the read voltage calibration process of a memory cell array, detect the number of read failure bits at multiple candidate times using a standard read voltage and detect the ambient temperature in which it is located. The read voltage is then calibrated based on the ambient temperature, the number of read failure bits, and a stored target offset function. This eliminates the effects of changes in the ambient temperature and the memory itself on the read voltage offset, improves the accuracy of the read voltage calibration, and reduces the failure rate of the read operation.

Brief Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0024] FIG1 is a schematic diagram of the structure of a system provided in an embodiment of the present application;

[0025] FIG2 is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0026] FIG3 is a flow chart of a voltage calibration method according to an embodiment of the present application;

[0027] FIG4 is another schematic flow chart of a voltage calibration method according to an embodiment of the present application;

[0028] FIG5 is a schematic structural diagram of a voltage calibration device provided in an embodiment of the present application;

[0029] FIG6 is a schematic structural diagram of another voltage calibration device provided in an embodiment of the present application. [Specific implementation method]

[0030] The present application will be further described in detail below in conjunction with the accompanying drawings and examples. It is particularly noted that the following examples are only intended to illustrate the present application and are not intended to limit the scope of the present application. Similarly, the following examples are only some examples of the present application and are not intended to be exhaustive. All other examples obtained by persons of ordinary skill in the art without creative effort are intended to fall within the scope of protection of the present application.

[0031] In this description, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the quantity of the technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of the aforementioned features.

[0032] It should also be understood that the terms “include” and / or “comprising” used herein specify the presence of stated features, integers, steps, operations, units and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0033] FIG1 is a block diagram of an exemplary system 100 provided in an embodiment of the present application. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. As shown in FIG1 , system 100 may include a host 101 and a memory system 102, and memory system 102 includes one or more memories 1021 and a controller 1022. Host 101 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SOC) (e.g., an application processor (AP)) of an electronic device. Host 101 may be configured to send data to or receive data from memory 1021.

[0034] In the examples of the present application, the memory 1021 is not limited to a three-dimensional NAND memory. Without violating the disclosure or teachings of the present application, the memory 1021 can be implemented as various other types of non-volatile memories that can retain stored data when the power is disconnected.

[0035] In some embodiments, the controller 1022 is coupled to the memory 1021 and the host 101 and is configured to control the memory 1021, such as controlling the memory 1021 to perform data write and read operations. The controller 1022 can manage data stored in the memory 1021 and communicate with the host 101.

[0036] The controller 1022 may be configured to control operations of the memory 1021, such as read, erase, and program operations. The controller 1022 may also be configured to manage various functions regarding data stored or to be stored in the memory 1021, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.

[0037] The controller 1022 and one or more memories 1021 can be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or eMMC package). That is, the memory system 102 can be implemented and packaged into different types of electronic products.

[0038] FIG2 is a schematic diagram of the structure of a memory 200 provided in an embodiment of the present application. The memory 200 includes a memory cell array 201 and a peripheral circuit structure 202 coupled to the memory cell array 201. The peripheral circuit structure 202 can be configured to perform operations such as reading, writing, erasing, and verifying on the memory cell array 201. The peripheral circuit structure 202 can also include any of the following voltage calibration devices 500.

[0039] In some embodiments, the peripheral circuit structure 202 may further include word line drivers, bit line drivers, column decoders, sensing circuits, data buffers, program verification logic, and erase verification circuits, etc., which may perform the above operations according to the acquired computer program instructions.

[0040] The memory cell array 201 may include multiple memory blocks. Each block is logically divided into multiple pages. Each page includes multiple memory cells. A page is the minimum unit for data read and write operations, and a block is the minimum unit for data erase operations. Memory cells can be divided into various types based on the amount of data that can be stored in each memory cell, such as single-level cells (SLC) that can store one bit of data, multi-level cells (MLC) that can store two bits of data, and triple-level cells (TLC) that can store three bits of data.

[0041] For a single memory cell in the memory cell array 201, it has different memory states when storing different numbers of electrons. For example, when the memory cell is of the TLC type, it has eight memory states, corresponding to "111," "110," "100," "000," "010," "011," "001," and "101," respectively. Different memory states correspond to different threshold voltages. Generally, for a memory cell with any memory state, when the read voltage applied to its control gate (equivalent to the word line) is greater than or equal to the threshold voltage of the corresponding memory state, the memory cell can be placed in a conductive state. In this way, for a memory cell, different read voltages can be applied to the control gate of the memory cell in sequence. Then, based on the conductive state of the corresponding bit line after applying the different read voltages, the memory state of the memory cell is determined, and the data reading result of the memory cell is further determined.

[0042] However, as the number of read and write times and the length of use increase, the memory 200 itself will experience a certain degree of wear and tear, and changes in the use environment will also affect the performance of the memory 200. These may cause the read voltage in the read operation to shift, and the shifted read voltage will cause errors when reading data. Therefore, the read voltage needs to be calibrated, and how to accurately calibrate the read voltage is a technical problem that urgently needs to be solved.

[0043] Embodiments of the present application provide a voltage calibration method and device, a memory, and a memory system.

[0044] Please refer to FIG3 , which is a flow chart of a voltage calibration method provided in an embodiment of the present application. The voltage calibration method may include the following steps S301 to S304 , wherein:

[0045] Step S301: Detect the current target temperature of the memory cell array;

[0046] Step S302: performing a read operation on the memory cell array at a plurality of candidate times using a standard read voltage, and obtaining a corresponding target number of read failure bits, wherein each candidate time corresponds to one target number of read failure bits;

[0047] Step S303: determining a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and the stored target offset function;

[0048] Step S304 : Calibrate the read voltage of the memory cell array during a read operation using the target read voltage offset parameter.

[0049] It should be understood that the steps shown in the above production method are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, steps S301 and S302 may be performed simultaneously or sequentially. The numerical order is merely an example of an execution order and is not intended to be limiting.

[0050] Among them, the standard read voltage and candidate time can be set and stored in advance by the developer. The standard read voltage is usually related to the threshold voltage of each memory state of the memory cell in the memory cell array. It is the best read voltage estimated when performing a read operation on the memory cell array, and can be considered as the read voltage with the least number of read failures. The candidate time is related to the standard read time of the memory cell array. The standard read time is the best read time estimated when performing a read operation on the memory cell array, and can be considered as the read time with the least number of read failures. The target offset function can be approximately regarded as a curve function, which is set in advance by the developer based on the read operation of the memory cell array at different temperatures.

[0051] It should be noted that the voltage calibration method provided in the embodiment of the present application can be manually triggered by the user, such as the user manually operates the electronic device to trigger the calibration of the read voltage, or it can be automatically triggered by the memory, such as automatically triggering the calibration of the read voltage when the specified time is reached.

[0052] The voltage calibration method provided in an embodiment of the present application sets a target offset function in advance based on the read operation conditions of the memory cell array at different temperatures and stores it in a memory. Subsequently, during the read voltage calibration process of the memory cell array, the number of read failure bits is detected at multiple candidate times using a standard read voltage, and the ambient temperature in which it is located is detected. The read voltage is then calibrated based on the ambient temperature, the number of read failure bits, and the target offset function. This eliminates the effects of changes in the ambient temperature and the memory itself on the read voltage offset, improves the accuracy of the read voltage calibration, and reduces the failure rate of the read operation.

[0053] Please continue to refer to FIG. 3 , and the above steps S301 - S304 will be further described below.

[0054] Step S301: Detect the current target temperature of the memory cell array.

[0055] The target temperature can be detected by a temperature sensor.

[0056] Step S302 . Performing a read operation on the memory cell array at a plurality of candidate times with a standard read voltage, and obtaining a corresponding target number of read failure bits, wherein each candidate time corresponds to one target number of read failure bits.

[0057] Among them, the standard read voltage and candidate time can be set and stored in advance by the developer. The standard read voltage is usually related to the threshold voltage of each memory state of the memory cell in the memory cell array. It is the best read voltage estimated when performing a read operation on the memory cell array. It can be considered as the read voltage with the least number of read failure bits.

[0058] The candidate time is related to the standard read time of the memory cell array and can be multiple times, including the standard read time. The standard read time is the estimated optimal read time for a memory cell array read operation and can be considered the read time with the least number of read failures. For example, if the standard read time is 1 second, the candidate times can include 0.5 seconds, 1 second, and 1.5 seconds.

[0059] The target number of read fail bits represents the amount of data that fails to be read. For the same memory cell array, each read operation may result in some data failure. Furthermore, the amount of failed data can vary depending on the read time or voltage. Typically, when performing a read operation with a standard read time and voltage, the amount of failed data is minimized, ideally to zero.

[0060] Step S303 : Determine a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and the stored target offset function.

[0061] The target offset function can be roughly viewed as a curve function, which is set in advance by the developer based on the read operation conditions of the memory cell array at different temperatures and stored in the memory. The target read voltage offset parameter can be viewed as a voltage offset relative to the standard read voltage.

[0062] In some embodiments, referring to FIG. 4 , the above step S303 may specifically include the following steps S3031-S3033, wherein:

[0063] S3031. Determine a first temperature compensation time and a first temperature compensation voltage corresponding to the target temperature.

[0064] Among them, since high temperature will have a certain impact on the performance of the memory itself, for example, under high temperature, the processing speed of the memory will slow down, so the memory can provide a temperature compensation function for data reading operations. This temperature compensation function mainly sets the compensation time (first temperature compensation time) and compensation voltage (first temperature compensation voltage) for different temperatures. The reading time and reading voltage are adjusted respectively in combination with the compensation time and compensation voltage, thereby eliminating the adverse effects of temperature on the memory reading operation.

[0065] Specifically, two temperature compensation formulas can be provided, one formula can calculate the compensation time based on the temperature value, and the other formula can calculate the compensation voltage based on the temperature value. These two formulas can be summarized by R&D personnel based on a large number of experiments.

[0066] S3032. Determine a target read time offset parameter according to the target number of read failures, the candidate time, and the standard read time.

[0067] In some implementations, the above step S3032 may specifically include:

[0068] Determine the candidate time corresponding to the target number of read failures with the smallest value as the target candidate time;

[0069] The difference between the target candidate time and the standard reading time is determined to obtain the target reading time offset parameter.

[0070] Among them, the larger the value of the target read failure bit, the worse the effect of the read operation at the corresponding read time, and the smaller the value, the better the effect of the read operation at the corresponding read time. The read time with the relatively best reading effect can be used as the target candidate time. For example, for candidate times t1 to t3, if the target read failure bit number read at t1 is the smallest, then t1 is used as the target candidate time, and if the standard read time is T0, then the target read time offset parameter Δt = t1-T0, wherein the target read time offset parameter can be regarded as a time offset relative to the standard read time, which can include 0, a positive number or a negative number.

[0071] S3033. Input the target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage into a stored target offset function to obtain the target read voltage offset parameter.

[0072] Among them, the target offset function may include multiple variables, such as a read time offset variable, a temperature compensation time variable, and a temperature compensation voltage variable. The target read voltage offset parameter can be calculated based on the actual values ​​of these variables. The target read voltage offset parameter may include 0, a positive number, or a negative number.

[0073] For example, the target offset function can be a binary linear curve equation m(x+b)+n(y+c)=p, where m, n and p are known quantities, b is the temperature compensation time variable, c is the temperature compensation voltage variable, x is the reading time offset variable, and y is the reading voltage offset variable. After substituting the numerical values ​​of each corresponding variable into the target offset function (that is, taking the first temperature compensation time as the value of the temperature compensation time variable b, taking the first temperature compensation voltage as the value of the temperature compensation voltage variable c, and taking the target reading time offset parameter as the value of the reading time offset variable x), the numerical value corresponding to the reading voltage offset variable y can be calculated, and this value is the target reading voltage offset parameter.

[0074] Step S304 : Calibrate a read voltage of the memory cell array during a read operation using the target read voltage offset parameter.

[0075] The sum of the standard read voltage and the target read voltage offset parameter may be calculated as the updated read voltage, and then during a read operation, the updated read voltage may be used to perform a data read operation.

[0076] It should be noted that the target offset function is usually designed during the R&D phase and stored in a memory. Specifically, please continue to refer to FIG4 . Before the above step of “determining the target read voltage offset parameter based on the target temperature, the first number of read failures, the candidate time, and the stored target offset function,” the voltage calibration method further includes:

[0077] S401. Place the memory cell array at a reference temperature and a preset temperature, respectively, and perform a read operation on the memory cell array at a standard read voltage and any one of a plurality of preset read times, and obtain a corresponding first read failure bit number and a second read failure bit number;

[0078] S402. placing the memory cell array at the reference temperature and the preset temperature, respectively, and performing a read operation on the memory cell array at any one of a plurality of preset read voltages and a standard read time, and obtaining a corresponding third read failure bit number and a fourth read failure bit number;

[0079] The reference temperature can be a temperature that has little or no effect on the read operation of the memory cell array, such as room temperature. Considering that low temperatures have little effect on the performance of most memories, while high temperatures have a greater impact, the preset temperature can be a temperature higher than the reference temperature. In actual operation, the memory can be placed in a temperature-controlled room with adjustable temperature. The preset read time is typically multiple times excluding the standard read time, and the preset read voltage is typically multiple voltages excluding the standard read voltage.

[0080] Specifically, the read conditions can be controlled by controlling the read voltage and read time. The effect of temperature on the read operation can be analyzed by placing the memory at different temperatures and performing read operations under the same read conditions. This allows the target offset function related to temperature, read time, and read voltage to be determined. The first and third read failure bit numbers are data read results measured at a reference temperature using only an offset in read time or only an offset in read voltage. The second and fourth read failure bit numbers are data read results measured at a preset temperature different from the reference temperature using only an offset in read time or only an offset in read voltage.

[0081] S403. Determine the target offset function based on the first read failure bit number, the second read failure bit number, the third read failure bit number, the fourth read failure bit number, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time;

[0082] S404. Store the target offset function.

[0083] For example, assuming that the reference temperature is H0, the standard read voltage is V0, the standard read time is T0, the preset temperatures include H1~Hn, the preset read voltages include V1~Vm, and the preset read times include T1~Tg, then for any temperature (that is, one of H0 and H1~Hn), the standard read time T0 can be used as a quantity, and different preset read voltages V1~Vm can be used as a single variable (that is, only the read voltage is offset) to set multiple read conditions, and the standard read voltage V0 can be used as a quantity, and different preset read times T1~Tg can be used as a single variable (that is, only the read time is offset) to set multiple read conditions, and different read conditions are used to perform read operations and obtain corresponding data read results (the number of read failure bits), and the impact of temperature on the read operation is analyzed based on the data read results of the same read conditions at different temperatures, and then the target offset function related to temperature, read time and read voltage is determined.

[0084] In some implementations, the above step S403 may specifically include:

[0085] determining a temperature difference between each of the preset temperatures and the reference temperature, a time difference between each of the preset reading times and the standard reading time, and a voltage difference between each of the preset reading voltages and the standard reading voltage;

[0086] determining, based on the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters;

[0087] The target offset function is determined according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits.

[0088] Among them, the benchmark mapping relationship can be regarded as a comparison table between the read time offset parameter and the read voltage offset parameter of the memory when it is not affected by temperature. The read time offset parameter is the offset relative to the standard read time, and the read voltage offset parameter is the offset relative to the standard read voltage.

[0089] Specifically, the temperature difference Δh1~Δhn between each of the preset temperatures H1~Hn and the reference temperature H0, the time difference Δt1~Δtg between each of the preset read times T1~Tg and the standard read time T0, and the voltage difference Δv1~Δvm between each of the preset read voltages V1~Vm and the standard read voltage V0 can be calculated. Based on these differences and the number of read failure bits, a comparison table (reference mapping relationship) between multiple offset voltages and offset times is determined when the memory is not affected by temperature, and based on the reference mapping relationship, a mapping formula (target offset function) between the offset voltage and offset time of the memory when it is at any temperature is further determined.

[0090] In some embodiments, the step of “determining a reference mapping relationship of the memory cell array in a read operation at the reference temperature based on the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits” may specifically include:

[0091] Determine a first digit difference between two first digits of failed read data corresponding to each time difference;

[0092] Determine a bit difference between two third read failure bit values ​​corresponding to each voltage difference value as a third bit difference value;

[0093] The reference mapping relationship is determined according to the time difference, the first bit difference, the voltage difference, and the third bit difference.

[0094] For example, for Δt1 in the time difference values ​​Δt1~Δtg, since Δt1=T1-T0, the number of first read failure bits corresponding to Δt1 is the two first read failure bits corresponding to T1 and T0; for Δv3 in the voltage difference values ​​Δv1~Δvm, since Δv3=v3-V0, the number of third read failure bits corresponding to Δv3 is the two third read failure bits corresponding to v3 and V0, so that each voltage difference value Δv corresponds to a bit difference (third bit difference), and each time difference value Δt corresponds to a bit difference (first bit difference).

[0095] When all first-digit differences and third-digit differences are calculated, an approximate linear compensation method can be used to determine the mapping relationship between the offset time and the offset voltage, that is, to obtain a comparison table (reference mapping relationship) between multiple offset times and offset voltages when the memory is not affected by temperature.

[0096] In some embodiments, the step of “determining the target offset function based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits” may specifically include:

[0097] Determine a bit difference between two of the second read failure bit values ​​corresponding to each of the time differences as a second bit difference, and determine a bit difference between two of the fourth read failure bit values ​​corresponding to each of the voltage differences as a fourth bit difference;

[0098] Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference;

[0099] Determining the reference relationship offset value according to the reference mapping relationship, the first difference, the second difference, and the temperature difference;

[0100] The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

[0101] The reference relationship offset value is equivalent to an offset of the mapping relationship between the offset time and the offset voltage after combining the temperature factor, which is equivalent to obtaining the slope a in the linear equation y=ax, where x is the offset time and y is the offset voltage.

[0102] For example, for Δt1 in the time difference values ​​Δt1~Δtg, since Δt1=T1-T0, the number of second read failure bits corresponding to Δt1 is the two second read failure bits corresponding to T1 and T0; for Δv3 in the voltage difference values ​​Δv1~Δvm, since Δv3=v3-V0, the number of fourth read failure bits corresponding to Δv3 is the two fourth read failure bits corresponding to v3 and V0, so that each voltage difference value Δv corresponds to a bit difference (fourth bit difference), and each time difference value Δt corresponds to a bit difference (second bit difference).

[0103] Since the first and third read failure bit numbers are data reading results measured at the reference temperature using only the offset read time or only the offset read voltage, and the second and fourth read failure bit numbers are data reading results measured at a preset temperature different from the reference temperature using only the offset read time or only the offset read voltage, the error between the bit difference values ​​corresponding to the preset temperature and the reference temperature can be calculated for the same reading condition (such as only the offset time or only the offset voltage), that is, the error (first difference and second difference) generated when reading data due to the temperature influence on the memory. Based on these errors, an approximate linear compensation method is used to adjust the voltage difference Δv and the time difference Δt, so that the time difference Δt (offset time) and the voltage difference Δv (offset voltage) roughly conform to the input value x and output value y of a linear equation y=ax, and the slope a of the linear equation can be used as the reference relationship offset value.

[0104] In some implementations, the above step of “determining the target offset function according to the reference relationship offset value and the reference mapping relationship” may specifically include:

[0105] Obtaining a second temperature compensation time and a second temperature compensation voltage corresponding to each of the preset temperatures;

[0106] determining an initial offset function according to the reference relationship offset value;

[0107] The target offset function is determined according to the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

[0108] The second temperature compensation time and the second temperature compensation voltage corresponding to each temperature can be determined by the temperature compensation formula stored in the memory. Specifically, the initial offset function can be directly constructed based on the reference relationship offset value. For example, the initial offset function can be y+c=a(x+b), where c is the temperature compensation voltage variable, b is the temperature compensation time variable, and a is the reference relationship offset value. Afterwards, the actual values ​​of each calculated variable are substituted into the initial offset function for testing and verification, and the initial offset function is manually fine-tuned so that each actual value roughly satisfies the fine-tuned initial offset function, such as obtaining m(x+b)+n(y+c)=p, where m, n, and p are obtained through fine-tuning, and the fine-tuned initial offset function is the target offset function.

[0109] Based on the voltage calibration method provided in the above embodiment, the present invention also provides a voltage calibration device. Please refer to Figure 5, which is a schematic diagram of the structure of a voltage calibration device 500 provided in the present invention. The voltage calibration device 500 is applied to a memory including a memory cell array. The voltage calibration device 500 includes:

[0110] The temperature sensor 501 is configured to detect the target temperature of the memory cell array;

[0111] A first processing unit 502 is electrically connected to the memory cell array and the temperature sensor 501, and is configured to perform a read operation on the memory cell array at a plurality of candidate times with a standard read voltage, and obtain a corresponding target number of read failures, where each candidate time corresponds to one target number of read failures; determine a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and a stored target offset function; and calibrate the read voltage of the memory cell array in the read operation with the target read voltage offset parameter.

[0112] Among them, the standard read voltage and candidate time can be set and stored in advance by the developer. The standard read voltage is usually related to the threshold voltage of each memory state of the memory cell in the memory cell array. It is the best read voltage estimated when performing a read operation on the memory cell array. It can be considered as the read voltage with the least number of read failure bits.

[0113] The candidate time is related to the standard read time of the memory cell array and can be multiple times, including the standard read time. The standard read time is the estimated optimal read time for a memory cell array read operation and can be considered the read time with the least number of read failures. For example, if the standard read time is 1 second, the candidate times can include 0.5 seconds, 1 second, and 1.5 seconds.

[0114] The target number of read fail bits represents the amount of data that fails to be read. For the same memory cell array, each read operation may result in some data failure. Furthermore, the amount of failed data can vary depending on the read time or voltage. Typically, when performing a read operation with a standard read time and voltage, the amount of failed data is minimized, ideally to zero.

[0115] The target offset function can be roughly viewed as a curve function. It is set in advance by the developer based on the read operation conditions of the memory cell array at different temperatures and stored in the memory. The target read voltage offset parameter can be viewed as the voltage offset relative to the standard read voltage.

[0116] In some embodiments, the first processing unit 502 is configured to:

[0117] determining a first temperature compensation time and a first temperature compensation voltage corresponding to the target temperature;

[0118] Determine a target read time offset parameter according to the target number of read failures, the candidate time, and the standard read time;

[0119] The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into a stored target offset function to obtain the target read voltage offset parameter.

[0120] Among them, since high temperature will have a certain impact on the performance of the memory itself, for example, under high temperature, the processing speed of the memory will slow down, so the memory can provide a temperature compensation function for data reading operations. This temperature compensation function mainly sets the compensation time (first temperature compensation time) and compensation voltage (first temperature compensation voltage) for different temperatures. The reading time and reading voltage are adjusted respectively in combination with the compensation time and compensation voltage, thereby eliminating the adverse effects of temperature on the memory reading operation.

[0121] Specifically, two temperature compensation formulas can be provided, one formula can calculate the compensation time based on the temperature value, and the other formula can calculate the compensation voltage based on the temperature value. These two formulas can be summarized by R&D personnel based on a large number of experiments.

[0122] The target offset function may include multiple variables, such as a read time offset variable, a temperature compensation time variable, and a temperature compensation voltage variable. The target read voltage offset parameter may be calculated based on the actual values ​​of these variables. The target read voltage offset parameter may include 0, a positive number, or a negative number.

[0123] For example, the target offset function can be a binary linear curve equation m(x+b)+n(y+c)=p, where m, n and p are known quantities, b is the temperature compensation time variable, c is the temperature compensation voltage variable, x is the reading time offset variable, and y is the reading voltage offset variable. After substituting the numerical values ​​of each corresponding variable into the target offset function (that is, taking the first temperature compensation time as the value of the temperature compensation time variable b, taking the first temperature compensation voltage as the value of the temperature compensation voltage variable c, and taking the target reading time offset parameter as the value of the reading time offset variable x), the numerical value corresponding to the reading voltage offset variable y can be calculated, and this value is the target reading voltage offset parameter.

[0124] In some embodiments, the first processing unit 502 is configured to:

[0125] Determine the candidate time corresponding to the target number of read failures with the smallest value as the target candidate time;

[0126] The difference between the target candidate time and the standard reading time is determined to obtain the target reading time offset parameter.

[0127] Among them, the larger the value of the target read failure bit, the worse the effect of the read operation at the corresponding read time, and the smaller the value, the better the effect of the read operation at the corresponding read time. The read time with the relatively best reading effect can be used as the target candidate time. For example, for candidate times t1 to t3, if the target read failure bit number read at t1 is the smallest, then t1 is used as the target candidate time, and if the standard read time is T0, then the target read time offset parameter Δt = t1-T0, wherein the target read time offset parameter can be regarded as a time offset relative to the standard read time, which can include 0, a positive number or a negative number.

[0128] Based on the voltage calibration method provided in the above embodiment, the present application also provides another voltage calibration device. Please refer to Figure 6, which is a schematic diagram of the structure of another voltage calibration device 600 provided in the embodiment of the present application. Voltage calibration device 600 is used to test electronic equipment in the R&D stage. It includes a second processing unit 601, which is electrically connected to the above-mentioned memory. The memory includes a memory cell array. The second processing unit 601 is configured to:

[0129] placing the memory cell array at a reference temperature and a preset temperature respectively, performing a read operation on the memory cell array at a standard read voltage and any one of a plurality of preset read times, and obtaining corresponding first and second read failure bit numbers;

[0130] placing the memory cell array at the reference temperature and the preset temperature respectively, performing a read operation on the memory cell array at any one of a plurality of preset read voltages and a standard read time, and obtaining a corresponding third read failure bit number and a fourth read failure bit number;

[0131] determining the target offset function according to the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, the fourth number of read failure bits, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time;

[0132] The target offset function is stored in the memory.

[0133] The reference temperature can be a temperature that has little or no effect on the read operation of the memory cell array, such as room temperature. Considering that low temperatures have little effect on the performance of most memories, while high temperatures have a greater impact, the preset temperature can be a temperature higher than the reference temperature. In actual operation, the memory can be placed in a temperature-controlled room with adjustable temperature. The preset read time is typically multiple times excluding the standard read time, and the preset read voltage is typically multiple voltages excluding the standard read voltage.

[0134] Specifically, the read conditions can be controlled by controlling the read voltage and read time. The effect of temperature on the read operation can be analyzed by placing the memory at different temperatures and performing read operations under the same read conditions. This allows the target offset function related to temperature, read time, and read voltage to be determined. The first and third read failure bit numbers are data read results measured at a reference temperature using only an offset in read time or only an offset in read voltage. The second and fourth read failure bit numbers are data read results measured at a preset temperature different from the reference temperature using only an offset in read time or only an offset in read voltage.

[0135] For example, assuming that the reference temperature is H0, the standard read voltage is V0, the standard read time is T0, the preset temperatures include H1~Hn, the preset read voltages include V1~Vm, and the preset read times include T1~Tg, then for any temperature (that is, one of H0 and H1~Hn), the standard read time T0 can be used as a quantity, and different preset read voltages V1~Vm can be used as a single variable (that is, only the read voltage is offset) to set multiple read conditions, and the standard read voltage V0 can be used as a quantity, and different preset read times T1~Tg can be used as a single variable (that is, only the read time is offset) to set multiple read conditions, and different read conditions are used to perform read operations and obtain corresponding data read results (the number of read failure bits), and the impact of temperature on the read operation is analyzed based on the data read results of the same read conditions at different temperatures, and then the target offset function related to temperature, read time and read voltage is determined.

[0136] In some embodiments, the second processing unit 601 is configured to:

[0137] determining a temperature difference between each of the preset temperatures and the reference temperature, a time difference between each of the preset reading times and the standard reading time, and a voltage difference between each of the preset reading voltages and the standard reading voltage;

[0138] determining, based on the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters;

[0139] The target offset function is determined according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits.

[0140] Among them, the benchmark mapping relationship can be regarded as a comparison table between the read time offset parameter and the read voltage offset parameter of the memory when it is not affected by temperature. The read time offset parameter is the offset relative to the standard read time, and the read voltage offset parameter is the offset relative to the standard read voltage.

[0141] Specifically, the temperature difference Δh1~Δhn between each of the preset temperatures H1~Hn and the reference temperature H0, the time difference Δt1~Δtg between each of the preset read times T1~Tg and the standard read time T0, and the voltage difference Δv1~Δvm between each of the preset read voltages V1~Vm and the standard read voltage V0 can be calculated. Based on these differences and the number of read failure bits, a comparison table (reference mapping relationship) between multiple offset voltages and offset times is determined when the memory is not affected by temperature, and based on the reference mapping relationship, a mapping formula (target offset function) between the offset voltage and offset time of the memory when it is at any temperature is further determined.

[0142] In some embodiments, the second processing unit 601 is configured to:

[0143] determining, based on the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters;

[0144] Determining a reference relationship offset value according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits;

[0145] The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

[0146] For example, for Δt1 in the time difference values ​​Δt1~Δtg, since Δt1=T1-T0, the number of first read failure bits corresponding to Δt1 is the two first read failure bits corresponding to T1 and T0; for Δv3 in the voltage difference values ​​Δv1~Δvm, since Δv3=v3-V0, the number of third read failure bits corresponding to Δv3 is the two third read failure bits corresponding to v3 and V0, so that each voltage difference value Δv corresponds to a bit difference (third bit difference), and each time difference value Δt corresponds to a bit difference (first bit difference).

[0147] When all first-digit differences and third-digit differences are calculated, an approximate linear compensation method can be used to determine the mapping relationship between the offset time and the offset voltage, that is, to obtain a comparison table (reference mapping relationship) between multiple offset times and offset voltages when the memory is not affected by temperature.

[0148] In some embodiments, the second processing unit 601 is configured to:

[0149] Determine a bit difference between two of the second read failure bit values ​​corresponding to each of the time differences as a second bit difference, and determine a bit difference between two of the fourth read failure bit values ​​corresponding to each of the voltage differences as a fourth bit difference;

[0150] Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference;

[0151] Determining the reference relationship offset value according to the reference mapping relationship, the first difference, the second difference, and the temperature difference;

[0152] The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

[0153] The reference relationship offset value is equivalent to an offset of the mapping relationship between the offset time and the offset voltage after combining the temperature factor, which is equivalent to obtaining the slope a in the linear equation y=ax, where x is the offset time and y is the offset voltage.

[0154] For example, for Δt1 in the time difference values ​​Δt1~Δtg, since Δt1=T1-T0, the number of second read failure bits corresponding to Δt1 is the two second read failure bits corresponding to T1 and T0; for Δv3 in the voltage difference values ​​Δv1~Δvm, since Δv3=v3-V0, the number of fourth read failure bits corresponding to Δv3 is the two fourth read failure bits corresponding to v3 and V0, so that each voltage difference value Δv corresponds to a bit difference (fourth bit difference), and each time difference value Δt corresponds to a bit difference (second bit difference).

[0155] Since the first and third read failure bit numbers are data reading results measured at the reference temperature using only the offset read time or only the offset read voltage, and the second and fourth read failure bit numbers are data reading results measured at a preset temperature different from the reference temperature using only the offset read time or only the offset read voltage, the error between the bit difference values ​​corresponding to the preset temperature and the reference temperature can be calculated for the same reading condition (such as only the offset time or only the offset voltage), that is, the error (first difference and second difference) generated when reading data due to the temperature influence on the memory. Based on these errors, an approximate linear compensation method is used to adjust the voltage difference Δv and the time difference Δt, so that the time difference Δt (offset time) and the voltage difference Δv (offset voltage) roughly conform to the input value x and output value y of a linear equation y=ax, and the slope a of the linear equation can be used as the reference relationship offset value.

[0156] In some embodiments, the second processing unit 601 is configured to:

[0157] Obtaining a second temperature compensation time and a second temperature compensation voltage corresponding to each of the preset temperatures;

[0158] determining an initial offset function according to the reference relationship offset value;

[0159] The target offset function is determined according to the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

[0160] The second temperature compensation time and the second temperature compensation voltage corresponding to each temperature can be determined by the temperature compensation formula stored in the memory. Specifically, the initial offset function can be directly constructed based on the reference relationship offset value. For example, the initial offset function can be y+c=a(x+b), where c is the temperature compensation voltage variable, b is the temperature compensation time variable, and a is the reference relationship offset value. Afterwards, the actual values ​​of each calculated variable are substituted into the initial offset function for testing and verification, and the initial offset function is manually fine-tuned so that each actual value roughly satisfies the fine-tuned initial offset function, such as obtaining m(x+b)+n(y+c)=p, where m, n, and p are obtained through fine-tuning, and the fine-tuned initial offset function is the target offset function.

[0161] As can be seen from the above, the voltage calibration method and its device, memory and memory system provided by the embodiments of the present application, during the read voltage calibration process of the memory cell array, detect the number of read failure bits at multiple candidate times with a standard read voltage and detect the ambient temperature in which it is located, and then calibrate the read voltage in combination with the ambient temperature, the number of read failure bits and the stored target offset function, thereby eliminating the impact of changes in the ambient temperature and the memory itself on the read voltage offset, improving the accuracy of the read voltage calibration, and reducing the failure rate of the read operation.

[0162] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A voltage calibration method, wherein include: Detecting the current target temperature of the storage cell array; Performing a read operation on the memory cell array at a plurality of candidate times respectively with a standard read voltage, and obtaining a corresponding target number of read failure bits, wherein each candidate time corresponds to one target number of read failure bits; Determine a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and a stored target offset function; The target read voltage offset parameter is used to calibrate a read voltage of the memory cell array in a read operation.

2. The voltage calibration method according to claim 1, in, Determining a target read voltage offset parameter according to the target temperature, the target number of read failures, the candidate time, and the stored target offset function includes: Determine a first temperature compensation time and a first temperature compensation voltage corresponding to the target temperature; Determine a target read time offset parameter according to the target number of read failures, the candidate time and the standard read time; The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into a stored target offset function to obtain the target read voltage offset parameter.

3. The voltage calibration method according to claim 2, in, Determining a target read time offset parameter according to the target number of read failures, the candidate time and the standard read time includes: Determine the candidate time corresponding to the target number of failed reads with the smallest value as the target candidate time; The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

4. The voltage calibration method according to claim 1, in, Before determining the target read voltage offset parameter according to the target temperature, the first number of read failure bits, the candidate time, and the stored target offset function, the method further includes: Placing the memory cell array at a reference temperature and a preset temperature respectively, and performing a read operation on the memory cell array at a standard read voltage and any one of a plurality of preset read times, and obtaining a corresponding first number of read failure bits and a second number of read failure bits; Placing the memory cell array at the reference temperature and the preset temperature respectively, and performing a read operation on the memory cell array at any preset read voltage among a plurality of preset read voltages and a standard read time, and obtaining a corresponding third read failure bit number and a fourth read failure bit number; determining the target shift function according to the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, the fourth number of read failure bits, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time; The target offset function is stored.

5. The voltage calibration method according to claim 4, in, The determining the target shift function according to the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, the fourth number of read failure bits, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time includes: Determine a temperature difference between each of the preset temperatures and the reference temperature, a time difference between each of the preset read times and the standard read time, and a voltage difference between each of the preset read voltages and the standard read voltage; Determine, according to the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters; The target shift function is determined according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits.

6. The voltage calibration method according to claim 5, in, The determining, according to the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature comprises: Determine a bit difference between two first read failure bit values ​​corresponding to each of the time difference values ​​as a first bit difference; Determine a bit difference between two third read failure bit values ​​corresponding to each voltage difference value as a third bit difference value; The reference mapping relationship is determined according to the time difference, the first bit difference, the voltage difference and the third bit difference.

7. The voltage calibration method according to claim 6, in, The determining the target shift function according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits includes: Determine the difference between the two second read failure bit numbers corresponding to each of the time difference values ​​as the second bit number difference, and determine the difference between the two fourth read failure bit numbers corresponding to each of the voltage difference values ​​as the fourth bit number difference; Determine a first difference between the first digit difference and the second digit difference corresponding to each of the temperature differences, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each of the temperature differences; Determining the reference relationship offset value according to the reference mapping relationship, the first difference, the second difference and the temperature difference; The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

8. The voltage calibration method according to claim 7, in, The determining the target offset function according to the reference relationship offset value and the reference mapping relationship comprises: Acquire the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures; Determining an initial offset function according to the reference relationship offset value; The target offset function is determined according to the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

9. A voltage calibration device, include: a temperature sensor configured to detect a target temperature currently located at the memory cell array; a first processing unit, the first processing unit being electrically connected to the memory cell array and the temperature sensor, and being configured to perform a read operation on the memory cell array at a plurality of candidate times at a standard read voltage, and obtain a corresponding target number of read failure bits, each of the candidate times corresponding to one target number of read failure bits; A target read voltage offset parameter is determined according to the target temperature, the target number of read failure bits, the candidate time, and the stored target offset function; and a read voltage of the memory cell array in a read operation is calibrated with the target read voltage offset parameter.

10. The voltage calibration device according to claim 9, in, The first processing unit is configured to: Determine a first temperature compensation time and a first temperature compensation voltage corresponding to the target temperature; Determine a target read time offset parameter according to the target number of read failures, the candidate time and the standard read time; The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into a stored target offset function to obtain the target read voltage offset parameter.

11. The voltage calibration device according to claim 10, in, The first processing unit is configured to: Determine the candidate time corresponding to the target number of failed reads with the smallest value as the target candidate time; The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

12. A voltage calibration device, in, The voltage calibration device includes a second processing unit, the second processing unit is electrically connected to a memory, the memory includes a storage unit array, and the second processing unit is configured as follows: Placing the memory cell array at a reference temperature and a preset temperature respectively, performing a read operation on the memory cell array at a standard read voltage and any one of a plurality of preset read times, and obtaining a corresponding first number of read failure bits and a second number of read failure bits; Placing the memory cell array at the reference temperature and the preset temperature respectively, and performing a read operation on the memory cell array at any preset read voltage among a plurality of preset read voltages and a standard read time, and obtaining a corresponding third read failure bit number and a fourth read failure bit number; determining the target shift function according to the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, the fourth number of read failure bits, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time; The target offset function is stored in the memory.

13. The voltage calibration device according to claim 12, in, The second processing unit is configured to: Determine a temperature difference between each of the preset temperatures and the reference temperature, a time difference between each of the preset read times and the standard read time, and a voltage difference between each of the preset read voltages and the standard read voltage; Determine the reading error of the memory cell array at the reference temperature according to the time difference, the voltage difference, the first read failure bit number and the third read failure bit number. a reference mapping relationship in operation, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters; The target shift function is determined according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits.

14. The voltage calibration device according to claim 13, in, The second processing unit is configured to: Determine, according to the time difference, the voltage difference, the first number of read failure bits, and the third number of read failure bits, a reference mapping relationship of the memory cell array in a read operation at the reference temperature, wherein the reference mapping relationship is a one-to-one correspondence between a plurality of read time offset parameters and a plurality of read voltage offset parameters; Determine a reference relationship offset value according to the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits; The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

15. The voltage calibration device according to claim 14, in, The second processing unit is configured to: Determine the difference between the two second read failure bit numbers corresponding to each of the time difference values ​​as the second bit number difference, and determine the difference between the two fourth read failure bit numbers corresponding to each of the voltage difference values ​​as the fourth bit number difference; Determine a first difference between the first digit difference and the second digit difference corresponding to each of the temperature differences, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each of the temperature differences; Determining the reference relationship offset value according to the reference mapping relationship, the first difference, the second difference and the temperature difference; The target offset function is determined according to the reference relationship offset value and the reference mapping relationship.

16. The voltage calibration device according to claim 15, in, The second processing unit is configured to: Acquire the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures; Determining an initial offset function according to the reference relationship offset value; The target offset function is determined according to the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

17. A memory comprising a memory cell array and a peripheral circuit structure coupled to the memory cell array, wherein the peripheral circuit structure comprises the voltage calibration device according to any one of claims 9 to 11.

18. A memory system comprising at least one memory according to claim 17, and a controller coupled to the memory, wherein the controller is used to control the memory to store data.

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