Voltage calibration method and apparatus, memory, and memory system

Abstract

A voltage calibration method and device, memory and memory system, the method comprising: detecting a target temperature at which a memory cell array currently is; performing read operations on the memory cell array at a plurality of candidate times respectively with a standard read voltage, and obtaining corresponding target read failure bit numbers; determining a target read voltage offset parameter according to the target temperature, the target read failure bit numbers, the candidate times and a stored target offset function, and calibrating the read voltage.

Description

[Technical Field]

[0001] This application relates to the field of semiconductor technology, specifically to a voltage calibration method and apparatus, a memory, and a memory system. [Background Technology]

[0002] With the advancement of storage technology, the application of three-dimensional memory (such as 3D NAND flash memory chips) is becoming more and more widespread. For example, three-dimensional memory can be used in devices such as mobile phones and computers.

[0003] In a three-dimensional memory, when reading data from any memory cell, different read voltages can be applied sequentially to the control gate of that memory cell. Then, based on the conduction state of the corresponding bit line after applying different read voltages, the data read result of that memory cell can be determined.

[0004] However, as usage time and number of read / write operations affect memory performance, the read voltage of the memory cell will shift. This shifted read voltage can lead to errors in the read data, thus requiring a read voltage calibration scheme. [Summary of the Invention]

[0005] This application provides a voltage calibration method, apparatus, memory, and memory system that can effectively calibrate the read voltage and improve the accuracy of data read operations.

[0006] On one hand, embodiments of this application provide a voltage calibration method, including:

[0007] Detect the target temperature of the storage cell array;

[0008] Using a standard read voltage, read operations are performed on the memory cell array at multiple candidate times, and the corresponding target read failure bit number is obtained, with each candidate time corresponding to one read failure bit number;

[0009] The target read voltage offset parameter is determined based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function;

[0010] The read voltage of the memory cell array during read operations is calibrated using the target read voltage offset parameter.

[0011] On the other hand, embodiments of this application also provide a voltage calibration device, including:

[0012] A temperature sensor is configured to detect the target temperature currently present in the memory cell array;

[0013] A first processing unit is electrically connected to the storage cell array and the temperature sensor, and is configured to perform read operations on the storage cell array at multiple candidate times using a standard read voltage, and obtain the corresponding target read failure number of bits, with each candidate time corresponding to one target read failure number of bits; determine a target read voltage offset parameter based on the target temperature, the target read failure number of bits, the candidate time, and a stored target offset function; and calibrate the read voltage of the storage cell array during the read operation using the target read voltage offset parameter.

[0014] On the other hand, embodiments of this application also provide a voltage calibration device, including a second processing unit electrically connected to a memory, the memory including a memory cell array, and the second processing unit being configured to:

[0015] The memory cell array is placed at a reference temperature and a preset temperature, respectively. A read operation is performed on the memory cell array using a standard read voltage and any preset read time from a plurality of preset read times, and the corresponding first read failure number and second read failure number are obtained.

[0016] The storage cell array is placed at the reference temperature and the preset temperature respectively, and a read operation is performed on the storage cell array with any preset read voltage and standard read time from a plurality of preset read voltages, and the corresponding third read failure number and fourth read failure number are obtained;

[0017] The target offset function is determined based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time.

[0018] The target offset function is stored in the memory.

[0019] On the other hand, embodiments of this application also provide a memory, including a memory cell array and a peripheral circuit structure coupled to the memory cell array, wherein the peripheral circuit structure includes any of the voltage calibration devices described above.

[0020] On the other hand, embodiments of this application also provide a memory system, including at least one memory as described above, and a controller coupled to the memory, the controller being used to control the memory to store data.

[0021] The voltage calibration method, apparatus, memory, and memory system provided in this application, during the read voltage calibration process of the memory cell array, detect the number of read failures at multiple candidate times using a standard read voltage and detect the ambient temperature. Then, the read voltage is calibrated by combining the ambient temperature, the number of read failures, and the stored target offset function. This eliminates the influence of ambient temperature and changes in the memory itself on the read voltage offset, improves the accuracy of read voltage calibration, and reduces the failure rate of read operations. [Attached Image Description]

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the system structure provided in the embodiments of this application;

[0024] Figure 2 This is a schematic diagram of the structure of the memory provided in the embodiments of this application;

[0025] Figure 3 This is a schematic flowchart of the voltage calibration method provided in the embodiments of this application;

[0026] Figure 4 This is another schematic flowchart of the voltage calibration method provided in the embodiments of this application;

[0027] Figure 5 This is a schematic diagram of the voltage calibration device provided in the embodiments of this application;

[0028] Figure 6 This is a schematic diagram of another voltage calibration device provided in an embodiment of this application.

Detailed Implementation Methods

[0029] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be noted that the following embodiments are for illustrative purposes only and do not limit the scope of the application. Similarly, the following embodiments are only some, not all, embodiments of the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0030] In this description, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features.

[0031] It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0032] Figure 1 This is a schematic diagram of the structure of an exemplary system 100 provided in an embodiment of this application. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 101 and a memory system 102, the memory system 102 including one or more memories 1021 and a controller 1022. The host 101 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SOC) (e.g., an application processor (AP)). The host 101 may be configured to send data to or receive data from the memory 1021.

[0033] In the examples of this application, memory 1021 is not limited to three-dimensional NAND memory. Without departing from the disclosure or teachings of this application, memory 1021 can be implemented as various other types of non-volatile memory that can retain the stored data when the power is disconnected.

[0034] In some implementations, controller 1022 is coupled to memory 1021 and host 101 and is configured to control memory 1021, such as controlling memory 1021 to perform data write and read operations. Controller 1022 can manage data stored in memory 1021 and communicate with host 101.

[0035] The controller 1022 can be configured to control the operation of the memory 1021, such as read, erase, and program operations. The controller 1022 can also be configured to manage various functions related to data stored or to be stored in the memory 1021, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0036] The controller 1022 and one or more memories 1021 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of electronic products.

[0037] Figure 2 This is a schematic diagram of the structure of the memory 200 provided in the embodiments of this application. The memory 200 includes a memory cell array 201 and a peripheral circuit structure 202 coupled to the memory cell array 201. The peripheral circuit structure 202 can be configured to perform operations such as reading, writing, erasing and verifying on the memory cell array 201, and the peripheral circuit structure 202 can include any of the following voltage calibration devices 500.

[0038] In some implementations, the peripheral circuit structure 202 may also include word line drivers, bit line drivers, column decoders, sensing circuits, data buffers, program verification logic, and erase verification circuits, which can perform the above operations according to the acquired computer program instructions.

[0039] The storage cell array 201 can include multiple storage blocks. Each block is logically divided into multiple pages, and each page includes multiple storage cells. A page is the smallest unit for data read and write operations, while a block is the smallest unit for data erase operations. Storage cells can be classified into various types based on the amount of data that can be stored within each cell, such as Single-Level Cell (SLC) for storing one bit of data, Multi-Level Cell (MLC) for storing two bits of data, and Triple-Level Cell (TLC) for storing three bits of data.

[0040] For a single memory cell in the memory cell array 201, different memory states exist when storing different numbers of electrons. For example, when the memory cell is of TLC type, it has eight memory states, corresponding to "111", "110", "100", "000", "010", "011", "001", and "101", respectively. Different memory states correspond to different threshold voltages. Typically, for a memory cell with any memory state, when the read voltage applied to its control gate (equivalent to a word line) is greater than or equal to the threshold voltage of the corresponding memory state, the memory cell can be turned on. Thus, for a memory cell, different read voltages can be applied sequentially to the control gate of the memory cell, and then the memory state of the memory cell can be determined based on the conduction state of the corresponding bit line after applying different read voltages, thereby determining the data read result of the memory cell.

[0041] However, as the number of read / write operations and usage time increase, the memory 200 itself will experience a certain degree of wear and tear, and changes in the usage environment will also affect the performance of the memory 200. These factors may cause the read voltage to deviate during read operations, and the deviated read voltage will cause errors when reading data. Therefore, it is necessary to calibrate the read voltage, and how to accurately calibrate the read voltage is an urgent technical problem to be solved.

[0042] This application provides a voltage calibration method and apparatus, a memory, and a memory system.

[0043] Please see Figure 3 , Figure 3 This is a schematic flowchart of a voltage calibration method provided in an embodiment of this application. The voltage calibration method may include the following steps S301-S304, wherein:

[0044] Step S301. Detect the target temperature of the storage cell array;

[0045] Step S302. Using a standard read voltage, perform read operations on the memory cell array at multiple candidate times and obtain the corresponding target read failure bit number, where each candidate time corresponds to one read failure bit number;

[0046] Step S303. Determine the target read voltage offset parameter based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function;

[0047] Step S304. Calibrate the read voltage of the memory cell array during read operations using the target read voltage offset parameter.

[0048] It should be understood that the steps shown in the above manufacturing method are not exclusive, and other steps can be performed before, after, or between any of the steps shown. Furthermore, steps S301 and S302 can be performed simultaneously or sequentially; the numerical order is merely an example of an execution order, and there is no restriction on the execution order here.

[0049] The standard read voltage and candidate time can be pre-set by the developers. The standard read voltage is typically related to the threshold voltage of each memory state in the memory cells of the memory array; it is the estimated optimal read voltage for reading the memory array, and can be considered the read voltage with the fewest read failures. The candidate time is related to the standard read time of the memory array; the standard read time is the estimated optimal read time for reading the memory array, and can be considered the read time with the fewest read failures. The target offset function can be approximated as a curve function, and it is set in advance by the developers based on the read operation conditions of the memory array at different temperatures.

[0050] It should be noted that the voltage calibration method provided in this application embodiment can be manually triggered by the user, such as the user manually operating the electronic device to trigger the calibration of the read voltage, or it can be automatically triggered by the memory, such as automatically triggering the calibration of the read voltage when a specified time is reached.

[0051] The voltage calibration method provided in this application sets a target offset function in advance based on the read operation of the memory cell array at different temperatures and stores it in the memory. Then, during the read voltage calibration process of the memory cell array, the number of read failures is detected at multiple candidate times using the standard read voltage, and the ambient temperature is detected. The read voltage is then calibrated by combining the ambient temperature, the number of read failures, and the target offset function. This eliminates the influence of ambient temperature and changes in the memory itself on the read voltage offset, improves the accuracy of read voltage calibration, and reduces the failure rate of read operations.

[0052] Please continue reading Figure 3 The steps S301-S304 described above will be further described below.

[0053] Step S301. Detect the target temperature of the storage cell array.

[0054] Among these, the target temperature can be detected using a temperature sensor.

[0055] Step S302. Using a standard read voltage, perform read operations on the memory cell array at multiple candidate times and obtain the corresponding target read failure bit number, with each candidate time corresponding to one target read failure bit number.

[0056] The standard read voltage and candidate time can be set and stored in advance by the developers. The standard read voltage is usually related to the threshold voltage of each memory state of the memory cell in the memory cell array. It is the estimated optimal read voltage when performing read operations on the memory cell array, and can be considered as the read voltage with the fewest read failures.

[0057] The candidate time is related to the standard read time of the storage cell array, and can be multiple times including the standard read time. The standard read time is the estimated optimal read time when performing a read operation on the storage cell array, which can be considered as the read time with the fewest read failures. For example, if the standard read time is 1 second, the candidate times can include 0.5 seconds, 1 second, and 1.5 seconds.

[0058] The target read failure bits represent the amount of data that failed to be read. For the same memory cell array, each read operation may result in some data read failures, and the amount of failed data may vary depending on the time of read or the voltage used. Typically, the amount of failed data is minimized when reading at the standard read time and standard read voltage, ideally reaching zero.

[0059] Step S303. Determine the target read voltage offset parameter based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function.

[0060] The target offset function can be approximated as a curve function. It is set in advance by the developers based on the read operation conditions of the memory cell array at different temperatures, and it is stored in the memory. The target read voltage offset parameter can be regarded as the voltage offset relative to the standard read voltage.

[0061] In some implementations, please refer to Figure 4 The above step S303 may specifically include the following steps S3031-S3033, wherein:

[0062] S3031. Determine the first temperature compensation time and the first temperature compensation voltage corresponding to the target temperature.

[0063] Since high temperatures can affect the performance of the memory itself, such as slowing down the processing speed at high temperatures, the memory can provide a temperature compensation function for data read operations. This temperature compensation function mainly sets the compensation time (first temperature compensation time) and compensation voltage (first temperature compensation voltage) for different temperatures. The read time and read voltage are adjusted by combining the compensation time and compensation voltage, thereby eliminating the adverse effects of temperature on the memory's read operations.

[0064] Specifically, two temperature compensation formulas can be provided. One formula can calculate the compensation time based on the temperature value, and the other formula can calculate the compensation voltage based on the temperature value. These two formulas can be obtained by the R&D personnel based on a large number of experiments.

[0065] S3032. Determine the target read time offset parameter based on the target number of read failures, the candidate time, and the standard read time.

[0066] In some implementations, step S3032 may specifically include:

[0067] The candidate time corresponding to the smallest number of target read failure bits is determined as the target candidate time;

[0068] The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

[0069] The larger the target read failure number, the worse the read operation performance at the corresponding read time; the smaller the value, the better the read operation performance at the corresponding read time. The read time with the best read performance can be used as the target candidate time. For example, for candidate times t1 to t3, if the target read failure number is the smallest at t1, then t1 is used as the target candidate time. If the standard read time is T0, then the target read time offset parameter Δt = t1 - T0. The target read time offset parameter can be regarded as the time offset relative to the standard read time, which can include 0, positive or negative numbers.

[0070] S3033. Input the target reading time offset parameter, the first temperature compensation time, and the first temperature compensation voltage into the stored target offset function to obtain the target reading voltage offset parameter.

[0071] The target offset function can include multiple variables, such as the read time offset variable, the temperature compensation time variable, and the temperature compensation voltage variable. The target read voltage offset parameter can be calculated based on the actual values ​​of these variables. The target read voltage offset parameter can be 0, positive, or negative.

[0072] For example, the target offset function can be a linear equation in two variables, m(x+b)+n(y+c)=p, where m, n, and p are known quantities, b is the temperature compensation time variable, c is the temperature compensation voltage variable, x is the reading time offset variable, and y is the reading voltage offset variable. Then, by substituting the values ​​of each corresponding variable into the target offset function (that is, taking the first temperature compensation time as the value of the temperature compensation time variable b, the first temperature compensation voltage as the value of the temperature compensation voltage variable c, and the target reading time offset parameter as the value of the reading time offset variable x), the value corresponding to the reading voltage offset variable y can be obtained. This value is the target reading voltage offset parameter.

[0073] Step S304. Calibrate the read voltage of the memory cell array during read operations using the target read voltage offset parameter.

[0074] Specifically, the sum of the standard read voltage and the target read voltage offset parameter can be calculated as the updated read voltage, and then the updated read voltage can be used to perform data reading operations during the read operation.

[0075] It should be noted that the target offset function mentioned above is usually designed and stored in memory during the R&D phase. For details, please refer to [link to relevant documentation]. Figure 4 Before the above step of "determining the target read voltage offset parameter based on the target temperature, the first read failure bit count, the candidate time, and the stored target offset function", the voltage calibration method further includes:

[0076] S401. Place the storage cell array at a reference temperature and a preset temperature respectively, and perform a read operation on the storage cell array with a standard read voltage and any preset read time among a plurality of preset read times, and obtain the corresponding first read failure number and second read failure number;

[0077] S402. Place the storage cell array at the reference temperature and the preset temperature respectively, and perform a read operation on the storage cell array with any preset read voltage and standard read time from a plurality of preset read voltages, and obtain the corresponding third read failure number and fourth read failure number;

[0078] The reference temperature can be a temperature that has little or no impact on the read operations of the memory cell array, such as room temperature. Considering that low temperatures have a relatively small impact on the performance of most memories, while high temperatures have a greater impact, the preset temperature can be a temperature higher than the reference temperature. In actual operation, the memory can be placed in a temperature-controlled room with adjustable temperature. The preset read time is usually a multiple time interval excluding the standard read time, and the preset read voltage is usually a multiple voltage interval excluding the standard read voltage.

[0079] Specifically, read conditions can be controlled by adjusting the read voltage and read time. Furthermore, by placing the memory at different temperatures and performing read operations under the same conditions, the impact of temperature on the read operation can be analyzed to determine the target offset function related to temperature, read time, and read voltage. The first and third read failure numbers are data read results measured at a reference temperature using either an offset only of the read time or an offset only of the read voltage. The second and fourth read failure numbers are data read results measured at preset temperatures different from the reference temperature using either an offset only of the read time or an offset only of the read voltage.

[0080] S403. Determine the target offset function based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time;

[0081] S404. Store the target offset function.

[0082] For example, assuming the reference temperature is H0, the standard reading voltage is V0, the standard reading time is T0, the preset temperatures include H1 to Hn, the preset reading voltages include V1 to Vm, and the preset reading times include T1 to Tg, then for any temperature (i.e., one of H0 and H1 to Hn), the standard reading time T0 can be used as a fixed quantity, and different preset reading voltages V1 to Vm can be used as single variables (i.e., only the reading voltage is offset) to set multiple reading conditions. Alternatively, the standard reading voltage V0 can be used as a fixed quantity, and different preset reading times T1 to Tg can be used as single variables (i.e., only the reading time is offset) to set multiple reading conditions. Reading operations are performed using different reading conditions, and the corresponding data reading results (number of read failures) are obtained. Based on the data reading results of the same reading conditions at different temperatures, the influence of temperature on the reading operation is analyzed, and then the target offset function related to temperature, reading time, and reading voltage is determined.

[0083] In some implementations, step S403 may specifically include:

[0084] Determine the temperature difference between each preset temperature and the reference temperature, the time difference between each preset reading time and the standard reading time, and the voltage difference between each preset reading voltage and the standard reading voltage;

[0085] Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters.

[0086] The target offset function is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failures, the second number of read failures, the third number of read failures, and the fourth number of read failures.

[0087] The reference mapping relationship can be seen as a lookup table between the read time offset parameter and the read voltage offset parameter of the memory when it is not affected by temperature. The read time offset parameter is the offset relative to the standard read time, and the read voltage offset parameter is the offset relative to the standard read voltage.

[0088] Specifically, the temperature difference Δh1 to Δhn between each of the preset temperatures H1 to Hn and the reference temperature H0 can be calculated; the time difference Δt1 to Δtg between each of the preset read times T1 to Tg and the standard read time T0 can be calculated; and the voltage difference Δv1 to Δvm between each of the preset read voltages V1 to Vm and the standard read voltage V0 can be calculated. Based on these differences and the number of read failures, a lookup table (reference mapping relationship) between multiple offset voltages and offset times can be determined when the memory is not affected by temperature. Based on the reference mapping relationship, the mapping formula (target offset function) between the offset voltage and offset time of the memory at any temperature can be further determined.

[0089] In some implementations, the step of "determining the reference mapping relationship of the memory cell array in the read operation at the reference temperature based on the time difference, the voltage difference, the first read failure number of bits, and the third read failure number of bits" may specifically include:

[0090] Determine the bit difference between the two first read failure bits corresponding to each time difference value, and use it as the first bit difference value;

[0091] The bit difference between the two third read failure bits corresponding to each voltage difference is determined as the third bit difference;

[0092] The reference mapping relationship is determined based on the time difference, the first bit difference, the voltage difference, and the third bit difference.

[0093] For example, for the time difference Δt1 to Δtg, since Δt1 = T1 - T0, the first read failure number corresponding to Δt1 is the two first read failure numbers corresponding to T1 and T0; for the voltage difference Δv3 to Δvm, since Δv3 = v3 - V0, the third read failure number corresponding to Δv3 is the two third read failure numbers corresponding to v3 and V0. Thus, each voltage difference Δv corresponds to one bit difference (third bit difference), and each time difference Δt corresponds to one bit difference (first bit difference).

[0094] Once all the first and third bit differences are calculated, an approximate linear compensation method can be used to determine the mapping relationship between offset time and offset voltage, that is, to obtain a reference mapping table (baseline mapping relationship) between multiple offset times and offset voltages when the memory is not affected by temperature.

[0095] In some implementations, the step of "determining the target offset function based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first read failure number of bits, the second read failure number of bits, the third read failure number of bits, and the fourth read failure number of bits" may specifically include:

[0096] The bit difference between the two second read failure bits corresponding to each time difference value is determined as the second bit difference value, and the bit difference between the two fourth read failure bits corresponding to each voltage difference value is determined as the fourth bit difference value;

[0097] Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference value, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference value;

[0098] The reference relationship offset value is determined based on the reference mapping relationship, the first difference, the second difference, and the temperature difference.

[0099] The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

[0100] The reference relationship offset value is equivalent to an offset of the mapping relationship between offset time and offset voltage after incorporating temperature factors. It is equivalent to obtaining the slope 'a' in the linear equation y = ax, where x is the offset time and y is the offset voltage.

[0101] For example, for the time difference Δt1 to Δtg, since Δt1 = T1 - T0, the second read failure number corresponding to Δt1 is the two second read failure numbers corresponding to T1 and T0; for the voltage difference Δv3 to Δvm, since Δv3 = v3 - V0, the fourth read failure number corresponding to Δv3 is the two fourth read failure numbers corresponding to v3 and V0. Thus, each voltage difference Δv corresponds to one bit difference (fourth bit difference), and each time difference Δt corresponds to one bit difference (second bit difference).

[0102] Since the first and third read failure numbers are data read results measured at a reference temperature using only the offset read time or only the offset read voltage, and the second and fourth read failure numbers are data read results measured at a preset temperature different from the reference temperature using only the offset read time or only the offset read voltage, for the same read condition (e.g., only the offset time or only the offset voltage), the error between the bit difference corresponding to the preset temperature and the reference temperature can be calculated. That is, the error (first difference and second difference) caused by the temperature effect on the memory when reading data can be calculated. Based on these errors, an approximately linear compensation method is used to adjust the voltage difference Δv and the time difference Δt, so that the time difference Δt (offset time) and the voltage difference Δv (offset voltage) roughly conform to the input value x and output value y of a linear equation y = ax, and the slope a of the linear equation can be used as the reference relationship offset value.

[0103] In some implementations, the step of "determining the target offset function based on the reference relationship offset value and the reference mapping relationship" may specifically include:

[0104] Obtain the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures;

[0105] The initial offset function is determined based on the aforementioned baseline relationship offset value;

[0106] The target offset function is determined based on the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

[0107] Specifically, the second temperature compensation time and second temperature compensation voltage corresponding to each temperature can be determined using the temperature compensation formula stored in memory. Specifically, an initial offset function can be directly constructed based on the baseline offset value. For example, the initial offset function could be y + c = a(x + b), where c is the temperature compensation voltage variable, b is the temperature compensation time variable, and a is the baseline offset value. Then, the actual values ​​of each calculated variable are substituted into the initial offset function for testing and verification. The initial offset function is then manually fine-tuned so that each actual value roughly satisfies the fine-tuned initial offset function, for example, obtaining m(x + b) + n(y + c) = p, where m, n, and p are obtained through fine-tuning. The fine-tuned initial offset function is the target offset function.

[0108] Based on the voltage calibration method provided in the above embodiments, this application also provides a voltage calibration device. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of the voltage calibration device 500 provided in an embodiment of this application. The voltage calibration device 500 is applied in a memory, the memory including a memory cell array, and the voltage calibration device 500 includes:

[0109] Temperature sensor 501 is configured to detect the target temperature currently present in the memory cell array;

[0110] A first processing unit 502 is electrically connected to the storage cell array and the temperature sensor 501, and is configured to perform read operations on the storage cell array at multiple candidate times using a standard read voltage, and obtain the corresponding target read failure number of bits, with each candidate time corresponding to one target read failure number of bits; determine a target read voltage offset parameter based on the target temperature, the target read failure number of bits, the candidate time, and a stored target offset function; and calibrate the read voltage of the storage cell array during the read operation using the target read voltage offset parameter.

[0111] The standard read voltage and candidate time can be set and stored in advance by the developers. The standard read voltage is usually related to the threshold voltage of each memory state of the memory cell in the memory cell array. It is the estimated optimal read voltage when performing read operations on the memory cell array, and can be considered as the read voltage with the fewest read failures.

[0112] The candidate time is related to the standard read time of the storage cell array, and can be multiple times including the standard read time. The standard read time is the estimated optimal read time when performing a read operation on the storage cell array, which can be considered as the read time with the fewest read failures. For example, if the standard read time is 1 second, the candidate times can include 0.5 seconds, 1 second, and 1.5 seconds.

[0113] The target read failure bits represent the amount of data that failed to be read. For the same memory cell array, each read operation may result in some data read failures, and the amount of failed data may vary depending on the time of read or the voltage used. Typically, the amount of failed data is minimized when reading at the standard read time and standard read voltage, ideally reaching zero.

[0114] The target offset function can be approximated as a curve function. It is set in advance by the developers based on the read operation conditions of the memory cell array at different temperatures, and it is stored in the memory. The target read voltage offset parameter can be regarded as the voltage offset relative to the standard read voltage.

[0115] In some embodiments, the first processing unit 502 is configured to:

[0116] Determine the first temperature compensation time and the first temperature compensation voltage corresponding to the target temperature;

[0117] The target read time offset parameter is determined based on the target number of read failures, the candidate time, and the standard read time;

[0118] The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into the stored target offset function to obtain the target read voltage offset parameter.

[0119] Since high temperatures can affect the performance of the memory itself, such as slowing down the processing speed at high temperatures, the memory can provide a temperature compensation function for data read operations. This temperature compensation function mainly sets the compensation time (first temperature compensation time) and compensation voltage (first temperature compensation voltage) for different temperatures. The read time and read voltage are adjusted by combining the compensation time and compensation voltage, thereby eliminating the adverse effects of temperature on the memory's read operations.

[0120] Specifically, two temperature compensation formulas can be provided. One formula can calculate the compensation time based on the temperature value, and the other formula can calculate the compensation voltage based on the temperature value. These two formulas can be obtained by the R&D personnel based on a large number of experiments.

[0121] The target offset function can include multiple variables, such as the read time offset variable, the temperature compensation time variable, and the temperature compensation voltage variable. The target read voltage offset parameter can be calculated based on the actual values ​​of these variables. The target read voltage offset parameter can be 0, positive, or negative.

[0122] For example, the target offset function can be a linear equation in two variables, m(x+b)+n(y+c)=p, where m, n, and p are known quantities, b is the temperature compensation time variable, c is the temperature compensation voltage variable, x is the reading time offset variable, and y is the reading voltage offset variable. Then, by substituting the values ​​of each corresponding variable into the target offset function (that is, taking the first temperature compensation time as the value of the temperature compensation time variable b, the first temperature compensation voltage as the value of the temperature compensation voltage variable c, and the target reading time offset parameter as the value of the reading time offset variable x), the value corresponding to the reading voltage offset variable y can be obtained. This value is the target reading voltage offset parameter.

[0123] In some embodiments, the first processing unit 502 is configured to:

[0124] The candidate time corresponding to the smallest number of target read failure bits is determined as the target candidate time;

[0125] The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

[0126] The larger the target read failure number, the worse the read operation performance at the corresponding read time; the smaller the value, the better the read operation performance at the corresponding read time. The read time with the best read performance can be used as the target candidate time. For example, for candidate times t1 to t3, if the target read failure number is the smallest at t1, then t1 is used as the target candidate time. If the standard read time is T0, then the target read time offset parameter Δt = t1 - T0. The target read time offset parameter can be regarded as the time offset relative to the standard read time, which can include 0, positive or negative numbers.

[0127] Based on the voltage calibration method provided in the above embodiments, this application also provides another voltage calibration device. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of another voltage calibration device 600 provided in this application embodiment. The voltage calibration device 600 is used to test electronic devices during the research and development phase. It includes a second processing unit 601, which is electrically connected to the aforementioned memory. The memory includes a memory cell array. The second processing unit 601 is configured to:

[0128] The memory cell array is placed at a reference temperature and a preset temperature, respectively. A read operation is performed on the memory cell array using a standard read voltage and any preset read time from a plurality of preset read times, and the corresponding first read failure number and second read failure number are obtained.

[0129] The storage cell array is placed at the reference temperature and the preset temperature respectively, and a read operation is performed on the storage cell array with any preset read voltage and standard read time from a plurality of preset read voltages, and the corresponding third read failure number and fourth read failure number are obtained;

[0130] The target offset function is determined based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time.

[0131] The target offset function is stored in the memory.

[0132] The reference temperature can be a temperature that has little or no impact on the read operations of the memory cell array, such as room temperature. Considering that low temperatures have a relatively small impact on the performance of most memories, while high temperatures have a greater impact, the preset temperature can be a temperature higher than the reference temperature. In actual operation, the memory can be placed in a temperature-controlled room with adjustable temperature. The preset read time is usually a multiple time interval excluding the standard read time, and the preset read voltage is usually a multiple voltage interval excluding the standard read voltage.

[0133] Specifically, read conditions can be controlled by adjusting the read voltage and read time. Furthermore, by placing the memory at different temperatures and performing read operations under the same conditions, the impact of temperature on the read operation can be analyzed to determine the target offset function related to temperature, read time, and read voltage. The first and third read failure numbers are data read results measured at a reference temperature using either an offset only of the read time or an offset only of the read voltage. The second and fourth read failure numbers are data read results measured at preset temperatures different from the reference temperature using either an offset only of the read time or an offset only of the read voltage.

[0134] For example, assuming the reference temperature is H0, the standard reading voltage is V0, the standard reading time is T0, the preset temperatures include H1 to Hn, the preset reading voltages include V1 to Vm, and the preset reading times include T1 to Tg, then for any temperature (i.e., one of H0 and H1 to Hn), the standard reading time T0 can be used as a fixed quantity, and different preset reading voltages V1 to Vm can be used as single variables (i.e., only the reading voltage is offset) to set multiple reading conditions. Alternatively, the standard reading voltage V0 can be used as a fixed quantity, and different preset reading times T1 to Tg can be used as single variables (i.e., only the reading time is offset) to set multiple reading conditions. Reading operations are performed using different reading conditions, and the corresponding data reading results (number of read failures) are obtained. Based on the data reading results of the same reading conditions at different temperatures, the influence of temperature on the reading operation is analyzed, and then the target offset function related to temperature, reading time, and reading voltage is determined.

[0135] In some embodiments, the second processing unit 601 is configured to:

[0136] Determine the temperature difference between each preset temperature and the reference temperature, the time difference between each preset reading time and the standard reading time, and the voltage difference between each preset reading voltage and the standard reading voltage;

[0137] Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters.

[0138] The target offset function is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failures, the second number of read failures, the third number of read failures, and the fourth number of read failures.

[0139] The reference mapping relationship can be seen as a lookup table between the read time offset parameter and the read voltage offset parameter of the memory when it is not affected by temperature. The read time offset parameter is the offset relative to the standard read time, and the read voltage offset parameter is the offset relative to the standard read voltage.

[0140] Specifically, the temperature difference Δh1 to Δhn between each of the preset temperatures H1 to Hn and the reference temperature H0 can be calculated; the time difference Δt1 to Δtg between each of the preset read times T1 to Tg and the standard read time T0 can be calculated; and the voltage difference Δv1 to Δvm between each of the preset read voltages V1 to Vm and the standard read voltage V0 can be calculated. Based on these differences and the number of read failures, a lookup table (reference mapping relationship) between multiple offset voltages and offset times can be determined when the memory is not affected by temperature. Based on the reference mapping relationship, the mapping formula (target offset function) between the offset voltage and offset time of the memory at any temperature can be further determined.

[0141] In some embodiments, the second processing unit 601 is configured to:

[0142] Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters.

[0143] The reference relationship offset value is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits;

[0144] The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

[0145] For example, for the time difference Δt1 to Δtg, since Δt1 = T1 - T0, the first read failure number corresponding to Δt1 is the two first read failure numbers corresponding to T1 and T0; for the voltage difference Δv3 to Δvm, since Δv3 = v3 - V0, the third read failure number corresponding to Δv3 is the two third read failure numbers corresponding to v3 and V0. Thus, each voltage difference Δv corresponds to one bit difference (third bit difference), and each time difference Δt corresponds to one bit difference (first bit difference).

[0146] Once all the first and third bit differences are calculated, an approximate linear compensation method can be used to determine the mapping relationship between offset time and offset voltage, that is, to obtain a reference mapping table (baseline mapping relationship) between multiple offset times and offset voltages when the memory is not affected by temperature.

[0147] In some embodiments, the second processing unit 601 is configured to:

[0148] The bit difference between the two second read failure bits corresponding to each time difference value is determined as the second bit difference value, and the bit difference between the two fourth read failure bits corresponding to each voltage difference value is determined as the fourth bit difference value;

[0149] Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference value, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference value;

[0150] The reference relationship offset value is determined based on the reference mapping relationship, the first difference, the second difference, and the temperature difference.

[0151] The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

[0152] The reference relationship offset value is equivalent to an offset of the mapping relationship between offset time and offset voltage after incorporating temperature factors. It is equivalent to obtaining the slope 'a' in the linear equation y = ax, where x is the offset time and y is the offset voltage.

[0153] For example, for the time difference Δt1 to Δtg, since Δt1 = T1 - T0, the second read failure number corresponding to Δt1 is the two second read failure numbers corresponding to T1 and T0; for the voltage difference Δv3 to Δvm, since Δv3 = v3 - V0, the fourth read failure number corresponding to Δv3 is the two fourth read failure numbers corresponding to v3 and V0. Thus, each voltage difference Δv corresponds to one bit difference (fourth bit difference), and each time difference Δt corresponds to one bit difference (second bit difference).

[0154] Since the first and third read failure numbers are data read results measured at a reference temperature using only the offset read time or only the offset read voltage, and the second and fourth read failure numbers are data read results measured at a preset temperature different from the reference temperature using only the offset read time or only the offset read voltage, for the same read condition (e.g., only the offset time or only the offset voltage), the error between the bit difference corresponding to the preset temperature and the reference temperature can be calculated. That is, the error (first difference and second difference) caused by the temperature effect on the memory when reading data can be calculated. Based on these errors, an approximately linear compensation method is used to adjust the voltage difference Δv and the time difference Δt, so that the time difference Δt (offset time) and the voltage difference Δv (offset voltage) roughly conform to the input value x and output value y of a linear equation y = ax, and the slope a of the linear equation can be used as the reference relationship offset value.

[0155] In some embodiments, the second processing unit 601 is configured to:

[0156] Obtain the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures;

[0157] The initial offset function is determined based on the aforementioned baseline relationship offset value;

[0158] The target offset function is determined based on the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

[0159] Specifically, the second temperature compensation time and second temperature compensation voltage corresponding to each temperature can be determined using the temperature compensation formula stored in memory. Specifically, an initial offset function can be directly constructed based on the baseline offset value. For example, the initial offset function could be y + c = a(x + b), where c is the temperature compensation voltage variable, b is the temperature compensation time variable, and a is the baseline offset value. Then, the actual values ​​of each calculated variable are substituted into the initial offset function for testing and verification. The initial offset function is then manually fine-tuned so that each actual value roughly satisfies the fine-tuned initial offset function, for example, obtaining m(x + b) + n(y + c) = p, where m, n, and p are obtained through fine-tuning. The fine-tuned initial offset function is the target offset function.

[0160] As can be seen from the above, the voltage calibration method and apparatus, memory and memory system provided in this application, during the reading voltage calibration process of the memory cell array, detect the number of read failures at multiple candidate times using a standard reading voltage and detect the ambient temperature. Then, the reading voltage is calibrated by combining the ambient temperature, the number of read failures, and the stored target offset function. This eliminates the influence of ambient temperature and changes in the memory itself on the offset of the reading voltage, improves the accuracy of reading voltage calibration, and reduces the failure rate of reading operations.

[0161] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A voltage calibration method, comprising: Detect the target temperature of the storage cell array; Using a standard read voltage, read operations are performed on the memory cell array at multiple candidate times, and the corresponding target read failure bit number is obtained, with each candidate time corresponding to one target read failure bit number; The target read voltage offset parameter is determined based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function; The read voltage of the memory cell array during read operations is calibrated using the target read voltage offset parameter; The step of determining the target read voltage offset parameter based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function includes: Determine the first temperature compensation time and the first temperature compensation voltage corresponding to the target temperature; The target read time offset parameter is determined based on the target number of read failures, the candidate time, and the standard read time; The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into the stored target offset function to obtain the target read voltage offset parameter.

2. The voltage calibration method according to claim 1, wherein, The step of determining the target read time offset parameter based on the target number of read failures, the candidate time, and the standard read time includes: The candidate time corresponding to the smallest number of target read failure bits is determined as the target candidate time; The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

3. The voltage calibration method according to claim 1, wherein, Before determining the target read voltage offset parameter based on the target temperature, the number of target read failure bits, the candidate time, and the stored target offset function, the method further includes: The storage cell array is placed at a reference temperature and a preset temperature, respectively, and a read operation is performed on the storage cell array with a standard read voltage and any preset read time from a plurality of preset read times, and the corresponding first read failure number and second read failure number are obtained. The storage cell array is placed at the reference temperature and the preset temperature respectively, and a read operation is performed on the storage cell array with any preset read voltage and standard read time from a plurality of preset read voltages, and the corresponding third read failure number and fourth read failure number are obtained; The target offset function is determined based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time. Store the target offset function.

4. The voltage calibration method according to claim 3, wherein, The step of determining the target offset function based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time includes: Determine the temperature difference between each preset temperature and the reference temperature, the time difference between each preset reading time and the standard reading time, and the voltage difference between each preset reading voltage and the standard reading voltage; Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters. The target offset function is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failures, the second number of read failures, the third number of read failures, and the fourth number of read failures.

5. The voltage calibration method according to claim 4, wherein, The step of determining the reference mapping relationship of the memory cell array in the read operation at the reference temperature based on the time difference, the voltage difference, the first read failure number of bits, and the third read failure number of bits includes: Determine the bit difference between the two first read failure bits corresponding to each time difference value, and use it as the first bit difference value; The bit difference between the two third read failure bits corresponding to each voltage difference is determined as the third bit difference; The reference mapping relationship is determined based on the time difference, the first bit difference, the voltage difference, and the third bit difference.

6. The voltage calibration method according to claim 5, wherein, The step of determining the target offset function based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first read failure number of bits, the second read failure number of bits, the third read failure number of bits, and the fourth read failure number of bits includes: The bit difference between the two second read failure bits corresponding to each time difference value is determined as the second bit difference value, and the bit difference between the two fourth read failure bits corresponding to each voltage difference value is determined as the fourth bit difference value; Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference value, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference value; The reference relationship offset value is determined based on the reference mapping relationship, the first difference, the second difference, and the temperature difference. The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

7. The voltage calibration method according to claim 6, wherein, Determining the target offset function based on the baseline offset value and the baseline mapping relationship includes: Obtain the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures; The initial offset function is determined based on the aforementioned baseline relationship offset value; The target offset function is determined based on the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

8. A voltage calibration device, comprising: A temperature sensor is configured to detect the target temperature currently present in the memory cell array; A first processing unit is electrically connected to the storage cell array and the temperature sensor, and is configured to perform read operations on the storage cell array at multiple candidate times with a standard read voltage, and obtain the corresponding target read failure number of bits, with each candidate time corresponding to one target read failure number of bits. The target read voltage offset parameter is determined based on the target temperature, the target number of read failures, the candidate time, and the stored target offset function; the read voltage of the memory cell array during read operations is calibrated using the target read voltage offset parameter. The first processing unit is configured as follows: Determine the first temperature compensation time and the first temperature compensation voltage corresponding to the target temperature; The target read time offset parameter is determined based on the target number of read failures, the candidate time, and the standard read time; The target read time offset parameter, the first temperature compensation time, and the first temperature compensation voltage are input into the stored target offset function to obtain the target read voltage offset parameter.

9. The voltage calibration device according to claim 8, wherein, The first processing unit is configured as follows: The candidate time corresponding to the smallest number of target read failure bits is determined as the target candidate time; The difference between the target candidate time and the standard read time is determined to obtain the target read time offset parameter.

10. A voltage calibration device, wherein, The voltage calibration device includes a second processing unit electrically connected to a memory, the memory including a memory cell array, and the second processing unit is configured to: The memory cell array is placed at a reference temperature and a preset temperature, respectively. A read operation is performed on the memory cell array using a standard read voltage and any preset read time from a plurality of preset read times, and the corresponding first read failure number and second read failure number are obtained. The storage cell array is placed at the reference temperature and the preset temperature respectively, and a read operation is performed on the storage cell array with any preset read voltage and standard read time from a plurality of preset read voltages, and the corresponding third read failure number and fourth read failure number are obtained; The target offset function is determined based on the first number of read failures, the second number of read failures, the third number of read failures, the fourth number of read failures, the reference temperature, the preset temperature, the standard read voltage, the preset read voltage, the standard read time, and the preset read time. The target offset function is stored in the memory.

11. The voltage calibration device according to claim 10, wherein, The second processing unit is configured as follows: Determine the temperature difference between each preset temperature and the reference temperature, the time difference between each preset reading time and the standard reading time, and the voltage difference between each preset reading voltage and the standard reading voltage; Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters. The target offset function is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failures, the second number of read failures, the third number of read failures, and the fourth number of read failures.

12. The voltage calibration device according to claim 11, wherein, The second processing unit is configured as follows: Based on the time difference, the voltage difference, the first number of read failures, and the third number of read failures, a reference mapping relationship is determined for the memory cell array in the read operation at the reference temperature. The reference mapping relationship is a one-to-one correspondence between multiple read time offset parameters and multiple read voltage offset parameters. The reference relationship offset value is determined based on the reference mapping relationship, the time difference, the voltage difference, the temperature difference, the first number of read failure bits, the second number of read failure bits, the third number of read failure bits, and the fourth number of read failure bits; The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

13. The voltage calibration device according to claim 12, wherein, The second processing unit is configured as follows: The bit difference between the two first read failure bits corresponding to each time difference is determined as the first bit difference, and the bit difference between the two third read failure bits corresponding to each voltage difference is determined as the third bit difference. The bit difference between the two second read failure bits corresponding to each time difference value is determined as the second bit difference value, and the bit difference between the two fourth read failure bits corresponding to each voltage difference value is determined as the fourth bit difference value; Determine a first difference between the first digit difference and the second digit difference corresponding to each temperature difference value, and determine a second difference between the third digit difference and the fourth digit difference corresponding to each temperature difference value; The reference relationship offset value is determined based on the reference mapping relationship, the first difference, the second difference, and the temperature difference. The target offset function is determined based on the baseline offset value and the baseline mapping relationship.

14. The voltage calibration device according to claim 13, wherein, The second processing unit is configured as follows: Obtain the second temperature compensation time and the second temperature compensation voltage corresponding to each of the preset temperatures; The initial offset function is determined based on the aforementioned baseline relationship offset value; The target offset function is determined based on the initial offset function, the second temperature compensation time, the second temperature compensation voltage, and the reference mapping relationship.

15. A memory comprising a memory cell array and a peripheral circuit structure coupled to the memory cell array, the peripheral circuit structure comprising a voltage calibration device as claimed in any one of claims 8-10.

16. A memory system comprising at least one memory as claimed in claim 15, and a controller coupled to the memory, the controller being configured to control the memory to store data.

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