Semiconductor device, semiconductor module, and manufacturing method

Abstract

A semiconductor device includes a first main electrode plate, a second main electrode plate, and a control electrode plate provided on one surface of the semiconductor device. And a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, a semiconductor module and a manufacturing method. Background Art

[0002] Patent Document 1 states that “a semiconductor module 100 including a semiconductor assembly 110 including a plurality of semiconductor chips 30 can be configured as a power device such as an inverter or an IPM (Intelligent Power Module) including a control circuit as a whole” (Paragraph 0031), “as an example, the PCB 40 is electrically connected to the semiconductor chip 30 using a bonding wire 55” (Paragraph 0032), “nickel plating may be applied to the external connection portion 50. By connecting a copper bus bar to the external connection portion 50, a large current can be applied to each main terminal 52 of the semiconductor assembly 110” (Paragraph 0033), and “the semiconductor assembly 110 may include a metal wiring plate 70 for electrically connecting the semiconductor chip 30 and the main terminal 52. The semiconductor chip 30 and the main terminal 52 may be electrically connected using a conductive member such as a wire and / or a ribbon instead of the metal wiring plate 70” (Paragraph 0035).

[0003] Patent Document 2 states that "Two semiconductor elements 3 are electrically connected by wiring component W1. One semiconductor element 3 is electrically connected to the second circuit layer 24 via wiring component W2. The second circuit layer 24 is electrically connected to the external terminal 27 described later via wiring component W3. The other semiconductor element 3 is electrically connected to the third circuit layer 25 via wiring component W4. The third circuit layer 25 is electrically connected to the other external terminal 27 via wiring component W5" (Paragraph 0023), "It should be noted that each of the above-mentioned wiring components uses a conductor wire. The material of the conductive wire can be gold, Any one of copper, aluminum, gold alloy, copper alloy, aluminum alloy, or a combination of these. In addition, components other than conductive wires can also be used as wiring components. For example, a tape can be used as a wiring component" (Paragraph 0024), "The insulating circuit substrate 2 and the semiconductor element 3 are covered by a shell 11 which is a frame portion surrounding the surroundings. The shell 11 is composed of an annular wall portion 12 surrounding the outer peripheral side of the insulating circuit substrate 2 and a cover portion 13 covering the upper part of the insulating circuit substrate 2 and the semiconductor element 3. For example, the shell 11 is formed of a synthetic resin" (Paragraph 0025).

[0004] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2021-2610 Patent Document 2: International Publication No. 2020 / 121680 Summary of the invention

[0005] Technical issues Miniaturize semiconductor modules and reduce the physical distance between control circuits and semiconductor devices.

[0006] Open to the public In a first embodiment of the present invention, a semiconductor device is provided, comprising: a switching element having a first main electrode and a control electrode on one surface and a second main electrode on an opposite surface; and a mounting substrate having a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode on the mounting surface of the switching element, and a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode in an area of ​​the mounting surface of the switching element where no switching element is configured.

[0007] The semiconductor device may include a sealing portion that covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

[0008] In any of the above-mentioned semiconductor devices, on the mounting surface of the switching element in the mounting substrate, the switching element may be arranged between the first main electrode plate and the control electrode plate.

[0009] In any of the above semiconductor devices, the first main electrode wiring may have a plurality of bumps in contact with the first main electrode, and the control wiring may have a plurality of bumps in contact with the control electrode.

[0010] In any of the semiconductor devices described above, the mounting substrate may include an insulating substrate, and a first main electrode wiring, a first main electrode plate, a control wiring, and a control electrode plate formed on the insulating substrate.

[0011] In any of the above-mentioned semiconductor devices, the mounting substrate may include a heat conduction plate formed on a surface of the insulating substrate opposite to the mounting surface.

[0012] In any of the above semiconductor devices, the mounting substrate may further include a sub wiring connected to the first main electrode on the mounting surface of the switching element, and may include a sub electrode plate connected to the sub wiring in a region of the mounting surface of the switching element where no switching element is arranged.

[0013] In any of the above semiconductor devices, the switching element may be a power MOSFET or an IGBT.

[0014] In any of the above semiconductor devices, the switching element may be a SiC semiconductor element.

[0015] In a second embodiment of the present invention, a semiconductor module is provided, comprising: at least one semiconductor device; a main substrate having a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate connected to the back side of the at least one semiconductor device; and a heat sink in contact with the surface of the at least one semiconductor device on the opposite side of the main substrate.

[0016] In the above-mentioned semiconductor module, the main substrate may have a terminal on the front side connected to the first main electrode plate of at least one semiconductor device via wiring in the main substrate, and a terminal connected to the second main electrode or the second main electrode plate via wiring in the main substrate.

[0017] Any of the above-mentioned semiconductor modules may include at least one control device mounted on the front surface of the main substrate and controlling at least one semiconductor device.

[0018] Any of the semiconductor modules described above is a converter device, and the at least one semiconductor device may include a plurality of semiconductor devices respectively allocated to upper arms and lower arms of each of the one or more phases.

[0019] In any of the above-mentioned semiconductor modules, each semiconductor device among the multiple semiconductor devices allocated to the upper arm of each phase can be arranged in a row on the back side of the main substrate, and each semiconductor device among the multiple semiconductor devices allocated to the lower arm of each phase can be arranged in a row side by side with the row of each semiconductor device allocated to the upper arm of each phase on the back side of the main substrate.

[0020] On the back side of the main substrate in any of the above-mentioned semiconductor modules, each semiconductor device allocated to the upper arm of each phase can be arranged with the first main electrode plate located on the side of the semiconductor device allocated to the opposite lower arm among the multiple semiconductor devices. On the back side of the main substrate, each semiconductor device allocated to the lower arm of each phase can be arranged with the first main electrode plate located on the side of the semiconductor device allocated to the opposite upper arm among the multiple semiconductor devices.

[0021] In a third aspect of the present invention, a manufacturing method is provided, comprising: a step of preparing a switching element having a first main electrode and a control electrode on one surface and a second main electrode on an opposite surface; a step of making a mounting substrate having a first main electrode wiring and a control wiring on the mounting surface on which the switching element is to be mounted; a step of mounting the switching element on the mounting surface of the mounting substrate on which the switching element is to be mounted by joining the first main electrode to the first main electrode wiring and joining the control electrode to the control wiring; and a step of joining the first main electrode plate connected to the first main electrode wiring and the control electrode plate connected to the control electrode to an area on which no switching element is configured on the mounting surface of the mounting substrate on which the switching element is to be mounted.

[0022] The above-mentioned manufacturing method may also include a step of sealing based on a sealing material in a manner that covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side, and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

[0023] Any of the above-mentioned manufacturing methods may include the steps of preparing a main substrate having a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate connected to at least one semiconductor device on the back side; the step of connecting at least one semiconductor device on the back side of the main substrate; and the step of installing a heat sink on the surface of at least one semiconductor device on the opposite side of the main substrate.

[0024] Any of the above-mentioned manufacturing methods may include the step of mounting at least one control device for controlling at least one semiconductor device on the front surface of the main substrate.

[0025] In a fourth aspect of the present invention, a semiconductor module is provided, comprising: at least one semiconductor device, which has a first main electrode plate, a second main electrode plate and a control electrode plate arranged on one surface, and has a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate; a main substrate, which has the first main electrode plate, the second main electrode plate and the control electrode plate of the at least one semiconductor device connected on the back side; and a heat sink arranged on the back side of the main substrate to which the at least one semiconductor device is connected.

[0026] In the above-mentioned semiconductor module, the main substrate may have at least one main substrate recess on the back side, and the at least one main substrate recess is for burying at least a portion of the at least one semiconductor device. The first main electrode plate, the second main electrode plate and the control electrode plate of the at least one semiconductor device may be connected to the main substrate at the bottom surface of the at least one main substrate recess.

[0027] Any of the above-mentioned semiconductor modules may include a thermally conductive material in at least a portion of a gap between the main substrate and the heat sink.

[0028] In any of the above-mentioned semiconductor modules, the heat sink may have at least one heat sink protrusion on a surface on the at least one semiconductor device side at a position corresponding to the at least one semiconductor device.

[0029] In any of the above semiconductor modules, the heat sink may have at least one heat sink recess on a surface on the at least one semiconductor device side, and at least a portion of the at least one semiconductor device may be buried in the at least one heat sink recess.

[0030] In any of the above-mentioned semiconductor modules, the heat sink may have: a plate-like component having a surface close to the main substrate and the at least one semiconductor device side; and at least one protrusion component, which is arranged on the surface of the plate-like component opposite to the main substrate and the at least one semiconductor device side. The main substrate can be fixed to the heat sink by using at least one fixing component with thermal conductivity that penetrates the plate-like component of the heat sink from the front side of the main substrate and reaches the at least one protrusion component.

[0031] In any of the above semiconductor modules, the at least one fixing member may be a screw, and the at least one protruding member may have a screw hole for fitting the screw.

[0032] In any of the above-mentioned semiconductor modules, the at least one semiconductor device may include at least one first semiconductor device and at least one second semiconductor device, and the main electrode plates on the negative side of the first main electrode plates and the second main electrode plates of each of the at least one first semiconductor device can be electrically connected to the main terminal plates on the positive side of the first main electrode plates and the second main electrode plates of the corresponding second semiconductor device in the at least one second semiconductor device.

[0033] In any of the above-mentioned semiconductor modules, the at least one semiconductor device may have a structure in which the second main electrode plate is arranged between the first main electrode plate and the control electrode plate on one surface.

[0034] In any of the above semiconductor modules, on the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device may be arranged in an orientation such that the first main electrode plates face each other.

[0035] In any of the above semiconductor modules, on the back side of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device may be arranged in a direction such that the first main electrode plate and the control electrode plate are opposed to each other.

[0036] In any of the above-mentioned semiconductor modules, the main substrate may have: a positive terminal, which is connected to the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via positive wiring within the main substrate; a negative terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via negative wiring within the main substrate; and an output terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via output wiring within the main substrate, and the positive wiring, the negative wiring, and the output wiring can be arranged in the main wiring area of ​​the main substrate corresponding to the area from the at least one first semiconductor device to the at least one second semiconductor device when viewed from above.

[0037] Any of the above-mentioned semiconductor modules may include: the first and second at least one first semiconductor devices, which are arranged in a row on the back side of the main substrate; the first and second at least one second semiconductor devices, which are arranged in a row side by side with the first and second at least one first semiconductor devices on the back side of the main substrate; the first output terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the first at least first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the first at least second semiconductor device via the first output wiring in the main substrate; and the second output terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the second at least first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the second at least second semiconductor device via the second output wiring in the main substrate, and the positive wiring, the negative wiring, the first output wiring and the second output wiring can be arranged in the main wiring area of ​​the main substrate corresponding to the column from the first and second at least one first semiconductor device to the column of the first and second at least one second semiconductor device when viewed from above.

[0038] Any of the above-mentioned semiconductor modules may have: at least one first control device, which is mounted on the front side of the main substrate and electrically connected to at least one of the control electrode plates in the at least one first semiconductor device; and at least one second control device, which is mounted on the front side of the main substrate and electrically connected to at least one of the control electrode plates in the at least one second semiconductor device. The at least one first control device can be configured in a first control wiring area that is close to the at least one first semiconductor device side relative to the main wiring area when viewed from above, and the at least one second control device can be configured in a second control wiring area that is close to the at least one second semiconductor device side relative to the main wiring area when viewed from above.

[0039] Any of the above-mentioned semiconductor modules may have: a first control connector, which is arranged in the first control wiring area on the front side of the main substrate and is electrically connected to the at least one first control device; and a second control connector, which is arranged in the second control wiring area on the front side of the main substrate and is electrically connected to the at least one second control device.

[0040] Any of the above-mentioned semiconductor modules may include at least one buffer capacitor disposed in the main wiring region on the front surface of the main substrate.

[0041] In any of the above-mentioned semiconductor modules, on the back side of the main substrate, each of the at least one first semiconductor device and the corresponding second semiconductor device in the at least one second semiconductor device can be configured to be arranged along a direction orthogonal to the arrangement of the first main electrode plate, the second main electrode plate and the control electrode plate.

[0042] In any of the above-mentioned semiconductor modules, the main substrate may have: a positive terminal, which is connected to the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via the positive wiring within the main substrate; a negative terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via the negative wiring within the main substrate; and an output terminal, which is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least second semiconductor device via the output wiring within the main substrate, and the positive wiring, the negative wiring and the output wiring may extend along the direction in which each of the at least one first semiconductor device is arranged with the corresponding second semiconductor device of the at least one second semiconductor device.

[0043] In the fifth aspect of the present invention, a manufacturing method is provided, comprising: a step of preparing at least one semiconductor device, wherein the at least one semiconductor device is provided with a first main electrode plate, a second main electrode plate and a control electrode plate on one surface, and has a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate; a step of preparing a main substrate to which the first main electrode plate, the second main electrode plate and the control electrode plate of the at least one semiconductor device are connected on the back side; a step of connecting the at least one semiconductor device on the back side of the main substrate; and a step of installing a heat sink on the back side of the main substrate to which the at least one semiconductor device is connected.

[0044] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a perspective view of the switching element 10 according to the present embodiment.

[0046] Figure 2 It is a perspective view of a semiconductor device 200 according to the present embodiment.

[0047] Figure 3 A method for manufacturing the semiconductor device 200 according to this embodiment is described.

[0048] Figure 4 It is a perspective view of a structure in which the second main electrode plate 230 and the switching element 10 of the present embodiment are joined.

[0049] Figure 5 It is a perspective view of the mounting substrate 210 according to the present embodiment.

[0050] Figure 6 It is a perspective view of a structure in which the switching element 10 to which the second main electrode plate 230 is bonded is bonded to the mounting substrate 210 of the present embodiment.

[0051] Figure 7 It is a perspective view of a structure in which the first main electrode plate 220 , the control electrode plate 240 , and the sub-electrode plate 250 are bonded to the mounting substrate 210 of the present embodiment.

[0052] Figure 8 It is a perspective view of a semiconductor module 800 according to the present embodiment.

[0053] Fig. 9 Schematic diagram showing the internal structure of the semiconductor module 800 according to the present embodiment.

[0054] Fig.10The connection of each wiring in the semiconductor module 800 of this embodiment is shown.

[0055] Fig.11 A method for manufacturing the semiconductor module 800 according to the present embodiment will be described.

[0056] Fig.12 It is a schematic diagram of a method for manufacturing the semiconductor module 800 according to the present embodiment.

[0057] Fig.13 It is a schematic diagram of a cross section of a semiconductor module 800 according to the present embodiment.

[0058] Fig.14 Yes Fig.13 Schematic diagram obtained by enlarging area S.

[0059] Fig.15 It is a perspective view of a semiconductor device 1500 according to a first modification example of the present embodiment.

[0060] Fig.16 It is a perspective view of a semiconductor module 1600 according to a second modification of the present embodiment.

[0061] Fig.17 This is a diagram of a semiconductor device 1500 according to a second modification of the present embodiment as viewed from the heat sink 1630 side.

[0062] Fig.18 The connection of each wiring in a semiconductor module 1800 according to a third modified example of the present embodiment is shown.

[0063] Fig.19 The connection of each wiring in a semiconductor module 1900 according to a fourth modified example of the present embodiment is shown.

[0064] Fig. 20 A semiconductor module 2000 according to a fifth modified example of the present embodiment is shown.

[0065] Fig.21 A semiconductor module 2100 according to a sixth modification of the present embodiment is shown.

[0066] Fig. 22 A semiconductor module 2200 according to a seventh modification of the present embodiment is shown.

[0067] Fig.23 It is a schematic diagram of a cross section of a semiconductor module 2300 according to an eighth modification of the present embodiment.

[0068] Fig.24 It is a schematic diagram of a cross section of a semiconductor module 2400 according to a ninth modification of the present embodiment.

[0069] Fig.25It is a schematic diagram of a cross section of a semiconductor module 2500 according to a tenth modification of the present embodiment.

[0070] Fig.26 FIG. 2 is a schematic diagram of a cross section of a semiconductor module 2600 according to an eleventh modification of the present embodiment.

[0071] Fig. 27 FIG. 2 is a schematic diagram of a cross section of a semiconductor module 2500 according to a twelfth modification of the present embodiment.

[0072] Explanation of symbols 10 Switching element, 100 First main electrode, 110 Control electrode, 120 Second main electrode, 130 Sensing electrode, 200 Semiconductor device, 210 Mounting substrate, 220 First main electrode plate, 230 Second main electrode plate, 240 Control electrode plate, 250 Sub-electrode plate, 260 Sealing portion, 500 Insulating substrate, 510 First main electrode wiring, 513 First main electrode contact, 515 Wiring, 517 First main electrode plate contact, 520 Control wiring, 523 Control electrode contact, 525 Wiring, 527 Control electrode plate contact, 530 Sub-wiring, 535 Wiring, 537 Sub-electrode plate contact, 800 Semiconductor module, 810 Main substrate, 812 P wiring, 813 N wiring, 814 U wiring, 815 V wiring, 816 W wiring, 820 Control device, 830 Heat sink, 1270 heat conducting plate, 1280 first main electrode plate contact, 1285 second main electrode plate contact, 1290 control electrode plate contact, 1500 semiconductor device, 1510 mounting substrate, 1520 first main electrode plate, 1530 second main electrode plate, 1540 control electrode plate, 1550 sub-electrode plate, 1560 sealing portion, 1600 semiconductor module, 1610 main substrate, 1620 control device, 1630 heat sink, 1640 buffer capacitor, 1650 control connector, 1660 fixing member, 1670 protruding member, 1710 protruding member, 1800 semiconductor module, 1812 P wiring, 1813 N wiring, 1814 U wiring, 1815 V wiring, 1816 W wiring, 1900 semiconductor module, 1912 P wiring, 1913 N wiring, 1914 U wiring, 1915 V wiring, 1916 W wiring, 2000 semiconductor module, 2010 main substrate, 2020 control device, 2050 control connector, 2100 semiconductor module, 2110 main substrate, 2120 control device, 2150 control connector, 2180 film capacitor, 2200 semiconductor module, 2300 semiconductor module, 2315 main substrate recess, 2390 thermal conductive material, 2400 semiconductor module, 2410 heat sink recess, 2500 semiconductor module, 2600 semiconductor module, 2620 heat sink protrusion, 2700 semiconductor module. DETAILED DESCRIPTION

[0073] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily all essential to the technical means of the invention.

[0074] Figure 1 It is a three-dimensional diagram of the switch element 10 of the present embodiment. The switch element 10 is a semiconductor switch element such as a MOSFET (metal oxide semiconductor field effect transistor). The switch element 10 can be a power MOSFET of a vertical structure. The switch element 10 can be a Si semiconductor element such as a Si-MOSFET, or a SiC semiconductor element such as a SiC-MOSFET that can switch at a higher speed, or a wide bandgap semiconductor such as GaN, diamond, gallium nitride-based materials, gallium oxide-based materials, AlN, AlGaN or ZnO can be used. Alternatively, the switch element 10 can be a semiconductor switch element such as an IGBT (insulated gate bipolar transistor), or a SiC-IGBT. In addition, the switch element 10 can be a HEMT (high electron mobility transistor).

[0075] The switching element 10 may be a semiconductor chip, and has a first main electrode 100 and a control electrode 110 on one surface (the upper surface in the figure), and has a second main electrode 120 on the opposite surface. In the example of this figure, the switching element 10 also has a sensing electrode 130 on the upper surface in the figure. When the switching element 10 is a MOSFET, the switching element 10 has a source and a drain as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sensing source as the sensing electrode 130. When the switching element 10 is an IGBT, the switching element 10 has an emitter and a collector as the first main electrode 100 and the second main electrode 120, a gate as the control electrode 110, and a sensing emitter as the sensing electrode 130. In this embodiment, for the sake of convenience of description, the case where the switching element 10 is a MOSFET is shown.

[0076] Figure 2 2 is a perspective view of a semiconductor device 200 according to this embodiment. Figure 1 A semiconductor module of a switching element such as the switching element 10 shown in the figure generally adopts a structure in which one surface of the switching element (e.g., the surface on the second main electrode 120 side) is bonded to a wiring pattern on a substrate, and each electrode on the other surface (e.g., the first main electrode 100, the control electrode 110, and the sensing electrode 130) is electrically connected to other wiring patterns by wire bonding. Such a semiconductor module is realized as an integrated module by resin-sealing the substrate on which the switching element is mounted, each bonding wire, and each metal plate connected to the positive terminal, the negative terminal, and the output terminal.

[0077] In contrast, the semiconductor device 200 has a structure in which each electrode plate electrically connected to each electrode of the switching element 10 is exposed on one surface of the plate-shaped semiconductor device 200. In the present embodiment, the semiconductor device 200 includes a mounting substrate 210, a first main electrode plate 220, a second main electrode plate 230, a control electrode plate 240, a sub-electrode plate 250, and a sealing portion 260.

[0078] The mounting substrate 210 mounts the switching element 10 on the mounting surface (the upper surface in the figure). The first main electrode plate 220 is electrically connected to the first main electrode 100 of the switching element 10. The second main electrode plate 230 is electrically connected to the second main electrode 120 of the switching element 10. The control electrode plate 240 is electrically connected to the control electrode 110 of the switching element 10. The sub-electrode plate 250 is electrically connected to the first main electrode 100 of the switching element 10. Here, the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 are exposed on the surface of the semiconductor device 200 opposite to the mounting substrate 210 side (the mounting surface side of the mounting substrate 210 on which the switching element 10 is mounted). The sealing portion 260 exposes the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250, and covers the mounting surface of the switching element 10 on the mounting substrate 210.

[0079] By using the semiconductor device 200 of this embodiment to join each electrode plate on one surface of the semiconductor device 200 to the wiring pattern on the substrate instead of modularizing the switching element such as the switching element 10 as described above, all the required electrodes in the switching element 10 can be electrically connected to the wiring on the substrate without wire bonding.

[0080] It should be noted that the semiconductor device 200 may also have an electrode plate electrically connected to the sensing electrode 130 on the same surface as the first main electrode plate 220. In addition, both the first main electrode plate 220 and the sub-electrode plate 250 are electrically connected to the first main electrode 100 of the switching element 10, but the first main electrode plate 220 has a large area and is used to flow a large current, and the sub-electrode plate 250 and the control electrode plate 240 are used in pairs to control the switching element 10. In other embodiments, the semiconductor device 200 may not have the sub-electrode plate 250, in which case the first main electrode plate 220 is also used to control the switching element 10.

[0081] Figure 3 The method for manufacturing the semiconductor device 200 of this embodiment is shown. Figures 4 to 7 The method for manufacturing the semiconductor device 200 will be described. In S300 (step 300 ), a switching element 10 having a first main electrode 100 and a control electrode 110 on one surface and a second main electrode 120 on the opposite surface is prepared.

[0082] In S310 , the second main electrode plate 230 is joined to the surface of the switching element 10 on the second main electrode 120 side. Figure 4 It is a three-dimensional diagram of a structure in which the second main electrode plate 230 is joined to the switch element 10 of the present embodiment. The second main electrode plate 230 is a conductive plate such as a copper plate. The second main electrode plate 230 can be joined to the second main electrode 120 using a sintering agent of nanosilver, or the second main electrode plate 230 can be joined to the second main electrode 120 by direct gold-gold bonding. Thus, the second main electrode plate 230 is electrically connected to the second main electrode 120 of the switch element 10. In addition to the above, the second main electrode plate 230 can also be joined by a solder material, or by direct copper-copper bonding. In addition, a plurality of bumps regularly or irregularly arranged on the second main electrode plate 230 can also be joined to the second electrode of the switch element 10.

[0083] In S320 , the mounting substrate 210 is produced. Figure 5 2 is a perspective view of the mounting substrate 210 of this embodiment. In this process, the mounting substrate 210 having the wiring pattern of the first main electrode wiring 510, the control wiring 520 and the sub wiring 530 is manufactured on the mounting surface of the insulating substrate 500 of Si, silicon nitride or aluminum nitride, etc., on which the switching element 10 is to be mounted. The insulating substrate 500 can also be manufactured using ceramic materials including the above.

[0084] The first main electrode wiring 510 is formed of a conductive metal film or metal plate such as copper. The first main electrode wiring 510 includes a first main electrode contact 513, a wiring 515, and a first main electrode plate contact 517. The first main electrode contact 513 is a portion connected to the first main electrode 100 of the switching element 10. The wiring 515 electrically connects the first main electrode contact 513 and the first main electrode plate contact 517. The first main electrode plate contact 517 is a portion connected to the first main electrode plate 220.

[0085] Similar to the first main electrode wiring 510, the control wiring 520 is formed of a conductive metal film or metal plate such as copper. The control wiring 520 includes a control electrode contact 523, a wiring 525, and a control electrode plate contact 527. The control electrode contact 523 is a portion connected to the control electrode 110 of the switching element 10. The wiring 525 electrically connects the control electrode contact 523 and the control electrode plate contact 527. The control electrode plate contact 527 is a portion connected to the control electrode plate 240.

[0086] Similar to the first main electrode wiring 510, the sub wiring 530 is formed of a conductive metal film or metal plate such as copper. The sub wiring 530 includes a first main electrode contact 513, a wiring 535, and a sub electrode plate contact 537. The first main electrode contact 513 is shared with the first main electrode wiring 510. The sub wiring 530 can use a portion of the first main electrode contact 513 used by the first main electrode wiring 510. The wiring 535 electrically connects the first main electrode contact 513 and the sub electrode plate contact 537. The wiring width of the wiring 535 can also be smaller than the wiring width of the wiring 515. The sub electrode plate contact 537 is a portion connected to the sub electrode plate 250.

[0087] Here, the first main electrode contact 513 and the first main electrode plate contact 517 of the first main electrode wiring 510, the control electrode contact 523 and the control electrode plate contact 527 of the control wiring 520, and the sub-electrode plate contact 537 of the sub-wiring 530, etc., and the regions where the electrodes of the switching element 10 or the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240, and the sub-electrode plate 250 are joined may have a plurality of bumps arranged regularly or irregularly. These plurality of bumps may be, for example, bumps of a conductive metal such as gold. These plurality of bumps may be formed, for example, by arranging a bump precursor of a conductive metal in each region by transfer printing, sintering the bump precursor, and solidifying it.

[0088] In S330 , the switching element 10 is mounted on the mounting surface of the mounting substrate 210 on which each wiring pattern is formed. Figure 6 2 is a perspective view of a structure in which the switching element 10 joined with the second main electrode plate 230 is joined to the mounting substrate 210 of this embodiment. Figure 4 As shown, the switching element 10 to which the second main electrode plate 230 is connected is Figure 4 The upper surface of the switch element 10 is bonded to the mounting surface of the mounting substrate 210 in a manner facing downward. As a result, the first main electrode 100 of the switch element 10 is bonded to the first main electrode wiring 510 and the first main electrode contact 513 of the sub wiring 530, and the control electrode 110 of the switch element 10 is bonded to the control electrode contact 523 of the control wiring 520. This bonding method can be the same as the bonding method of the second main electrode plate 230 to the second main electrode 120.

[0089] In S340 , each electrode plate is bonded to each wiring of the mounting substrate 210 . Figure 7 2 is a perspective view of a structure in which the first main electrode plate 220, the control electrode plate 240 and the sub-electrode plate 250 are bonded to the mounting substrate 210 of this embodiment. Figure 6As shown, the first main electrode plate contact 517 of the first main electrode wiring 510, the control electrode plate contact 527 of the control wiring 520, and the sub-electrode plate contact 537 of the sub-wiring 530 are located in the region where the switching element 10 is not arranged in the mounting surface of the mounting substrate 210 where the switching element 10 is to be mounted. In this process, the first main electrode plate 220, the control electrode plate 240, and the sub-electrode plate 250 are respectively bonded to such first main electrode plate contact 517, control electrode plate contact 527, and sub-electrode plate contact 537. The bonding method can be the same as the bonding method of the second main electrode plate 230 to the second main electrode 120.

[0090] Thus, the first main electrode plate 220, the control electrode plate 240, and the sub-electrode plate 250 are located in the region where the switch element 10 is not arranged on the mounting surface of the switch element 10, and are respectively electrically connected to the first main electrode wiring 510, the control wiring 520, and the sub-wiring 530. In this way, the mounting substrate 210 is manufactured, and the mounting substrate 210 has the insulating substrate 500, and the first main electrode wiring 510, the first main electrode plate 220, the control wiring 520, the control electrode plate 240, the sub-wiring 530, and the sub-electrode plate 250 formed on the insulating substrate 500.

[0091] Here, in the semiconductor device 200 of the present embodiment, the switching element 10 is arranged between the first main electrode plate 220 and the control electrode plate 240 on the mounting surface of the switching element 10 in the mounting substrate 210. The sub-electrode plate 250 can be arranged on the same side as the control electrode plate 240 with respect to the switching element 10. Thus, the semiconductor device 200 can adopt a configuration in which control wiring can be connected to the control electrode plate 240 and the sub-electrode plate 250 located at one end of the semiconductor device 200.

[0092] In S350, the mounting surface of the mounting substrate 210 is sealed with a sealing material so that each electrode plate is exposed to form a sealing portion 260, thereby obtaining Figure 2 The semiconductor device 200 shown in FIG. Here, the sealing portion 260 covers the mounting surface of the switch element 10 in the mounting substrate 210 and the surface of the switch element 10 on the mounting substrate 210 side, and the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240 and the sub-electrode plate 250 are on the terminal surface ( Figure 2 The seal may be a resin seal based on a molding material.

[0093] In this process, after sealing is performed in a manner that covers the mounting surface of the switch element 10 in the mounting substrate 210 and the surface of the switch element 10 on the mounting substrate 210 side, the terminal surface of the semiconductor device 200 may be polished to cut off excess sealing material to expose each electrode plate. In other embodiments, the sealing process may be omitted, and the semiconductor device 200 may not have the sealing portion 260. It should be noted that after this process, an anti-oxidation film may be formed by plating the exposed surface of each electrode plate with Sn, etc.

[0094] According to the manufacturing method shown above, it is possible to manufacture a semiconductor device 200 in which each terminal electrically connected to each electrode of the switching element 10 is exposed on one surface. It should be noted that in the manufacturing method shown above, the second main electrode plate 230 is bonded to the surface on the second main electrode 120 side of the switching element 10 in S310, but this step may also be omitted. In this case, the second main electrode 120 may be directly exposed on the terminal surface of the semiconductor device 200.

[0095] In addition, in the manufacturing method shown above, the order of each process can also be changed within a possible range. For example, S340 can be performed before S330, and the switch element 10 can be mounted on the mounting substrate 210 after each electrode plate is bonded to each wiring of the mounting substrate 210. In addition, S310 can be performed after S330, and the second main electrode plate 230 can be bonded to the surface on the side of the second main electrode 120 of the switch element 10 after the mounting substrate 210 is mounted on the switch element 10. In addition, S300, S310, and S320 can be performed one by one or in parallel.

[0096] It should be noted that the semiconductor device 200 may include a temperature sensing diode or other temperature sensor for measuring the temperature of the semiconductor device 200 or the switching element 10. In this case, the semiconductor device 200 may also include an electrode plate connected to electrodes of a temperature sensor such as an anode electrode and a cathode electrode of the temperature sensing diode on the same surface as the first main electrode plate 220, for example.

[0097] In addition, the number of electrode plates arranged on the same surface as the first main electrode plate 220 in the semiconductor device 200, as well as the size, shape and type of each electrode plate, can be appropriately selected according to the use mode of the semiconductor device 200, the temperature sensor or other additional circuits attached to the semiconductor device 200, etc. For example, the area of ​​the control electrode plate 240 of the semiconductor device 200 can be further reduced, and a new electrode plate can be set at the position where the vacancy is generated thereby. As the newly set electrode plate, for example, at least one of a sensing electrode plate electrically connected to the sensing electrode 130, one or more temperature sensing electrode plates respectively connected to the electrodes of the temperature sensor of the switching element 10, etc., and an electrode plate (sub-electrode plate, etc.) with the same potential as the second main electrode plate 230 can be listed. In addition, for example, other electrode plates such as the second main electrode plate 230 can also be extended to the position where the vacancy is generated by reducing the area of ​​the control electrode plate 240.

[0098] Such additional electrodes can be used to measure various electrical quantities for monitoring the state of the semiconductor device 200 or the switching element 10. Such additional electrodes can be arranged, for example, near the side of the semiconductor device 200 where the control electrode plate 240 and the sub-electrode plate 250 are provided, at a position away from the first main electrode plate 220 and the second main electrode plate 230, and the main wiring connected to these main electrode plates, where a large current flows. Thus, the semiconductor device 200 can reduce the influence of at least one of noise and heat generated by the flow of a large current on the additional electrodes.

[0099] In addition, for example, a second sub-electrode plate different from the sub-electrode plate 250 may be provided at a location where a vacant space is created by reducing the area of ​​the control electrode plate 240. The sub-electrode plate 250 (also referred to as a "first sub-electrode plate") and the second sub-electrode plate may be arranged on both sides of the control electrode plate 240 in such a manner that the control electrode plate 240 is sandwiched between the sub-electrode plates. The arrangement of sandwiching the control electrode plate between the two sub-electrode plates is similar to the arrangement of sandwiching the control electrode plate between the two sub-electrode plates. Fig.15 The control electrode plate 1540 and the two sub-electrode plates 1550 are the same. In order to realize such a configuration, the mounting substrate 210 may have, in addition to the sub-wiring 530, a second sub-wiring that electrically connects the first main electrode 100 of the switching element 10 and the second sub-electrode plate on the mounting surface of the switching element 10. The sub-wiring 530 (also represented as "first sub-wiring") and the second sub-wiring may be arranged on both sides of the control wiring 520 in such a manner that the control wiring 520 is sandwiched between the sub-wirings. In this way, by adopting a structure in which the control electrode plate 240 is sandwiched between two sub-electrode plates, the semiconductor device 200 can reduce the wiring inductance in the path in which the current that drives the semiconductor device 200 (i.e., the current of the control signal that flows in the control electrode 110 of the switching element 10) flows.

[0100] Figure 8 It is a perspective view of a semiconductor module 800 according to the present embodiment. Fig. 9 Schematic diagram showing the internal structure of the semiconductor module 800 of the present embodiment. The semiconductor module 800 includes one or more semiconductor devices 200 , a main substrate 810 , one or more control devices 820 , and a heat sink 830 .

[0101] The semiconductor module 800 of the present embodiment is an inverter device, and includes a plurality of semiconductor devices 200. The plurality of semiconductor devices 200 are respectively allocated to the upper arm and the lower arm of each phase in one or more phases. Figure 8 and 9 In the example, the semiconductor module 800 is a three-phase converter, and each phase is allocated two semiconductor devices 200 in the upper arm and two semiconductor devices 200 in the lower arm. Therefore, the semiconductor module 800 has 12 (=3 phases×(2 in the upper arm+2 in the lower arm)) semiconductor devices 200. It should be noted that the semiconductor module 800 can have any number of semiconductor devices 200 depending on the application.

[0102] The main substrate 810 may be a printed wiring substrate, and each electrode on the back side is connected to the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240 and the sub-electrode plate 250 of each of the plurality of semiconductor devices 200. The main substrate 810 has P wiring 812, N wiring 813, U wiring 814, V wiring 815 and W wiring 816 in the inner layer. Fig. 9 In order to facilitate observation of the structure of the wiring layer, a P wiring 812 , an N wiring 813 , a U wiring 814 , a V wiring 815 , and a W wiring 816 are schematically shown separately on the lower side of the substrate of the main substrate 810 .

[0103] The P wiring 812, the N wiring 813, the U wiring 814, the V wiring 815, and the W wiring 816 may be conductive patterns formed in different layers in the inner layer of the main substrate 810. In the present embodiment, the N wiring 813 is formed in two or more layers connected by conductive through holes or the like, and at least a portion of each of the P wiring 812, the U wiring 814, the V wiring 815, and the W wiring 816 is sandwiched between two layers of the N wiring 813.

[0104] The main substrate 810 has a terminal on the front side that is connected to the first main electrode plate 220 of the plurality of semiconductor devices 200 via wiring in the main substrate 810, and a terminal that is connected to the second main electrode plate 230 via wiring in the main substrate 810. In the example of this embodiment, the main substrate 810 has a P terminal (positive terminal), an N terminal (negative terminal), a U terminal (U phase output terminal), a V terminal (V phase output terminal), and a W terminal (W phase output terminal) on the front side. The connection between each terminal provided on the front side of the main substrate 810 and one or more semiconductor devices 200 is performed by each wiring such as the P wiring 812, using Fig.10 Described later.

[0105] A plurality of control devices 820 are mounted on the front surface of the main substrate 810. One or more control devices 820 are electrically connected to the respective control electrode plates 240 and sub-electrode plates 250 in one or more semiconductor devices 200 via wiring within the main substrate 810. Each control device 820 controls the semiconductor device 200 by controlling the voltage of the control electrode plate 240 of the semiconductor device 200 relative to the sub-electrode plate 250. Each control device 820 can be connected to one semiconductor device 200 to control one semiconductor device 200, or can be connected to more than two semiconductor devices 200 to control more than two semiconductor devices 200. It should be noted that one or more control devices 820 can receive a control signal from an external control device to control one or more semiconductor devices 200.

[0106] The heat sink 830 is in contact with the surface of one or more semiconductor devices 200 opposite to the main substrate 810. The heat sink 830 may be, for example, a radiator, a heat sink, or a heat exchanger for liquid cooling.

[0107] Fig.10The connection of each wiring in the semiconductor module 800 of the present embodiment is shown. In this figure, the semiconductor device 200 (UU1) and the semiconductor device 200 (UU2) are allocated to the U-phase upper arm, and the semiconductor device 200 (UD1) and the semiconductor device 200 (UD2) are allocated to the U-phase lower arm. The second main electrode plate 230 of each semiconductor device 200 of the U-phase upper arm is connected to the P terminal via the P wiring 812. The first main electrode plate 220 of each semiconductor device 200 of the U-phase upper arm is connected to the U terminal via the U wiring 814. The second main electrode plate 230 of each semiconductor device 200 of the U-phase lower arm is connected to the U terminal and the first main electrode plate 220 of each semiconductor device 200 of the U-phase upper arm via the U wiring 814. The first main electrode plate 220 of each semiconductor device 200 of the U-phase lower arm is connected to the N terminal via the N wiring 813. Through this connection, each semiconductor device 200 of the U-phase upper arm and each semiconductor device 200 of the U-phase lower arm are connected in series in sequence between the P terminal and the N terminal, and the node between the first main electrode plate 220 (for example, the source) of each semiconductor device 200 of the U-phase upper arm and the second main electrode plate 230 (for example, the drain) of each semiconductor device 200 of the U-phase lower arm is connected to the U terminal.

[0108] The semiconductor device 200 (VU1) and the semiconductor device 200 (VU2) are allocated to the V-phase upper arm, and the semiconductor device 200 (VD1) and the semiconductor device 200 (VD2) are allocated to the V-phase lower arm. The semiconductor devices 200 of the V-phase upper arm and the V-phase lower arm are connected in the same manner as the semiconductor devices 200 of the U-phase upper arm and the U-phase lower arm, except that they are connected to the V terminal instead of the U terminal.

[0109] The semiconductor device 200 (WU1) and the semiconductor device 200 (WU2) are allocated to the W-phase upper arm, and the semiconductor device 200 (WD1) and the semiconductor device 200 (WD2) are allocated to the W-phase lower arm. The semiconductor devices 200 of the W-phase upper arm and the W-phase lower arm are connected in the same manner as the semiconductor devices 200 of the U-phase upper arm and the U-phase lower arm, except that they are connected to the W terminal instead of the U terminal.

[0110] As shown in this figure, each semiconductor device 200 allocated to the upper arm of each phase among the multiple semiconductor devices 200 can be arranged in a row (the upper row in the figure) on the back side of the main substrate 810. Each semiconductor device 200 allocated to the lower arm of each phase among the multiple semiconductor devices 200 can be arranged in a row (the lower row in the figure) on the back side of the main substrate 810 side by side with the row of each semiconductor device 200 allocated to the upper arm of each phase. With such a configuration, since the second main electrode plate 230 of each semiconductor device 200 of the upper arm and the first main electrode plate 220 of each semiconductor device 200 of the lower arm are arranged in a row, the P wiring 812 and the N wiring 813 can be respectively extended along the arrangement direction of each semiconductor device 200 of the upper arm and the arrangement direction of each semiconductor device 200 of the lower arm and connected to each semiconductor device 200. In addition, along with this, the U wiring 814, V wiring 815 and W wiring 816 can also extend along the arrangement direction of each semiconductor device 200, and be connected to the first main electrode plate 220 of each semiconductor device 200 of the corresponding upper arm and the second main electrode plate 230 of each semiconductor device 200 of the corresponding lower arm.

[0111] In addition, as shown in this figure, on the back side of the main substrate 810, each semiconductor device 200 allocated to the upper arm of each phase can be arranged in an orientation in which the first main electrode plate 220 is located on the side of the semiconductor device 200 allocated to the opposite lower arm among the plurality of semiconductor devices 200 (in the figure, the first main electrode plate 220 is oriented at the lower side of the figure). On the back side of the main substrate 810, each semiconductor device 200 allocated to the lower arm of each phase can be arranged in an orientation in which the first main electrode plate 220 is located on the side of the semiconductor device 200 allocated to the opposite upper arm among the plurality of semiconductor devices 200 (in the figure, the first main electrode plate 220 is oriented at the upper side of the figure). In such an arrangement, the control electrode plate 240 and the sub-electrode plate 250 of each semiconductor device 200 are located at the end of the semiconductor device 200 on the opposite side of the semiconductor device 200 of the opposite arm. Thus, the semiconductor devices 200 of the upper and lower arms can be opposed to each other, and the control wiring can be arranged outside the region where the P wiring 812 , N wiring 813 , U wiring 814 , V wiring 815 , and W wiring 816 through which large current flows are arranged.

[0112] Fig.11 The manufacturing method of the semiconductor module 800 of this embodiment is shown. In S1100, at least one semiconductor device 200 is prepared. In S1110, a main substrate 810 is prepared to which the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240 and the sub-electrode plate 250 to be connected to the back of the at least one semiconductor device 200.

[0113] In S1120, at least one control device 820 is mounted on the front side of the main substrate 810 by soldering the at least one control device 820 on the front side of the main substrate 810. In S1130, at least one semiconductor device 200 is sandwiched between the back side of the main substrate 810 and the heat sink 830, and the back side of the main substrate 810 is connected to each electrode plate of the semiconductor device 200, and the heat sink 830 is installed on the surface of each semiconductor device 200 opposite to the main substrate 810.

[0114] Fig.12 800 of the present embodiment. In particular, this figure schematically illustrates the manufacturing method of the semiconductor module 800 using a schematic cross-sectional structure of a main substrate 810, a semiconductor device 200, and a heat sink 830. Fig.11 The main substrate 810 carries at least one control device 820 on the front side, and has terminals such as a P terminal and a U terminal. Each terminal such as a P terminal and a U terminal may have a structure formed by plating a conductive metal layer on the inner surface of a non-through hole or a through hole, and the non-through hole or the through hole has a depth of at least up to the wiring layer having a wiring pattern to which each terminal is electrically connected. Alternatively, each terminal may be formed by burying a conductive terminal component (a columnar copper component having a screw hole on the inside, etc.) having a depth of at least up to the wiring layer having a wiring pattern to which each terminal is electrically connected in the main substrate 810.

[0115] The main substrate 810 has a first main electrode plate contact 1280 to be joined to the first main electrode plate 220 of the semiconductor device 200, a second main electrode plate contact 1285 to be joined to the second main electrode plate 230, and a control electrode plate contact 1290 to be joined to the control electrode plate 240 on the back side. The main substrate 810 may further have an electrode plate contact to be joined to the sub-electrode plate 250. The U terminal and the first main electrode plate contact 1280 may be electrically connected via a conductive through hole and a U wiring 814, and the P terminal and the second main electrode plate contact 1285 may be electrically connected via a P wiring 812.

[0116] exist Fig.11 In S1130, at least one semiconductor device 200 may be first connected to the back of the main substrate 810. That is, the first main electrode plate 220, the second main electrode plate 230, the control electrode plate 240 and the sub-electrode plate 250 of each semiconductor device 200 are connected to the corresponding electrodes (the first main electrode plate contact 1280 if it is the first main electrode plate 220 of this figure, the second main electrode plate contact 1285 if it is the second main electrode plate 230 of this figure, and the control electrode plate contact 1290 if it is the control electrode plate 240 of this figure) on the back of the main substrate 810 through nanosilver paste or direct bonding of gold-gold.

[0117] Next, a heat sink 830 can be installed on the surface of at least one semiconductor device 200 on the opposite side to the main substrate 810. The semiconductor device 200 and the heat sink 830 can be directly crimped or can be in contact via a thermally conductive material. The thermally conductive material can be a paste-like thermal grease or filler, a thermally conductive sheet or a heat sink, or any other TIM (Thermal Interface Material). In addition, the semiconductor device 200 and the heat sink 830 can be crimped in a state where a thermally conductive material is provided on one or both of the semiconductor device 200 or the heat sink 830. As shown in this figure, the mounting substrate 210 of the semiconductor device 200 can have a thermally conductive plate 1270 formed on the surface of the insulating substrate 500 on the opposite side to the mounting surface of the switching element 10. The thermally conductive plate 1270 can be a thermally conductive component such as a copper plate having a higher thermal conductivity than the insulating substrate 500.

[0118] Fig.13 FIG. 8 is a schematic diagram of a cross section of a semiconductor module 800 according to the present embodiment. Fig.11 In the step S1130, as shown in the example of this figure, the main substrate 810 can be fixed to the heat sink 830 by screwing a screw into a screw hole provided on the surface of the heat sink 830, and the screw passes through the main substrate 810 and reaches the area on the surface of the heat sink 830 where the semiconductor device 200 is not located. The semiconductor module 800 can be sold and used in the configuration of this figure, or can be sold and used in a configuration in which the main substrate 810 and the heat sink 830 are sealed by resin sealing or the like.

[0119] Fig.14 Yes Fig.13 Schematic diagram of an enlarged area S shown. The electrode plates such as the second main electrode plate 230 and the control electrode plate 240 in the semiconductor device 200 are electrically connected to the terminals or the control device 820 on the front side of the main substrate 810 via the electrode contacts and wirings of the main substrate 810. The semiconductor module 800 can be miniaturized or thinned by connecting the switching element 10 and the P terminal and other terminals with a small wiring distance using the inner layer wiring of the main substrate 810. In addition, the semiconductor module 800 can reduce the inductance between the first main electrode plate 220 and the second main electrode plate 230 of the switching element 10 and each terminal (also expressed as "main circuit inductance"), and the inductance between the control electrode plate 240 and the sub-electrode plate 250 of the switching element 10 and the control device 820 (also expressed as "gate control circuit inductance").

[0120] In addition, in the semiconductor module 800, the second main electrode plate 230 is bonded to the surface on the second main electrode 120 side of the switching element 10 (the surface on the upper side in the figure), and the second main electrode plate 230 is electrically connected to the P terminal and the like on the front surface of the main substrate 810 via the wiring and the like in the main substrate 810. Here, since such an electrical connection path is formed of a metal material having high thermal conductivity such as copper, the semiconductor module 800 can transfer the heat from the surface on the second main electrode 120 side of the switching element 10 to each terminal and the like through the wiring pattern in the main substrate 810, and dissipate the heat to the busbar and the like connected to each terminal.

[0121] In addition, the surface of the switching element 10 on the side of the first main electrode 100 and the control electrode 110 (the lower surface in the figure) is electrically connected to the first main electrode contact 513 of the first main electrode wiring 510 and the control electrode contact 523 of the control wiring 520 formed on the mounting surface side of the switching element 10 of the insulating substrate 500. The semiconductor module 800 can transfer heat from the surface of the switching element 10 on the side of the control electrode 110 and the like to the heat sink 830 via the first main electrode wiring 510 and the control wiring 520, the insulating substrate 500, and the heat transfer plate 1270, and dissipate the heat from the heat sink 830.

[0122] As a modification of this embodiment, Fig.10 The semiconductor device 200 (UU1) and the semiconductor device 200 (UD1) in the semiconductor device 200 shown can also be assembled with a main substrate 810 for wiring the two semiconductor devices 200 to form a two-in-one module equipped with an upper arm and a lower arm of one phase. In addition, the upper arm and the lower arm for three phases can also form a six-in-one module. In this case, the number of semiconductor devices 200 constituting the upper arm and the lower arm is not limited to one. In addition, in this case, the semiconductor device 200 is Figure 3 After the step S350 shown, individual semiconductor devices 200 are formed by dicing or the like. However, the semiconductor devices 200 constituting a two-in-one module or a six-in-one module may be integrated without being diced.

[0123] As another modified example of this embodiment, a converter device Figure 8In the semiconductor module, a smoothing capacitor not shown in the figure may be connected to the P terminal and the N terminal, or a current sensor not shown in the figure may be provided at at least two of the U terminal, the V terminal, and the W terminal. The current sensor may be mounted on the main substrate 810, may be mounted on another substrate not shown in the figure, or may be provided in the inner layer of the main substrate 810. In addition, when the current sensor is mounted on the main substrate 810, a magnetic shielding plate may be appropriately provided at least a portion of the periphery of the current sensor. The magnetic shielding plate may be installed in a manner of being inserted into a slit provided in the main substrate 810, or may be installed in the inner layer of the main substrate 810 as a pattern or the like.

[0124] The connection between the smoothing capacitor and the main substrate 810 can be achieved by connecting the terminals of the smoothing capacitor to the connection terminals provided on the main substrate 810. Such connection of the smoothing capacitor can be listed in the following Fig.21 An example of description is given. In addition, Figure 8 The heat sink 830 may be independently provided for at least one semiconductor device 200 , or may be independently provided for all semiconductor devices 200 .

[0125] in addition, Figure 8 The semiconductor module 800 may also include a temperature sensor (not shown). The temperature sensor may be mounted on the main substrate 810 or may be provided in an inner layer of the main substrate 810. By providing the temperature sensor in the inner layer of the main substrate 810, the temperature of the semiconductor device 200 may be measured with higher accuracy.

[0126] in addition, Figure 8 The semiconductor module 800 may also include a gate resistor (not shown). The gate resistor is connected in series with the control wiring between the control electrode plate 240 of the semiconductor device 200 and the control device 820. The gate resistor may be mounted on the main substrate 810 or may be disposed in an inner layer of the main substrate 810. By disposing the gate resistor in an inner layer of the main substrate 810, since the gate resistor can be disposed closest to the semiconductor device 200, the vibration of the voltage generated at the control electrode 110 of the semiconductor device 200 can be reduced.

[0127] in addition, Figure 8 The semiconductor module 800 may also include a buffer capacitor (not shown). The buffer capacitor may be mounted on the main substrate 810 or may be disposed in an inner layer of the main substrate 810. By disposing the buffer capacitor in an inner layer of the main substrate 810, the buffer capacitor can be disposed closest to the semiconductor device 200, thereby further suppressing the high voltage generated instantaneously when the semiconductor device 200 is switched.

[0128] in addition, Figure 8The semiconductor module 800 may also include an external control device (not shown) that generates a signal for controlling at least the control device, so as to cover at least a portion of the front surface of the main substrate 810. The control signal generated in this way is transmitted to the back through the Fig.16 The control connector described in is input to the control device.

[0129] Figure 8 The control device 820 mounted on the main substrate 810 can also be mounted in a configuration determined according to the heat distribution of the semiconductor device 200. As an example, a case where the surface of the main substrate 810 corresponding to the semiconductor device 200 is avoided can be cited. In addition, in order to mitigate the influence of temperature during mounting, a slit can be provided in the main substrate 810 around the control device 820.

[0130] in addition, Figure 8 The control device 820 mounted on the main substrate 810 can be mounted at a position determined according to the wiring path of the main wiring. As an example, each control device 820 can be arranged to avoid the position corresponding to the top of each main wiring (P wiring 812, N wiring 813, U wiring 814, V wiring 815 and W wiring 816) on the front surface of the main substrate 810. In this way, the control device 820 can be prevented from being affected by the noise generated by the large current flowing in the main wiring and malfunctioning.

[0131] exist Figure 8 The main substrate 810 may also be provided with another heat sink on the surface of the main substrate 810 on the opposite side to the side where the heat sink 830 is arranged. In this case, it may also be a heat capacity body independent of the heat sink 830.

[0132] Fig.15 FIG. 1 is a perspective view of a semiconductor device 1500 according to a first variation of the present embodiment. Figures 1 to 7 The semiconductor device 1500 is a modification of the semiconductor device 200 shown in FIG. 1 and 2 , and therefore description thereof is omitted except for the following differences. The semiconductor device 1500 may have the same size as the semiconductor device 200 or may have a size similar to that of the semiconductor device 200. The semiconductor device 1500 has a configuration similar to that of the semiconductor device 200. Figure 1 The switching element 10 and other switching elements shown in the figure have electrode plates electrically connected to each other exposed on one surface of the plate-shaped semiconductor device 1500. In this modification, the case where the switching element 10 is used as the switching element is described, but the semiconductor device 1500 may also be equipped with switching elements other than the switching element 10.

[0133] In this modification, the semiconductor device 1500 includes a mounting substrate 1510, a first main electrode plate 1520, a second main electrode plate 1530, a sub-electrode plate 1550, a control electrode plate 1540, and a sealing portion 1560. The first main electrode plate 1520, the second main electrode plate 1530, the sub-electrode plate 1550, and the control electrode plate 1540 are arranged on one surface (the upper surface in the figure) of the semiconductor device 1500. The semiconductor device 1500 may have a structure in which the second main electrode plate 1530 is arranged between the first main electrode plate 1520 and the control electrode plate 1540 on one surface.

[0134] The mounting substrate 1510 mounts a switching element such as the switching element 10 on a mounting surface (the upper surface in the figure). The mounting substrate 1510 corresponds to the mounting substrate 210 in the semiconductor device 200. The mounting substrate 1510 can mount the switching element 10 by bonding the surface on the second main electrode 120 side of the switching element 10 to the mounting surface of the mounting substrate 1510. The mounting substrate 1510 can have a pattern of wiring and electrode contacts different from that of the mounting substrate 210 depending on the direction in which the switching element 10 is mounted.

[0135] The first main electrode plate 1520 is electrically connected to the second main electrode 120 of the switching element 10. The first main electrode plate 1520 corresponds to the first main electrode plate 220 in the semiconductor device 200. The second main electrode plate 1530 is electrically connected to the first main electrode 100 of the switching element 10. The second main electrode plate 1530 corresponds to the second main electrode plate 230 in the semiconductor device 200. In this modification, the second main electrode plate 1530 is bonded to the first main electrode 100 in a region where the first main electrode 100 is formed in the surface on the first main electrode 100 side of the switching element 10. The second main electrode plate 1530 may have a cutout so as not to be located above a region where the control electrode 110 is formed in the surface on the first main electrode 100 side of the switching element 10. Except for the central portion on the inner side of the figure adjacent to the control electrode plate 1540, the second main electrode plate 1530 can be led out to the side of the semiconductor device 1500 opposite to the first main electrode plate 1520 (the inner side of the figure), and the led-out portion can be used as a sub-electrode plate 1550. The sub-electrode plate 1550 corresponds to the sub-electrode plate 250 of the semiconductor device 200.

[0136] The control electrode plate 1540 is electrically connected to the control electrode 110 of the switching element 10. The control electrode plate 1540 corresponds to the control electrode plate 240 in the semiconductor device 200. The control electrode plate 1540 is bonded to the control electrode 110 in the area where the control electrode 110 is formed on the surface of the first main electrode 100 side of the switching element 10. The control electrode plate 1540 can be led out to the side of the semiconductor device 1500 opposite to the first main electrode plate 1520 side (the inner side in the drawing). The sealing portion 1560 exposes the first main electrode plate 1520, the second main electrode plate 1530, and the control electrode plate 1540, and covers the mounting surface of the switching element 10 of the mounting substrate 1510.

[0137] Here, the semiconductor device 200 has a structure in which the second main electrode plate 230 connected to the second main electrode 120 of the switching element 10 is arranged between the first main electrode plate 220 connected to the first main electrode 100 of the switching element 10 and the control electrode plate 240 connected to the control electrode 110 of the switching element 10. In contrast, the semiconductor device 1500 may have a structure in which the second main electrode plate 1530 connected to the first main electrode 100 of the switching element 10 is arranged between the first main electrode plate 1520 connected to the second main electrode 120 of the switching element 10 and the control electrode plate 1540 connected to the control electrode 110 of the switching element 10. In this case, the polarity of the main electrode of the switching element 10 of the first main electrode plate 220 and the second main electrode plate 230 of the semiconductor device 200 is reversed from the polarity of the main electrode of the switching element 10 of the first main electrode plate 1520 and the second main electrode plate 1530 of the semiconductor device 1500. For example, when the first main electrode plate 220 of the semiconductor device 200 is a source and the second main electrode plate 230 is a drain, the first main electrode plate 1520 of the semiconductor device 1500 is a drain and the second main electrode plate 1530 is a source. By using the semiconductor device 200 and the semiconductor device 1500 having different electrode configurations, a semiconductor device having a more appropriate electrode configuration can be selected and used according to the mounting position of each semiconductor device in the semiconductor module 800 or other semiconductor modules.

[0138] It should be noted that, for the sake of convenience, when focusing on the arrangement of the semiconductor device, among the main electrodes of the switching element such as the switching element 10 mounted on the semiconductor device 1500, the main electrode connected to the first main electrode plate 1520 is sometimes expressed as the first main electrode, and the main electrode connected to the second main electrode plate 1530 is sometimes expressed as the second main electrode. For example, when the first main electrode 100 of the switching element 10 is connected to the second main electrode plate 1530 and the second main electrode 120 of the switching element 10 is connected to the first main electrode plate 1520, for the sake of convenience, the first main electrode 100 of the switching element 10 is expressed as the second main electrode, and the second main electrode 120 of the switching element 10 is expressed as the first main electrode.

[0139] Fig.16 It is a perspective view of a semiconductor module 1600 according to a second modification of the present embodiment. Fig.17 This is a diagram of a semiconductor device 1500 according to a second variation of the present embodiment as viewed from the heat sink 1630 side. Figures 8 to 14 The semiconductor module 1600 is a modification of the semiconductor module 800 shown, and therefore description thereof is omitted except for the following differences: The semiconductor module 1600 includes one or more semiconductor devices 200, a main substrate 1610, one or more control devices 1620, one or more buffer capacitors 1640, one or more control connectors 1650, a heat sink 1630, and a fixing member 1660.

[0140] The semiconductor module 1600 of this modification is a converter device similar to the semiconductor module 800. Fig.16 and 17 In the example, the semiconductor module 1600 is a three-phase converter, and each phase is assigned a semiconductor device 200 in the upper arm and a semiconductor device 200 in the lower arm. Therefore, the semiconductor module 1600 has 6 (=3 phases×(1 in the upper arm+1 in the lower arm)) semiconductor devices 200. The semiconductor module 1600 and Figure 8 and Fig. 9 The semiconductor module 800 shown in FIG. 1 also adopts a structure in which a plurality of semiconductor devices 200 are sandwiched between a main substrate 1610 and a heat sink 1630. Fig.16 and Fig.17 In the figure, the plurality of semiconductor devices 200 are not shown.

[0141] It should be noted that the semiconductor module 1600 may include a semiconductor device 200 of one phase, a semiconductor device 200 of two phases, or semiconductor devices 200 of any number of phases, and may include one or more semiconductor devices 200 in each arm of each phase. In addition, the semiconductor module 1600 may have any circuit configuration using semiconductor devices 200 such as a three-level converter or a multi-level converter or a diode bridge having one or more phases, and may include any number of semiconductor devices 200 depending on the application. In addition, as at least a part of the semiconductor device, the semiconductor module 1600 may be equipped with the semiconductor device 1500 instead of the semiconductor device 200.

[0142] The main substrate 1610 corresponds to the main substrate 810 in the semiconductor module 800. The first main electrode plate 220, the second main electrode plate 230, and the control electrode plate 240 of at least one semiconductor device 200 are connected to the back of the main substrate 1610. In the case where the semiconductor module 1600 carries at least one semiconductor device 1500, the first main electrode plate 1520, the second main electrode plate 1530, and the control electrode plate 1540 of at least one semiconductor device 1500 are connected to the back of the main substrate 1610.

[0143] The three semiconductor devices (also referred to as "first semiconductor devices") of the upper arm of the semiconductor devices such as the semiconductor device 200 and the semiconductor device 1500 are arranged at positions corresponding to the three control devices 1620a and the three buffer capacitors 1640a (the three buffer capacitors 1640 on the left side of the six buffer capacitors 1640 in the figure) on the back side of the main substrate 1610. Therefore, the three semiconductor devices of the upper arm are arranged in a row along the Y direction in the figure on the back side of the main substrate 1610.

[0144] The three semiconductor devices of the lower arm (also indicated as "second semiconductor devices") are arranged at positions corresponding to the three control devices 1620b and the three buffer capacitors 1640b (three buffer capacitors 1640 on the right side of the six buffer capacitors 1640 in the figure) on the back side of the main substrate 1610. Therefore, the three semiconductor devices of the lower arm are arranged in a row along the Y direction in the figure on the back side of the main substrate 1610 in parallel with the three semiconductor devices of the upper arm.

[0145] The front side of the main substrate 1610 has a P terminal and an N terminal near the inner side in the Y direction in the figure. In addition, the front side of the main substrate 1610 has a U terminal, a V terminal, and a W terminal near the side opposite to the side where the P terminal and the N terminal are provided. The P terminal, the N terminal, the U terminal, the V terminal, and the W terminal may have through holes into which bolts or the like for fixing a wiring cable or a busbar for a large current to each terminal can be inserted.

[0146] The P wiring between the P terminal and each semiconductor device 200, the N wiring between the N terminal and each semiconductor device 200, the U wiring between the U terminal and the U-phase semiconductor device 200, the V wiring between the V terminal and the V-phase semiconductor device 200, and the W wiring between the W terminal and the W-phase semiconductor device 200 are arranged in the range or area corresponding to the three control devices 1620a and the three control devices 1620b in the X direction within the main substrate 1610, and extend along the Y direction. The area of ​​the main substrate 1610 corresponding to the column of three semiconductor devices 200 from the upper arm to the column of semiconductor devices 200 of the lower arm is represented as a "main wiring area". The main wiring area can be an area of ​​the rectangular main substrate 1610 within the range between the column of three first semiconductor devices 200 of the upper arm and the column of three second semiconductor devices 200 of the lower arm, from the sides on the U terminal, V terminal and W terminal sides to the sides on the P terminal and N terminal sides. For the main wiring area, use Fig.18 and Fig.19 Examples are further described below.

[0147] One or more control devices 1620 are mounted on the front surface of the main substrate 1610. The control device 1620 corresponds to the control device 820 in the semiconductor module 800. The one or more control devices 1620 are electrically connected to the control electrode plate 240 and the sub-electrode plate 250 of one or more semiconductor devices 200 via the wiring in the main substrate 1610. The control device 1620 controls the semiconductor device 200 by controlling the voltage of the control electrode plate 240 of the semiconductor device 200 relative to the sub-electrode plate 250. Each control device 1620 can be connected to one semiconductor device 200 to control one semiconductor device 200, or can be connected to more than two semiconductor devices 200 to control more than two semiconductor devices 200. The control device 1620 that controls one or more semiconductor devices 1500 can be electrically connected to the control electrode plate 1540 and the sub-electrode plate 1550 of each semiconductor device 1500 via the wiring in the main substrate 1610.

[0148] In this variation, three control devices 1620a (also indicated as "first control devices 1620a") respectively control each of the three first semiconductor devices 200 of the upper arm. The three first control devices 1620a are configured to be arranged along the Y direction at a position on the front side of the semiconductor module 1600 that is farther away from the three second semiconductor devices 200 of the lower arm than the three first semiconductor devices 200 of the upper arm (i.e., on the left side in the X direction in the figure). The area of ​​the main substrate 1610 that is connected to the first semiconductor device 200 side of the upper arm relative to the main wiring area when viewed from above and is configured with each first control device 1620a for controlling the upper arm is indicated as a "first control wiring area". The first control wiring area may be an area of ​​the rectangular main substrate 1610 that is located further to the left in the X direction than the main wiring area, up to the edge extending along the Y direction (the edge on the left side in the X direction). For the first control wiring area, use Fig.18 and Fig.19 Examples are further described below.

[0149] The three control devices 1620b (also indicated as "second control devices 1620b") each control the three second semiconductor devices 200 of the lower arm. The three second control devices 1620b are arranged along the Y direction at a position on the front side of the semiconductor module 1600 that is farther away from the three first semiconductor devices 200 of the upper arm than the three second semiconductor devices 200 of the lower arm (i.e., on the right side in the X direction in the figure). The area of ​​the main substrate 1610 that is in contact with the second semiconductor device 200 side of the lower arm relative to the main wiring area when viewed from above and is provided with each second control device 1620b for controlling the lower arm is indicated as a "second control wiring area". The second control wiring area may be an area of ​​the rectangular main substrate 1610 that is located further to the right in the X direction than the main wiring area, up to the edge extending along the Y direction (the edge on the right side in the X direction). For the second control wiring area, use Fig.18 and Fig.19 Examples are further described below.

[0150] A plurality of buffer capacitors 1640 are arranged in the main wiring area on the front side of the main substrate 1610. At least one buffer capacitor 1640a (also indicated as a "first buffer capacitor 1640a") can be provided corresponding to each phase of the upper arm. In this variation, three buffer capacitors 1640a are provided corresponding to three phases of the upper arm. The three buffer capacitors 1640a can be provided above the P wiring in the main substrate 1610. Each buffer capacitor 1640a is connected in parallel with the corresponding semiconductor device 200 between the P wiring and the output wiring of the corresponding phase in the U wiring, V wiring or W wiring, so as to suppress the instantaneous generation of high voltage when the corresponding semiconductor device 200 is switched.

[0151] At least one buffer capacitor 1640b (also indicated as "second buffer capacitor 1640b") may be provided in correspondence with each phase of the lower arm. In this modification, three buffer capacitors 1640b are provided in correspondence with three phases of the lower arm. The three buffer capacitors 1640b may be provided above the N wiring in the main substrate 1610. Each buffer capacitor 1640b is connected in parallel with the corresponding semiconductor device 200 between the N wiring and the output wiring of the corresponding phase among the U wiring, the V wiring, or the W wiring, to suppress the instantaneous generation of high voltage when the corresponding semiconductor device 200 is switched.

[0152] In addition, each snubber capacitor may be connected between the P wiring and the N wiring of the corresponding arm. The snubber capacitor can also suppress the instantaneous generation of high voltage when the corresponding semiconductor device 200 is switched by such a connection method.

[0153] At least one control connector 1650 is mounted on the front surface of the main substrate 1610 and is electrically connected to at least one control device 1620. The semiconductor module 1600 is electrically connected to an external control device via a cable that is detachably connected to the at least one control connector 1650. The at least one control device 1620 can receive a control signal from an external control device via the cable and the at least one control connector 1650 to control one or more semiconductor devices 200.

[0154] In this variation, at least one control connector 1650a (also indicated as "first control connector 1650a") is arranged in a first control wiring area on the front of the main substrate 1610, and is electrically connected to at least one first control device 1620a. At least one control connector 1650b (also indicated as "second control connector 1650b") is arranged in a second control wiring area on the front of the main substrate 1610, and is electrically connected to at least one second control device 1620b.

[0155] The heat sink 1630 is disposed on the back side of the main substrate 1610 to which at least one semiconductor device 1500 is connected. The heat sink 1630 is connected to the surface of one or more semiconductor devices 200 opposite to the main substrate 810. The heat sink 1630 corresponds to the heat sink 830 in the semiconductor module 800. The heat sink 1630 may be, for example, a heat sink, a heat sink, or a heat exchanger for liquid cooling.

[0156] In this modification, the heat sink 1630 has a structure in which one or more protrusions 1670 and one or more protrusions 1710 are provided on the surface of the plate-like component opposite to the main substrate 1610 and the at least one semiconductor device 1500 side relative to the plate-like component (the main body of the heat sink 1630), and the plate-like component has a surface close to the main substrate 1610 and the at least one semiconductor device 1500 side. The plate-like component of the heat sink 1630 may have a size that does not cover the P terminal, N terminal, U terminal, V terminal, and W terminal on the back side of the main substrate 1610.

[0157] One or more protrusions 1670 are cylindrical or other shaped protrusions protruding from the surface of the plate-shaped part of the heat sink 1630 opposite to the main substrate 1610. The protrusions 1670 are fixed to the main substrate 1610 by the fixing part 1660, which passes through the plate-shaped part of the heat sink 1630 from the front side of the main substrate 1610 and reaches the protrusions 1670. In this way, the heat sink 1630 is fixed to the back side of the main substrate 1610. Fig.23 Examples are described later.

[0158] At least a portion of the plurality of protrusions 1670 (six protrusions 1670 in the example of the present figure) are arranged along the Y-direction side located to the left and right of the X-direction in the figure of the heat sink 1630. In addition, another portion of the plurality of protrusions 1670 (two protrusions 1670 in the example of the present figure) are arranged along the Y-direction side in the center portion of the heat sink 1630 in the figure in the X-direction.

[0159] The one or more protrusions 1710 are cylindrical or other arbitrary shaped protrusions protruding from the surface of the plate-like member of the heat sink 1630 opposite to the main substrate 1610 side. The protrusion 1670 may not have the function of being fixed to the main substrate 1610 by the fixing member 1660 or the like. The plurality of protrusions 1710 may also be arranged within a range corresponding to the main wiring area of ​​the main substrate 1610.

[0160] The protrusions 1670 and 1710 increase the surface area of ​​the heat sink 1630 to improve the heat dissipation efficiency. Here, the surface of the heat sink 1630 provided with the protrusions 1670 and 1710 may be in contact with the gas or liquid refrigerant, or may be exposed in the refrigerant flow path.

[0161] Fig.18 The connection of each wiring in the semiconductor module 1800 of the third modification of this embodiment is shown. Fig.10 Since this is a modification of the connection structure of each wiring in the semiconductor module 800 shown in FIG. 8 , the description thereof will be omitted except for the following differences. Fig.10 In the semiconductor module 800 shown in FIG. 1 , six groups of semiconductor devices 200 of upper and lower arms are connected from Fig.10 From the left side of , they are arranged in the order of U phase, V phase, W phase, U phase, V phase, and W phase. Fig.18 In the semiconductor module 1800 shown in FIG. 1 , six groups of semiconductor devices 200 of upper and lower arms are connected from Fig.18 From the left side, the semiconductor devices 200 are arranged adjacent to each corresponding upper and lower two in the order of W phase, W phase, V phase, V phase, U phase, and U phase.

[0162] For the U phase, at least one semiconductor device 200 includes at least one first semiconductor device 200 (UU1, UU2) and at least one second semiconductor device 200 (UD1, UD2). At least one first semiconductor device 200 (UU1, UU2) is a semiconductor device 200 of the upper arm (the semiconductor device 200 on the upper side in the figure), and at least one second semiconductor device 200 (UD1, UD2) is a semiconductor device 200 of the lower arm (the semiconductor device 200 on the lower side in the figure). The at least one first semiconductor device 200 of the U phase is also represented as the first at least one first semiconductor device 200. In addition, the at least one second semiconductor device 200 of the U phase is also represented as the first at least one second semiconductor device 200.

[0163] Similarly, for the V phase, the at least one semiconductor device 200 includes at least one first semiconductor device 200 (VU1, VU2) and at least one second semiconductor device 200 (VD1, VD2). The at least one first semiconductor device 200 of the V phase is also represented as the second at least one first semiconductor device 200. In addition, the at least one second semiconductor device 200 of the V phase is also represented as the second at least one second semiconductor device 200.

[0164] Similarly, for the W phase, the at least one semiconductor device 200 includes at least one first semiconductor device 200 (WU1, WU2) and at least one second semiconductor device 200 (WD1, WD2). The at least one first semiconductor device 200 of the W phase is also represented as the third at least one first semiconductor device 200. In addition, the at least one second semiconductor device 200 of the W phase is also represented as the third at least one second semiconductor device 200.

[0165] The first semiconductor devices 200 of the U phase, V phase and W phase are arranged in a row on the back side of the main substrate 1610. The second semiconductor devices 200 of the U phase, V phase and W phase are arranged in a row on the back side of the main substrate 1610 in parallel with the row of the first semiconductor devices 200.

[0166] In this modification, at least one first semiconductor device 200 and the corresponding second semiconductor device 200 in at least one second semiconductor device 200 are arranged on the back side of the main substrate 1610 in such a manner that the first main electrode plate 220 faces each other. Thus, the semiconductor module 1800 can arrange the control electrode plate 240 and the sub-electrode plate 250 connected with the control wiring on the opposite side of the opposing semiconductor device 200, and can easily arrange the control wiring separately from the main wiring such as the P wiring 1812, the N wiring 1813, the U wiring 1814, the V wiring 1815, and the W wiring 1816 through which the main current flows. It should be noted that, depending on the installation situation, at least one first semiconductor device 200 and the corresponding second semiconductor device 200 in at least one second semiconductor device 200 can also be arranged on the back side of the main substrate 1610 in such a manner that the first main electrode plate 220 faces the control electrode plate 240.

[0167] The main electrode plate on the positive side of the first main electrode plate 220 and the second main electrode plate 230 of at least one first semiconductor device 200 (UU1, UU2, VU1, VU2, WU1, WU2) of each phase (the second main electrode plate 230 as the drain in the example of this figure) is connected to the P terminal via the P wiring 1812 in the main substrate 1610. The main electrode plate on the negative side of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (UD1, UD2, VD1, VD2, WD1, WD2) of each phase (the first main electrode plate 220 as the source) is connected to the N terminal via the N wiring 1813 in the main substrate 1610. The main electrode plate on the negative side of the first main electrode plate 220 and the second main electrode plate 230 of at least one first semiconductor device 200 of each phase (the first main electrode plate 220 serving as the source) is electrically connected to the main terminal plate on the positive side of the first main electrode plate 220 and the second main electrode plate 230 of the corresponding second semiconductor device 200 in at least one second semiconductor device 200 (the second main electrode plate 230 serving as the drain).

[0168] For the U phase, the main electrode plate on the negative side (the first main electrode plate 220 serving as the source) of at least the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (UU1, UU2) and the main electrode plate on the positive side (the second main electrode plate 230 serving as the drain) of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (UD1, UD2) are connected to the U terminal serving as the first output terminal via the U wiring 1814 serving as the first output wiring within the main substrate 1610. For the V phase, the main electrode plate on the negative side (the first main electrode plate 220 serving as the source) of at least the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (VU1, VU2) and the main electrode plate on the positive side (the second main electrode plate 230 serving as the drain) of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (VD1, VD2) are connected to the V terminal serving as the second output terminal via the V wiring 1815 serving as the second output wiring within the main substrate 1610. For the W phase, the main electrode plate on the negative side of the first main electrode plate 220 and the second main electrode plate 230 of at least the first semiconductor device 200 (WU1, WU2) (the first main electrode plate 220 serving as the source) and the main electrode plate on the positive side of the first main electrode plate 220 and the second main electrode plate 230 of at least one second semiconductor device 200 (WD1, WD2) (the second main electrode plate 230 serving as the drain) are connected to the U terminal serving as the first output terminal via the W wiring 1816 serving as the third output wiring within the main substrate 1610.

[0169] The P wiring 1812, the N wiring 1813, the U wiring 1814, the V wiring 1815, and the W wiring 1816 are arranged in the main wiring area of ​​the main substrate 1610 corresponding to the column of the first semiconductor device 200 of the U phase, the V phase, and the W phase to the column of the second semiconductor device 200 of the U phase, the V phase, and the W phase in a plan view. Here, in the case where the control electrode plate 240 of each semiconductor device 200 is arranged on the opposite side to the opposing semiconductor device 200, the main wiring area may be an area including the first main electrode plate 220 and the second main electrode plate 230 of the semiconductor device 200. In contrast, most of the control wirings such as the control device 1620 and the control wirings from the control device to the control electrode plate 240 and the sub-electrode plate 250 of each semiconductor device 200 are arranged in the control wiring area that is distinguished from the main wiring area. As a result, the semiconductor module 1800 can suppress the increase of noise in the control device and the control wiring in the control wiring area due to the large current flowing in the main wiring arranged in the main wiring area.

[0170] It should be noted that the semiconductor module 800 may have the connection structure of each wiring of this modification instead of Fig.10The connection structure of each wiring shown. Figures 16-17 The semiconductor module 1600 shown may have a connection structure of each wiring in which the number of semiconductor devices 200 in each arm of each phase is set to one in this figure (i.e., a structure obtained by removing the semiconductor devices 200 of UU2, UD2, VU2, VD2, WU2 and WD2 from the semiconductor module 1800).

[0171] Fig.19 FIG. 1 shows the connection of each wiring in a semiconductor module 1900 according to a fourth modification of the present embodiment. Fig.18 The semiconductor module 1800 shown is a modification example, and therefore descriptions thereof are omitted except for the following differences.

[0172] In the semiconductor module 1900, each semiconductor device as the lower arm includes a semiconductor device 1500 instead of the semiconductor device 200. The second main electrode plate 230 on the positive side of each first semiconductor device 200 is connected to the P terminal via the P wiring 1912 in the main substrate 1610, similarly to the semiconductor module 1800. Since the main electrode plate on the negative side of each second semiconductor device 1500 is the second main electrode plate 1530, the second main electrode plate 1530 of each second semiconductor device 1500 is connected to the N terminal via the N wiring 1913. Since the main electrode plate on the positive side of each second semiconductor device 1500 is the first main electrode plate 1520, the first main electrode plate 1520 of each second semiconductor device 1500 is connected to the first main electrode plate 220 and the U terminal, V terminal, or W terminal of the corresponding first semiconductor device 200 via the U wiring 1914, the V wiring 1915, or the W wiring 1916.

[0173] According to this modification, the upper and lower arms are formed by using the semiconductor device 1500 and the semiconductor device 200 whose main electrode plates have polarities different from those of the semiconductor device 200, so that the output wirings such as the U wiring 1914, the V wiring 1915, and the W wiring 1916 only need to connect the opposing first main electrode plate 220 and the first main electrode plate 1520. Therefore, according to this modification, the wiring length from the P wiring to the N wiring via the semiconductor devices of the upper and lower arms can be further shortened.

[0174] Fig. 20 A semiconductor module 2000 according to a fifth modification of the present embodiment is shown. Figures 16-17 The semiconductor module 1600 shown in FIG. 1 is a modified example, and therefore description thereof is omitted except for the following differences. Figures 8-9 The semiconductor module 800 shown, Fig.18 The semiconductor module 1800 and Fig.19The semiconductor module 1900 shown in the figure is modified in the same manner as in the present variation. The semiconductor module 2000 includes one or more semiconductor devices 200 , a main substrate 2010 , one or more control devices 2020 , and one or more control connectors 2050 .

[0175] The semiconductor module 2000 of this modification has a structure equivalent to the upper and lower arms of a phase in the converter device. The semiconductor module 2000 has four semiconductor devices 200 allocated to the upper arm and four semiconductor devices 200 allocated to the lower arm. Alternatively, the semiconductor module 2000 may also have a number other than 4 (1, 2, 3, or any number greater than 5) of semiconductor devices 200 in each of the upper and lower arms. Figures 16-17 The semiconductor module 1600 shown in the figure similarly adopts a structure in which a plurality of semiconductor devices 200 are sandwiched between a main substrate 2010 and a heat sink (not shown) on the back side of the figure. Fig. 20 , the plurality of semiconductor devices 200 are not shown. It should be noted that the semiconductor module 2000 may be configured as an example in which a part of the semiconductor devices 200 is replaced with the semiconductor device 1500 as in the semiconductor module 1900 .

[0176] The main substrate 2010 corresponds to the main substrate 1610 in the semiconductor module 1600. On the back side of the main substrate 2010, the four semiconductor devices 200 (first semiconductor devices 200) of the upper arm are arranged in a row on the right side of the four first control devices 2020a in the figure when viewed from above, and the four semiconductor devices 200 (second semiconductor devices 200) of the lower arm are arranged in a row on the left side of the four second control devices 2020b in the figure when viewed from above.

[0177] The main substrate 2010 has a P terminal and an N terminal near the upper side in the figure on the front side. In addition, the main substrate 2010 has an output terminal near the side on the front side opposite to the side on which the P terminal and the N terminal are provided. The output terminal can be used as a U terminal, a V terminal, a W terminal or other terminals. The P wiring between the P terminal and each semiconductor device 200 of the upper arm, the N wiring between the N terminal and each semiconductor device 200 of the lower arm, and the output wiring between the output terminal and each semiconductor device 200 are arranged in the main wiring area corresponding to the four semiconductor devices 200 of the upper arm (equivalent to the right side of the four control devices 2020a in the figure) to the four semiconductor devices 200 of the lower arm (equivalent to the left side of the four control devices 2020b in the figure) in the main substrate 2010 when viewed from above, and extend in the up and down direction in the figure.

[0178] A plurality of control devices 2020 are mounted on the front surface of the main substrate 2010. The control devices 2020 correspond to the control devices 1620 in the semiconductor module 1600. In this modification, four control devices 2020a (first control devices 2020a) control each of the four first semiconductor devices 200 of the upper arm. The four first control devices 2020a are arranged in the first control wiring area on the front surface of the main substrate 2010, which is in contact with the four first semiconductor devices 200 of the upper arm relative to the main wiring area when viewed from above, and are arranged along the vertical direction in the figure. Four control devices 2020b (second control devices 2020b) control each of the four second semiconductor devices 200 of the lower arm. The four second control devices 2020b are arranged in the second control wiring area on the front surface of the main substrate 2010, which is in contact with the four second semiconductor devices 200 of the lower arm relative to the main wiring area when viewed from above, and are arranged along the vertical direction in the figure.

[0179] A plurality of control connectors 2050 are mounted on the front surface of the main substrate 2010 and are electrically connected to a plurality of control devices 2020. The control connector 2050 corresponds to the control connector 1650 in the semiconductor module 1600. In this variation, the first control connector 2050a is arranged in the first control wiring area on the front surface of the main substrate 2010 and is electrically connected to each first control device 2020a. The second control connector 2050b is arranged in the second control wiring area on the front surface of the main substrate 2010 and is electrically connected to each second control device 2020b.

[0180] A converter device having multiple phases can be implemented by installing semiconductor modules 2000 corresponding to the number of phases. For example, a three-phase converter device is implemented by connecting a semiconductor module 2000 for U phase, a semiconductor module 2000 for V phase, and a semiconductor module 2000 for W phase in parallel. These multiple semiconductor modules 2000 can be arranged horizontally in the figure. Alternatively, a converter device having multiple phases can also be implemented by using the semiconductor module 2000 shown in this figure as a basic block and using one main substrate to install the basic blocks of multiple phase quantities.

[0181] Fig.21 The semiconductor module 2100 and the thin film capacitor 2180 of the sixth modification of the present embodiment are shown together. Figures 16-17 The semiconductor module 1600 shown in FIG. 1 is a modified example, and therefore the description thereof is omitted except for the following differences. Figures 8-9 The semiconductor module 800 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, and Fig. 20The semiconductor module 2000 shown in the figure is subjected to the same changes as those in the present modification. The semiconductor module 2100 includes one or more semiconductor devices 200 , a main substrate 2110 , one or more control devices 2120 , and one or more control connectors 2150 .

[0182] The semiconductor module 2100 of this variation is a converter device similar to the semiconductor module 1600. In the example of this figure, the semiconductor module 2100 is a three-phase converter, and each phase has four semiconductor devices 200 allocated to the upper arm and four semiconductor devices 200 allocated to the lower arm. Therefore, the semiconductor module 2100 has 24 (=3 phases×(4 upper arms+4 lower arms)) semiconductor devices 200. Figures 16-17 The semiconductor module 1600 shown in the figure similarly adopts a structure in which a plurality of semiconductor devices 200 are sandwiched between a main substrate 2110 and a heat sink (not shown) on the back side of the figure. Fig.21 , the plurality of semiconductor devices 200 are not shown. It should be noted that the semiconductor module 2100 may be configured as an example in which a part of the semiconductor devices 200 are replaced with the semiconductor devices 1500 as in the semiconductor module 1900 .

[0183] The main substrate 2110 corresponds to the main substrate 1610 in the semiconductor module 1600. On the back side of the main substrate 2110, the twelve semiconductor devices 200 (first semiconductor devices 200) of the upper arm are arranged in a row on the right side of the twelve first control devices 2120a in the figure, and the twelve semiconductor devices 200 (second semiconductor devices 200) of the lower arm are arranged in a row on the left side of the twelve second control devices 2020b in the figure.

[0184] The main substrate 2110 has a P terminal and an N terminal near the upper side in the figure on the front side. In addition, the main substrate 2110 has output terminals of a U terminal, a V terminal, and a W terminal near the side on the front side opposite to the side on which the P terminal and the N terminal are provided. The P wiring between the P terminal and each semiconductor device 200 of the upper arm, the N wiring between the N terminal and each semiconductor device 200 of the lower arm, and the output wiring between each output terminal and the corresponding semiconductor device 200 are arranged in a main wiring area corresponding to the right side of the twelve control devices 2120a and the left side of the twelve control devices 2120b in the main substrate 2110, extending in the up-down direction in the figure. The semiconductor module 2100 can be adopted by Fig.18 Semiconductor module 1800 or Fig.19 The semiconductor module 1900 has a structure in which the number of semiconductor devices in each arm of each phase is increased from two to four.

[0185] A plurality of control devices 2120 are mounted on the front surface of the main substrate 2110. The control devices 2120 correspond to the control devices 1620 in the semiconductor module 1600. In this modification, twelve control devices 2120a (first control devices 2120a) control each of the twelve first semiconductor devices 200 of the upper arm. The twelve first control devices 2120a are arranged in the first control wiring area on the front surface of the main substrate 2110, which is in contact with the twelve first semiconductor devices 200 of the upper arm relative to the main wiring area when viewed from above, and are arranged along the vertical direction in the figure. Twelve control devices 2120b (second control devices 2120b) control each of the twelve second semiconductor devices 200 of the lower arm. The twelve second control devices 2120b are arranged in the second control wiring area on the front surface of the main substrate 2010, which is in contact with the twelve second semiconductor devices 200 of the lower arm relative to the main wiring area when viewed from above, and are arranged along the vertical direction in the figure.

[0186] A plurality of control connectors 2150 are mounted on the front of the main substrate 2110 and are electrically connected to a plurality of control devices 2120. The control connector 2150 corresponds to the control connector 1650 in the semiconductor module 1600. In this variant, a first control connector 2150a is provided for each upper arm of each phase. Each first control connector 2150a is arranged in the first control wiring area on the front of the main substrate 2110, and is electrically connected to the four first control devices 2120a corresponding to each phase, respectively. A second control connector 2150b is provided for each lower arm of each phase. Each second control connector 2150b is arranged in the second control wiring area on the front of the main substrate 2110, and is electrically connected to the four first control devices 2120b corresponding to each phase, respectively.

[0187] The film capacitor 2180 can be connected to the semiconductor module 2100 at the side where the P terminal and the N terminal are provided in the semiconductor module 2100. The film capacitor 2180 can have substantially the same width as the semiconductor module 2100 (the horizontal length in the figure), or can have a width larger than the semiconductor module 2100 or a width smaller than the semiconductor module 2100. The film capacitor 2180 is electrically connected between the P terminal and the N terminal. The film capacitor 2180 is a capacitor having a larger capacity than a buffer capacitor such as the buffer capacitor 1640. The film capacitor 2180 stabilizes the potential of the P terminal and the N terminal of the semiconductor module 2100, and suppresses the fluctuation of the potential of the P terminal and the N terminal even when the magnitude of the current output from each output terminal changes significantly. The semiconductor module 2100 can be connected to a capacitor other than a film capacitor instead of the film capacitor 2180. Figures 8-9 The semiconductor module 800 shown, Figures 16-17The semiconductor module 1600 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, and Fig. 20 The semiconductor module 2000 shown may also have a capacitor such as a thin film capacitor 2180 connected between the P terminal and the N terminal.

[0188] Fig. 22 A semiconductor module 2200 according to a seventh variation of the present embodiment is shown. Fig.10 The semiconductor module 800 shown, Fig.18 The semiconductor module 1800 shown, and Fig.19 The present invention is a modification of the semiconductor module 1900 shown in FIG. 1 , and therefore description thereof is omitted except for the following differences. Fig. 20 The semiconductor module 2000 shown, and Fig.21 The semiconductor module 2100 shown in the figure is subjected to the same changes as those in the present modification. The semiconductor module 2200 includes a plurality of semiconductor devices 200 .

[0189] In this variation, at least one first semiconductor device 200 is arranged on the back side of a main substrate such as main substrate 810, main substrate 1610, main substrate 2010 or main substrate 2110, and each of the at least one second semiconductor device 200 and the corresponding second semiconductor device 200 is arranged along a direction orthogonal to the arrangement of the first main electrode plate 220, the second main electrode plate 230 and the control electrode plate 240 (the arrangement direction of the electrode plates in the semiconductor device 200). In the example of this figure, the first semiconductor device 200 on the upper side of the figure and the second semiconductor device 200 on the lower side of the figure are arranged along a direction orthogonal to the arrangement direction of each electrode plate.

[0190] The positive terminal of the semiconductor module 2200 is connected to the main electrode plate on the positive side of the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (in the example of this figure, the second main electrode plate 230 of the upper semiconductor device 200) via the positive wiring. The negative terminal of the semiconductor module 2200 is connected to the main electrode plate on the negative side of the first main electrode plate 220 and the second main electrode plate 230 of the second semiconductor device 200 (in the example of this figure, the first main electrode plate 220 of the lower semiconductor device 200) via the negative wiring. The output terminal of the semiconductor module 2200 is connected to the main electrode plate on the negative side of the first main electrode plate 220 and the second main electrode plate 230 of the first semiconductor device 200 (in the example of the present figure, the first main electrode plate 220 of the upper semiconductor device 200), and the main electrode plate on the positive side of the first main electrode plate 220 and the second main electrode plate 230 of the second semiconductor device 200 (in the example of the present figure, the second main electrode plate 230 of the lower semiconductor device 200) via output wiring.

[0191] In the semiconductor module 2200, the positive wiring, the negative wiring, and the output wiring extend in a direction in which at least one first semiconductor device 200 is arranged with a corresponding second semiconductor device 200 in at least one second semiconductor device 200. In the example of this figure, the positive wiring, the negative wiring, and the output wiring extend in the up-down direction in the figure.

[0192] In the example of this figure, the semiconductor module 2200 has one semiconductor device 200 in each arm. Alternatively, the semiconductor module 2200 may have two or more semiconductor devices 200 in each arm, and the semiconductor module 2200 may be configured so that two or more first semiconductor devices 200 and two or more second semiconductor devices 200 are arranged in a row along a direction orthogonal to the arrangement direction of the electrode plates. In addition, the semiconductor module 2200 may have one or more first semiconductor devices 200 and one or more second semiconductor devices 200 for each of the multiple phases, and the semiconductor module 2200 may be configured so that these semiconductor devices 200 are arranged in a row along a direction orthogonal to the arrangement direction of the electrode plates.

[0193] Fig.23 is a schematic diagram of a cross section of a semiconductor module 2300 according to an eighth variation of the present embodiment. Fig.16 The modified example of the semiconductor module 1600 shown in FIG. 1 has a cross-sectional structure of Figures 8 to 14 This is a modification of the semiconductor module 800 shown in FIG. 1 , and therefore the description thereof is omitted except for the following differences. Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, Fig. 20 The semiconductor module 2000 shown in FIG. Fig.21 The semiconductor module 2100 shown, and Fig. 22 The semiconductor module 2200 shown is subjected to the same changes as those of the present variation.

[0194] The semiconductor module 2300 may be Fig.11 In S1100, one or more semiconductor devices 200 are prepared, wherein the one or more semiconductor devices 200 are provided with a first main electrode plate 220, a second main electrode plate 230 and a control electrode plate 240 on one surface, and have a switching element having a first main electrode connected to the first main electrode plate 220, a second main electrode connected to the second main electrode plate 230, and a control electrode connected to the control electrode plate 240. A part of the semiconductor device may also be a semiconductor device 1500 instead of the semiconductor device 200.

[0195] In S1110, a main substrate 1610 having a first main electrode plate 220, a second main electrode plate 230, a sub-electrode plate 250, and a control electrode plate 240 connected to at least one semiconductor device 200 on the back is prepared. In this modification, the main substrate 1610 has at least one main substrate recess 2315 on the back, and the main substrate recess 2315 is used to bury at least a portion of the at least one semiconductor device 200. The main substrate 1610 may have a respective main substrate recess 2315 for each of all the semiconductor devices 200 mounted on the back of the main substrate 1610. Alternatively, the main substrate 1610 may also have a common main substrate recess 2315 for two or more semiconductor devices 200.

[0196] The main substrate recess 2315 may have a depth greater than the thickness of the semiconductor device 200 so that the entire semiconductor device 200 is contained in the recess. Alternatively, the main substrate recess 2315 may have a depth less than the thickness of the semiconductor device 200 so that only a portion of the semiconductor device 200 is contained in the recess and the remaining portion protrudes from the back side of the main substrate 1610.

[0197] In S1120, at least one control device 1620 is mounted on the front surface of the main substrate 810 by soldering the at least one control device 1620 on the front surface of the main substrate 1610. In this modification, the control device 1620 is arranged in a control wiring area, which is located on the semiconductor device 200 side of the connection target relative to the main wiring area, and the main wiring area is arranged with main wiring connected to the first main electrode plate 220 and the second main electrode plate 230 of the semiconductor device 200.

[0198] In S1130, at least one semiconductor device 200 is sandwiched between the back side of the main substrate 1610 and the heat sink 1630, and the electrode plates of the semiconductor device 200 are connected on the back side of the main substrate 1610. The first main electrode plate 220, the second main electrode plate 230, and the control electrode plate 240 of at least one semiconductor device 200 are connected to the main substrate 1610 at the bottom surface of at least one main substrate recess 2315. It should be noted that in S1120 and S1130, after the at least one semiconductor device 200 is connected to the back side of the main substrate 1610, the at least one control device 1620 may be mounted on the front side of the main substrate 1610.

[0199] Then, the heat sink 1630 is mounted on the back surface of the main substrate 1610 to which at least one semiconductor device 200 is connected. Thus, the heat sink 830 is mounted on the surface of each semiconductor device 200 on the opposite side from the main substrate 1610 .

[0200] A thermally conductive material 2390 may be provided in a part or the whole of the gap between the main substrate 1610 and the heat sink 1630 by embedding, coating, injecting or pasting. The thermally conductive material 2390 may be a paste-like thermal grease or filler, a thermally conductive sheet or heat sink, or any other TIM (Thermal Interface Material). The thermally conductive material 2390 can improve the thermal conductivity between the surface on the insulating substrate 500 side of the semiconductor device 200 (or the thermally conductive plate 1270) and the back side of the main substrate 1610 and the heat sink 1630, so that the semiconductor device 200 and the main substrate 1610 can be cooled more efficiently.

[0201] In addition, the main substrate 1610 is fixed to the heat sink 1630 by using at least one fixing member 1660 of thermal conductivity that penetrates the plate-shaped member of the heat sink 1630 from the front of the main substrate 1610 and reaches at least one protruding member 1670. As an example, each fixing member 1660 can be a screw, and each protruding member 1670 can have a screw hole for fitting the screw. The fixing member 1660 and the protruding member 1670 can be made of metal such as copper, aluminum, iron or stainless steel. Thus, the fixing member 1660 for fixing the heat sink 1630 to the main substrate 1610 can transfer the heat from the main substrate 1610 to the protruding member 1670, and the protruding member 1670 can release the heat from the fixing member 1660 to the refrigerant. Therefore, the fixing member 1660 and the protruding member 1670 can improve the cooling performance of the main substrate 1610.

[0202] Fig.24 is a schematic diagram of a cross section of a semiconductor module 2400 according to a ninth variation of the present embodiment. Fig.23This is a modification of the semiconductor module 2300 shown in FIG. 1 , and therefore description thereof is omitted except for the following differences. Figures 8 to 14 The semiconductor module 800 shown, Fig.16 The semiconductor module 1600 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, Fig. 20 The semiconductor module 2000 shown in FIG. Fig.21 The semiconductor module 2100 shown, and Fig. 22 The semiconductor module 2200 shown is subjected to the same changes as those of the present variation.

[0203] In this modification, the main substrate 1610 does not have the main substrate recess 2315, and has at least one heat sink recess 2410 on the surface of the heat sink 1630 on the side of at least one semiconductor device 200, and at least one heat sink recess 2410 is used to bury at least a part of the at least one semiconductor device 200. The heat sink 1630 may have a heat sink recess 2410 for each of all the semiconductor devices 200 mounted on the back side of the main substrate 1610. Alternatively, the heat sink 1630 may also have a common heat sink recess 2410 for two or more semiconductor devices 200. The heat sink recess 2410 may also have a depth less than the thickness of the semiconductor device 200, and only a part of the semiconductor device 200 is accommodated in the recess, and the remaining part protrudes from the upper surface of the heat sink 1630 in the figure. Alternatively, the heat sink recess 2410 may have a depth of about the thickness of the semiconductor device 200 to accommodate the entire semiconductor device 200 in the recess.

[0204] The heat conductive material 2390 may be in the form of a paste or a fluid, and may be filled into the heat sink recess 2410. One or more grooves may be formed on the bottom surface of the heat sink recess 2410, extending from the bottom of the semiconductor device 200 to the surroundings. One or more grooves may be formed in a manner that extends over the side of the heat sink recess 2410. Thus, if the heat sink 1630 is pressed against the main substrate 1610 in order to fix the heat sink 1630 to the main substrate 1610, excess heat conductive material 2390 flows out from the bottom of the semiconductor device 200 to the surroundings through the plurality of grooves. Thus, the semiconductor module 2400 can make the heat sink 1630 more closely attached to the semiconductor device 200.

[0205] The semiconductor module 2400 can reduce the gap between the main substrate 1610 and the heat sink 1630 and improve the cooling efficiency of the main substrate 1610 by having the heat sink recess 2410 on the heat sink 1630 side. It should be noted that the main substrate 1610 of the semiconductor module 2400 can further have a main substrate recess 2315, and the semiconductor device 200 can be accommodated between the main substrate recess 2315 and the heat sink recess 2410.

[0206] Fig.25 2 is a schematic diagram of a cross section of a semiconductor module 2500 according to a tenth variation of the present embodiment. Fig.24 The semiconductor module 2400 shown in FIG. 1 is a modified example, and therefore description thereof is omitted except for the following differences. Figures 8 to 14 The semiconductor module 800 shown, Fig.16 The semiconductor module 1600 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, Fig. 20 The semiconductor module 2000 shown in FIG. Fig.21 The semiconductor module 2100 shown, and Fig. 22 The semiconductor module 2200 shown is subjected to the same changes as those of the present variation.

[0207] In this modification, the thermally conductive material 2390 is provided only near or around each semiconductor device 200 in the gap between the main substrate 1610 and the heat sink 1630. In the example of this figure, the thermally conductive material 2390 is filled in the heat sink recess 2410 and covers the surface and side surface of the semiconductor device 200 on the heat sink 1630 side. Thus, the semiconductor module 2500 can improve the cooling efficiency of the semiconductor device 200.

[0208] Fig.26 2 is a schematic diagram of a cross section of a semiconductor module 2600 according to an eleventh variation of the present embodiment. Fig.23 This is a modification of the semiconductor module 2300 shown in FIG. 1 , and therefore description thereof is omitted except for the following differences. Figures 8 to 14 The semiconductor module 800 shown, Fig.16 The semiconductor module 1600 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, Fig. 20 The semiconductor module 2000 shown in FIG. Fig.21 The semiconductor module 2100 shown, and Fig. 22 The semiconductor module 2200 shown is subjected to the same changes as those of the present variation.

[0209] In this variation, the main substrate 1610 does not have the main substrate recess 2315, and the heat sink 1630 has at least one heat sink protrusion 2620 on the surface on the side of at least one semiconductor device 200, at a position corresponding to at least one semiconductor device 200. The heat sink 1630 may have a heat sink protrusion 2620 for each of all semiconductor devices 200 mounted on the back side of the main substrate 1610. Alternatively, the heat sink 1630 may have a common heat sink protrusion 2620 for two or more semiconductor devices 200.

[0210] One or more grooves extending from the bottom of the semiconductor device 200 to the surroundings may be formed on the upper surface of the heat sink protrusion 2620. Thus, when the heat sink 1630 is pressed against the main substrate 1610 in order to fix the heat sink 1630 to the main substrate 1610, the excess thermal conductive material 2390 flows out from the bottom of the semiconductor device 200 to the surroundings through the plurality of grooves. Thus, the semiconductor module 2600 can make the heat sink 1630 more closely attached to the semiconductor device 200.

[0211] The semiconductor module 2600 has a heat sink protrusion 2620 on the heat sink 1630 side, which can reduce the gap between the semiconductor device 200 and the heat sink 1630 and improve the cooling efficiency of the semiconductor device 200. It should be noted that the main substrate 1610 of the semiconductor module 2600 may further have a main substrate recess 2315 and accommodate at least a portion of the semiconductor device 200. In addition, the main substrate 1610 may also have a main substrate protrusion at a position where each semiconductor device 200 is connected.

[0212] Fig. 27 is a schematic diagram of a cross section of a semiconductor module 2700 according to a twelfth variation of the present embodiment. Fig.26 The semiconductor module 2600 shown in FIG. 1 is a modified example, and therefore the description thereof is omitted except for the following differences. Figures 8 to 14 The semiconductor module 800 shown, Fig.16 The semiconductor module 1600 shown, Fig.18 The semiconductor module 1800 shown, Fig.19 The semiconductor module 1900 shown, Fig. 20 The semiconductor module 2000 shown in FIG. Fig.21 The semiconductor module 2100 shown, and Fig. 22 The semiconductor module 2200 shown is subjected to the same changes as those of the present variation.

[0213] In this modification, the thermal conductive material 2390 is provided only near or around each semiconductor device 200 in the gap between the main substrate 1610 and the heat sink 1630. In the example of this figure, the thermal conductive material 2390 is disposed on the heat sink protrusion 2620 by coating or the like, and covers the surface and side surfaces of the semiconductor device 200 on the heat sink 1630 side. Thus, the semiconductor module 2700 can improve the cooling efficiency of the semiconductor device 200.

[0214] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It can be clearly known from the description of the claims that such changes or improvements can also be included in the technical scope of the present invention.

[0215] It should be noted that the execution order of the actions, sequences, steps, stages, etc. in the devices, systems, programs, and methods shown in the claims, specifications, and drawings can be implemented in any order unless it is specifically stated that "before...", "prior to...", etc., and the output of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in this order.

[0216] According to this specification, each aspect shown below is also disclosed.

[0217] In a first embodiment, a semiconductor device is provided, comprising: a switching element having a first main electrode and a control electrode on one surface and a second main electrode on an opposite surface; and a mounting substrate having a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode on the mounting surface of the switching element, and a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode in an area of ​​the mounting surface of the switching element where no switching element is configured.

[0218] The semiconductor device may include a sealing portion that covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

[0219] In any of the above-mentioned semiconductor devices, on the mounting surface of the switching element in the mounting substrate, the switching element may be arranged between the first main electrode plate and the control electrode plate.

[0220] In any of the above semiconductor devices, the first main electrode wiring may have a plurality of bumps in contact with the first main electrode, and the control wiring may have a plurality of bumps in contact with the control electrode.

[0221] In any of the semiconductor devices described above, the mounting substrate may include an insulating substrate, and a first main electrode wiring, a first main electrode plate, a control wiring, and a control electrode plate formed on the insulating substrate.

[0222] In any of the above-mentioned semiconductor devices, the mounting substrate may include a heat conduction plate formed on a surface of the insulating substrate opposite to the mounting surface.

[0223] In any of the above semiconductor devices, the mounting substrate may further include a sub wiring connected to the first main electrode on the mounting surface of the switching element, and may include a sub electrode plate connected to the sub wiring in a region of the mounting surface of the switching element where no switching element is arranged.

[0224] In any of the above semiconductor devices, the switching element may be a power MOSFET, an IGBT, or a HEMT.

[0225] In any of the above-mentioned semiconductor devices, the switching element may be a Si semiconductor and / or a SiC semiconductor element or a GaN semiconductor element.

[0226] In a second embodiment, a semiconductor module is provided, comprising: at least one semiconductor device; a main substrate having a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate connected to the back side of the at least one semiconductor device; and a heat sink in contact with a surface of the at least one semiconductor device on the opposite side of the main substrate.

[0227] In the above-mentioned semiconductor module, the main substrate may have a terminal on the front side connected to the first main electrode plate of at least one semiconductor device via wiring in the main substrate, and a terminal connected to the second main electrode or the second main electrode plate via wiring in the main substrate.

[0228] Any of the above-mentioned semiconductor modules may include at least one control device mounted on the front surface of the main substrate and controlling at least one semiconductor device.

[0229] Any of the semiconductor modules described above is a converter device, and the at least one semiconductor device may include a plurality of semiconductor devices respectively allocated to upper arms and lower arms of each of the one or more phases.

[0230] In any of the above-mentioned semiconductor modules, each semiconductor device among the multiple semiconductor devices allocated to the upper arm of each phase can be arranged in a row on the back side of the main substrate, and each semiconductor device among the multiple semiconductor devices allocated to the lower arm of each phase can be arranged in a row side by side with the row of each semiconductor device allocated to the upper arm of each phase on the back side of the main substrate.

[0231] On the back side of the main substrate in any of the above-mentioned semiconductor modules, each semiconductor device allocated to the upper arm of each phase can be arranged with the first main electrode plate located on the side of the semiconductor device allocated to the opposite lower arm among the multiple semiconductor devices. On the back side of the main substrate, each semiconductor device allocated to the lower arm of each phase can be arranged with the first main electrode plate located on the side of the semiconductor device allocated to the opposite upper arm among the multiple semiconductor devices.

[0232] In a third aspect, a manufacturing method is provided, comprising: a step of preparing a switching element having a first main electrode and a control electrode on one surface and a second main electrode on an opposite surface; a step of making a mounting substrate having a first main electrode wiring and a control wiring on a mounting surface on which the switching element is to be mounted; a step of mounting the switching element on the mounting surface of the mounting substrate on which the switching element is to be mounted by joining the first main electrode to the first main electrode wiring and joining the control electrode to the control wiring; and a step of joining the first main electrode plate connected to the first main electrode wiring and the control electrode plate connected to the control electrode to an area on which no switching element is configured on the mounting surface of the mounting substrate on which the switching element is to be mounted.

[0233] The above-mentioned manufacturing method may also include a step of sealing based on a sealing material in a manner that covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side, and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

[0234] Any of the above-mentioned manufacturing methods may include: the steps of preparing a main substrate having a first main electrode plate, a second main electrode or a second main electrode plate connected to the second main electrode, and a control electrode plate connected to at least one semiconductor device on the back side; the step of connecting at least one semiconductor device on the back side of the main substrate; and the step of installing a heat sink on the surface of at least one semiconductor device on the opposite side of the main substrate.

[0235] Any of the above-mentioned manufacturing methods may include the step of mounting at least one control device for controlling at least one semiconductor device on the front surface of the main substrate.

Claims

1. A semiconductor device, characterized in that: have: a switching element having a first main electrode and a control electrode on one face and a second main electrode on an opposite face; and A mounting substrate having a first main electrode wiring connected to the first main electrode and a control wiring connected to the control electrode on a mounting surface of the switching element, and a first main electrode plate connected to the first main electrode wiring and a control electrode plate connected to the control electrode in an area of ​​the mounting surface of the switching element where the switching element is not configured.

2. The semiconductor device according to claim 1, wherein: The semiconductor device also includes a sealing portion, which covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side, and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

3. The semiconductor device according to claim 1 or 2, characterized in that: The switching element is arranged between the first main electrode plate and the control electrode plate on the mounting surface of the mounting substrate on which the switching element is mounted.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first main electrode wiring has a plurality of bumps in contact with the first main electrode, The control wiring has a plurality of bumps in contact with the control electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that The mounting substrate comprises: Insulating substrate; as well as The first main electrode wiring, the first main electrode plate, the control wiring, and the control electrode plate are formed on an insulating substrate.

6. The semiconductor device according to claim 5, characterized in that The mounting substrate includes a heat conducting plate formed on a surface of the insulating substrate opposite to the mounting surface.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that The mounting substrate further includes a sub wiring connected to the first main electrode on a mounting surface of the switching element, and includes a sub electrode plate connected to the sub wiring in a region of the mounting surface of the switching element where the switching element is not arranged.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that The switch element is a power MOSFET or an IGBT.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that The switching element is a SiC semiconductor element.

10. A semiconductor module, characterized in that: have: At least one semiconductor device according to any one of claims 1 to 9; a main substrate, on the back of which the first main electrode plate of the at least one semiconductor device, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate are connected; as well as A heat sink is in contact with a surface of the at least one semiconductor device on the opposite side from the main substrate.

11. The semiconductor module according to claim 10, characterized in that The main substrate has a terminal on the front surface connected to the first main electrode plate of the at least one semiconductor device via wiring in the main substrate, and a terminal connected to the second main electrode or the second main electrode plate via wiring in the main substrate.

12. The semiconductor module according to claim 10 or 11, characterized in that The semiconductor module further includes at least one control device mounted on the front surface of the main substrate and controlling the at least one semiconductor device.

13. The semiconductor module according to any one of claims 10 to 12, characterized in that The semiconductor module is a converter device. The at least one semiconductor device includes a plurality of semiconductor devices respectively allocated to upper arms and lower arms of each of the one or more phases.

14. The semiconductor module according to claim 13, characterized in that The semiconductor devices allocated to the upper arms of the respective phases among the plurality of semiconductor devices are arranged in a row on the back side of the main substrate. The semiconductor devices allocated to the lower arms of the phases among the plurality of semiconductor devices are arranged in a row on the back surface of the main substrate in parallel with the rows of the semiconductor devices allocated to the upper arms of the phases.

15. The semiconductor module according to claim 14, characterized in that On the back side of the main substrate, the semiconductor devices allocated to the upper arms of the respective phases are arranged in such a manner that the first main electrode plate is located on the side of the semiconductor devices allocated to the opposite lower arms among the plurality of semiconductor devices. On the back surface of the main substrate, the semiconductor devices allocated to the lower arms of the respective phases are arranged in an orientation such that the first main electrode plate is located on the side of the semiconductor devices allocated to the opposing upper arms among the plurality of semiconductor devices.

16. A manufacturing method, characterized in that: include: The step of preparing a switching element having a first main electrode and a control electrode on one face and a second main electrode on an opposite face; A step of manufacturing a mounting substrate having a first main electrode wiring and a control wiring on a mounting surface where the switching element is to be mounted; a step of mounting the switching element on a mounting surface of the mounting substrate on which the switching element is to be mounted by bonding the first main electrode to the first main electrode wire and bonding the control electrode to the control wire; as well as The step of bonding a first main electrode plate connected to the first main electrode wire and a control electrode plate connected to the control electrode to a region where the switching element is not arranged on a mounting surface of the mounting substrate where the switching element is to be mounted.

17. The manufacturing method according to claim 16, characterized in that: The manufacturing method also includes a step of performing sealing based on a sealing material in a manner that covers the mounting surface of the switching element in the mounting substrate and the surface of the switching element on the mounting substrate side, and exposes the first main electrode plate, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate.

18. The manufacturing method according to claim 16 or 17, characterized in that: The manufacturing method further comprises: The step of preparing a main substrate having the first main electrode plate connected to at least one semiconductor device on the back side, the second main electrode or the second main electrode plate connected to the second main electrode, and the control electrode plate; The step of connecting the at least one semiconductor device on the back side of the main substrate; and A step of mounting a heat sink on a surface of the at least one semiconductor device on the opposite side from the main substrate.

19. The manufacturing method according to claim 18, characterized in that: The manufacturing method further includes the step of mounting at least one control device for controlling the at least one semiconductor device on the front surface of the main substrate.

20. A semiconductor module, characterized in that: have: at least one semiconductor device, which has a first main electrode plate, a second main electrode plate and a control electrode plate provided on one surface, and has a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate; a main substrate, on the back of which the first main electrode plate, the second main electrode plate and the control electrode plate of the at least one semiconductor device are connected; as well as A heat sink is arranged on the back side of the main substrate to which the at least one semiconductor device is connected.

21. The semiconductor module according to claim 20, characterized in that The main substrate has at least one main substrate recess on the back side, and at least a part of the at least one semiconductor device is buried in the at least one main substrate recess. The first main electrode plate, the second main electrode plate, and the control electrode plate of the at least one semiconductor device are connected to the main substrate at the bottom surface of the at least one recessed portion of the main substrate.

22. The semiconductor module according to claim 20 or 21, characterized in that A thermally conductive material is provided in at least a portion of a gap between the main substrate and the heat sink.

23. The semiconductor module according to claim 20, characterized in that The heat sink has at least one heat sink protrusion on a surface on the at least one semiconductor device side at a position corresponding to the at least one semiconductor device.

24. The semiconductor module according to any one of claims 20 to 22, characterized in that The heat sink has at least one heat sink recess on a surface on the at least one semiconductor device side, and at least a portion of the at least one semiconductor device is buried in the at least one heat sink recess.

25. The semiconductor module according to any one of claims 20 to 22, characterized in that The radiator has: a plate-shaped member having a surface close to the main substrate and the at least one semiconductor device; and at least one protruding member provided on a surface of the plate-like member opposite to the main substrate and the at least one semiconductor device side, The main substrate is fixed to the heat sink by at least one thermally conductive fixing member that passes through the plate-shaped member of the heat sink from the front surface of the main substrate and reaches the at least one protruding member.

26. The semiconductor module according to claim 25, characterized in that The at least one fixing component is a screw, The at least one protruding member has a screw hole into which the screw is fitted.

27. The semiconductor module according to any one of claims 20 to 26, characterized in that The at least one semiconductor device includes at least one first semiconductor device and at least one second semiconductor device, The negative-side main electrode plates of the first and second main electrode plates of each of the at least one first semiconductor device are electrically connected to the positive-side main terminal plates of the first and second main electrode plates of the corresponding second semiconductor device of the at least one second semiconductor device.

28. The semiconductor module according to any one of claims 20 to 26, characterized in that The at least one semiconductor device has a structure in which the second main electrode plate is arranged between the first main electrode plate and the control electrode plate on one surface.

29. The semiconductor module according to claim 28, characterized in that On the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are arranged in an orientation such that the first main electrode plates face each other.

30. The semiconductor module according to claim 28, characterized in that On the back surface of the main substrate, each of the at least one first semiconductor device and a corresponding second semiconductor device among the at least one second semiconductor device are arranged in an orientation such that the first main electrode plate and the control electrode plate face each other.

31. The semiconductor module according to any one of claims 28 to 30, characterized in that The main substrate comprises: a positive terminal connected to a positive-side main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via a positive wiring in the main substrate; a negative electrode terminal connected to a negative electrode side main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via a negative electrode wiring in the main substrate; as well as an output terminal connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via output wiring in the main substrate, The positive wiring, the negative wiring, and the output wiring are provided in a main wiring region of the main substrate corresponding to a region from the at least one first semiconductor device to the at least one second semiconductor device in a plan view.

32. The semiconductor module according to claim 31, characterized in that have: The first and second at least one first semiconductor devices are arranged in a row on the back side of the main substrate; The first and second at least one second semiconductor devices are arranged in a row side by side with the first and second at least one first semiconductor devices on the back side of the main substrate; The first output terminal is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the first at least first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the first at least second semiconductor device via the first output wiring in the main substrate; as well as The second output terminal is connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the second at least first semiconductor device, and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the second at least second semiconductor device via the second output wiring in the main substrate, The positive wiring, the negative wiring, the first output wiring and the second output wiring are arranged in a main wiring area of ​​the main substrate corresponding to between the columns of the first and second at least one first semiconductor device and the columns of the first and second at least one second semiconductor device when viewed from above.

33. The semiconductor module according to claim 31, characterized in that have: at least one first control device mounted on the front surface of the main substrate and electrically connected to at least one control electrode plate in the at least one first semiconductor device; and at least one second control device mounted on the front side of the main substrate and electrically connected to at least one control electrode plate in the at least one second semiconductor device, The at least one first control device is arranged in a first control wiring region on the at least one first semiconductor device side relative to the main wiring region in a plan view, The at least one second control device is arranged in a second control wiring region on the at least one second semiconductor device side relative to the main wiring region in a plan view.

34. The semiconductor module according to claim 33, characterized in that have: A first control connector, which is arranged in the first control wiring area on the front side of the main substrate and is electrically connected to the at least one first control device; as well as The second control connector is arranged in the second control wiring area on the front surface of the main substrate and is electrically connected to the at least one second control device.

35. The semiconductor module according to any one of claims 31 to 34, characterized in that The semiconductor module includes at least one buffer capacitor disposed in the main wiring region on the front surface of the main substrate.

36. The semiconductor module according to claim 28, characterized in that On the back side of the main substrate, each of the at least one first semiconductor device and the corresponding second semiconductor device of the at least one second semiconductor device are configured to be arranged along a direction orthogonal to the arrangement of the first main electrode plate, the second main electrode plate and the control electrode plate.

37. The semiconductor module according to claim 36, characterized in that The main substrate comprises: a positive terminal connected to a positive-side main electrode plate of the first main electrode plate and the second main electrode plate of the at least one first semiconductor device via a positive wiring in the main substrate; a negative electrode terminal connected to a negative electrode side main electrode plate of the first main electrode plate and the second main electrode plate of the at least one second semiconductor device via a negative electrode wiring in the main substrate; as well as an output terminal connected to the main electrode plate on the negative side of the first main electrode plate and the second main electrode plate of the at least first semiconductor device and the main electrode plate on the positive side of the first main electrode plate and the second main electrode plate of the at least second semiconductor device via output wiring in the main substrate, The positive wiring, the negative wiring, and the output wiring extend along a direction in which each of the at least one first semiconductor device is aligned with a corresponding second semiconductor device of the at least one second semiconductor device.

38. A manufacturing method, characterized in that: include: The step of preparing at least one semiconductor device, wherein the at least one semiconductor device is provided with a first main electrode plate, a second main electrode plate and a control electrode plate on one surface, and has a switching element in which a first main electrode is connected to the first main electrode plate, a second main electrode is connected to the second main electrode plate, and a control electrode is connected to the control electrode plate; A step of preparing a main substrate having the first main electrode plate, the second main electrode plate and the control electrode plate connected to the back side of the at least one semiconductor device; The step of connecting the at least one semiconductor device on the back side of the main substrate; as well as The step of mounting a heat sink on the back surface of the main substrate to which the at least one semiconductor device is connected.

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