Nonvolatile memory cell and nonvolatile semiconductor memory device

Abstract

The invention provides a nonvolatile memory cell and a nonvolatile semiconductor memory device capable of realizing integration and miniaturization. In a nonvolatile semiconductor memory device, a memory cell (C) obtained by connecting a memory transistor (MT), a drain-side selection transistor (DT), and a source-side selection transistor (ST) in series can have a three-dimensional structure, and by having the memory cell (C) have a three-dimensional structure, integration and miniaturization of the memory cell (C) can be achieved without being restricted by two-dimensional scaling.

Description

Technical Field

[0001] The present invention relates to a nonvolatile memory cell and a nonvolatile semiconductor storage device. Background Art

[0002] In non-patent document 1, a semiconductor storage device is disclosed in which a plurality of non-volatile memory cells are formed at a predetermined interval along the axial direction of a gate electrode, wherein the plurality of non-volatile memory cells share: a cylindrical gate electrode, and a circular ring-shaped multi-layer insulating layer including a charge storage layer which is arranged circumferentially on the side surface of the gate electrode. In this non-patent document 1, a predetermined interval is arranged along the axial direction of the gate electrode, a polysilicon layer is arranged around the gate insulating layer, and source lines and bitlines are connected to each polysilicon layer in each layer in parallel in a direction orthogonal to the axial direction of the gate electrode, thereby realizing a three-dimensional structure of the non-volatile memory cell. Prior art literature Non-patent literature

[0003] Non-patent document 1: Yoohyun Noh et al., Synaptic Devices Based on 3-D ANDFlash Memory Architecture for Neuromorphic Computing, in IEEE 11thInternational Memory Workshop (IMW) (2019) Summary of the invention Problems to be solved by the invention

[0004] Thus, in recent years, it has been desired to provide a nonvolatile memory cell with a three-dimensional structure, to integrate the nonvolatile memory cell without being restricted by two-dimensional scaling, and to achieve miniaturization.

[0005] The present invention has been made in view of the above problems, and an object of the present invention is to provide a nonvolatile memory cell and a nonvolatile semiconductor storage device that can be integrated and miniaturized. Means for solving problems

[0006] The nonvolatile memory cell of the present invention comprises: a drain diffusion layer, a source diffusion layer, one or more columnar memory gate electrodes, a columnar drain side selection gate electrode, a columnar source side selection gate electrode, a multi-layer insulation layer, a drain side selection gate insulation layer, a source side selection gate insulation layer and a semiconductor layer, wherein the drain diffusion layer is extended along the surface direction of the substrate and is electrically connected to a bit line; the source diffusion layer is extended along the surface direction in parallel with the drain diffusion layer and is electrically connected to a source line; one or more columnar memory gate electrodes are vertically arranged on the substrate through an insulation layer and are arranged in a region between the parallel drain diffusion layer and the source diffusion layer; a columnar drain side selection gate electrode is vertically arranged on the substrate through an insulation layer and is arranged in a region between the drain diffusion layer and the memory gate electrode; a columnar source side selection gate electrode is vertically arranged on the substrate through an insulation layer and is arranged in a region between the drain diffusion layer and the memory gate electrode; The electrode is vertically arranged on the substrate through an insulating layer, and is arranged in the area between the source diffusion layer and the memory gate electrode; the multi-layer insulating layer is arranged in contact with the memory gate electrode; the drain side selection gate insulating layer is arranged in contact with the drain side selection gate electrode; the source side selection gate insulating layer is arranged in contact with the source side selection gate electrode; the semiconductor layer is arranged in the area between the parallel drain diffusion layer and the source diffusion layer, and is respectively in contact with the drain side selection gate insulating layer, the source side selection gate insulating layer, the multi-layer insulating layer, the drain diffusion layer and the source diffusion layer, wherein the multi-layer insulating layer has a first memory gate insulating layer in contact with the memory gate electrode, a charge storage layer in contact with the first memory gate insulating layer, and a second memory gate insulating layer in contact with the charge storage layer and the semiconductor layer.

[0007] In addition, the nonvolatile semiconductor storage device of the present invention is a nonvolatile semiconductor storage device in which a plurality of nonvolatile memory cells are arranged in a matrix in the surface direction of the substrate surface and are arranged in layers along a vertical direction orthogonal to the surface direction, wherein the nonvolatile memory cells are the aforementioned nonvolatile memory cells. Effects of the Invention

[0008] According to the present invention, by making a nonvolatile memory cell into a three-dimensional structure, it is possible to achieve integration and miniaturization without being restricted by two-dimensional scaling. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a circuit diagram showing a configuration of an equivalent circuit of the nonvolatile semiconductor memory device according to the first embodiment. Figure 2A is a circuit diagram showing the structure of an equivalent circuit of a nonvolatile memory cell, Figure 2B It is a schematic diagram showing a cross-sectional structure of a nonvolatile memory cell when viewed from above. Figure 3 It is a cross-sectional view showing the cross-sectional structure of the memory array when viewed from above. Figure 4 Yes means Figure 3 A cross-sectional view of the cross-sectional structure of the AA′ portion. Figure 5 Yes means Figure 3 A cross-sectional view of the cross-sectional structure of the BB′ part. FIG. 6 is a cross-sectional view showing a cross-sectional structure of a nonvolatile memory cell according to another embodiment of the first embodiment. Fig. 7A is a circuit diagram showing the voltages of various parts of a nonvolatile memory cell during a write operation. Figure 7B This is a schematic diagram for explaining the operation of a nonvolatile memory cell during a write operation. Fig. 8A is a circuit diagram for explaining a memory array during a write operation. Figure 8B This is a table showing the voltage of each part during the writing operation. Fig.9A is a circuit diagram showing voltages of various parts of a nonvolatile memory cell during an erase operation. Fig. 9B This is a schematic diagram for explaining the operation of the nonvolatile memory cell during the erasing operation. Fig. 10A This is a circuit diagram for explaining a memory array during a clear operation. Fig. 10B This is a table showing the voltage of each part during the clearing operation. Fig.11A This is a circuit diagram for explaining a memory array during a read operation. Fig. 11B This is a table showing the voltage of each part during the reading operation. Fig. 11C This is a table showing other voltages of various parts during the reading operation. Fig.12 It is a schematic diagram showing the position of a cross-sectional portion used in explaining each manufacturing process. FIG. 13 is a schematic diagram showing a manufacturing process (1) of a memory array. Fig.13A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 13B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 13C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 14 is a schematic diagram showing a manufacturing process (2) of a memory array. Fig.14A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 14B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 14C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 15 is a schematic diagram showing a manufacturing process (3) of a memory array. Fig.15A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 15B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 15C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 16 is a schematic diagram showing a manufacturing process (4) of a memory array. Fig.16A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 16B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 16C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 17 is a schematic diagram showing a manufacturing process (5) of a memory array. Fig.17A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 17B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 17C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 18 is a schematic diagram showing a manufacturing process (6) of a memory array. Fig.18A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig.18B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig. 18C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 19 is a schematic diagram showing a manufacturing process (7) of a memory array. Fig.19A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig.19B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the FF′ part, Fig.19C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 20 is a schematic diagram showing a manufacturing process (8) of a memory array. Fig. 20AYes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 20B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the HH′ portion, Fig. 20C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 21 is a schematic diagram showing a manufacturing process (9) of a memory array. Fig.21A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig.21B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the HH′ portion, Fig. 21C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. FIG. 22 is a schematic diagram showing a manufacturing process (10) of a memory array. Fig.22A Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the EE′ part, Fig. 22B Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the HH′ portion, Fig. 22C Yes means Fig.12 A cross-sectional view of the cross-sectional structure of the GG′ part. Fig.23 is a circuit diagram showing a structure of an equivalent circuit of a nonvolatile semiconductor memory device according to another embodiment of the first embodiment. Fig.24 is a circuit diagram showing a structure of an equivalent circuit of a memory array provided in the nonvolatile semiconductor memory device according to the second embodiment. Fig.25A is a circuit diagram showing the structure of an equivalent circuit of a nonvolatile memory cell, Fig.25B It is a schematic diagram showing a cross-sectional structure of a nonvolatile memory cell when viewed from above. Fig.26 It is a cross-sectional view showing the cross-sectional structure of the memory array when viewed from above. Fig.27A Yes means Fig.26 A cross-sectional view of the cross-sectional structure of the JJ′ portion, Fig.27B Yes means Fig.26 A cross-sectional view of the cross-sectional structure of the KK′ part. Fig.28 It is a cross-sectional view of a memory cell in a plan view according to another embodiment of the second embodiment. Fig.29A is a circuit diagram for explaining a memory array during a write operation. Fig.29B This is a table showing the voltage of each part during the writing operation. Fig. 30A This is a circuit diagram for explaining a memory array during a clear operation. Fig. 30B This is a table showing the voltage of each part during the clearing operation. Fig. 30C This is a table showing other voltages of various parts during the clearing operation. Fig.31A This is a circuit diagram for explaining a memory array during a read operation. Fig.31B This is a table showing the voltage of each part during the reading operation. Fig. 31C This is a table showing other voltages of various parts during the reading operation. Fig.32 is a circuit diagram showing a structure of an equivalent circuit of a memory array provided in the nonvolatile semiconductor memory device according to the third embodiment. Fig.33A is a circuit diagram showing the structure of an equivalent circuit of a nonvolatile memory cell, Fig.33B It is a schematic diagram showing a cross-sectional structure of a nonvolatile memory cell when viewed from above. Fig.34A is a circuit diagram for explaining a memory array during a write operation. Fig.34B This is a table showing the voltage of each part during the writing operation. Fig.35A This is a circuit diagram for explaining a memory array during a clear operation. Fig.35B This is a table showing the voltage of each part during the clearing operation. Fig.35C This is a table showing other voltages of various parts during the clearing operation. Fig.36A This is a circuit diagram for explaining a memory array during a read operation. Fig.36B This is a table showing the voltage of each part during the reading operation. Fig.36C This is a table showing other voltages of various parts during the reading operation. Fig.37 This is a schematic diagram showing the manufacturing process (1) of a memory array. FIG38 is a schematic diagram showing a manufacturing process (2) of a memory array. Fig.38A is a schematic diagram showing the structure when viewed from above. Fig.38B Yes means Fig.38A A cross-sectional view of the cross-sectional structure of the MM′ part. FIG39 is a schematic diagram showing the manufacturing process (3) of the memory array. Fig.39A Yes means Fig.38A A cross-sectional view of the cross-sectional structure of the MM' portion in the next process, Fig.39B Yes means Fig.38A A cross-sectional view of the cross-sectional structure of the MM′ part in the next process. FIG40 is a schematic diagram showing a manufacturing process (4) of a memory array. Fig.40A Yes means Fig.38A A cross-sectional view of the cross-sectional structure of the MM' portion in the next process, Fig.40B Yes means Fig.38A A cross-sectional view of the cross-sectional structure of the MM′ part in the next process. FIG41 is a schematic diagram showing a manufacturing process (5) of a memory array. Fig.41A is a schematic diagram showing the structure when viewed from above. Fig.41B Yes means Fig.41A A cross-sectional view of the cross-sectional structure of the MM′ part. FIG. 42 is a schematic diagram showing a manufacturing process (6) of a memory array. Fig.42A is a schematic diagram showing the structure when viewed from above. Fig.42B Yes means Fig.42A A cross-sectional view of the cross-sectional structure of the NN′ portion, Fig.42C Yes means Fig.42A A cross-sectional view of the cross-sectional structure of the NN′ part in the next process. FIG43 is a schematic diagram showing a manufacturing process (7) of a memory array. Fig.43A is a schematic diagram showing the structure when viewed from above. Fig.43B Yes means Fig.43A A cross-sectional view of the cross-sectional structure of the OO′ part. FIG. 44 is a schematic diagram showing a manufacturing process (8) of a memory array. Fig.44A Yes means Fig.43A A cross-sectional view of the cross-sectional structure of the OO' portion in the next process, Fig.44B Yes means Fig.43A A cross-sectional view of the cross-sectional structure of the OO′ part in the next process. Fig.45 is a schematic diagram showing the manufacturing process (9) of the memory array, Fig.43A A cross-sectional view of the cross-sectional structure of the OO′ part in the next process. Fig.46 It is a schematic diagram showing the manufacturing process (10) of the memory array, and is a schematic diagram showing the structure when viewed from above. Fig.47 It is a schematic diagram showing the manufacturing process (11) of the memory array and is a cross-sectional view showing the cross-sectional structure of the memory array. Fig.48 It is a schematic diagram showing a cross-sectional structure of a nonvolatile memory cell according to the fourth embodiment when viewed from above. Fig.49 It is a schematic diagram showing a cross-sectional structure of a memory array according to a fourth embodiment when viewed from above. Fig.50 Yes means Fig.49 A cross-sectional view of the cross-sectional structure of the RR′ part. Fig.51 It is a schematic diagram showing a manufacturing process (1) of a memory array according to the fourth embodiment. FIG. 52 is a schematic diagram showing a manufacturing process (2) of a memory array according to the fourth embodiment. Fig.52A is a schematic diagram showing the structure when viewed from above. Fig.52B Yes means Fig.52A A cross-sectional view of the cross-sectional structure of the SS′ part. FIG53 is a schematic diagram showing a manufacturing process (3) of a memory array according to the fourth embodiment. Fig.53A is a schematic diagram showing a cross-sectional structure when viewed from above. Fig.53B Yes means Fig.53A A cross-sectional view of the cross-sectional structure of the SS′ part. FIG. 54 is a schematic diagram showing a manufacturing process (4) of a memory array according to the fourth embodiment. Fig.54A is a schematic diagram showing a cross-sectional structure when viewed from above. Fig.54B Yes means Fig.54A A cross-sectional view of the cross-sectional structure of the SS′ part. FIG. 55 is a schematic diagram showing a manufacturing process (5) of a memory array according to the fourth embodiment. Fig.55A Yes means Fig.54A A cross-sectional view of the cross-sectional structure of the SS′ part in the next process, Fig.55B Yes means Fig.55A The cross-sectional view shows the cross-sectional structure of the SS' portion in the next step of the process shown. FIG. 56 is a schematic diagram showing a manufacturing process (6) of a memory array according to the fourth embodiment. Fig.56A Yes means Fig.55B Schematic diagram of the structure when viewed from above at the height position of the TT′ part, Fig.56B Yes means Fig.56A A cross-sectional view of the cross-sectional structure of the UU′ part. FIG. 57 is a schematic diagram showing a manufacturing process (7) of a memory array according to the fourth embodiment. Fig.57A Yes means Fig.56A A cross-sectional view of the cross-sectional structure of the UU′ part in the next process, Fig.57B Yes means Fig.56A A cross-sectional view showing the cross-sectional structure of the UU' portion in the next step of the process shown. DETAILED DESCRIPTION

[0010] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in this specification and the accompanying drawings, components having substantially the same functional structure are given the same reference numerals and repeated descriptions are omitted.

[0011] (1) First Embodiment (1-1) Structure of Equivalent Circuit of Nonvolatile Semiconductor Memory Device According to First Embodiment exist Figure 1 In the embodiment, the nonvolatile semiconductor memory device 1 includes: a row decoder 2a, a column decoder 2b, a memory array CA, a plurality of bit lines BL, a plurality of source lines SL, a plurality of drain side selection gate lines BGL, a plurality of source side selection gate lines SGL, and a plurality of word lines WL. In addition, in the present embodiment, the X direction in which the bit lines BL and the source lines SL are extended is referred to as the column direction (hereinafter also referred to as the column direction X), the Y direction in which the drain side selection gate lines BGL, the source side selection gate lines SGL, and the plurality of word lines WL are extended and orthogonal to the bit lines BL and the source lines SL is referred to as the row direction (hereinafter also referred to as the row direction Y), and the Z direction orthogonal to the direction of the plane including both the X direction and the Y direction (hereinafter referred to as the plane direction) is referred to as the vertical direction (hereinafter also referred to as the vertical direction Z).

[0012] The memory array CA has the following structure: a plurality of nonvolatile memory cells (hereinafter referred to as memory cells) C are arranged in a matrix in the plane direction, and the plurality of memory cells C arranged in a matrix in the plane direction are arranged hierarchically along a vertical direction Z orthogonal to the plane direction. Figure 1 , an example of a memory array CA in which a plurality of memory cells C are arranged in three rows and two columns in the plane direction and a plurality of memory cells C arranged in three rows and two columns are provided in two layers of an upper layer and a lower layer is shown.

[0013] The bit lines BL are respectively extended in the column direction X in each layer of the memory array CA, and are connected to a plurality of memory cells C arranged in the same column in each layer. In addition, the source lines SL are respectively extended in the column direction X in parallel with the bit lines BL in each layer of the memory array CA, and are connected to the memory cells C in the same column in each layer. That is, in each layer, a plurality of memory cells C arranged in the column direction X share one bit line BL and one source line SL.

[0014] In addition, the drain side selection gate line BGL, the source side selection gate line SGL and the word line WL are respectively arranged in each row (page), and are connected to a plurality of memory cells C arranged in the same row (within the same page) including different levels. That is, in the memory cells C in the pages respectively arranged along the row direction Y including different levels, there is a total of one drain side selection gate line BGL, one source side selection gate line SGL and one word line WL.

[0015] The memory array CA according to the present embodiment has the following structure: the drain side selection gate line BGL, the source side selection gate line SGL and the word line WL do not extend along the row direction Y in the second layer as the lower layer, but only extend along the row direction Y in the first layer as the upper layer, and the drain side selection gate line BGL, the source side selection gate line SGL and the word line WL arranged in the upper layer are also electrically connected to each memory cell C configured in the lower layer, respectively.

[0016] In the following, when distinguishing each memory cell C, i, j and k are respectively 1, 2, 3, ..., and the memory cell at the i-th row, j-th column and k-th level is referred to as memory cell C. ijk In addition, when the bit lines BL and source lines SL are divided into specific columns or layers, the bit line BL in the jth column and the kth layer is defined as jk and source line SL jk In the following description, when the drain side selection gate line BGL, the source side selection gate line SGL, and the word line WL are divided into specific rows, the i-th row is used as the drain side selection gate line BGL. i , source side selection gate line SGL i and word line WL i At this time, the memory cell C at the i-th row, j-th column, and k-th level ijk bit lines BL jk , source line SL jk , drain side selection gate line BGL i , source side selection gate line SGL i and word line WL i In addition, when the hierarchy is not distinguished, the mark "k" indicating the kth hierarchy is omitted, and the memory cell C ij , bit line BL j and source line SL j Provide explanation.

[0017] Furthermore, when distinguishing between memory cells C that are targets of data writing, erasing, and reading and memory cells C that are not targets, the former are referred to as "selected memory cells C" and the latter are referred to as "non-selected memory cells C" for explanation.

[0018] In addition, in the memory array CA according to the present embodiment, since the configuration structure of the plurality of memory cells C arranged in a matrix in each layer is the same in each layer, here, without the need to distinguish between each layer, the configuration structure of the plurality of memory cells C arranged in the first layer of the upper layer will be mainly described.

[0019] The memory cells C all have the same structure, and each has a drain side selection transistor DT, a memory transistor MT, and a source side selection transistor ST. The memory cells C have a structure in which the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST are connected in series. In addition, the details of the structure of the memory cells C will be described later.

[0020] In this case, the bit line BL is connected to the end of the drain side selection transistor DT of each memory cell C in the corresponding column, and the source line SL is connected to the end of the source side selection transistor ST of each memory cell C in the corresponding column. In addition, the drain side selection gate line BGL is connected to the drain side selection transistor DT of each memory cell C in the corresponding row, the source side selection gate line SGL is connected to the source side selection transistor ST of each memory cell C in the corresponding row, and the word line WL is connected to the memory transistor MT of each memory cell C in the corresponding row.

[0021] In addition, the drain side selection gate line BGL, the source side selection gate line SGL and the word line WL are connected to the row decoder 2a, respectively, and the bit line BL and the source line SL are connected to the column decoder 2b, respectively. In the memory cell C, the voltages of the connected bit line BL, source line SL, drain side selection gate line BGL, source side selection gate line SGL and word line WL are controlled by the row decoder 2a and the column decoder 2b, so that data is written, cleared and read for the memory transistor MT.

[0022] Here, a structure including a plurality of memory cells C arranged in different layers and columns and arranged in a row direction Y (a vertical direction (a normal direction to the surface direction) perpendicular to the surface direction and extending in the row direction Y) is referred to as a page ( Figure 1 The following table contains the information marked as “1page” in the figure. Figure 1 In the example of the memory array CA shown, since the memory cells C are arranged in three rows, it has a three-page structure.

[0023] Furthermore, for the sake of convenience, when writing data, a page including memory cells C to which data is written is referred to as a "write selection page", and a page consisting only of memory cells C to which data is not written is referred to as a "write non-selection page". In addition, when clearing data, a page including memory cells C to which data is cleared is referred to as an "clear selection page", and a page consisting only of memory cells C to which data is not cleared is referred to as an "clear non-selection page". Furthermore, when reading data, a page including memory cells C to which data is read is referred to as a "read selection page", and a page consisting only of memory cells C to which data is not read is referred to as a "read non-selection page".

[0024] In addition, the details of the data writing operation, clearing operation, and reading operation in the nonvolatile semiconductor memory device 1 will be described later. In this case, since the drain side selection gate line BGL and the source side selection gate line SGL are independently wired in each page, the data of the memory cell C can be selectively read and the data can be written to the memory cell C for each page. However, the data of the memory cell C is cleared in units of n pages.

[0025] (1-2) Structure of memory cell Next, the structure of the memory cell C will be described. Figure 2A is a circuit diagram showing the structure of an equivalent circuit of a memory cell C. Figure 2A As shown, in the memory cell C, one end of a drain-side selection transistor DT is connected to one end of a memory transistor MT having a charge storage layer described later, and one end of a source-side selection transistor ST is connected to the other end of the memory transistor MT.

[0026] The other end of the drain side selection transistor DT is connected to the bit line BL, and the other end of the source side selection transistor ST is connected to the source line SL. Furthermore, the drain side selection gate line BGL is connected to the drain side selection gate electrode DG (at Figure 2B The source side selection gate line SGL is connected to the source side selection gate electrode SG of the source side selection transistor ST, and the word line WL is connected to the memory gate electrode MG of the memory transistor MT.

[0027] Figure 2B Indicated in Figure 2A An example of a cross-sectional structure of a memory cell C in a top view is shown. The memory cell C is formed in a region between a bit line BL and a source line SL extending in parallel in a column direction X, and includes: a drain diffusion layer 7 extending in the column direction X in contact with the bit line BL; and a source diffusion layer 6 extending in the column direction X in contact with the source line SL. In addition, these source diffusion layer 6 and drain diffusion layer 7 are n+ type diffusion layers with a high impurity concentration in, for example, polysilicon.

[0028] In the memory cell C, a semiconductor layer 17 made of polysilicon or the like is provided in a region between the parallel drain diffusion layer 7 and the source diffusion layer 6, and the semiconductor layer 17 is in contact with the side surfaces of the drain diffusion layer 7 and the source diffusion layer 6. In addition, in the semiconductor layer 17 provided between the parallel drain diffusion layer 7 and the source diffusion layer 6, a memory gate structure 10, a drain side selection gate structure 11, and a source side selection gate structure 12 are provided in a manner penetrating the semiconductor layer 17.

[0029] The memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12 of the present embodiment are respectively formed into columns with circular cross-sections, and the memory gate structure 10 is arranged between the drain side selection gate structure 11 and the source side selection gate structure 12. These memory gate structures 10, the drain side selection gate structure 11 and the source side selection gate structure 12 are arranged in a straight line.

[0030] In addition, here, the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12 are selected to have the same diameter as the diameter of the cross-sectional circle, and are selected at equal intervals between the memory gate structure 10 and the drain side selection gate structure 11, and between the memory gate structure 10 and the source side selection gate structure 12, but the present invention is not limited to this. For the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12, the diameters of the cross-sectional circles can be selected as different diameters, respectively, or the distances between the memory gate structure 10 and the drain side selection gate structure 11, and between the memory gate structure 10 and the source side selection gate structure 12 can be selected as different distances.

[0031] The memory gate structure 10 includes a cylindrical memory gate electrode MG and a ring-shaped multilayer insulating layer 15 provided in a circumferential direction on the side of the memory gate electrode MG. The multilayer insulating layer 15 includes a ring-shaped first memory gate insulating layer 15a provided in a circumferential direction on the side of the memory gate electrode MG, a ring-shaped charge storage layer 15b provided in contact with the outer periphery of the first memory gate insulating layer 15a, and a ring-shaped second memory gate insulating layer 15c provided in contact with the outer periphery of the charge storage layer 15b. In addition, the first memory gate insulating layer 15a and the second memory gate insulating layer 15c are formed of silicon oxide (SiO2) or the like, and the charge storage layer 15b is formed of silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), or the like.

[0032] In the memory gate structure 10 of the present embodiment, from the viewpoint of process margin, the diameter of the memory gate electrode MG at the uppermost portion is preferably 20 to 70 nm. In addition, when viewed from above, from the viewpoint of reliability, the distance in the plane direction from the inner surface (inner periphery) to the outer surface (outer periphery) of the multilayer insulating layer 15 (hereinafter referred to as the distance in the plane direction of the multilayer insulating layer 15) rm is preferably 12 to 22 nm. When viewed from above, the distance in the plane direction from the inner surface to the outer surface of the first memory gate insulating layer 15a (hereinafter referred to as the distance in the plane direction of the first memory gate insulating layer 15a) is preferably 3 to 10 nm. When viewed from above, the distance in the plane direction from the inner surface to the outer surface of the charge storage layer 15b (hereinafter referred to as the distance in the plane direction of the charge storage layer 15b) is preferably 5 to 10 nm. When viewed from above, the distance in the plane direction from the inner surface to the outer surface of the second memory gate insulating layer 15c (hereinafter referred to as the distance in the plane direction of the second memory gate insulating layer 15c) is preferably 3 to 10 nm.

[0033] The drain-side selection gate structure 11 includes a cylindrical drain-side selection gate electrode DG and an annular drain-side selection gate insulating layer 14a provided along the circumferential direction on the side surface of the drain-side selection gate electrode DG. In addition, the source-side selection gate structure 12 includes a cylindrical source-side selection gate electrode SG and an annular source-side selection gate insulating layer 14b provided along the circumferential direction on the side surface of the source-side selection gate electrode SG.

[0034] In addition, the memory cell C of this embodiment describes the case where the distance in the surface direction of the drain side selection gate insulating layer 14a and the distance in the surface direction of the source side selection gate insulating layer 14b are selected to be the same size, but the present invention is not limited to this. The distance in the surface direction of the drain side selection gate insulating layer 14a and the distance in the surface direction of the source side selection gate insulating layer 14b may be selected to be different sizes.

[0035] In addition, the drain side selection gate line BGL connected to the drain side selection gate electrode DG, the source side selection gate line SGL connected to the source side selection gate electrode SG, and the word line WL connected to the memory gate electrode MG are respectively extended in the row direction Y orthogonal to the bit line BL, the source line SL, the drain diffusion layer 7 and the source diffusion layer 6.

[0036] In addition to such a structure, the semiconductor layer 17 of the present embodiment is arranged around these memory gate structures 10 , the drain side selection gate structures 11 , and the source side selection gate structures 12 along their outer contour shapes, so as to surround these memory gate structures 10 , the drain side selection gate structures 11 , and the source side selection gate structures 12 .

[0037] In addition, in the semiconductor layer 17, the region surrounding the periphery of the memory gate structure 10 is referred to as a memory peripheral region 17b, the region surrounding the periphery of the drain side selection gate structure 11 is referred to as a drain side peripheral region 17a, and the region surrounding the periphery of the source side selection gate structure 12 is referred to as a source side peripheral region 17c. These memory peripheral region 17b, the drain side peripheral region 17a, and the source side peripheral region 17c are formed integrally.

[0038] The drain-side peripheral region 17a of the semiconductor layer 17 maintains a predetermined distance a along the side surface of the drain-side selection gate structure 11 in the plane direction, and then both side surfaces extend linearly to the drain diffusion layer 7, and the outer contour shape is formed into an inverted D shape, and the end surface is along the side surface of the drain diffusion layer 7 and linearly contacts the side surface of the drain diffusion layer 7. Similarly, the source-side peripheral region 17c of the semiconductor layer 17 also maintains a predetermined distance a along the side surface of the source-side selection gate structure 12 in the plane direction, and then both side surfaces extend linearly to the source diffusion layer 6, and the outer contour shape is formed into a D shape, and the end surface is linearly contacted along the side surface of the drain diffusion layer 7.

[0039] Here, if each distance a in the surface direction of the drain side peripheral region 17a, the memory peripheral region 17b, and the source side peripheral region 17c is 40nm or more, when gate voltages are applied to the memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG, respectively, it becomes difficult to control the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST, and leakage current may be generated during the data reading operation. Therefore, the size of the distance a is preferably less than 40nm in order to more accurately control the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST, and suppress the generation of leakage current during the data reading operation.

[0040] In this embodiment, the distance between the memory gate structure 10 and the drain side selection gate structure 11 is a, the memory peripheral area 17b and the drain side peripheral area 17a of the semiconductor layer 17 are repeatedly formed, and the distance between the memory gate structure 10 and the source side selection gate structure 12 is also a, and the memory peripheral area 17b and the source side peripheral area 17c of the semiconductor layer 17 are repeatedly formed.

[0041] In addition, in the present embodiment, a semiconductor layer 17 is provided between the drain-side selection gate insulating layer 14a and the drain diffusion layer 7, and a semiconductor layer 17 is also provided between the source-side selection gate insulating layer 14b and the source diffusion layer 6. However, the present invention is not limited to this. The semiconductor layer 17 may not be provided between the drain-side selection gate insulating layer 14a and the drain diffusion layer 7, so that a structure in which the drain-side selection gate insulating layer 14a is in contact with the drain diffusion layer 7 may be formed. In addition, a semiconductor layer 17 may not be provided between the source-side selection gate insulating layer 14b and the source diffusion layer 6, so that a structure in which the source-side selection gate insulating layer 14b is in contact with the source diffusion layer 6 may be formed.

[0042] (1-3) Structure of memory array Next, the cross-sectional structure of the memory array CA in which the memory cells C are arranged in a matrix is ​​described. Figure 1 In order to simply explain the structure of the equivalent circuit of the memory array CA, the structure of the equivalent circuit is explained without focusing on the physical configuration positions of each part. However, here, the following explanation is made focusing on the physical configuration positions of each part when the memory cell C is actually manufactured.

[0043] Figure 3 It is a cross-sectional view showing the cross-sectional structure of the memory array CA when viewed from above. Figure 4 Yes means Figure 3 A cross-sectional view of the cross-sectional structure of the AA′ portion. Figure 5 Yes means Figure 3 A cross-sectional view of the cross-sectional structure of the BB′ part.

[0044] exist Figure 3 In FIG. 1 , one direction represents the column direction X when viewed from above, and another direction orthogonal to the one direction represents the row direction Y. For example, a structure in which the memory cells C are arranged in 3 rows and 2 columns in the first layer is shown. Figure 3 , the memory cells C arranged in the first row and first column, the second row and first column, and the third row and first column on the left side of the drawing are respectively represented as memory cells C 11 , C 21 , C 31 , the memory cells C arranged in the first row and second column, the second row and second column, and the third row and second column on the right side of the drawing are respectively represented as memory cells C 12 , C 22 , C 32 .

[0045] Figure 1 This is a circuit diagram focusing on the structure of an equivalent circuit of the memory array CA. Figure 3 An example of the arrangement of the various parts when the memory array CA is manufactured is shown. Figure 3In the memory array CA shown in FIG. 1 , the memory cells C arranged in the first column 11 , C 21 , C 31 and the memory cells C arranged in the second column 12 , C 22 , C 32 The bit lines BL1 in the first column and the bit lines BL2 in the second column are arranged to be symmetrical.

[0046] In addition to configuring the first column of memory cells C 11 , C 21 , C 31 The structure and configuration of the second column memory cell C 12 , C 22 , C 32 The structure is formed to be bilaterally symmetrical, and the other structures are the same, so the following description focuses on the memory cells in the first column. In this case, the bit line BL1 and the source line SL1 are extended in parallel, the source diffusion layer 6 is extended in contact with the side surface of the source line SL1, and the drain diffusion layer 7 is extended in contact with the side surface of the bit line BL1.

[0047] In the region between the source diffusion layer 6 and the drain diffusion layer 7 parallel to each other in the column direction X, memory cells C are also arranged in the column direction X. 11 , C 21 , C 31 , each memory cell C 11 , C 21 , C 31 The side surfaces of the semiconductor layer 17 are in contact with the side surfaces of the source diffusion layer 6 and the drain diffusion layer 7, respectively. 11 , C 21 , C 31 The source line SL1, the bit line BL1, the source diffusion layer 6 and the drain diffusion layer 7 are shared. 11 , C 21 , C 31 An insulating layer 19 is provided between each memory cell C 11 , C 21 , C 31 Insulated.

[0048] The drain side selection gate line BGL1 extending in the row direction Y is connected to the memory cells C arranged in the first and second columns on the same row. 11 , C 12 The drain side selection gate electrodes DG of the memory cells are connected to the source side selection gate lines SGL1 extending in the row direction Y and connected to the memory cells C arranged in the first and second columns on the same row. 11, C 12 The word line WL1 extending in the row direction Y is connected to the first and second memory cells C arranged in the same row. 11 , C 12 The memory gate electrode MG is connected.

[0049] Next, Figure 4 shown Figure 3 The cross-sectional structure of the AA′ portion is described. Figure 4 This is a diagram showing a longitudinal cross-sectional structure in the vertical direction Z regarding the positions at which the memory gate structure 10 , the drain side selection gate structure 11 , and the source side selection gate structure 12 constituting the memory cell C are arranged.

[0050] At this time, the columnar memory gate structure 10, the columnar drain side selection gate structure 11, and the columnar source side selection gate structure 12 are respectively arranged on the substrate 20 via the insulating layer 19. On the substrate 20, along the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12, the memory cells C from the first level to the kth level in the vertical direction Z are arranged. 121 , C 122 , C 123 , …, C 12k Thus, a plurality of memory cells C arranged in the vertical direction Z are formed at predetermined intervals. 121 , C 122 , C 123 , …, C 12k There are a memory gate structure 10 , a drain side selection gate structure 11 and a source side selection gate structure 12 .

[0051] In the memory gate structure 10, a columnar memory gate electrode MG is extended in a vertical direction Z relative to the surface of the substrate 20, and a multi-layer insulating layer 15 is formed on the side and bottom surfaces of the memory gate electrode MG. The word line WL1 is connected to the upper end of the memory gate electrode MG via a contact 18. Thus, a plurality of memory cells C arranged in the vertical direction Z are 121 , C 122 , C 123 , …, C 12k The same voltage is applied to the memory gate electrodes MG.

[0052] In the drain side selection gate structure 11, a columnar drain side selection gate electrode DG is extended in a vertical direction Z relative to the surface of the substrate 20, and a drain side selection gate insulating layer 14a is formed on the side and bottom surfaces of the drain side selection gate electrode DG. The upper end of the drain side selection gate electrode DG is connected to the drain side selection gate line BGL1 via the contact 18. Thus, in the plurality of memory cells C arranged in the vertical direction Z, 121 , C 122 , C 123 , …, C 12k The same voltage is applied to the drain side selection gate electrode DG.

[0053] In the source side selection gate structure 12, a columnar source side selection gate electrode SG is extended in the vertical direction Z relative to the surface of the substrate 20, and a source side selection gate insulating layer 14b is formed on the side and bottom surfaces of the source side selection gate electrode SG. The source side selection gate line SGL1 is connected to the upper end of the source side selection gate electrode SG via the contact 18. Thus, in the plurality of memory cells C arranged in the vertical direction Z, 121 , C 122 , C 123 , …, C 12k The same voltage is applied to the source side selection gate electrode SG.

[0054] In addition, on the substrate 20, a layer in which source lines SL, source diffusion layers 6, semiconductor layers 17, drain diffusion layers 7, and bit lines BL are arranged, and an insulating layer 19 are alternately arranged in the vertical direction Z. On the layer in which the source lines SL, source diffusion layers 6, semiconductor layers 17, drain diffusion layers 7, and bit lines BL are arranged, memory cells C are formed respectively. 121 , C 122 , C 123 , …, C 12k .

[0055] Next, Figure 5 shown Figure 3 The cross-sectional structure of the BB′ portion will be described. Figure 5 It is about the memory cell C of each level in the first row and first column 111 , C 112 , C 113 , …, C 11k The common memory gate structure 10 and the memory cells C of each layer in the second row and the first column 211 , C 212 , C 213 , …, C 21k The arrangement position of the common memory gate structure 10 is shown in a diagram showing a longitudinal cross-sectional structure in the vertical direction Z.

[0056] In this case, the memory cell C in the first row and first column 111 , C 112 , C 113 , …, C 11k and memory cell C in the second row and first column 211 , C 212 , C 213 , …, C 21k The insulation is performed by the insulating layer 19. In addition, the memory cells C of each layer in the first row and the first column 111 , C 112 , C 113 , …, C 11k The word line WL1 is connected to the upper end of the common memory gate electrode MG. 211 , C 212 , C 213 , …, C 21k A word line WL2 different from the word line WL1 is connected to the upper end of the common memory gate electrode MG. 111 , C 112 , C 113 , …, C 11k The memory gate electrode MG of the second row and the first column of the memory cell C 211 , C 212 , C 213 , …, C 21k Different voltages can be applied to the memory gate electrode MG through different word lines WL1 and WL2.

[0057] (1-4) Structure of Memory Cell According to Another Embodiment Next, the structure of a memory cell according to another embodiment is described. FIG6 shows a cross-sectional structure of a memory cell Cb according to another embodiment, which is different from the above-described memory cell C in the structures of the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12a, and in that a memory-drain region connecting portion 17d and a memory-source region connecting portion 17e are provided on the semiconductor layer 17.

[0058] Here, when distinguishing each memory cell Cb, k is set to 1, 2, 3, ..., and the memory cell at the kth level is set as the memory cell Cb. k Provide explanation. Fig. 6A An example of a cross-sectional structure of a memory cell Cb when viewed from above is shown. Figure 6BThis is a diagram showing a longitudinal cross-sectional structure in the vertical direction Z, with respect to positions where the memory gate structure 10 a , the drain-side selection gate structure 11 a , and the source-side selection gate structure 12 a constituting the memory cell Cb are arranged.

[0059] like Fig. 6A As shown, the memory cell Cb is formed in a region between the bit line BL and the source line SL extending in parallel in the column direction X, and has: a drain diffusion layer 7 extending in the column direction X in contact with the bit line BL; and a source diffusion layer 6 extending in the column direction X in contact with the source line SL. In the memory cell Cb, a semiconductor layer 17 made of polysilicon or the like is provided in a region between the parallel drain diffusion layer 7 and the source diffusion layer 6, and the side surfaces of the semiconductor layer 17 are in contact with the side surfaces of the drain diffusion layer 7 and the side surfaces of the source diffusion layer 6, respectively. In addition, in the present embodiment, in a plan view, the contact width between the side surfaces of the source diffusion layer 6 and the side surfaces of the semiconductor layer 17, and the contact width between the side surfaces of the drain diffusion layer 7 and the side surfaces of the semiconductor layer 17 are set to a predetermined distance d and are in contact with each other.

[0060] In addition, in the semiconductor layer 17 provided between the parallel drain diffusion layer 7 and the source diffusion layer 6, the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12a are provided so as to penetrate the semiconductor layer 17. The memory cell Cb has the semiconductor layer 17 formed so as to surround the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12a. The semiconductor layer 17 includes: a memory peripheral region 17b surrounding the periphery of the memory gate structure 10a; a drain side peripheral region 17a surrounding the periphery of the drain side selection gate structure 11a; a source side peripheral region 17c surrounding the periphery of the source side selection gate structure 12a; a memory-drain region connecting portion 17d connecting the memory peripheral region 17b and the drain side peripheral region 17a; and a memory-source region connecting portion 17e connecting the memory peripheral region 17b and the source side peripheral region 17c.

[0061] In this case, the memory peripheral region 17b is formed along the side of the memory gate structure 10a whose cross section is circular when viewed from above, and is formed into a cross-sectional annular shape in which the distance a from the side of the memory gate structure 10a to the outer surface (periphery) is selected to be a predetermined size. In addition, the drain side peripheral region 17a is also formed along the side of the drain side selection gate structure 11a whose cross section is circular when viewed from above, and is formed into a cross-sectional annular shape in which the distance a from the side of the drain side selection gate structure 11a to the outer surface is selected to be a predetermined size. In addition, the source side peripheral region 17c is also formed along the side of the source side selection gate structure 12a whose cross section is circular when viewed from above, and is formed into a cross-sectional annular shape in which the distance a from the side of the source side selection gate structure 12a to the outer surface is selected to be a predetermined size.

[0062] The memory-drain region connecting portion 17d is formed of a rectangular cross-section in a plan view, and a distance b from one end to the other end is selected to be a predetermined size. One end of the memory-drain region connecting portion 17d is connected to the periphery of the memory peripheral region 17b at a distance a from the side of the memory gate structure 10a, and the other end is connected to the periphery of the drain side peripheral region 17a at a distance a from the side of the drain side selection gate structure 11a.

[0063] In addition, the memory-source region connecting portion 17e is also formed in a rectangular shape in a plan view, and the distance b from one end to the other end is selected to be a predetermined size. One end of the memory-source region connecting portion 17e is connected to the periphery of the memory peripheral region 17b at a distance a from the side of the memory gate structure 10a, and the other end is connected to the periphery of the source side peripheral region 17c at a distance a from the side of the source side selection gate structure 12a.

[0064] Here, if the distances a in the plane direction of the drain side peripheral region 17a, the memory peripheral region 17b, and the source side peripheral region 17c are greater than 40 nm, when gate voltages are applied to the memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG, respectively, it becomes difficult to control the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST, and leakage current may be generated during the data reading operation. Therefore, in order to more accurately control the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST, and to suppress the generation of leakage current during the data reading operation, the size of the distance a in the plane direction is preferably less than 40 nm.

[0065] In addition, in the memory cell Cb of this embodiment, a case has been described in which the distance a of the memory peripheral area 17b, the distance a of the drain side peripheral area 17a, and the distance a of the source side peripheral area 17c are respectively selected as the same distance a, but the present invention is not limited to this, and the distance a of the memory peripheral area 17b, the distance a of the drain side peripheral area 17a, and the distance a of the source side peripheral area 17c, or all of the distances, or any one of the distances, may be selected as different distances.

[0066] However, when the memory peripheral region 17b and the drain side peripheral region 17a are directly connected without providing the memory-drain region connecting portion 17d, in order to prevent the memory gate structure 10a and the drain side selection gate structure 11a from contacting each other, when the memory gate structure 10a and the drain side selection gate structure 11a are separately formed, if the memory peripheral region 17b and the drain side peripheral region 17a formed around the separated memory gate structure 10a and the drain side selection gate structure 11a are directly connected, the distances a in the surface direction of the memory peripheral region 17b and the drain side peripheral region 17a will also increase. Therefore, it may be difficult to reduce the distances a in the surface direction of the memory peripheral region 17b and the drain side peripheral region 17a.

[0067] In contrast, in the present embodiment, by providing a memory-drain region connecting portion 17d for connecting the memory peripheral region 17b and the drain side peripheral region 17a, even if it is assumed that the memory gate structure 10a and the drain side selection gate structure 11a are formed separately, the distance a in the surface direction between the memory peripheral region 17b and the drain side peripheral region 17a can be reduced. At the same time, the memory peripheral region 17b and the drain side peripheral region 17a can be reliably connected through the memory-drain region connecting portion 17d.

[0068] In addition, in the memory peripheral region 17b and the source side peripheral region 17c, by providing a memory-source region connecting portion 17e for connecting these memory peripheral region 17b and the source side peripheral region 17c, even if it is assumed that the memory gate structure 10a and the source side selection gate structure 12a are formed separately, the memory peripheral region 17b and the source side peripheral region 17c can be reliably connected through the memory-source region connecting portion 17e while reducing the distance a in the surface direction between the memory peripheral region 17b and the source side peripheral region 17c.

[0069] like Figure 6BAs shown, the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12a are formed in a columnar shape, and are vertically arranged on the substrate 20 via an insulating layer 23 and an insulating layer 24 made of an insulating material different from the insulating layer 23. In addition, for example, the substrate 20 is made of a component such as silicon, the insulating layer 23 is made of an insulating material such as a silicon oxide film and a silicon nitride film, and the insulating layer 24 is made of an insulating material such as Al2O3 and carbon or a semiconductor material such as silicon and SiC.

[0070] Columnar contact bonding portions 30a for connecting to contacts (not shown) are provided at upper ends of the memory gate electrode MG of the memory gate structure 10a, the drain side select gate electrode DG of the drain side select gate structure 11a, and the source side select gate electrode SG of the source side select gate structure 12a.

[0071] In addition, the memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG have a cylindrical enlarged diameter portion 30b and a cylindrical reduced diameter portion 30c having a smaller diameter than the enlarged diameter portion 30b, and below the contact junction portion 30a, the enlarged diameter portion 30b and the reduced diameter portion 30c are alternately arranged along the axial direction. The memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG are formed in a columnar shape by aligning the central axes of the contact junction portion 30a, the enlarged diameter portion 30b, and the reduced diameter portion 30c. In addition, in the present embodiment, the diameter of the contact junction portion 30a is formed to be larger than the diameter of the reduced diameter portion 30c and smaller than the diameter of the enlarged diameter portion 30b.

[0072] The contact joint portion 30a, the enlarged diameter portion 30b, and the reduced diameter portion 30c are formed at the same height of the memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG, respectively. That is, the structure has the following: the enlarged diameter portions 30b of the drain side selection gate electrode DG and the source side selection gate electrode SG are arranged on the side of the enlarged diameter portion 30b of the memory gate electrode MG, and the reduced diameter portions 30c of the drain side selection gate electrode DG and the source side selection gate electrode SG are arranged on the side of the reduced diameter portion 30c of the memory gate electrode MG.

[0073] On the memory gate electrode MG, a multilayer insulating layer 15 is formed along the circumferential direction on the side surfaces of the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c, and a multilayer insulating layer 15 is also formed on the bottom surface. In this case, the multilayer insulating layer 15 is formed with concavoconvexities on the side surfaces corresponding to the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c of the memory gate electrode MG, with a convex portion 31 formed on the expanded diameter portion 30b, and a concave portion 32 formed on the contact joint portion 30a and the reduced diameter portion 30c.

[0074] In addition, on the drain side selection gate electrode DG, the drain side selection gate insulating layer 14a is formed on the side surfaces of the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c along the circumferential direction, and the drain side selection gate insulating layer 14a is also formed on the bottom surface. Thus, on the drain side selection gate insulating layer 14a, concavities and convexities are formed on the side surfaces corresponding to the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c of the drain side selection gate electrode DG, a convex portion 31 is formed on the expanded diameter portion 30b, and a concave portion 32 is formed on the contact joint portion 30a and the reduced diameter portion 30c.

[0075] In addition, on the source side selection gate electrode SG, the source side selection gate insulating layer 14b is also formed along the circumferential direction on the side surfaces of the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c, and the source side selection gate insulating layer 14b is also formed on the bottom surface. Thus, on the source side selection gate insulating layer 14b, concavities and convexities are also formed on the side surfaces corresponding to the contact joint portion 30a, the expanded diameter portion 30b, and the reduced diameter portion 30c of the source side selection gate electrode SG, the convex portion 31 is formed on the expanded diameter portion 30b, and the concave portion 32 is formed on the contact joint portion 30a and the reduced diameter portion 30c.

[0076] In addition, on the insulating layer 24 provided on the substrate 20 via the insulating layer 23, the bit line BL, the source line SL, the drain diffusion layer 7, and the source diffusion layer 6 extending in the column direction X are provided on the layer where the memory gate structure 10a, the drain side selection gate structure 11a, and the expanded diameter portion 30b of the source side selection gate structure 12a are formed. In addition, the layered semiconductor layer 17 is provided on the region between the source diffusion layer 6 and the expanded diameter portion 30b of the source side selection gate structure 12a, the region between the expanded diameter portion 30b of the source side selection gate structure 12a and the expanded diameter portion 30b of the memory gate structure 10a, the region between the expanded diameter portion 30b of the memory gate structure 10a and the expanded diameter portion 30b of the drain side selection gate structure 11a, and the region between the expanded diameter portion 30b of the drain side selection gate structure 11a and the drain diffusion layer 7.

[0077] The bit line BL is connected to the side surface of the semiconductor layer 17 provided on the side surface of the enlarged diameter portion 30b of the drain side selection gate structure 11a through the drain diffusion layer 7. The source line SL is connected to the side surface of the semiconductor layer 17 provided on the side surface of the enlarged diameter portion 30b of the source side selection gate structure 12a through the source diffusion layer 6.

[0078] On the other hand, an insulating layer 19 and an interlayer insulating layer 25 are formed on the layer formed by the reduced diameter portion 30c of the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12a. At this time, the interlayer insulating layer 25 is provided between the upper semiconductor layer 17 and the lower semiconductor layer 17, and insulates the upper semiconductor layer 17 and the lower semiconductor layer 17 arranged in the vertical direction Z. In addition, the insulating layer 19 is provided between the upper bit line BL, the source line SL, the drain diffusion layer 7, and the source diffusion layer 6 and the lower bit line BL, the upper source line SL, the upper drain diffusion layer 7, and the upper source diffusion layer 6, and insulates the upper and lower bit lines BL, the upper and lower source lines SL, the upper and lower drain diffusion layers 7, and the upper and lower source diffusion layers 6 arranged in the vertical direction Z. In addition, a mask layer 27 is formed on the uppermost interlayer insulating layer 25d in the interlayer insulating layer 25.

[0079] In this way, the semiconductor layer 17, the bit line BL, the source line SL, the drain diffusion layer 7, and the source diffusion layer 6 are formed on the layer where the expanded diameter portions 30b of the memory gate electrode MG, the drain side selection gate electrode DG, and the source side selection gate electrode SG are arranged. In addition, the semiconductor layer 17 is formed so as to contact the multilayer insulation layer 15 formed on the side surfaces of the expanded diameter portions 30b, the side surfaces of the convex portions 31 of the drain side selection gate insulation layer 14a and the source side selection gate insulation layer 14b, the side surfaces of the drain diffusion layer 7, and the side surfaces of the source diffusion layer 6.

[0080] The memory cells Cb1, Cb2, Cb3, and Cb4 of different levels arranged along the vertical direction Z are respectively formed on the positions (layers) where the semiconductor layers 17 of the memory gate structure 10a, the drain side selection gate structure 11a, and the source side selection gate structure 12 are arranged, and can be insulated from each other by the interlayer insulating layer 25 located between the upper and lower semiconductor layers 17, and the insulating layer 19 located between the upper and lower bit lines BL, between the source lines SL, between the drain diffusion layers 7, and between the source diffusion layers 6.

[0081] In addition, the distance x1 in the surface direction of the semiconductor layer 17 formed between the multilayer insulating layer 15 and the drain side selection gate insulating layer 14a is the sum of the distance a in the surface direction of the memory peripheral region 17b, the distance a in the surface direction of the drain side peripheral region 17a, and the distance b in the surface direction of the memory-drain region connecting portion 17d. Similarly, the distance x1 in the surface direction of the semiconductor layer 17 formed between the multilayer insulating layer 15 and the source side selection gate insulating layer 14b is also the sum of the distance a in the surface direction of the memory peripheral region 17b, the distance a in the surface direction of the source side peripheral region 17c, and the distance b in the surface direction of the memory-source region connecting portion 17e.

[0082] (1-5) Data writing operation Next, the data writing operation in the memory cell C shown in FIG. 2 will be described. Fig. 7A It is a circuit diagram showing the structure of the equivalent circuit of the memory cell C. When writing data to the memory cell C, for example, a source voltage V of 1V is applied to the source line SL, and a source side gate voltage V smaller than the threshold voltage Vt of the source side selection transistor ST is applied to the source side selection gate electrode SG to make the source side selection transistor ST in the cut-off state. SL applied to the source line SL, and a source side gate voltage V smaller than the threshold voltage Vt of the source side selection transistor ST is applied to the source side selection gate electrode SG to make the source side selection transistor ST in the cut-off state. SGS applied to the source side selection gate electrode SG to make the source side selection transistor ST in the cut-off state.

[0083] In addition, at this time, a write bit voltage V of 0V is applied to the bit line BL (hereinafter, also referred to as the write selection bit voltage), and a drain side gate voltage V larger than the threshold voltage Vt of the drain side selection transistor DT is applied to the drain side selection gate electrode DG to make the drain side selection transistor DT in the on state. BL (hereinafter, also referred to as the write selection bit voltage), and a drain side gate voltage V larger than the threshold voltage Vt of the drain side selection transistor DT is applied to the drain side selection gate electrode DG to make the drain side selection transistor DT in the on state. SGD to make the drain side selection transistor DT in the on state.

[0084] Furthermore, for example, by applying a high voltage write memory gate voltage V of 10V to the memory gate electrode MG (hereinafter, also referred to as the write selection memory gate voltage), in the memory cell C, as shown, the semiconductor layer 17 near the outer periphery of the memory gate structure 10 becomes the same potential as the write selection bit voltage V. Thus, in the memory cell C, charges move between the charge storage layer 15b included in the multi-layer insulating layer 15 of the memory gate structure 10 and the semiconductor layer 17 and / or the memory gate electrode MG, and a state where data is written is achieved. CG0 (hereinafter, also referred to as the write selection memory gate voltage), so that in the memory cell C, as shown, the semiconductor layer 17 near the outer periphery of the memory gate structure 10 becomes the same potential as the write selection bit voltage V. Figure 7B shown, the semiconductor layer 17 near the outer periphery of the memory gate structure 10 becomes the same potential as the write selection bit voltage V. BL0 the same potential. Thus, in the memory cell C, charges move between the charge storage layer 15b included in the multi-layer insulating layer 15 of the memory gate structure 10 and the semiconductor layer 17 and / or the memory gate electrode MG, and a state where data is written is achieved.

[0085] In addition, in the multi-layer insulating layer 15 including the charge storage layer 15b, if the distance ta in the plane direction of the first memory gate insulating layer 15a is greater than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta>tc), there is a charge movement between the semiconductor layer 17 around the outer periphery of the second memory gate insulating layer 15c and the charge storage layer 15b. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta<tc), there is a charge movement between the memory gate electrode MG and the charge storage layer 15b.

[0086] Next, as shown in Fig. 8AAs shown, two memory cells C1 and C2 are arranged along the column direction X in the first layer of the upper layer, and two memory cells C3 and C4 are also arranged along the column direction X in the lower layer of the first layer. Taking a memory array CA in which one page is composed of the memory cells C1 and C3 arranged in the vertical direction Z and another page is composed of the memory cells C2 and C4 also arranged in the vertical direction Z as an example, the writing action of data in the memory array CA is explained.

[0087] Here, the case where the memory cell C1 among the memory cells C1, C2, C3, and C4 is used as the selected memory cell C1 for writing data is described. At this time, the page including the selected memory cell C1 for writing data is used as the write selected page, and the page consisting of only the non-selected memory cells C2 and C4 to which data is not written is used as the write non-selected page.

[0088] In addition, without specifically distinguishing between the memory transistors MT1, MT2, MT3, MT4, the drain side selection transistors DT1, DT2, DT3, DT4, and the source side selection transistors ST1, ST2, ST3, ST4, they are simply represented as the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST.

[0089] in addition, Figure 8B 2 shows an example of voltages of various parts in the memory array CA at this time. In the memory array CA, a write selection bit voltage V is applied to the selection bit line connected to the selected memory cell C1, that is, the bit line BL1. BL1 (For example, a low voltage of 0 to 1.5 V) A write selection drain gate voltage V higher than the threshold voltage Vt (preferably a positive value, also expressed as Vt(DT)) of the drain selection transistor DT is applied to the drain selection gate line BGL1 connected to the selected memory cell C1. SGD1 As a result, in the selected memory cell C1, the drain side selection transistor DT1 becomes conductive, and the selection bit voltage V is written. BL1 Delivered to memory transistor MT1.

[0090] In addition, in the memory array CA, a positive voltage (e.g., 1 to 2 V) is applied to all source lines SL. A write selection source side gate voltage Vt (preferably a positive value, also indicated as Vt(ST)) lower than the threshold voltage Vt of the source side selection transistor ST1 is applied to the source side selection gate line SGL1 connected to the selected memory cell C1. SGS1 As a result, in the selected memory cell C1, the source side selection transistor ST1 is turned off.

[0091] In addition, a write selection memory gate voltage V is applied to the word line WL1 connected to the selected memory cell C1.CG1 (e.g., a high voltage of 10 V). Thus, in the selected memory cell C1, the write-select memory gate voltage V of the word line WL1 is used to CG1 make the potential of the memory gate electrode MG high. For example, when ta > tc, electrons are injected from the semiconductor layer 17 into the charge storage layer 15b, or holes are injected from the charge storage layer 15b into the semiconductor layer 17, resulting in a state where data is written. Thus, the threshold voltage of the memory transistor MT1 of the selected memory cell C1 becomes high. On the other hand, when ta < tc, electrons escape from the charge storage layer 15b to the memory gate electrode MG, or holes are injected from the memory gate electrode MG into the charge storage layer 15b. Thus, the threshold voltage of the memory transistor MT1 of the selected memory cell C1 becomes low. As described above, charges move (are injected) into the charge storage layer 15b through the quantum channel effect, resulting in a state where data is written.

[0092] At this time, a write-non-select bit voltage V is applied to another bit line BL2 that is a non-select bit line not connected to the selected memory cell C1. BL2 The write-non-select bit voltage V BL2 is a positive voltage (e.g., 1.5 - 3 V) and is preferably a voltage higher than (V SGD1 - Vt). V SGD1 is the write-select drain-side gate voltage applied to the drain-side select gate line BGL1. Here, Vt is the threshold voltage of the drain-side select transistor DT (preferably a positive value), and is also denoted as Vt(DT).

[0093] Thus, in the non-select memory cell C3 in the write-select page where data is not written, the same voltage as that of the selected memory cell C1 is applied from the drain-side select gate line BGL1 shared with the selected memory cell C1 to the drain-side select gate electrode DG of the drain-side select transistor DT3. By applying the write-non-select bit voltage V BL2 to the bit line BL2 that is a non-select bit line, the drain-side select transistor DT3 is turned off.

[0094] In the write-select page, the non-select memory cell C3 shares the drain-side select gate line BGL1, the word line WL1, and the source-side select gate line SGL1 with the selected memory cell C1. However, the drain-side select transistor DT3 and the source-side select transistor ST3 of the non-select memory cell C3 are turned off. Therefore, in the non-select memory cell C3, even if a write-select memory gate voltage V CG1 (e.g., a high voltage of 7 - 10 V) is applied from the word line WL1 to the memory gate electrode MG, since the potential of the semiconductor layer 17 around the memory transistor MT3 rises, the write-select memory gate voltage V CG1Therefore, in the non-selected memory cell C3, the channel current does not flow into the charge storage layer 15b of the memory transistor MT3, and the injection of charges into the charge storage layer 15b can be blocked, thereby preventing the writing of data.

[0095] In addition, Fig. 8A In the figure, no illustration is given for the non-selected memory cells arranged on other columns in the write selection page (i.e., the memory cells arranged on the deeper side of the paper or the front side of the paper relative to the memory cells C1 and C3), but these non-selected memory cells also share the drain side selection gate line BGL1, word line WL1 and source side selection gate line SGL1 with the selection memory cell C1, and similarly to the above-mentioned non-selected memory cell C3, by applying the same voltage as the bit line BL2 and the source line SL2 to each bit line BL and the source line SL, respectively, the drain side selection transistor DT and the source side selection transistor ST are turned off, thereby preventing data from being written.

[0096] Next, a write non-selected page consisting only of non-selected memory cells C2 and C4 is described. In this case, since the bit lines BL1 and BL2 and the source lines SL1 and SL2 connected to the non-selected memory cells C2 and C4 are shared with the memory cells C1 and C3 in the above-mentioned write selected page, their description is omitted here, and the drain side selection gate line BGL2, the word line WL2 and the source side selection gate line SGL2 are described.

[0097] In writing non-selected pages, a low potential (for example, 0 V) ​​writing non-selected drain side gate voltage V is applied to the drain side selection gate line BGL2, the word line WL2, and the source side selection gate line SGL2. SGD2 , write non-select memory gate voltage V CG2 and write non-selected source side gate voltage V SGS2 . Thus, in each non-selected memory cell C2, C4 in which the non-selected page is written, at both ends of the memory transistors MT2, MT4, the drain side selection transistors DT2, DT4 and the source side selection transistors ST2, ST4 are respectively turned off, so that the channel current does not flow into the charge storage layer 15b of the memory transistors MT2, MT4, and the injection of charges into the charge storage layer 15b can be prevented, thereby preventing the writing of data. In addition, in each memory transistor MT of the non-selected memory cells C2, C3, C4, since the injection of charges into the charge storage layer 15b is prevented, the threshold voltage does not change.

[0098] In this way, in the memory array CA, data can be prevented from being written to the non-selected memory cells C2, C3, and C4, and data can be written only to the selected memory cell C1.

[0099] (1-6) Data clearing action Next, the operation of clearing data in the memory cell C shown in FIG. 2 will be described. Fig.9A 1 is a circuit diagram showing the structure of an equivalent circuit of a memory cell C. When data is cleared in the memory cell C, for example, a high voltage source voltage V SL Applied to the source line SL, the source voltage V SL A low high voltage (e.g., 7V) clear select source side gate voltage V SGS , is applied to the source side selection gate line SGL connected to the source side selection gate electrode SG of the source side selection transistor ST.

[0100] Similarly, the high voltage V BL Applied to the bit line BL, the bit voltage V BL A low high voltage (e.g. 7V) clear select drain side gate voltage V SGD , is applied to the drain side selection gate line BGL connected to the drain side selection gate electrode DG of the drain side selection transistor DT.

[0101] Furthermore, a clear selection memory gate voltage V of a negative voltage to 0 V (eg, -5 to 0 V) ​​is applied to the word line WL connected to the memory gate electrode MG of the memory transistor MT. CG0 In addition, at this time, the clear selection memory gate voltage V CG0 and clear select drain side gate voltage V SGD The potential difference and the clear selection memory gate voltage V CG0 and clear select source side gate voltage V SGS The potential difference is preferably 9V or more. For example, if the clear selection memory gate voltage V CG0 is 0V, then the drain side gate voltage V SGD and clear select source side gate voltage V SGS Set to 9V. In addition, if the clear select memory gate voltage V CG0 is -5V, then the drain side gate voltage V SGD and clear select source side gate voltage V SGS Set to 4V.

[0102] like Fig. 9BAs shown, during the data erasure operation, in the memory cell C, by applying a negative voltage to the memory gate electrode MG, due to the potential difference between the gate and the drain generated in the drain-side select transistor DT and the potential difference between the gate and the source generated in the source-side select transistor ST, junction breakdown is induced in the semiconductor layer 17 (the region indicated by "×" in the figure) near the drain diffusion layer 7 and the source diffusion layer 6, generating electron-hole pairs (junction current induction).

[0103] In the memory cell C, the electrons generated within the semiconductor layer 17 flow through the source line SL and the bit line BL, and holes (indicated by "h" in the figure) flow through the semiconductor layer 17 near the memory gate structure 10. As a result, the potential of the semiconductor layer 17 near the memory gate structure 10 rises. Thus, in the memory cell C, a potential difference is generated between the memory gate electrode MG and the surrounding semiconductor layer 17, and charges escape from within the charge storage layer 15b, resulting in a state where the data is erased.

[0104] In the multilayer insulating layer 15 including the charge storage layer 15b, if the distance ta in the plane direction of the first memory gate insulating layer 15a is greater than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta > tc), then during the data erasure operation, electrons escape from the charge storage layer 15b into the semiconductor layer 17, or holes are injected from the semiconductor layer 17 into the charge storage layer 15b. As a result, the threshold of the memory transistor MT decreases. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta < tc), then electrons are injected from the memory gate electrode MG into the charge storage layer 15b, or holes escape from the charge storage layer 15b and move to the memory gate electrode MG. As a result, the threshold of the memory transistor MT increases.

[0105] Next, similar to the above-mentioned "(1-5) Data writing operation", as Fig. 10A shown, taking a memory array CA in which the memory cells C1 and C3 arranged in the vertical direction Z form one page and the memory cells C2 and C4 arranged in the same vertical direction Z form another page as an example, the data erasure operation in this memory array CA will be described.

[0106] Here, a case where data is cleared in units of pages, data is cleared for a page composed of memory cells C1 and C3, and data is not cleared for a page composed of memory cells C2 and C4 is described. At this time, the page from which data is cleared is set as a clearing selected page, and the page composed of only non-selected memory cells C2 and C4 from which data is not cleared is set as a clearing non-selected page. In addition, the threshold voltage Vt of the drain side selection transistor DT and the source side selection transistor ST of the memory cells C1, C2, C3, and C4 is preferably a positive value.

[0107] in addition, Fig. 10B FIG. 8 is an example of voltages of various parts in the memory array CA at this time. In the memory array CA, the clear bit voltage V is applied to the bit lines BL1 and BL2 shared by the clear selected page and the clear non-selected page. BL (For example, a high voltage of 7 to 12 V), and a clearing voltage V is applied to the source lines SL1 and SL2. BL (For example, a high voltage of 7 to 12 V) The same voltage source voltage V SL .

[0108] In the clear selection page, for example, the clear selection drain side gate voltage V is set to a high voltage of 4 to 9 V. SGD1 The drain side select gate line BGL1 is applied to the drain side select gate line. Similarly, the clear select source side gate voltage V SGS1 is applied to the source side selection gate line SGL1. In addition, in the clear selection page, the clear selection memory gate voltage V CG1 This is applied to the word line WL1. Thus, in the erase selected page, in each of the memory cells C1 and C3, a potential difference is generated between the memory gate electrode MG and the surrounding semiconductor layer 17, and charges are transferred from the charge storage layer 15b, thereby erasing the data.

[0109] On the other hand, in the erase non-selected page, the same voltage as the bit lines BL1 and BL2 (for example, a high voltage of 7 to 12 V) is used as the erase non-selected drain side gate voltage V SGD2 , Clear the non-selected source side gate voltage V SGS2 and clear the non-select memory gate voltage V CG2 The voltage is applied to the drain side selection gate line BGL2, the source side selection gate line SGL2 and the word line WL2. Therefore, in erasing the non-selected page, in each memory cell C2, C4, no potential difference is generated between the memory gate electrode MG and the semiconductor layer 17 around it, and the charge does not escape from the charge storage layer 15b, which can prevent the data from being erased.

[0110] Furthermore, in the above embodiment, the case where data is erased in units of pages is described, but the present invention is not limited thereto, and all pages may be set as erase selection pages to erase data in all memory cells C constituting the memory array CA at once.

[0111] (1-7) Data reading action Next, the data reading operation in the memory array CA is described. In addition, here, similarly to the above-mentioned "(1-5) data writing operation", Fig.11A As shown, a memory array CA in which memory cells C1 and C3 arranged in the vertical direction Z constitute one page and memory cells C2 and C4 arranged in the vertical direction Z constitute another page is taken as an example to describe the data reading operation in the memory array CA.

[0112] Here, a case where data is read from the memory cells C1, C3, for example, as the selected memory cells C1, C3 among the memory cells C1, C2, C3, and C4 is described. At this time, a page including the selected memory cells C1, C3 for reading data is a read selected page, and a page consisting only of the non-selected memory cells C2, C4 for not reading data is a read non-selected page.

[0113] in addition, Fig. 11B 2 shows an example of voltages of various parts in the memory array CA at this time. In the memory array CA, a read bit voltage V is applied to the bit lines BL1 and BL2 shared by the read selected page and the read non-selected page. BL1 、V BL2 (all of which are the same positive voltage, such as 1V), and apply a read source voltage V SL (The source lines SL are all at the same voltage, for example, 0V).

[0114] In addition, in the read selection page, for example, a voltage higher than the threshold voltage Vt of the drain side selection transistor DT1 (for example, 2V) is set as the read selection drain side gate voltage V SGD1 The drain side selection gate line BGL1 is applied to the drain side selection gate line BGL1. Similarly, a voltage higher than the threshold voltage Vt of the source side selection transistor ST1 (for example, 2V) is used as the read selection source side gate voltage V SGS1 The voltage is applied to the source-side selection gate line SGL1 , thereby turning on the drain-side selection transistor DT1 and the source-side selection transistor ST1 of the selected memory cell C1 .

[0115] Furthermore, in the read selection page, for example, the read selection memory gate voltage V is set to 0 to 6V. CG1Applied to word line WL1. Thus, in the selected memory cell C1, if the threshold voltage Vt of the memory transistor MT1 is lower than the read selection memory gate voltage V CG1 , current flows from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 changes.

[0116] On the other hand, when the threshold voltage Vt of the memory transistor MT1 is higher than the read selection memory gate voltage V CG1 In this case, current does not flow from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 does not change. Then, by using the column decoder 2b ( Figure 1 ) detects the change in the potential of the bit line BL1, and can read the data of the selected memory cell C1. Figure 1 ) detects the change in the potential of the bit line BL2, and data can be read similarly from another selected memory cell C3 in the read selected page.

[0117] In reading the non-selected page, a voltage lower than the threshold voltage Vt of the drain-side selection transistor DT2 (for example, 0V) is used as the non-selected drain-side gate voltage Vt. SGD2 The drain side selection gate line BGL2 is applied. Similarly, a voltage lower than the threshold voltage Vt of the source side selection transistor ST (for example, 0V) is used as the reading non-selected source side gate voltage V SGS2 Applied to the source side selection gate line SGL2.

[0118] Thus, the drain side selection transistors DT and source side selection transistors ST of the non-selected memory cells C2 and C4 of the read non-selected page are turned off, and current does not flow from the source lines SL1 and SL2 to the bit lines BL1 and BL2. As described above, data is read only from the selected memory cells C1 and C3 of the read selected page.

[0119] In addition, in the case of detecting multi-value data in one memory cell C, by changing the read selection memory gate voltage V CG1 By detecting the change in the potential of the bit line BL1 at each voltage value, it is possible to detect the fine threshold voltage of the memory transistor MT and read multi-value data.

[0120] in addition, Fig. 11C 1 shows an example of voltages of various parts in a data reading operation according to another embodiment. In this case, in a read selection page, the read selection memory gate voltage V CG1 As a fixed voltage is applied to the word line WL1. At this time, if the threshold voltage of the memory transistor MT1 in the selected memory cell C1 is lower than the read selection memory gate voltage VCG1 , the current flows from the source line SL1 to the bit line BL1.

[0121] The cell current flowing from the source line SL1 to the bit line BL1 through the selected memory cell C1 is determined by the read selected memory gate voltage V CG1 The threshold difference (V CG1 The column decoder 2b detects the magnitude of the cell current flowing from the source line SL1 to the bit line BL1 via the selected memory cell C1, and the column decoder 2b determines the threshold voltage Vt of the memory transistors MT1 and MT3 to determine whether data is written into the memory transistors MT1 and MT3.

[0122] In this case, the data written to the memory transistors MT1 and MT3 can be distinguished according to the value of the cell current flowing from the source line SL1 to the bit line BL1 via the selected memory cell C1, so as to read multi-valued data. Fig. 11B The same, so the description is omitted here.

[0123] (1-8) Specific Examples of Voltages in Data Writing, Erasing, and Reading Operations Specific examples (voltage examples) of voltage combinations in the above-described data writing operation, erasing operation, and reading operation are shown in the following Table 1. The unit of the voltage values ​​shown in Table 1 is "V".

[0124] In Table 1, "BL column" indicates a column of a memory cell C group electrically connected to a bit line BL extending from a column decoder 2b in a column direction X. Figure 1 As shown in FIG. 1 , the column decoder 2 b is configured as a two-dimensional structure of the row direction Y and the vertical direction Z as the paper depth direction in the figure. There are two directions in the BL column, the row direction Y and the vertical direction Z as the paper depth direction. Strictly speaking, they can also be defined. However, in Table 1, in order to simplify the description, the row direction Y and the vertical direction Z as the paper depth direction are not particularly distinguished, and the focus is on Fig. 8A , Fig. 10A and Fig.11A The actions are organized into selected and non-selected pages as shown.

[0125] Table 1

[0126] In the nonvolatile semiconductor memory device 1 , as shown in Table 1, by applying voltages respectively, the voltages can be adjusted in units of pages in the memory array CA, and data can be selectively written, erased, and read for predetermined memory cells C.

[0127] (1-9) Method for manufacturing a memory array according to another embodiment Next, a method for manufacturing a memory array CA composed of memory cells Cb according to another embodiment shown in FIG. 6 will be described. Figure 3 , Figure 4 and Figure 5 The manufacturing method of the memory array CA shown can also be applied to the manufacturing method of the third embodiment described later, so the description thereof is omitted here.

[0128] Fig.12 28 is a schematic diagram showing the position of the cross-sectional portion used in explaining each manufacturing process, and represents the outer contour of the area formed by the memory gate structure 10a, the drain side selection gate structure 11a, the source side selection gate structure 12a, and the semiconductor layer 17 of the memory cell Cb shown in FIG. 6 when viewed from above (hereinafter referred to as the memory cell formation area).

[0129] exist Fig.12 , three memory cell formation regions 28a, 28b, and 28c are arranged in parallel. In addition, since the three memory cell formation regions 28a, 28b, and 28c have the same structure, they are simply referred to as memory cell formation regions 28 when there is no need to distinguish them.

[0130] In the memory cell formation region 28, the region formed by the drain side selection gate structure 11a and the drain side peripheral region 17a of the semiconductor layer 17 shown in Figure 6 is the drain side formation region 117a, the region formed by the memory gate structure 10a and the memory peripheral region 17b of the semiconductor layer 17 is the memory formation region 117b, and the region formed by the source side selection gate structure 12a and the source side peripheral region 17c of the semiconductor layer 17 is the source side formation region 117c.

[0131] In addition, in the memory cell forming region 28, an area where a memory-drain region connecting portion 17d is formed for connecting the memory peripheral region 17b and the drain side peripheral region 17a shown in FIG6 is a memory-drain connection setting forming region 117d, and an area where a memory-source region connecting portion 17e is formed for connecting the memory peripheral region 17b and the source side peripheral region 17c is a memory-source connection setting forming region 117e.

[0132] Next, a method for manufacturing the memory array CA will be described using FIGS. 13 to 22. Fig.13A , 13BAs shown in FIG. 13C, an insulating layer 23 and another insulating layer 24 of a different type from the insulating layer 23 are stacked on a substrate 20 made of silicon, for example, and further, a layered interlayer insulating layer 25a made of, for example, a silicon oxide film and another layered interlayer insulating layer 33 made of, for example, a silicon nitride film are alternately stacked on the insulating layer 24. In addition, a mask layer 27a for masking made of Al2O3, carbon, SiC, etc. having the same outer contour shape as the memory cell formation region 28b is formed on the interlayer insulating layer 25a located at the uppermost layer, and the interlayer insulating layers 25a and 33 are etched using the mask layer 27a as a mask.

[0133] Thus, interlayer insulating layers 25a and 33 having the same outer contour shape as the outer contour shape of the memory cell forming regions 28a, 28b, and 28c are formed. The insulating layer 24 is exposed in the region ER1 where the interlayer insulating layers 25a and 33 are etched. In the following, since the memory cell forming regions 28a, 28b, and 28c are manufactured in the same manner, the focus is on the region ER2. Fig.12 Each cross-sectional portion of the memory cell formation regions 28a and 28b shown will be described below.

[0134] Next, by dry etching such as reactive ion etching, the interlayer insulating layer 33 sandwiched by the interlayer insulating layer 25a among the alternately stacked interlayer insulating layers 25a and 33 is selectively side-etched from the surface direction of the substrate 20, as shown in FIG. Fig.14A , as shown in 14B and 14C, there are formed: a gap 35 where the interlayer insulating layer 33 is removed; and a columnar interlayer insulating layer 33a where the interlayer insulating layer 33 remains in a columnar shape.

[0135] The columnar interlayer insulating layer 33a is formed at a predetermined position where the drain side selection gate electrode DG, the memory gate electrode MG, and the source side selection gate electrode SG are formed in the memory cell formation region 28b. In addition, the diameter of the columnar interlayer insulating layer 33a is formed to be substantially the same as the diameter of the drain side selection gate electrode DG, the memory gate electrode MG, and the source side selection gate electrode SG to be formed.

[0136] Thus, in the memory cell formation region 28, the columnar interlayer insulating layer 33a is formed only at the predetermined positions where the drain side selection gate electrode DG, the memory gate electrode MG, and the source side selection gate electrode SG are formed, and the gap 35 is formed around the columnar interlayer insulating layer 33a. Fig. 14C As shown, a gap 35 is formed in the memory-drain connection arrangement forming region 117d.

[0137] Then, if Fig.15A , 15BAs shown in FIG. 15C , for example, by depositing a semiconductor material such as polysilicon, the gaps 35 between the stacked interlayer insulating layers 25a are filled with the semiconductor material, thereby forming a semiconductor layer 36a in the gaps 35. In addition, at this time, the semiconductor material is also deposited on the exposed insulating layer 24 other than the memory cell formation region 28b, on the side of the memory cell formation region 28b, and on the mask layer 27a to form the semiconductor layer 36b. Then, the surface is polished to remove the semiconductor material deposited on the mask layer 27a, so that the mask layer 27a is exposed.

[0138] Next, the semiconductor layer 36b in the area not covered by the mask layer 27a is removed using the mask layer 27a as a mask. Fig.16A , 16B As shown in FIG. 16C, in the region ER1 where the insulating layer 24 is exposed, an insulating material such as a silicon oxide film is deposited in the region ER1 to form an insulating layer 19, and then the surface is polished to remove the interlayer insulating layer formed on the mask layer 27a to expose the mask layer 27a.

[0139] Then, if Fig.17A , 17B As shown in FIG. 17C , for example, a new patterned mask layer 40 made of a photoresist material or the like is formed on the existing mask layer 27a and the insulating layer 19. An opening 40a is formed in the new mask layer 40 in accordance with a predetermined position where the memory gate electrode MG is to be formed. In addition, the diameter of the opening 40a is formed to be slightly larger than the distance in the surface direction of the columnar interlayer insulating layer 33a.

[0140] Next, using the mask layer 40 as a mask, the mask layer 27a, interlayer insulating layer 25a, and columnar interlayer insulating layer 33a exposed from the opening 40a are etched by dry etching to form a hole ER2 for forming a memory gate electrode in which the surface of the insulating layer 24 is exposed from the opening 40a.

[0141] Here, when etching the mask layer 27a, the interlayer insulating layer 25a, and the columnar interlayer insulating layer 33a, an etching method that does not etch the semiconductor layer 36a is used, so that the semiconductor layer 36a remains in the hole ER2 for forming the memory gate electrode. As a result, in the hole ER2 for forming the memory gate electrode, a hole ER4 having an opening diameter equal to the opening 40a of the mask layer 40 is formed in the mask layer 27a and the interlayer insulating layer 25b between the new mask layer 40 and the uppermost semiconductor layer 36a. In addition, in the hole ER2 for forming the memory gate electrode, a hole ER3 having an opening diameter smaller than the hole ER4 and having the diameter of the removed columnar interlayer insulating layer 33a is formed, in which the uppermost semiconductor layer 36a serves as a mask.

[0142] In addition, the opening portion 40a of the mask layer 40 is formed to be slightly larger than the diameter of the columnar interlayer insulating layer 33a provided between the semiconductor layers 36a arranged in the surface direction, thereby being able to reliably remove the columnar interlayer insulating layer 33a between the semiconductor layers 36a arranged in the surface direction during etching.

[0143] Then, if Fig.18A , 18B As shown in Figs. 18C, after removing the mask layer 40, the semiconductor layer 36a exposed in the hole ER2 for forming the memory gate electrode is selectively etched by dry etching to form a semiconductor layer 36c in which the distance of the semiconductor layer 36a in the surface direction is narrowed. Fig.18A As shown, a hole ER6 for forming a memory gate electrode is formed in a gap between semiconductor layers 36c adjacent to each other in the plane direction.

[0144] Here, if Fig.18B As shown, the distance in the surface direction of the semiconductor layer 36c in the memory cell formation regions 28a and 28b is selected to be the optimal distance a smaller than 40 nm as described above.

[0145] In addition, the width of the gap in the uppermost interlayer insulating layer 25b located directly under the mask layer 27a is slightly larger than the width of the gap in the lower interlayer insulating layer 25c, so the uppermost semiconductor layer 36c portion located directly under the uppermost interlayer insulating layer 25b is likely to be more side-etched than the semiconductor layer 36c below it. Therefore, the uppermost semiconductor layer 36c is not used as the memory cell Cb, but it is preferred to form the memory cell Cb in the semiconductor layer 36c portion below the uppermost semiconductor layer 36c.

[0146] Then, if Fig.19A , 19B As shown in FIG. 19C, after forming the multilayer insulating layer 15 along the side and bottom surfaces in the hole ER6 for forming the memory gate electrode, a gate material such as low-resistance polysilicon or metal such as tungsten is deposited on the multilayer insulating layer 15, thereby forming the memory gate electrode MG in the area surrounded by the multilayer insulating layer 15. Then, the insulating material or the gate material of the multilayer insulating layer 15 deposited on the mask layer 27a or the insulating layer 19 is removed by surface grinding to expose the mask layer 27a. In this way, the memory gate structure 10a is formed in the hole ER6 for forming the memory gate electrode.

[0147] In addition, as shown in Figure 6, the multilayer insulating layer 15 is formed by stacking in sequence a second memory gate insulating layer 15c composed of silicon oxide (SiO2) or the like, a charge storage layer 15b composed of silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), or the like, and a first memory gate insulating layer 15a composed of silicon oxide (SiO2) or the like on the side and bottom surfaces of the hole ER6 for forming a memory gate electrode.

[0148] Then, if Fig. 20A , 20B As shown in FIG. 20C, for example, a new patterned mask layer 42 made of a photoresist material or the like is formed on the existing mask layer 27a, the memory gate structure 10a, and the insulating layer 19. In the new mask layer 42, openings 42a are formed at respective predetermined positions for forming the drain side selection gate electrode DG and the source side selection gate electrode SG. In addition, the diameter of the opening 42a is formed to be slightly larger than the distance in the surface direction of the columnar interlayer insulating layer 33a.

[0149] Next, using the new mask layer 42 as a mask, the existing mask layer 27a, interlayer insulating layer 25b, and columnar interlayer insulating layer 33a exposed from the opening 42a are etched by dry etching to form holes ER8 for forming selection gate electrodes on the surface of the insulating layer 24 exposed from the opening 42a.

[0150] Here, the columnar interlayer insulating layer 33a is removed by etching, and when the mask layer 27, the interlayer insulating layer 25d, and the 25 having the hole ER8 are formed, an etching method is used in which the semiconductor layer 36c is not etched, so that the semiconductor layer 36c remains in the hole ER8 for forming the selection gate electrode. As a result, in the hole ER8 for forming the selection gate electrode, a hole ER9 having an opening diameter equal to the opening 42a of the mask layer 42 is formed in the mask layer 27 and the interlayer insulating layer 25d located between the new mask layer 42 and the uppermost semiconductor layer 36c. In addition, in the hole ER8 for forming the selection gate electrode, a hole ER10 having an opening diameter smaller than the hole ER9 and having the diameter of the removed columnar interlayer insulating layer 33a is formed, in which the uppermost semiconductor layer 36c serves as a mask.

[0151] Furthermore, the opening 42a of the mask layer 42 is formed slightly larger than the diameter of the columnar interlayer insulating layer 33a provided between the semiconductor layers 36c, thereby making it possible to reliably remove the columnar interlayer insulating layer 33a between the semiconductor layers 36c during etching.

[0152] Then, if Fig.21A , 21BAs shown in Figs. 21C, after removing the mask layer 42, the semiconductor layer 36c exposed in the hole ER8 for forming the selection gate electrode is selectively etched by dry etching to form a semiconductor layer 17 having a narrower distance in the plane direction. Fig.21A As shown, a hole ER12 for forming a selection gate electrode is formed in which the width in the plane direction (space width) x5 of the space between semiconductor layers 17 adjacent to each other in the plane direction is approximately 5 to 7 times that of the semiconductor layer 17 .

[0153] Here, in the hole ER12 in which the drain side selection gate structure 11a is formed, the gap width x5 between the semiconductor layers 17 adjacent in the surface direction becomes the diameter of the expanded diameter portion 30b of the drain side selection gate structure 11a to be formed in the hole ER12 (that is, the diameter of the drain side selection gate electrode DG and the drain side selection gate insulating layer 14a combined in the expanded diameter portion 30b).

[0154] In addition, in the hole ER12 in which the source side selection gate structure 12a is formed, the gap width x5 between the semiconductor layers 17 adjacent in the plane direction becomes the diameter of the enlarged diameter portion 30b of the source side selection gate structure 12a to be formed in the hole ER12 (that is, the diameter of the source side selection gate electrode SG and the source side selection gate insulating layer 14b combined in the enlarged diameter portion 30b). At this time, Fig.21A and 21B As shown, the distance a in the surface direction of the semiconductor layer 17 in the drain-side formation region 117 a and the source-side formation region 117 c is selected to be less than 40 nm as described above.

[0155] In addition, as described above, the width of the gap in the uppermost interlayer insulating layer 25d located directly below the mask layer 27 is slightly larger than the width of the gap in the lower interlayer insulating layer 25, and therefore, the uppermost semiconductor layer 17 portion located directly below the uppermost interlayer insulating layer 25d may be more side-etched than the lower semiconductor layer 17. Therefore, the uppermost semiconductor layer 17 is not used as the memory cell Cb, and the memory cell Cb is preferably formed in the portion of the semiconductor layer 17 that is lower than the uppermost semiconductor layer 17.

[0156] Next, insulating materials such as silicon oxide films are deposited on the side and bottom surfaces of the hole ER12 for forming the selection gate electrode. Fig.22A , 22BAs shown in FIG. 22C, a drain side selection gate insulating layer 14a and a source side selection gate insulating layer 14b are formed along the side and bottom surfaces of the hole ER12 for forming the selection gate electrode. Next, a gate material such as low-resistance polysilicon or metal such as tungsten is deposited on the drain side selection gate insulating layer 14a and the source side selection gate insulating layer 14b, respectively, so that a drain side selection gate electrode DG and a source side selection gate electrode SG are formed in the region surrounded by the drain side selection gate insulating layer 14a and the source side selection gate insulating layer 14b.

[0157] Then, the insulating material or the gate material of the drain side selection gate insulating layer 14a and the source side selection gate insulating layer 14b deposited on the mask layer 27 or the insulating layer 19 is removed by surface grinding to expose the mask layer 27. In addition, in FIG6 and FIG22, the structure in which the mask layer 27 is left as it is is formed, but it is preferable to remove the mask layer 27 by surface grinding.

[0158] In this way, the drain side selection gate structure 11 a and the source side selection gate structure 12 a are formed in the hole ER12 for forming the memory gate electrode.

[0159] Next, by using a general semiconductor manufacturing process using a film forming technology such as photolithography technology, CVD (Chemical Vapor Deposition), an etching technology, and an ion implantation method, a drain diffusion layer 7 and a bit line BL are formed in a region of the insulating layer 19 adjacent to the drain side forming region 117a, and a source diffusion layer 6 and a source line SL are formed in a region of the insulating layer 19 adjacent to the source side forming region 117c. At this time, the drain diffusion layer 7 and the bit line BL, the source diffusion layer 6 and the source line SL, as shown in FIG. Fig.22A As shown, the insulating layer 19 is formed on the layer where the semiconductor layer 17 is formed. In addition, the insulating layer 19 is formed between the upper layer and the lower layer where the drain diffusion layer 7 and the bit line BL are formed, or between the upper layer and the lower layer where the source diffusion layer 6 and the source line SL are formed. As described above, the memory cell Cb shown in FIG. 6 can be formed.

[0160] (1-10) Function and Effect In the above structure, the memory cell C is configured as follows: in the area between the parallel drain diffusion layer 7 and the source diffusion layer 6 extending in the surface direction of the substrate 20, a columnar memory gate electrode MG is arranged upright on the substrate 20 through the insulating layer 19; in the area between the drain diffusion layer 7 and the memory gate electrode MG, a columnar drain side selection gate electrode DG is arranged upright on the substrate 20 through the insulating layer 19; in the area between the source diffusion layer 6 and the memory gate electrode MG, a columnar source side selection gate electrode SG is arranged upright on the substrate 20 through the insulating layer 19.

[0161] In addition, a multilayer insulating layer 15 including a charge storage layer 15b is provided on the side of the memory gate electrode MG, a drain side selection gate insulating layer 14a is provided on the side of the drain side selection gate electrode DG, and a source side selection gate insulating layer 14b is provided on the side of the source side selection gate electrode SG.

[0162] In addition, in the memory cell C, a semiconductor layer 17 is set in the area between the parallel drain diffusion layer 7 and the source diffusion layer 6, and the semiconductor layer 17 is in contact with the side surface of the drain side selection gate insulation layer 14a, the side surface of the source side selection gate insulation layer 14b, the side surface of the multilayer insulation layer 15, the side surface of the drain diffusion layer 7, and the side surface of the source diffusion layer 6, respectively.

[0163] Thus, in this embodiment, a three-dimensional structure is realized for the memory cell C obtained by connecting the memory transistor MT, the drain side selection transistor DT and the source side selection transistor ST in series. By making the memory cell C a three-dimensional structure, the memory cell C can be integrated and miniaturized without being restricted by two-dimensional scaling.

[0164] In addition, the memory gate structure 10 of the present embodiment has a multilayer insulating layer 15 provided along the circumferential direction on the side surface of the cylindrical memory gate electrode MG, and the side surface of the multilayer insulating layer 15 in contact with the semiconductor layer 17 has no corners and has a shape with a smoothly curved side surface. In addition, the drain side selection gate structure 11 also has a drain side selection gate insulating layer 14a provided along the circumferential direction on the side surface of the cylindrical drain side selection gate electrode DG, and the side surface of the drain side selection gate insulating layer 14a in contact with the semiconductor layer 17 has no corners and has a shape with a smoothly curved side surface. In addition, the source side selection gate structure 12 also has a source side selection gate insulating layer 14b provided along the circumferential direction on the side surface of the cylindrical source side selection gate electrode SG, and the side surface of the source side selection gate insulating layer 14b in contact with the semiconductor layer 17 has no corners and has a shape with a smoothly curved side surface.

[0165] However, in a general two-dimensional memory cell, the gate electrode is formed of a planar gate structure, and during a data writing operation, the electric field is concentrated on the corners of the gate electrode, which may reduce disturbance immunity.

[0166] In contrast, in the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 of the present embodiment, as described above, there are no corners on the side surfaces in contact with the semiconductor layer 17, and the side surfaces are formed into a smooth curved shape, so there are no areas where the electric field is concentrated. Therefore, compared with the existing planar gate type structure, the anti-interference performance can be improved accordingly.

[0167] (1-11) Other Implementation Methods In addition, the present invention is not limited to the above-mentioned embodiment. For example, instead of the drain side selection gate insulating layer 14a and the source side selection gate insulating layer 14b composed of only a single layer of insulating material, a drain side selection gate insulating layer 14a and a source side selection gate insulating layer 14b having a multilayer structure including a charge storage layer may be applied in the same manner as the multilayer insulating layer 15.

[0168] In this case, for example, as shown in FIG. 18 and FIG. 19 , it is only necessary to simultaneously manufacture the drain side selection gate structure 11a and the source side selection gate structure 12a in the process of manufacturing the memory gate structure 10a. Specifically, when forming the hole ER2 for forming the memory gate electrode, the hole ER8 for forming the selection gate electrode is formed, and in the process of forming the multilayer insulating layer 15, the drain side selection gate insulating layer and the source side selection insulating layer having the same structure as the multilayer insulating layer 15 are manufactured simultaneously with the multilayer insulating layer 15, and in the process of forming the memory gate electrode MG, it is only necessary to simultaneously form the drain side selection gate electrode DG and the source side selection gate electrode SG with the memory gate electrode MG.

[0169] In addition, in the present embodiment, as the columnar memory gate electrode, the columnar drain side selection gate electrode, and the columnar source side selection gate electrode, the cylindrical memory gate electrode MG, the cylindrical drain side selection gate electrode DG, and the cylindrical source side selection gate electrode SG are used, but the present invention is not limited thereto, and for example, columnar memory gate electrodes, columnar drain side selection gate electrodes, and columnar source side selection gate electrodes formed in various shapes such as quadrangular prisms and polygonal prisms may also be applied. In addition, in this case, the multilayer insulating layer, the drain side selection gate insulating layer, and the source side selection gate insulating layer are formed around the shape of each side surface of the memory gate electrode, the drain side selection gate electrode, and the source side selection gate electrode.

[0170] In addition, in the present embodiment, as a structure in which the semiconductor layer is in contact with each side surface of the drain side selection gate insulating layer, the source side selection gate insulating layer, the multilayer insulating layer, the drain diffusion layer, and the source diffusion layer, for example, as shown in FIG. 2 , the semiconductor layer 17 is also provided between the drain diffusion layer 7 and the drain side selection gate insulating layer 14 a, and the semiconductor layer 17 is also provided between the source diffusion layer 6 and the source side selection gate insulating layer 14 b, but the present invention is not limited thereto. For example, it is also possible to configure that the semiconductor layer 17 is not provided between the drain diffusion layer 7 and the drain side selection gate insulating layer 14 a so that the side surface of the drain diffusion layer 7 is in contact with the side surface of the drain side selection gate insulating layer 14 a, or that the semiconductor layer 17 is not provided between the source diffusion layer 6 and the source side selection gate insulating layer 14 b so that the side surface of the source diffusion layer 6 is in contact with the side surface of the source side selection gate insulating layer 14 b.

[0171] In addition, in this embodiment, multiple memory cells are configured in multiple rows, multiple columns, and multiple levels, but the present invention is not limited to this. The number of rows, columns, and levels only needs to be greater than 1. For example, it can be 1 row, multiple columns, and multiple levels, or multiple rows, 1 column, and 1 level.

[0172] (1-12) Memory Cell of Another Embodiment in Which a Plurality of Memory Transistors Is Provided Between a Drain-Side Select Transistor and a Source-Side Select Transistor (1-12-1) Structure of Nonvolatile Semiconductor Memory Device In addition, in the above-mentioned embodiment, a case is described in which a memory cell C having a memory transistor MT is provided between a pair of drain side selection transistors DT and source side selection transistors ST, but the present invention is not limited to this, and a memory cell formed by connecting a plurality of memory transistors in series may also be provided between a pair of drain side selection transistors DT and source side selection transistors ST.

[0173] here, Fig.23 1 is a circuit diagram showing the structure of an equivalent circuit of a nonvolatile semiconductor memory device 1h having a memory cell Ch in which a plurality of memory transistors MT11 and MT12 are arranged in series. In addition, here, when distinguishing between the individual memory cells, i and j are 1, 2, 3, ..., respectively, and the memory cell in the i-th row and j-th column is the memory cell Ch. ij In the description, when the memory cells are not distinguished, they are described only as the memory cell Ch.

[0174] In addition, the nonvolatile semiconductor storage device 1h is actually Figure 1The nonvolatile semiconductor memory device 1 shown in FIG. 1 also has a memory array CAh, wherein the memory array CAh is obtained by arranging a plurality of memory cells Ch arranged in a matrix in the plane direction in a hierarchical manner along a vertical direction Z orthogonal to the plane direction. In addition, in the arrangement structure of the plurality of memory cells Ch arranged in a matrix in each hierarchy, since each hierarchy is the same, Fig.23 , only the arrangement structure of the plurality of memory cells Ch arranged in the first layer in the upper layer is shown, and the arrangement structure of the plurality of memory cells Ch arranged in the lower layer is omitted.

[0175] Fig.23 The memory array CAh shown in FIG. 1 shows an example in which a plurality of memory cells Ch are arranged in 4 rows and 2 columns in the plane direction. Figure 1 Similarly, a structure including a plurality of memory cells Ch arranged in different layers and columns and arranged in a row direction Y (a vertical plane direction extending in the row direction Y orthogonal to the plane direction (a normal direction to the plane direction)) is called a page ( Figure 1 In addition, a plurality of pages in which the first memory transistor MT11 shares the first word line WL1 and the second memory transistor MT12 shares the second word line WL2 are referred to as one segment for description.

[0176] In addition, Fig.23 In the example of setting two segments (i) and (j), two pages (i, 1) and (i, 2) are set in one segment (i), and two pages (j, 1) and (j, 2) are also set in the other segment (j). Here, when the segments or pages, word lines WL, drain side selection gate lines BGL, and source side selection gate lines SGL respectively set in the segments are distinguished, they are marked i and j for description. When they are not particularly distinguished, i and j are not indicated, and they are only described as segments, pages, word lines WL, drain side selection gate lines BGL, and source side selection gate lines SGL.

[0177] In this case, the bit line BL is Figure 1 Similarly, in each layer of the memory array CAh, the source lines SL are extended in the column direction X and connected to a plurality of memory cells Ch arranged in the same column in each layer. Figure 1 Similarly, in each layer of the memory array CAh, the bit lines BL are arranged in parallel with each other in the column direction X, and are connected to the memory cells Ch in the same column in each layer. That is, in each layer, a plurality of memory cells Ch arranged in the column direction X share one bit line BL and one source line SL.

[0178] In addition, the drain side selection gate line BGL and the source side selection gate line SGL are provided for each row (page), and are connected to a plurality of memory cells Ch arranged in the same row (in the same page) including different layers. That is, in the memory cells Ch in the page arranged along the row direction Y including different layers, there is a drain side selection gate line BGL and a source side selection gate line SGL.

[0179] For example, in a segment (i), for a plurality of memory cells Ch located in a page (i, 1) 11 , Ch 12 , the drain side selection gate electrode DG of each drain side selection transistor DT is connected to the drain side selection gate line BGL (i, 1), and the source side selection gate electrode SG of each source side selection transistor ST is connected to the source side selection gate line SGL (i, 1). In addition, in the segment (i), for a plurality of memory cells Ch in another page (i, 2) 21 , Ch 22 Another drain side selection gate line BGL (i, 2) is connected to the drain side selection gate electrode DG of each drain side selection transistor DT, and another source side selection gate line SGL (i, 2) is connected to the source side selection gate electrode SG of each source side selection transistor ST.

[0180] The word line WL1 (WL2) is provided for each segment and connected to a plurality of memory transistors MT11 (MT12) arranged in the same segment, including different pages and different levels. For example, in segment (i), including different pages (i, 1), (i, 2), and different levels, a plurality of first memory transistors MT11 provided in the segment (i) share a first word line WL1 (i), and a plurality of second memory transistors MT12 provided in the segment (i) share a second word line WL2 (i).

[0181] More specifically, in segment (i), the memory gate electrode MG of the first memory transistor MT11 disposed in one page (i, 1), the memory gate electrode MG of the first memory transistor MT11 disposed in another page (i, 2), and the first word line WL1 (i) are connected. In addition, in segment (i), the memory gate electrode MG of the second memory transistor MT12 disposed in one page (i, 1), the memory gate electrode MG of the second memory transistor MT12 disposed in another page (i, 2), and the second word line WL2 (i) are connected.

[0182] Thus, in the memory array CAh, among the multiple pages (i, 1) and (i, 2) arranged in a segment (i), there is a common first word line WL1(i) in the first memory transistor MT11, and a common second word line WL2(i) in the second memory transistor MT12. Therefore, the word line WL is not set separately for each page (i, 1) and (i, 2), and the structure can be simplified accordingly.

[0183] The memory array CAh has the following structure: the drain side selection gate line BGL, the source side selection gate line SGL and the word lines WL1 and WL2 do not extend along the row direction Y in the second layer which is the lower layer not shown in the figure, but only extend along the row direction Y in the first layer which is the upper layer, and the drain side selection gate line BGL, the source side selection gate line SGL and the word lines WL1 and WL2 arranged in the upper layer are also electrically connected to each memory cell Ch arranged in the lower layer, respectively.

[0184] Here, about Fig.23 The cross-sectional structure of the memory cell Ch represented by the equivalent circuit in the top view is shown in FIG. Figure 2B The structure of the memory cell C shown has a cross-sectional structure in which a plurality of memory gate structures 10 are arranged linearly between a pair of drain-side select gate structures 11 and source-side select gate structures 12 , and therefore detailed descriptions thereof are omitted here to avoid duplication of descriptions.

[0185] In addition, regarding Fig.23 The longitudinal cross-sectional structure of the memory cell Ch in the vertical direction Z represented by the equivalent circuit in FIG. Figure 4 The memory cell C shown has a longitudinal cross-sectional structure in which a plurality of memory gate structures 10 are arranged linearly between a pair of drain-side select gate structures 11 and source-side select gate structures 12 , and therefore detailed descriptions thereof are omitted to avoid duplication of descriptions.

[0186] In addition, for the multiple memory gate structures 10, drain side selection gate structures 11 and source side selection gate structures 12 of the memory array CAh, as shown in Figure 6, the expanded diameter portions 30b and the reduced diameter portions 30c can be alternately arranged on the side surfaces of the memory gate electrode MG, the drain side selection gate electrode DG and the source side selection gate electrode SG, respectively, so that the side surfaces can be formed into a concave-convex shape.

[0187] In addition, in this way, the memory array CAh in which the expanded diameter portions 30b and the reduced diameter portions 30c are alternately formed on the side surfaces of the plurality of memory gate electrodes MG, the drain side selection gate electrodes DG, and the source side selection gate electrodes SG can be configured as described above. Fig.12 The manufacturing process shown in FIG. 22 is performed by forming a plurality of adjacent memory gate structures 10 .

[0188] (1-12-2) Specific Examples of Voltages in Data Writing, Reading, and Erasing Operations The following Table 2 shows Fig.23 Specific examples (voltage examples) of voltage combinations during data writing and reading operations in the nonvolatile semiconductor memory device 1h are shown in Table 2, and specific examples (voltage examples) of voltage combinations during data erasing operations in segment units in the nonvolatile semiconductor memory device 1h are shown in Table 3 below. The unit of the voltage values ​​shown in Tables 2 and 3 is "V".

[0189] Table 2

[0190] Table 3

[0191] In the above Tables 2 and 3, in order to simplify the description, Fig.23 As shown in FIG. 1 , the operations are summarized with attention paid to the structure in which the memory cells Ch are arranged in a matrix in the column direction X and the row direction Y in the plane direction. Fig.23 A column of a memory cell Ch group electrically connected to a bit line BL extending from a column decoder 2b along a column direction X is called a "BL column", a BL column including memory cells Ch for writing and reading data is called a "selected BL column", and a BL column including only memory cells Ch for not writing and reading data is called a "non-selected BL column".

[0192] The V shown in Table 2 and Table 3 CG1 、V CG2 、V CG3 、V SGS1 、V SGS2 、V SGS3 、V SGD1 、V SGD2 、V SGD3 、V BL 、V SL As in Table 1, the symbols are used to represent the voltages applied to the respective lines. In addition, in this embodiment, since there are two word lines WL1 and WL2, the memory gate voltage applied to the word lines WL1 and WL2 is different from Table 1. CG1 、V CG2 、V CG3 These three represent.

[0193] In addition, in Table 2, the memory cell Ch that performs data writing and data reading is called a selected cell, and the memory cell Ch that does not perform data writing and data reading is called a non-selected cell. Furthermore, a page including a selected cell is called a selected page, and a page including only non-selected cells is called a non-selected page.

[0194] In the example of the data writing operation shown in Table 2 (labeled as "writing" in Table 2), it is shown that Fig.23 In the memory array CAh, the memory cell Ch in the first row and the first column is 11 The voltage of the first memory transistor MT11 when writing data. At this time, page (i, 1) becomes the selected page, and the remaining pages (i, 2), (j, 1), and (j, 2) become non-selected pages. Fig.23 In the middle, the upper memory cell Ch 11 , Ch 21 , Ch 31 , Ch 41 The column of the group becomes the selected BL column, and the memory cell Ch in the lower row 12 , Ch 22 , Ch 32 , Ch 42 The columns of the group become non-selected BL columns.

[0195] In the example of the data reading operation shown in Table 2 (in Table 2, marked as "read"), it is shown that Fig.23 In the memory array CAh, the memory cell Ch in the first row and the first column is read. 11 At this time, page (i, 1) becomes the selected page, and the remaining pages (i, 2), (j, 1), and (j, 2) become non-selected pages. Fig.23 In the middle, the upper memory cell Ch 11 , Ch 21 , Ch 31 , Ch 41 The column of the group becomes the selected BL column, and the memory cell Ch in the lower row 12 , Ch 22 , Ch 32 , Ch 42 The columns of the group become non-selected BL columns.

[0196] In Table 3, the pages included in the segment where data is to be cleared are referred to as selected pages, and the pages included in the segment where data is not to be cleared are referred to as non-selected pages. Fig.23 In the memory array CAh, the memory cell Ch arranged in the segment (i) is cleared. 11 , Ch 12, Ch 21 , Ch 22 The voltage when the data of each first memory transistor MT11 is input.

[0197] In the nonvolatile semiconductor memory device 1, by applying voltages as shown in Table 2 and Table 3, data can be selectively written, read, and erased to predetermined memory cells Ch based on the same principle as in the first embodiment.

[0198] (1-12-3) Actions and Effects In the above memory cell Ch, as in FIG. 2 and Figure 4 Similarly, in the memory cell C shown, a plurality of columnar memory gate electrodes MG are provided on the substrate 20 via an insulating layer 19 in a region between the parallel drain diffusion layer 7 and the source diffusion layer 6 extending in the surface direction of the substrate 20. In addition, in the memory cell Ch, a columnar drain side selection gate electrode DG is provided on the substrate 20 via an insulating layer 19 in a region between the drain diffusion layer 7 and the memory gate electrode MG located on one side, and a columnar source side selection gate electrode SG is provided on the substrate 20 via an insulating layer 19 in a region between the source diffusion layer 6 and the memory gate electrode MG located on the other side.

[0199] The memory cell Ch is configured such that a multilayer insulating layer 15 including a charge storage layer 15b is provided on each side of a plurality of memory gate electrodes MG, a drain side selection gate insulating layer 14a is provided on the side of the drain side selection gate electrode DG, and a source side selection gate insulating layer 14b is provided on the side of the source side selection gate electrode SG.

[0200] In addition, in the memory cell Ch, a semiconductor layer 17 is provided in a region between the parallel drain diffusion layer 7 and the source diffusion layer 6, and the semiconductor layer 17 is in contact with the side surface of the drain side selection gate insulating layer 14a, the side surface of the source side selection gate insulating layer 14b, the side surface of the multilayer insulating layer 15, the side surface of the drain diffusion layer 7, and the side surface of the source diffusion layer 6, respectively.

[0201] Thus, in this embodiment, a three-dimensional structure can be realized for a memory cell Ch in which a plurality of memory transistors MT11, MT12, a drain side selection transistor DT, and a source side selection transistor ST are connected in series. By making the memory cell Ch a three-dimensional structure, it is not restricted by two-dimensional scaling, and the memory cell Ch can be integrated and miniaturized.

[0202] In the memory cell Ch according to the present embodiment, the word lines WL1 and WL2 are not provided in page units but in segment units consisting of a plurality of pages. Therefore, the number of word lines WL1 and WL2 can be reduced accordingly, and the structure can be simplified.

[0203] (2) Second Embodiment (2-1) Structure of Equivalent Circuit of Nonvolatile Semiconductor Memory Device According to Second Embodiment Fig.24 FIG. 1 is a schematic diagram showing a structure of an equivalent circuit of a memory array CAc provided in a nonvolatile semiconductor memory device according to the second embodiment. Figure 1 The difference of the memory array CA of the first embodiment shown is that an auxiliary gate line AGL and an auxiliary gate electrode AG are provided. The nonvolatile semiconductor memory device of the second embodiment includes: a memory array CAc, a plurality of bit lines BL, a plurality of source lines SL, a plurality of drain side selection gate lines BGL, a plurality of source side selection gate lines SGL, a plurality of word lines WL, and an auxiliary gate line AGL.

[0204] The auxiliary gate line AGL is extended in the column direction X in parallel with the bit line BL and the source line SL extended in the column direction X, and is connected to a plurality of memory cells Cc arranged in the same column including different levels. That is, a plurality of memory cells Cc arranged in the same column direction X including different levels share one auxiliary gate line AGL. Each auxiliary gate line AGL arranged in each column including different levels is respectively connected to a column decoder 2b not shown. In addition, since the bit line BL, the source line SL, the drain side selection gate line BGL, the source side selection gate line SGL and the word line WL are arranged in the same structure as the first embodiment, their description is omitted here.

[0205] In the memory cell Cc, the voltages of the connected bit line BL, source line SL, drain side selection gate line BGL, source side selection gate line SGL, word line WL and auxiliary gate line AGL are controlled by a row decoder 2a and a column decoder 2b (not shown), so that data is written, cleared and read from the memory transistor MT. The data writing action, clearing action and reading action in the nonvolatile semiconductor memory device according to the second embodiment will be described in detail later.

[0206] In the memory array CAc of the present embodiment, since the configuration structure of the plurality of memory cells Cc arranged in a matrix at each level is the same for each level, here, when there is no need to distinguish by level, the configuration structure of the plurality of memory cells Cc arranged at the first level of the upper layer will be mainly explained.

[0207] Memory cell Cc and Figure 1 The memory cell C of the first embodiment shown is different in that an auxiliary gate electrode AG is provided. The memory cells Cc are all of the same structure, and each has a drain side selection transistor DT, a memory transistor MT, a source side selection transistor ST, and an auxiliary gate electrode AG, and the memory cell Cc has a structure in which the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST are connected in series. The memory cell Cc has one auxiliary gate electrode AG in common for the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST. In addition, the details of the structure of the memory cell Cc will be described later.

[0208] (2-2) Structure of memory cell Next, the structure of the memory cell Cc will be described. Fig.25A is a circuit diagram showing the structure of an equivalent circuit of a memory cell Cc. Fig.25A As shown, in the memory cell Cc, one end of the drain side selection transistor DT is connected to one end of the memory transistor MT having a charge storage layer described later, and one end of the source side selection transistor ST is connected to the other end of the memory transistor MT.

[0209] The other end of the drain side selection transistor DT is connected to the bit line BL, and the other end of the source side selection transistor ST is connected to the source line SL. Furthermore, the drain side selection gate line BGL is connected to the drain side selection gate electrode DG (hereinafter, in Fig.25B The source side selection gate line SGL is connected to the source side selection gate electrode SG of the source side selection transistor ST (later, in Fig.25B The word line WL is connected to the memory gate electrode MG of the memory transistor MT. The auxiliary gate line AGL is connected to the auxiliary gate electrode AG shared by the drain side selection transistor DT, the memory transistor MT and the source side selection transistor ST.

[0210] Fig.25B express Fig.25AFIG. 1 is an example of a cross-sectional structure of a memory cell Cc in a plan view. The memory cell Cc is formed in a region between a bit line BL and a source line SL extending in parallel in a column direction X, and includes a drain diffusion layer 7 in contact with the bit line BL and extending in the column direction X, and a source diffusion layer 6 in contact with the source line SL and extending in the column direction X. In addition, these source diffusion layer 6 and drain diffusion layer 7 are n+ type diffusion layers with a high impurity concentration, such as polysilicon.

[0211] In the memory cell Cc, a semiconductor layer 17 made of polysilicon or the like is provided in a region between the parallel drain diffusion layer 7 and the source diffusion layer 6, and the semiconductor layer 17 is in contact with the side surfaces of the drain diffusion layer 7 and the source diffusion layer 6. In addition, in the semiconductor layer 17 provided between the parallel drain diffusion layer 7 and the source diffusion layer 6, a memory gate structure 10, a drain side selection gate structure 11, and a source side selection gate structure 12 are provided in a manner penetrating the semiconductor layer 17.

[0212] The memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 of this embodiment are each formed in a columnar shape with a circular cross section, and the memory gate structure 10 is arranged between the drain side selection gate structure 11 and the source side selection gate structure 12, and these memory gate structures 10, drain side selection gate structures 11, and source side selection gate structures 12 are arranged in a straight line. In addition, the detailed structures of the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 are the same as those in the first embodiment, and therefore the description thereof is omitted.

[0213] In the present embodiment, a wall-shaped auxiliary gate insulating layer 45 is formed in parallel in the row direction Y between the drain diffusion layer 7 and the source diffusion layer 6 which are parallel in the column direction X, and a semiconductor layer 17 is provided between the parallel auxiliary gate insulating layers 45, and the semiconductor layer 17 surrounds the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12. In this way, the parallel auxiliary gate insulating layers 45 are formed to sandwich the semiconductor layer 17 in the column direction X. Here, one end of the auxiliary gate insulating layer 45 is in contact with the drain diffusion layer 7, and the other end is in contact with the source diffusion layer 6, and is provided between the drain diffusion layer 7 and the source diffusion layer 6. In addition, one side surface of the auxiliary gate insulating layer 45 is in contact with the side surface of the semiconductor layer 17 extending in the row direction Y, and the other side surface is in contact with the side surface of the auxiliary gate electrode AG. Thus, the auxiliary gate insulating layer 45 insulates the semiconductor layer 17 from the auxiliary gate electrode AG, and electrically isolates the auxiliary gate electrode AG from the semiconductor layer 17.

[0214] The auxiliary gate electrode AG is formed in a wall shape and is formed in parallel in the row direction Y between the drain diffusion layer 7 and the source diffusion layer 6 which are parallel in the column direction X. The semiconductor layer 17 surrounding the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12 and the auxiliary gate insulating layer 45 are provided between the parallel auxiliary gate electrodes AG. Here, the auxiliary gate electrode AG is arranged to face the drain side selection gate structure 11, the memory gate structure 10 and the source side selection gate structure 12 in the column direction X via the auxiliary gate insulating layer 45 and the semiconductor layer 17. In the present embodiment, in the column direction X, one end of the auxiliary gate electrode AG is arranged in a region facing the source side selection gate electrode SG via the semiconductor layer 17 and the auxiliary gate insulating layer 45, and the other end of the auxiliary gate electrode AG is arranged in a region facing the drain side selection gate electrode DG via the semiconductor layer 17 and the auxiliary gate insulating layer 45. The auxiliary gate insulating layer 46 is formed between one end of the auxiliary gate electrode AG and the source diffusion layer 6 and between the other end of the auxiliary gate electrode AG and the drain diffusion layer 7 , respectively.

[0215] Thus, the auxiliary gate electrode AG is insulated from the source diffusion layer 6 and the drain diffusion layer 7 by the auxiliary gate insulating layer 46 and is electrically isolated from the source diffusion layer 6 and the drain diffusion layer 7. In addition, an auxiliary gate line AGL provided in parallel with the source line SL and the bit line BL is electrically connected to the parallel auxiliary gate electrode AG.

[0216] exist Fig.25B In the figure, the auxiliary gate insulating layer 45a represents an auxiliary gate insulating layer in contact with the semiconductor layer of other memory cells (not shown), wherein the other memory cells are adjacent to the memory cell Cc in the column direction X. The auxiliary gate insulating layer 45a has the same structure as the auxiliary gate insulating layer 45, and insulates the semiconductor layer of other memory cells (not shown) adjacent to the memory cell Cc in the column direction X from the auxiliary gate electrode AG, so that the auxiliary gate electrode AG is electrically isolated from the semiconductor layer.

[0217] In addition, in this embodiment, if Fig.25B As shown in the figure, when viewed from above, one auxiliary gate electrode AG and another auxiliary gate electrode AG are arranged in parallel along the row direction Y, and the semiconductor layer 17 and the auxiliary gate insulating layer 45 surrounding the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12 are arranged in a structure sandwiched by the parallel auxiliary gate electrodes AG, but the present invention is not limited to this. For example, when viewed from above, only one auxiliary gate electrode AG and another auxiliary gate electrode AG may be arranged along the row direction Y, and the semiconductor layer 17 and the auxiliary gate insulating layer 45 may be arranged in a structure not sandwiched by the auxiliary gate electrode AG.

[0218] (2-3) Structure of memory array Next, the cross-sectional structure of a portion where a plurality of memory cells Cc are arranged in a column direction X in the memory array CA in which the memory cells Cc are arranged in a matrix will be described. Fig.24 In order to simply explain the structure of the equivalent circuit of the memory array CAc, the structure of the equivalent circuit is explained without focusing on the physical configuration positions of each part. However, here, the physical configuration positions of each part when the memory cell Cc is actually manufactured are focused on and the following explanation is given.

[0219] Fig.26 2 is a cross-sectional view showing a cross-sectional structure of a portion where a plurality of memory arrays CAc are arranged along the column direction X when viewed from above. Fig.26 In the embodiment, the auxiliary gate insulating layer 45a shown in FIG. 25 is used only as the auxiliary gate insulating layer 45.

[0220] exist Fig.26 In FIG. 1 , the vertical direction represents the column direction X, and the horizontal direction represents the row direction Y. For example, it represents a structure in which the memory cells Cc are arranged in 3 rows and 1 column in the first layer. Fig.26 In the example, the memory cells Cc in the first row and first column, the second row and first column, and the third row and first column are respectively represented as memory cells Cc 11 , Cc 21 , Cc 31 .exist Fig.26 In the memory cell Cc 11 With memory cell Cc 21 An auxiliary gate electrode AG between the two electrodes is represented as auxiliary gate electrode AG 11 , will be configured in the memory cell Cc 21 With memory cell Cc 31 Another auxiliary gate electrode AG between the two electrodes is represented as auxiliary gate electrode AG 21 .

[0221] Fig.24 This is a circuit diagram focusing on the structure of an equivalent circuit of the memory array CAc. Fig.26 FIG. 2 shows an example of the configuration of each part when the memory array CAc is manufactured. Fig.26 FIG. 2 shows memory cells Cc arranged in the first column among memory cells Cc arranged in a matrix in the memory array CAc. 11 , Cc 21 , Cc 31 and auxiliary gate electrode AG 11 AG 21 In addition, although Fig.26Although not shown in the figure, similarly to the first embodiment, the memory cells Cc arranged in the first column 11 , Cc 21 , Cc 31 and auxiliary gate electrode AG 11 AG 21 , and memory cells Cc arranged in a second column not shown 12 , Cc 22 , Cc 32 and auxiliary gate electrode AG 12 AG 22 The bit line BL of the first column and the bit line BL of the second column (not shown) are arranged adjacent to each other with the insulating layer 19 interposed therebetween (see Figure 3 ).

[0222] Here, the second embodiment is different from the first embodiment in that an auxiliary gate electrode AG is provided between the source diffusion layer 6 in contact with the side surface of the source line SL and the drain diffusion layer 7 in contact with the side surface of the bit line BL. 11 AG 21 , the auxiliary gate line AGL1 and the auxiliary gate electrode AG 11 AG 21 Electrical Connection: Hereinafter, description of the same structures as those of the first embodiment will be omitted, and description will be given focusing mainly on differences from the first embodiment.

[0223] In the region between the source diffusion layer 6 and the drain diffusion layer 7 parallel to the column direction X, memory cells Cc are also arranged along the column direction X. 11 , Cc 21 , Cc 31 , in the memory cell Cc 11 , Cc 21 An auxiliary gate electrode AG is formed between 11 , and in the memory cell Cc 21 , Cc 31 An auxiliary gate electrode AG is formed between 21 Here, the auxiliary gate electrode AG 11 AG 21 The side surface of the auxiliary gate electrode AG is formed into a curved shape along the outer shape of each side surface of the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12, which have a circular cross section when viewed from above. 11 AG 21 The side surface of the auxiliary gate electrode AG has a convex portion, which can increase the auxiliary gate electrode AG accordingly. 11 AG 21 formation area.

[0224] In addition, the auxiliary gate electrode AG 11 AG21 Since the auxiliary gate insulating layer 45 is formed along the concave portion of the side surface of the semiconductor layer 17, the semiconductor layer 17 can be substantially uniformly applied by applying the auxiliary gate electrode AG. 11 AG 21 The electric field generated by the voltage on the

[0225] In addition, each memory cell Cc 11 , Cc 21 , Cc 31 The side surfaces of the semiconductor layer 17 are in contact with the side surfaces of the source diffusion layer 6 and the drain diffusion layer 7, respectively. 11 , Cc 21 , Cc 31 The source line SL, the bit line BL, the source diffusion layer 6 and the drain diffusion layer 7 are shared.

[0226] In addition, in each memory cell Cc 11 , Cc 21 , Cc 31 The semiconductor layer 17 and the auxiliary gate electrode AG 11 AG 21 Auxiliary gate insulating layers 45 are provided between the auxiliary gate electrodes AG. 11 AG 21 Between the source diffusion layer 6 and the auxiliary gate electrode AG 11 AG 21 An auxiliary gate insulating layer 46 is provided between the drain diffusion layer 7 and the auxiliary gate electrode AG. 11 AG 21 It is electrically isolated from the semiconductor layer 17 by the auxiliary gate insulating layer 45 , and is electrically isolated from the source diffusion layer 6 and the drain diffusion layer 7 by the auxiliary gate insulating layer 46 .

[0227] In the second embodiment, similarly to the first embodiment, in addition to the drain side selection gate lines BGL1, BGL2, BGL3, the source side selection gate lines SGL1, SGL2, SGL3, and the word lines WL1, WL2 extending in the row direction Y, the auxiliary gate line AGL1 extending in the column direction X. The auxiliary gate line AGL1 and the auxiliary gate electrode AG arranged in the first column in the same column are connected. 11 AG 21 Connect to the auxiliary gate electrode AG in the same column 11 AG 21 There is an auxiliary gate line AGL1.

[0228] Here, Fig.27A express Fig.26 The cross-sectional structure of the JJ′ part, Fig.27Bexpress Fig.26 The cross-sectional structure of the KK′ part. Fig.27A In the example, regarding the memory cells Cc arranged in each layer in the first row 111 , Cc 112 , Cc 113 ,…,Cc 11k The common memory gate structure 10 and the memory cells C of each layer in the second row 121 , C 122 , C 123 , …, C 12k The common memory gate structure 10 and the auxiliary gate electrode AG 11 AG 21 The position represents the longitudinal section structure in the vertical direction Z. Fig.27B The memory cells Cc in the second row arranged in the column direction X are shown in FIG. 21 The memory cell Cc in the third row 31 The auxiliary gate electrode AG disposed between 21 The longitudinal section structure in the vertical direction Z.

[0229] like Fig.27A As shown in FIG. 1 , on the substrate 20, similarly to the first embodiment, the columnar memory gate structure 10 is vertically arranged via the insulating layer 19 as an interlayer insulating film. For example, the memory cells Cc from the first level to the kth level arranged in the vertical direction Z 111 , Cc 112 , Cc 113 ,…,Cc 11k The memory gate structure 10 is formed at predetermined intervals along the memory gate structure 10. In the second embodiment, as in the first embodiment, a plurality of memory cells Cc arranged in the vertical direction Z are 111 , Cc 112 , Cc 113 ,…,Cc 11k In the embodiment, there is a memory gate structure 10. In addition, the drain side selection gate structure 11 and the source side selection gate structure 12 (not shown) also have the same Figure 4 The same structure as the first embodiment shown in FIG. 1 is provided in which a plurality of memory cells Cc are arranged in the vertical direction Z. 111 , Cc 112 , Cc 113 ,…,Cc 11k There are a drain side selection gate structure 11 and a source side selection gate structure 12. The vertical cross-sectional structures of the drain side selection gate structure 11 and the source side selection gate structure 12 are the same as those of the first embodiment, and thus description thereof is omitted here.

[0230] like Fig.27A and Fig.27B As shown, the auxiliary gate electrode AG 11 AG 21 The auxiliary gate electrode AG is formed in a wall shape by extending in the vertical direction Z relative to the surface of the substrate 20 and also extending in the row direction Y. 11 AG 21 An auxiliary gate insulating layer 45 is formed on the side and bottom surfaces of the auxiliary gate electrode AG. 11 The memory cells Cc of each layer are arranged in the first row in the vertical direction Z. 121 , Cc 122 , Cc 123 ,…,Cc 12k and the memory cells Cc of each level of the second row arranged in the vertical direction Z 211 , Cc 212 , Cc 213 ,…,Cc 21k In this way, the memory cells Cc of each layer in the first row are arranged to extend in the vertical direction Z. 121 , Cc 122 , Cc 123 ,…,Cc 12k and the memory cells Cc of each level of the second row 211 , Cc 212 , Cc 213 ,…,Cc 21k There is a total of one auxiliary gate electrode AG 11 . Auxiliary gate electrode AG 11 AG 21 The upper end of the auxiliary gate electrode AG is connected to the auxiliary gate line AGL1 via the contact 18, and the auxiliary gate line AGL1 uniformly supplies the auxiliary gate electrode AG 11 AG 21 The same voltage is applied.

[0231] Here, if Fig.27B As shown, the auxiliary gate electrode AG 21 The auxiliary gate insulating layers 46 formed at both ends of the row direction Y extend in the vertical direction Z and are respectively connected to the gate insulating layers in the column direction X ( Fig.26 ) are extended on the side of each layer of the source diffusion layer 6 and the side of the drain diffusion layer 7. In this way, the auxiliary gate electrode AG 21 The auxiliary gate insulating layer 46 electrically isolates the source diffusion layer 6 and the drain diffusion layer 7 respectively provided at each layer.

[0232] (2-4) Structure of Other Embodiments of Memory Cell In the above-mentioned second embodiment, the case of using an auxiliary gate electrode AG having a shape in which the side surface is partially curved along the curved side surface of the memory gate structure 10, the drain side selection gate structure 11 and the source side selection gate structure 12 is described, but the present invention is not limited to this, and auxiliary gate electrodes of various shapes may also be used. Fig.28 FIG. 1 is a top cross-sectional view of a memory cell Cd provided with another example of an auxiliary gate electrode AGa. In this example, the auxiliary gate electrode AGa is formed into a rectangular cross-sectional shape when viewed from above. Fig.25B The description of the structure of the memory cell Cc shown in FIG. Fig.25B The differences are explained below.

[0233] In this case, the outer shape of the semiconductor layer 17 surrounding the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 when viewed from above is formed into a rectangular cross-section shape, and an auxiliary gate insulating layer 45 is formed along the side of the semiconductor layer 17 extending linearly in the row direction Y. An auxiliary gate electrode AGa is provided on the side of the auxiliary gate insulating layer 45, and the auxiliary gate electrode AGa has a rectangular cross-section shape when viewed from above, and the longitudinal direction extends along the row direction Y. In addition, an auxiliary gate insulating layer 46 having a quadrilateral cross-section when viewed from above is provided between one end (side) of the auxiliary gate electrode AGa in the row direction Y and the source diffusion layer 6, and between the other end (side) of the auxiliary gate electrode AGa in the row direction Y and the drain diffusion layer 7.

[0234] (2-5) Data writing operation Next, the operation of writing data into the memory cell Cc shown in FIG. 25 is described. When writing data into the memory cell Cc shown in FIG. 25, for example, the source voltage V SL The source side gate voltage Vt is applied to the source line SL, which is smaller than the threshold voltage Vt of the source side selection transistor ST. SGS The voltage is applied to the source side selection gate electrode SG, and the source side selection transistor ST is turned off.

[0235] At this time, a write voltage V of 0 V is applied to the bit line BL. BL (hereinafter also referred to as write selection bit voltage), the drain side gate voltage Vt greater than the threshold voltage Vt of the drain side selection transistor DT is set to SGD The voltage is applied to the drain-side selection gate electrode DG, and the drain-side selection transistor DT is turned on.

[0236] Furthermore, for example, by applying a high voltage memory gate voltage V for writing of 10 V to the memory gate electrode MG, CG0(Write the select memory gate voltage), so that in the memory cell Cc, as Fig.25B shown, the semiconductor layer 17 near the outer periphery of the memory gate structure 10 becomes the same potential as the write select bit voltage V BL0 . Thus, in the memory cell Cc, charges move from the semiconductor layer 17 and / or the memory gate electrode MG to the charge storage layer 15b included in the multi-layer insulating layer 15 of the memory gate structure 10, and the data is written.

[0237] In addition, in the second embodiment, similar to the first embodiment above, in the multi-layer insulating layer 15 including the charge storage layer 15b, if the distance ta in the plane direction of the first memory gate insulating layer 15a is greater than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta>tc), then charges move from the semiconductor layer 17 around the outer periphery of the second memory gate insulating layer 15c to the charge storage layer 15b. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta<tc), then charges move from the memory gate electrode MG to the charge storage layer 15b.

[0238] Next, as Fig.29A shown, on the upper first level, two memory cells Cc1 and Cc2 are arranged in the column direction X. Similarly, on the lower layer of the first level, two memory cells Cc3 and Cc4 are arranged in the column direction X. Taking the memory array CAc in which the memory cells Cc1 and Cc3 arranged in the vertical direction Z form one page, and the memory cells Cc2 and Cc4 arranged in the same vertical direction Z form another page as an example, the write operation of data in the memory array CAc will be described.

[0239] Here, the case of writing data to the memory cell Cc1 among the memory cells Cc1, Cc2, Cc3, and Cc4 as the selected memory cell Cc1 will be described. At this time, the page including the selected memory cell Cc1 with the written data is regarded as the write select page, and the page composed only of the non-selected memory cells Cc2 and Cc4 that do not write data is regarded as the write non-select page.

[0240] In addition, when the memory transistors MT1, MT2, MT3, MT4, drain side select transistors DT1, DT2, DT3, DT4, and source side select transistors ST1, ST2, ST3, ST4 are not particularly distinguished, they are only represented as memory transistors MT, drain side select transistors DT, and source side select transistors ST.

[0241] In addition, Fig.29B2 shows an example of voltages of various parts in the memory array CAc at this time. An auxiliary gate voltage V is applied to the auxiliary gate line AGL connected to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist (For example, a positive voltage of 0 to 6 V) Thus, a predetermined voltage is applied to the semiconductor layer 17 of the memory cells Cc1, Cc2, Cc3, and Cc4.

[0242] In the memory array CAc, a write selection bit voltage V is applied to the bit line BL1 which is the selection bit line connected to the selected memory cell Cc1. BL1 (For example, a low voltage of 0 to 1.5 V) A write selection drain gate voltage V higher than the threshold voltage Vt (preferably a positive value, also expressed as Vt(DT)) of the drain selection transistor DT1 is applied to the drain selection gate line BGL1 connected to the selected memory cell Cc1. SGD1 As a result, in the selected memory cell Cc1, the drain side selection transistor DT1 becomes conductive, and the selection bit voltage V is written. BL1 Passed to memory transistor MT1.

[0243] Thus, in the non-selected memory cell Cc3 in which data is not written in the write selected page, the same voltage as that of the selected memory cell Cc1 is applied from the drain side selection gate line BGL1 shared with the selected memory cell Cc1 to the drain side selection gate electrode DG of the drain side selection transistor DT3, and the write non-selected bit voltage V is applied to the bit line BL2 which becomes the non-selected bit line. BL2 , so that the drain side selection transistor DT3 becomes cut off.

[0244] In addition, in the memory array CAc, a positive voltage (e.g., 1 to 2 V) is uniformly applied to the source line SL. A write selection source side gate voltage Vt lower than the threshold voltage Vt (preferably a positive value, also expressed as Vt(ST)) of the source side selection transistor ST1 is applied to the source side selection gate line SGL1 connected to the selected memory cell Cc1. SGS1 As a result, in the selected memory cell Cc1, the source side selection transistor ST1 is turned off.

[0245] In addition, a write selection memory gate voltage V is applied to the word line WL1 connected to the selected memory cell Cc1. CG1 (For example, a high voltage of 7 to 15 V). Thus, in the selected memory cell Cc1, the write selection memory gate voltage V CG1, the potential of the memory gate electrode MG becomes high. Similar to the first embodiment, for example, when ta (the distance in the plane direction of the first memory gate insulating layer 15a) > tc (the distance in the plane direction of the second memory gate insulating layer 15c), electrons move from the semiconductor layer 17 to the charge storage layer 15b, or holes move from the charge storage layer 15b to the semiconductor layer 17, and a data-written state is achieved. Thus, the threshold voltage of the memory transistor MT1 that selects the memory cell Cc1 becomes high. On the other hand, when ta < tc, electrons escape from the charge storage layer 15b and move to the memory gate electrode MG, or holes move from the memory gate electrode MG to the charge storage layer 15b. Thus, the threshold voltage of the memory transistor MT1 that selects the memory cell Cc1 becomes low.

[0246] At this time, a write non-selection bit voltage V is applied to another bit line BL2 that becomes a non-selection bit line not connected to the selected memory cell Cc1. BL2 . The write non-selection bit voltage V BL2 is preferably a positive voltage (for example, 1.5 to 3 V).

[0247] Thus, in the non-selection memory cell Cc3 that does not write data in the write selection page, the same voltage as that of the selected memory cell Cc1 is applied from the drain-side selection gate line BGL1 shared with the selected memory cell Cc1 to the drain-side selection gate electrode DG of the drain-side selection transistor DT3. By applying the write non-selection bit voltage V to the bit line BL2 that becomes a non-selection bit line BL2 , the drain-side selection transistor DT3 becomes in an off state.

[0248] In the write selection page, although the non-selection memory cell Cc3 shares the drain-side selection gate line BGL1, the word line WL1, and the source-side selection gate line SGL1 with the selected memory cell Cc1, the drain-side selection transistor DT3 and the source-side selection transistor ST3 of the non-selection memory cell Cc3 become in off states. Therefore, in the non-selection memory cell Cc3, even if a write selection memory gate voltage V CG1 (for example, a high voltage of 7 to 15 V) is applied from the word line WL1 to the memory gate electrode MG, since the potential of the semiconductor layer 17 around the memory transistor MT3 rises, the potential difference from the write selection memory gate voltage V CG1 becomes smaller. Therefore, in the non-selection memory cell Cc3, channel current does not flow into the charge storage layer 15b of the memory transistor MT3, the movement of charges to the charge storage layer 15b can be blocked, and data writing can be prevented.

[0249] In addition, in Fig.29AIn the non-selected memory cells arranged on other columns in the write selection page (i.e., memory cells arranged on the deep side of the paper or the front side of the paper relative to the memory cells Cc1 and Cc3), although not shown in the figure, in the case of the non-selected memory cells, the drain side selection gate line BGL1, the word line WL1 and the source side selection gate line SGL1 are shared with the selected memory cell Cc1, but similarly to the non-selected memory cell Cc3, the same voltage as the bit line BL2 and the source line SL2 is applied to each bit line BL and the source line SL, respectively, so that the drain side selection transistor DT and the source side selection transistor ST can be turned off to prevent the writing of data. In addition, similarly to the above, at this time, since the auxiliary gate voltage V is also applied from the auxiliary gate line AGL to these non-selected memory cells, Assist Therefore, the potential of the semiconductor layer 17 near the word line WL1 is also affected by the auxiliary gate voltage V Assist When the auxiliary gate voltage V Assist When the potential of the semiconductor layer 17 rises, the potential difference between the potential of the semiconductor layer 17 and the word line WL1 decreases. This makes it possible to more effectively prevent data from being written.

[0250] Next, a write non-selected page consisting only of non-selected memory cells Cc2 and Cc4 is described. In this case, since the bit lines BL1 and BL2 and the source lines SL1 and SL2 connected to the non-selected memory cells Cc2 and Cc4 are shared with the memory cells Cc1 and Cc3 in the above-mentioned write selected page, their description is omitted here, and the drain side selection gate line BGL2, the word line WL2 and the source side selection gate line SGL2 are described.

[0251] In writing non-selected pages, a low potential (for example, 0 V) ​​writing non-selected drain side gate voltage V is applied to the drain side selection gate line BGL2, the word line WL2, and the source side selection gate line SGL2. SGD2 , write non-select memory gate voltage V CG2 and write non-selected source side gate voltage V SGS2 Thus, in each non-selected memory cell Cc2, Cc4 in which the non-selected page is written, at both ends of the memory transistors MT2, MT4, the drain side selection transistors DT2, DT4 and the source side selection transistors ST2, ST4 are respectively turned off, so that the channel current does not flow into the charge accumulation layer 15b of the memory transistors MT2, MT4, and the movement of charges to the charge accumulation layer 15b can be blocked, thereby preventing the writing of data.

[0252] In addition, similarly to the above, at this time, the positive auxiliary gate voltage V is also applied from the auxiliary gate line AGL to the non-selected memory cells Cc2 and Cc4 of the non-selected page.Assist , so that the potential of the semiconductor layer 17 near the gate of the drain side selection transistors DT2, DT4 and the source side selection transistors ST2, ST4 is in an increased state. Therefore, even in the non-selected page, these drain side selection transistors DT2, DT4 and source side selection transistors ST2, ST4 can be reliably turned off. In addition, in each memory transistor MT of the non-selected memory cells Cc2, Cc3, Cc4, since the movement of charges to the charge storage layer 15b is blocked, the threshold voltage does not change.

[0253] In this way, in the memory array CAc, data can be prevented from being written to the non-selected memory cells Cc2, Cc3, and Cc4, and data can be written only to the selected memory cell Cc1.

[0254] (2-6) Data clearing action Next, the data clearing operation in the memory cell Cc shown in FIG. 25 is described. When data is cleared in the memory cell Cc of FIG. 25, for example, a positive high voltage (for example, 7 to 12 V) source voltage V SL Applied to the source line SL, the bit voltage V BL The same clear select source side gate voltage V SGS The voltage is applied to the source side selection gate line SGL connected to the source side selection gate electrode SG of the source side selection transistor ST.

[0255] Similarly, a positive high voltage (e.g., 7 to 12 V) bit voltage V BL Applied to the bit line BL, it will be connected to the bit voltage V BL Same clear select drain side gate voltage V SGD The voltage V is applied to the drain side selection gate line BGL connected to the drain side selection gate electrode DG of the drain side selection transistor DT. As a result, the potential of the semiconductor layer 17 on the drain side of the source side selection transistor ST becomes V SGS -V t Similarly, the potential of the semiconductor layer 17 on the drain side of the drain side selection transistor DT also becomes V SGD -V t .

[0256] Furthermore, a positive high voltage (for example, 7 to 12 V) auxiliary gate voltage V is applied to the auxiliary gate line AGL. Assist As a result, the potential of the semiconductor layer 17 near the auxiliary gate electrode AG rises and becomes substantially uniform near the semiconductor layer 17 of the memory transistor MT.

[0257] In addition, the clear selection memory gate voltage V CG1A word line WL is applied to a memory gate electrode MG of a memory transistor MT. As a result, a potential difference is generated between the memory gate electrode MG of the memory transistor MT and a semiconductor layer 17, and charges move from within a charge storage layer 15b, resulting in a state where data is erased. At this time, in the second embodiment, by an auxiliary gate voltage V Assist the potential of the semiconductor layer 17 is raised, so the potential difference from the negative memory gate electrode MG becomes larger, and electrons within the charge storage layer 15b move at a higher speed (channel current induction).

[0258] In addition, in the second embodiment, similarly to the above-described first embodiment, in a multilayer insulating layer 15 including the charge storage layer 15b, if a distance ta in a plane direction of a first memory gate insulating layer 15a is greater than a distance tc in a plane direction of a second memory gate insulating layer 15c (that is, ta > tc), then during a data erasing operation, electrons move from the charge storage layer 15b into the semiconductor layer 17, or holes move from the semiconductor layer 17 into the charge storage layer 15b. As a result, the threshold value of the memory transistor MT is lowered. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (that is, ta < tc), then electrons move from the charge storage layer 15b into the memory gate electrode MG, or holes move from the memory gate electrode MG into the charge storage layer 15b. As a result, the threshold value of the memory transistor MT is raised.

[0259] Next, similarly to the above-described "(2-5) Data writing operation", as Fig. 30A shown, taking a memory array CAc in which memory cells Cc1 and Cc3 arranged in a vertical direction Z form one page and memory cells Cc2 and Cc4 arranged in the same vertical direction Z form another page as an example, a data erasing operation in this memory array CAc will be described.

[0260] Here, regarding erasing data in units of pages, a case where data is erased from the page composed of the memory cells Cc1 and Cc3 and data is not erased from the page composed of the memory cells Cc2 and Cc4 will be described. At this time, the page for which data is erased is set as an erase selection page, and the page composed only of non-selection memory cells Cc2 and Cc4 for which data is not erased is set as a write non-selection page. In addition, threshold voltages Vt of drain-side selection transistors DT and source-side selection transistors ST of the memory cells Cc1, Cc2, Cc3, and Cc4 are preferably positive values.

[0261] In addition, Fig. 30BAn example of voltages of various parts in the memory array CAc at this time is shown. A positive high voltage (for example, 7 to 12 V) auxiliary gate voltage V is applied to the auxiliary gate line AGL connected to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist Thus, a predetermined voltage is applied to the semiconductor layer 17 of the memory cells Cc1, Cc2, Cc3, and Cc4.

[0262] In the memory array CAc, the clear bit voltage V is applied to the bit lines BL1 and BL2 shared by the clear selected page and the clear non-selected page. BL (For example, a high voltage of 7 to 12 V) is applied to the source lines SL1 and SL2 with the clearing voltage V BL (For example, a high voltage of 7 to 12 V) The same voltage as the source voltage V SL .

[0263] In the clear selection page, for example, the clear bit voltage V BL The same 7-12V high voltage clear select drain side gate voltage V SGD1 Applied to the drain side select gate line BGL1, similarly, it will be connected to the clear bit voltage V BL The same 7-12V high voltage clear select source side gate voltage V SGS1 is applied to the source side selection gate line SGL1. In addition, in the clear selection page, the clear selection memory gate voltage V CG1 This is applied to the word line WL1. Thus, in the erase selected page, a potential difference is generated between the memory gate electrode MG and the surrounding semiconductor layer 17 in each of the memory cells Cc1 and Cc3, and charges are transferred from the charge storage layer 15b, thereby erasing the data.

[0264] in addition, Fig. 30C An example of voltages of various parts in the data clearing operation of another embodiment is shown. In this case, a positive high voltage (for example, 5 to 10 V) auxiliary gate voltage V is applied to the auxiliary gate line AGL connected to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist Thus, a predetermined voltage is applied to the semiconductor layer 17 of the memory cells Cc1, Cc2, Cc3, and Cc4.

[0265] In this case, in the memory array CAc, the clear bit voltage V is applied to the bit lines BL1 and BL2 common to the clear selected page and the clear non-selected page. BL (For example, a high voltage of 7 to 12 V) is applied to the source lines SL1 and SL2 with the clearing voltage V BL (For example, a high voltage of 7 to 12 V) The same voltage as the source voltage VSL .

[0266] In the clear selection page, for example, a positive clear selection drain side gate voltage V SGD1 Apply to the drain side select gate line BGL1, and similarly, a 4-9V positive clear select source side gate voltage V SGS1 This is applied to the source side selection gate line SGL1. Thus, in the erase selection page, a potential difference is generated between the memory gate electrode MG and the surrounding semiconductor layer 17 in each of the memory cells Cc1 and Cc3, and charges are transferred from the charge storage layer 15b, thereby erasing the data.

[0267] In the case of erasing non-selected pages, the erase bit voltage V BL (e.g., a high voltage of 7 to 12 V) as the clear non-selected drain side gate voltage V SGD2 , Clear the non-selected source side gate voltage V SGS2 and clear the non-selected memory gate voltage V CG2 , applied to the drain side selection gate line BGL2, the source side selection gate line SGL2 and the word line WL2. As a result, in erasing the non-selected page, in each memory cell Cc2, Cc4, no potential difference is generated between the memory gate electrode MG and the semiconductor layer 17 surrounding it, and the charge does not move from the charge storage layer 15b, which can prevent the data from being erased.

[0268] In the second embodiment, during the data clearing operation, a positive auxiliary gate voltage V is applied to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist , so that the potential of the semiconductor layer 17 near the memory gate electrode MG becomes high. Therefore, the non-selected memory gate voltage V CG2 The potential difference becomes smaller, and the auxiliary gate voltage V is not applied Assist Compared with the case where data is cleared, it is possible to more effectively suppress the clearing of data.

[0269] In the above embodiment, data is erased in units of pages, but the present invention is not limited thereto, and all pages may be set as erase selection pages to erase data in all memory cells Cc constituting the memory array CAc.

[0270] (2-7) Data reading operation Next, the data reading operation in the memory array CAc is described. In addition, here, similarly to the above-mentioned "(2-4) Data writing operation", Fig.31AAs shown, taking a memory array CAc in which memory cells Cc1 and Cc3 arranged in the vertical direction Z constitute one page and memory cells Cc2 and Cc4 arranged in the vertical direction Z constitute another page as an example, the data reading operation in the memory array CAc is described.

[0271] Here, the case where data is read from the memory cells Cc1, Cc3, for example, as the selected memory cells Cc1, Cc3 among the memory cells Cc1, Cc2, Cc3, and Cc4 is described. At this time, the page including the selected memory cells Cc1, Cc3 containing the read data is the read selected page, and the page consisting of only the non-selected memory cells Cc2, Cc4 from which data is not read is the read non-selected page.

[0272] in addition, Fig.31B : shows an example of the voltage of each part in the memory array CAc at this time. In this case, a low voltage (for example, 0V) auxiliary gate voltage V is applied to the auxiliary gate line AGL connected to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist In the memory array CAc, a read bit voltage V is applied to the common bit lines BL1 and BL2 of the read selected page and the read non-selected page. BL1 、V BL2 (all are the same positive voltage, such as 1V), and a read source voltage V is applied to the source line SL. SL (The source lines SL are all at the same voltage, for example, 0V).

[0273] In addition, in the read selection page, for example, a voltage higher than the threshold voltage Vt(DT) of the drain side selection transistor DT1 (for example, 2V) is set as the read selection drain side gate voltage V SGD1 The drain side selection gate line BGL1 is applied to the drain side selection gate line BGL1. Similarly, a voltage higher than the threshold voltage Vt(ST) of the source side selection transistor ST1 (for example, 2V) is used as the read selection source side gate voltage V SGS1 is applied to the source side selection gate line SGL1. As a result, the drain side selection transistor DT1 and the source side selection transistor ST1 of the selected memory cell Cc1 are turned on. At this time, by applying a low voltage (for example, 0V) auxiliary gate voltage V Assist , thereby reducing the potential of the semiconductor layer 17 near the auxiliary gate electrode AG, and thus it is possible to suppress leakage current from the source line SL1 to the bit line BL1 near the auxiliary gate electrode AG.

[0274] Furthermore, in the read selection page, for example, the read selection memory gate voltage V is set to 0 to 6V. CG1Thus, in the selected memory cell Cc1, if no data is written in the memory transistor MT1, the threshold voltage Vt of the memory transistor MT1 is higher than the read selection memory gate voltage V CG1 If the voltage is low, current flows from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 changes.

[0275] On the other hand, when data is written into the memory transistor MT1 of the selected memory cell Cc1, the threshold voltage Vt of the memory transistor MT1 is higher than the read selection memory gate voltage Vt. CG1 When the voltage is high, the current does not flow from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 does not change. Then, by using the column decoder 2b ( Figure 1 ) detects the change in the potential of the bit line BL1, and can read the data of the selected memory cell Cc1. In addition, at this time, by using the column decoder 2b ( Figure 1 ) detects the change in the potential of the bit line BL2, and data can also be read from other selected memory cells Cc3 in the read selection page.

[0276] In reading the non-selected page, a voltage lower than the threshold voltage Vt of the drain-side selection transistor DT2 (for example, 0V) is used as the non-selected drain-side gate voltage Vt. SGD2 The drain side selection gate line BGL2 is applied to the drain side selection gate line. Similarly, a voltage lower than the threshold voltage Vt of the source side selection transistor ST2 (for example, 0V) is used as the reading non-selected source side gate voltage V SGS2 Applied to the source side selection gate line SGL2.

[0277] As a result, the drain side selection transistors DT and source side selection transistors ST of the non-selected memory cells Cc2 and Cc4 of the read non-selected page are turned off, and current does not flow from the source lines SL1 and SL2 to the bit lines BL1 and BL2. As described above, data is read only from the selected memory cells Cc1 and Cc3 of the read selected page.

[0278] In addition, when detecting multi-valued data using one memory cell Cc, by changing the read selection memory gate voltage V CG1 By detecting the change in the potential of the bit line BL1 at each voltage value, it is possible to detect a tiny threshold voltage of the memory transistor MT and read multi-value data.

[0279] in addition, Fig. 31CAn example of voltages of various parts in the data reading operation of another embodiment is shown. In this case, a low voltage (for example, 0 V) ​​auxiliary gate voltage V is also applied to the auxiliary gate line AGL connected to the memory cells Cc1, Cc2, Cc3, and Cc4. Assist In the read selection page, the read selection memory gate voltage V CG1 (e.g., 0V) is applied as a fixed voltage to the word line WL1. At this time, if the threshold voltage of the memory transistor MT1 in the selected memory cell Cc1 is higher than the read selection memory gate voltage V CG1 If the current is low, the current flows from the source line SL1 to the bit line BL1. At this time, by applying a low voltage (for example, 0V) auxiliary gate voltage V Assist , thereby reducing the potential of the semiconductor layer 17 near the auxiliary gate electrode AG, and thus it is possible to suppress leakage current from the source line SL1 to the bit line BL1 near the auxiliary gate electrode AG.

[0280] The cell current flowing from the source line SL1 to the bit line BL1 through the selected memory cell Cc1 is determined by the read selected memory gate voltage V CG1 The threshold difference (V CG1 The column decoder 2b detects the magnitude of the cell current flowing from the source line SL1 to the bit line BL1 via the selected memory cell Cc1, and in the column decoder 2b, the threshold voltage Vt of the memory transistors MT1 and MT3 is determined to determine whether data is written into the memory transistors MT1 and MT3.

[0281] In this case, the data written into the memory transistors MT1 and MT3 can be distinguished and multi-valued data can be read according to the value of the cell current flowing from the source line SL1 to the bit line BL1 through the selected memory cell Cc1. Fig.31B The same, so the description is omitted here.

[0282] (2-8) Specific Examples of Voltages in Data Writing, Erasing, and Reading Operations Table 4 below shows specific examples (voltage examples) of combinations of voltages during the data writing operation, the erasing operation (the erasing operation by channel current induction and the erasing operation by junction breakdown induction), and the reading operation of the second embodiment. The unit of the voltage values ​​shown in Table 4 is "V".

[0283] In Table 4, "BL column" indicates a column of a memory cell Cc group electrically connected to a bit line BL extending from the column decoder 2b in the column direction X. Figure 1Similarly, the column decoder 2b is configured as a two-dimensional structure of the row direction Y and the vertical direction Z as the paper depth direction in the figure. There are two directions in the row direction Y and the vertical direction Z as the paper depth direction in the BL column. Strictly speaking, they can also be specified. However, in Table 4, in order to simplify the description, the row direction Y and the vertical direction Z as the paper depth direction are not particularly distinguished, and the focus is on Fig.29A , Fig. 30A and Fig.31A The actions are organized into selected and non-selected pages as shown. Table 4

[0284] In the nonvolatile semiconductor memory device 1 , as shown in Table 4 above, by applying voltages respectively, the voltages can be adjusted in units of pages in the memory array CAc, and data can be selectively written, erased, and read for predetermined memory cells Cc.

[0285] (2-9) Method for Manufacturing Memory Array According to Second Embodiment Next, for Fig.26 The manufacturing method of the memory array of the second embodiment of the present invention is described below. In addition, in the manufacturing method of the memory array of the second embodiment, a step of manufacturing the auxiliary gate electrode AG is added to the manufacturing method of the first embodiment. In the manufacturing method of the memory array of the second embodiment, for example, similarly to the manufacturing method of the first embodiment, Fig.12 22 , a memory array in which the auxiliary gate electrode AG is not formed is manufactured.

[0286] Then, for example, Fig. 22B and Fig. 22C As shown, in order to form the auxiliary gate electrode AG between the memory cell formation regions 28b and 28c, a new patterned mask layer (not shown) composed of a resist material or the like is formed on the memory gate structure 10a, the drain side selection gate structure 11a, the source side selection gate structure 12a, and the existing mask layer 27, etc. On the new mask layer, an opening is formed in combination with a predetermined region (hereinafter referred to as an auxiliary gate electrode formation region) where the auxiliary gate electrode AG is to be formed between the memory cell formation regions 28b and 28c.

[0287] Next, the insulating layer 19 as the interlayer insulating film exposed from the opening is etched in the vertical direction Z by dry etching using the new mask layer as a mask, thereby forming a hole for forming an auxiliary gate electrode in the insulating layer 19. At this time, for example, Fig.26 As shown, adjacent memory cells Cc in the column direction X 11 , Cc 21 , Cc31 Between each unit, the insulating layer 19 is left as auxiliary gate insulating layers 45 and 46 to form holes for auxiliary gate electrode formation.

[0288] Next, a gate material such as low-resistance polysilicon or metal such as tungsten is deposited inside the auxiliary gate electrode forming hole surrounded by the auxiliary gate insulating layers 45 and 46 formed in the above-described steps, thereby forming an auxiliary gate electrode AG.

[0289] In addition, about Fig.28 The manufacturing method of the memory cell Cd shown can be the same as the manufacturing method in the third embodiment described later, so the description thereof is omitted here.

[0290] Thus, the memory cell of the second embodiment having the auxiliary gate electrode AG can be manufactured by adding the step of forming the auxiliary gate electrode AG to the manufacturing process of the memory array CA of the first embodiment. The order of the manufacturing steps is not limited to the above order.

[0291] (2-10) Function and Effect In the above structure, in the second embodiment, a three-dimensional structure is also realized for the memory cell Cc having the memory transistor MT, the drain side selection transistor DT and the source side selection transistor ST connected in series. By making the memory cell Cc a three-dimensional structure, the memory cell Cc can be integrated and miniaturized without being restricted by two-dimensional scaling.

[0292] In addition, since the memory cell Cc of the second embodiment is provided with an auxiliary gate electrode AG, not only the potentials of the source diffusion layer 6, the drain diffusion layer 7, the source side selection gate electrode SG, the memory gate electrode MG, and the drain side selection gate electrode DG, but also the potential of the semiconductor layer 17 can be determined by the potential of the auxiliary gate electrode AG.

[0293] In the data writing operation, as described above, a positive voltage (for example, 1 V) is applied to the auxiliary gate electrode AG. Assist , the potential of the semiconductor layer 17 can be increased. As a result, in the write selection page, the source side gate voltage V SGS1 The potential difference with the semiconductor layer 17 is reduced, so the source side selection transistors ST1 and ST3 can be reliably set to the off state, thereby suppressing the leakage current. In addition, when writing to the non-selected page, the potential of the semiconductor layer 17 is set to be lower than the source side gate voltage V SGS2 and the drain side gate voltage V SGD2 At a relatively higher potential, the drain-side selection transistors DT2 and DT4 and the source-side selection transistors ST2 and ST4 can be reliably turned off, thereby suppressing leakage current.

[0294] On the other hand, in the data clearing operation, as described above, a positive voltage (for example, 7 to 12 V) of the auxiliary gate voltage V is applied to the auxiliary gate electrode AG. Assist , the potential of the semiconductor layer 17 can be raised. Thus, in the erase selection page, the negative voltage (eg, -5 to 0 V) ​​of the memory gate voltage V CG1 The potential difference between the semiconductor layer 17 and the memory gate voltage V is increased, so data can be erased more efficiently. In addition, even when erasing non-selected pages, the potential of the semiconductor layer 17 can be set to be higher than the memory gate voltage V CG2 A relatively higher potential or an equivalent potential (e.g., 7 to 12 V) is used to make the memory gate voltage V CG2 The potential difference becomes smaller, so data clearing can be suppressed more effectively.

[0295] Furthermore, during the data reading operation, as described above, a constant voltage (for example, 0 V) ​​of the auxiliary gate voltage V is applied to the auxiliary gate electrode AG. Assist , the potential of the semiconductor layer 17 can be lowered. Thus, the potential of the semiconductor layer 17 and the read selection drain side gate voltage V SGD1 The potential difference of the semiconductor layer 17 can be maintained at a potential difference greater than the threshold voltage Vt(DT) of the drain side selection transistor DT1. SGS1 The potential difference is maintained at a potential difference greater than the threshold voltage Vt(ST) of the source side selection transistor ST1. Thus, leakage current from the source line SL1 to the bit line BL1 in the vicinity of the auxiliary gate electrode AG can be suppressed.

[0296] Furthermore, in the memory cell Cc of the second embodiment, as described above, the side surface of the auxiliary gate electrode AG is formed into a curved surface along the shape of each side surface of the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12, which have circular cross sections when viewed from above, so that an electric field can be applied substantially uniformly to the semiconductor layer 17 surrounding the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12. As a result, the auxiliary gate voltage V Assist The voltage can more accurately control the potential of the semiconductor layer 17.

[0297] (3) Third Embodiment (3-1) Structure of Equivalent Circuit of Nonvolatile Semiconductor Memory Device According to Third Embodiment In the second embodiment described above, a memory cell Cc in which the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST share one auxiliary gate electrode AG is described, but the present invention is not limited thereto, and a memory cell in which independent auxiliary gate electrodes are provided for the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST, respectively. Hereinafter, as a third embodiment, a memory cell in which independent auxiliary gate electrodes are provided for the drain side selection transistor DT, the memory transistor MT, and the source side selection transistor ST, respectively.

[0298] Fig.32 FIG. 1 is a schematic diagram showing a structure of an equivalent circuit of a memory array CAd provided in a nonvolatile semiconductor memory device according to the third embodiment. Figure 1 The difference of the memory array CA of the first embodiment shown is that: a drain side auxiliary gate line DAGL, a memory side auxiliary gate line MAGL, a source side auxiliary gate line SAGL, a drain side auxiliary gate electrode DAG, a memory side auxiliary gate electrode MAG, and a source side auxiliary gate electrode SAG are provided. As the other structures are the same as the non-volatile semiconductor memory device 1 of the first embodiment described above, the following description is made here focusing on the differences from the first embodiment.

[0299] The drain-side auxiliary gate line DAGL is extended in the column direction X in parallel with the bit line BL and the source line SL extended in the column direction X, and is connected to each drain-side auxiliary gate electrode DAG of a plurality of memory cells Ce arranged in the same column including different layers. That is, a plurality of memory cells Ce arranged in the same column direction X including different layers share one drain-side auxiliary gate line DAGL. Each drain-side auxiliary gate line DAGL provided in each column including different layers is connected to a column decoder 2b not shown.

[0300] The memory side auxiliary gate line MAGL is extended in the column direction X in parallel with the bit line BL and the source line SL extended in the column direction X, and is connected to each memory side auxiliary gate electrode MAG of a plurality of memory cells Ce arranged in the same column including different levels. That is, a plurality of memory cells Ce arranged in the same column direction X including different levels share one memory side auxiliary gate line MAGL. Each memory side auxiliary gate line MAGL arranged in each column including different levels is connected to a column decoder 2b not shown.

[0301] The source side auxiliary gate line SAGL is extended in the column direction X in parallel with the bit line BL and the source line SL extended in the column direction X, and is connected to each source side auxiliary gate electrode SAG of a plurality of memory cells Ce arranged in the same column including different levels. That is, a plurality of memory cells Ce arranged in the same column direction X including different levels share one source side auxiliary gate line SAGL. Each source side auxiliary gate line SAGL arranged in each column including different levels is connected to a column decoder 2b not shown.

[0302] In addition, the bit lines BL, source lines SL, drain side selection gate lines BGL, source side selection gate lines SGL, and word lines WL are provided in the same structure as in the first embodiment, and therefore their description is omitted here.

[0303] In the memory cell Ce, the voltages of the connected bit line BL, source line SL, drain side selection gate line BGL, source side selection gate line SGL, word line WL, drain side auxiliary gate line DAGL, memory side auxiliary gate line MAGL, and source side auxiliary gate line SAGL are controlled by a row decoder 2a and a column decoder 2b (not shown), thereby writing data to the memory transistor MT, clearing data, and reading data. Details of the data writing action, clearing action, and reading action in the nonvolatile semiconductor memory device of the third embodiment will be described later.

[0304] In the memory array CAd of the present embodiment, the configuration structure of a plurality of memory cells Ce arranged in a matrix on the XY plane is the same for each level. Therefore, here, without the need to distinguish between each level, the following description will mainly focus on the configuration structure of a plurality of memory cells Ce arranged in the first level of the upper layer.

[0305] Memory cell Ce and Figure 1 The memory cell C of the first embodiment shown is different in that a drain side auxiliary gate electrode DAG, a memory side auxiliary gate electrode MAG, and a source side auxiliary gate electrode SAG are provided. The memory cells Ce all have the same structure, and have a structure in which a drain side auxiliary gate electrode DAG is provided for the drain side selection transistor DT, a memory side auxiliary gate electrode MAG is provided for the memory transistor MT, and a source side auxiliary gate electrode SAG is provided for the source side selection transistor ST.

[0306] (3-2) Structure of memory cell Next, the structure of the memory cell Ce will be described. Note that, here, since the description of the same structure as that of the second embodiment is redundant, it will be omitted, and the following description will focus on the differences. Fig.33Ais a circuit diagram showing the structure of an equivalent circuit of a memory cell Ce. Fig.33A As shown, the drain side auxiliary gate line DAGL is connected to the drain side auxiliary gate electrode DAG of the drain side selection transistor DT, the memory side auxiliary gate line MAGL is connected to the memory side auxiliary gate electrode MAG, and the source side auxiliary gate line SAGL is connected to the source side auxiliary gate electrode SAG.

[0307] Fig.33B express Fig.33A FIG. 1 is an example of a cross-sectional structure of a memory cell Ce when viewed from above. Here, the following description focuses on one memory cell Ce among the memory cells Ce. Fig.28 The memory cell Cd of the second embodiment shown has the following differences: a source side auxiliary gate electrode SAG1 (SAG2), a memory side auxiliary gate electrode MAG1 (MAG2), and a drain side auxiliary gate electrode DAG1 (DAG2) are provided between the drain diffusion layer 7 and the source diffusion layer 6 which are parallel in the column direction X, and between the parallel auxiliary gate insulating layers 45a, 45b which extend linearly in the row direction Y.

[0308] In addition, in the present embodiment, the source side auxiliary gate electrode SAG1, the memory side auxiliary gate electrode MAG1, and the drain side auxiliary gate electrode DAG1 arranged on one side, and the source side auxiliary gate electrode SAG2, the memory side auxiliary gate electrode MAG2, and the drain side auxiliary gate electrode DAG2 arranged on the other side are symmetrically arranged with the source side selection gate structure 12, the memory gate structure 10, and the drain side selection gate structure 11 as the center. Since the source side auxiliary gate electrode SAG1, the memory side auxiliary gate electrode MAG1, and the drain side auxiliary gate electrode DAG1 arranged on one side have the same structure as the source side auxiliary gate electrode SAG2, the memory side auxiliary gate electrode MAG2, and the drain side auxiliary gate electrode DAG2 arranged on the other side, the description will be mainly focused on the source side auxiliary gate electrode SAG1, the memory side auxiliary gate electrode MAG1, and the drain side auxiliary gate electrode DAG1 arranged on one side.

[0309] In this case, one side surface of the auxiliary gate insulating layer 45 a extending in the row direction Y contacts the side surface of the semiconductor layer 17 , and the other side surface extending in the row direction Y contacts the side surfaces of the source side auxiliary gate electrode SAG1 , the memory side auxiliary gate electrode MAG1 , and the drain side auxiliary gate electrode DAG1 . Thus, the auxiliary gate insulating layer 45 a electrically isolates the source side auxiliary gate electrode SAG1 , the memory side auxiliary gate electrode MAG1 , and the drain side auxiliary gate electrode DAG1 from the semiconductor layer 17 .

[0310] The drain-side auxiliary gate electrode DAG1, the memory-side auxiliary gate electrode MAG1, and the source-side auxiliary gate electrode SAG1 are formed in a columnar shape with a rectangular cross section when viewed from above, and are arranged in a straight line along the row direction Y between the drain diffusion layer 7 and the source diffusion layer 6 parallel to each other in the column direction X. The drain-side auxiliary gate electrode DAG1 is arranged opposite to the drain-side selection gate structure 11 in the column direction X via the auxiliary gate insulating layer 45a and the semiconductor layer 17. The memory-side auxiliary gate electrode MAG1 is arranged opposite to the memory gate structure 10 in the column direction X via the auxiliary gate insulating layer 45a and the semiconductor layer 17. The source-side auxiliary gate electrode SAG1 is arranged opposite to the source-side selection gate structure 12 in the column direction X via the auxiliary gate insulating layer 45a and the semiconductor layer 17.

[0311] More specifically, the source-side auxiliary gate electrode SAG1 is arranged in a region of the source-side selection gate structure 12 that faces the source-side selection gate electrode SG, with the semiconductor layer 17 and the auxiliary gate insulating layer 45a interposed therebetween. The memory-side auxiliary gate electrode MAG1 is arranged in a region of the memory gate structure 10 that faces the memory gate electrode MG, with the semiconductor layer 17 and the auxiliary gate insulating layer 45a interposed therebetween. The drain-side auxiliary gate electrode DAG1 is arranged in a region of the drain-side selection gate structure 11 that faces the drain-side selection gate electrode DG, with the semiconductor layer 17 and the auxiliary gate insulating layer 45a interposed therebetween.

[0312] In addition, an auxiliary gate insulating layer 45c is provided between the source-side auxiliary gate electrode SAG1 (SAG2) and the source diffusion layer 6, and an auxiliary gate insulating layer 45c is also provided between the drain-side auxiliary gate electrode DAG1 (DAG2) and the drain diffusion layer 7. Thus, the drain-side auxiliary gate electrode DAG1 (DAG2) is electrically isolated from the drain diffusion layer 7 by the auxiliary gate insulating layer 45c. The source-side auxiliary gate electrode SAG1 (SAG2) is electrically isolated from the source diffusion layer 6 by the auxiliary gate insulating layer 45c.

[0313] In addition, auxiliary gate insulating layers 49a and 49b are also provided between the memory side auxiliary gate electrode MAG1 (MAG2) and the source side auxiliary gate electrode SAG1 (SAG2), and between the memory side auxiliary gate electrode MAG1 (MAG2) and the drain side auxiliary gate electrode DAG1 (DAG2). Thus, the memory side auxiliary gate electrode MAG1 (MAG2), the source side auxiliary gate electrode SAG1 (SAG2), and the drain side auxiliary gate electrode DAG1 (DAG2) are electrically isolated from each other by the auxiliary gate insulating layers 49a and 49b.

[0314] In addition, a drain side auxiliary gate line DAGL1 is electrically connected to the drain side auxiliary gate electrodes DAG1 and DAG2 in parallel with the source line SL and the bit line BL, a memory side auxiliary gate line MAGL1 is electrically connected to the memory side auxiliary gate electrodes MAG1 and MAG2 in parallel with the source line SL and the bit line BL, and a source side auxiliary gate line SAGL1 is electrically connected to the source side auxiliary gate electrodes SAG1 and SAG2 in parallel with the source line SL and the bit line BL.

[0315] The auxiliary gate insulating layer 45b is in contact with the semiconductor layer of other memory cells (not shown) adjacent to the memory cell Ce in the column direction X. Fig.33B The auxiliary gate insulating layer 45b located above makes the semiconductor layer 17 of other memory cells (not shown) adjacent to the memory cell Ce above in the column direction X electrically isolated from the drain side auxiliary gate electrode DAG1, the memory side auxiliary gate electrode MAG1 and the source side auxiliary gate electrode SAG1.

[0316] In addition, the auxiliary gate insulating layers 45a, 45b, 45c formed in a manner surrounding the source side auxiliary gate electrode SAG1 (SAG2), the memory side auxiliary gate electrode MAG1 (MAG2) and the drain side auxiliary gate electrode DAG1 (DAG2) are manufactured as an integrated auxiliary gate insulating layer 45 during manufacturing.

[0317] like Fig.33B As shown, one side of the semiconductor layer 17 of the memory cell Ce contacts the source diffusion layer 6, and the other side contacts the side of the drain diffusion layer 7. The source line SL, the bit line BL, the source diffusion layer 6, and the drain diffusion layer 7 are shared by the memory cells Ce in the same column.

[0318] In addition, if Fig.33B As shown, the drain-side auxiliary gate line DAGL1 is connected to and shared with the drain-side auxiliary gate electrodes DAG1 and DAG2 arranged in the same column. The memory-side auxiliary gate line MAGL1 is connected to and shared with the memory-side auxiliary gate electrodes MAG1 and MAG2 arranged in the same column. The source-side auxiliary gate line SAGL1 is connected to and shared with the source-side auxiliary gate electrodes SAG1 and SAG2 arranged in the same column.

[0319] In the third embodiment, the drain side selection gate line BGL1, the source side selection gate line SGL1 and the word line WL1 extend in the row direction Y, and the drain side auxiliary gate line DAGL1, the memory side auxiliary gate line MAGL1 and the source side auxiliary gate line SAGL1 extend in the column direction X.

[0320] In addition, in this embodiment, if Fig.33BAs shown, in a top view, the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 are arranged between the drain side auxiliary gate electrode DAG1, the memory side auxiliary gate electrode MAG1, and the source side auxiliary gate electrode SAG1 arranged along the straight line in the row direction Y, and the drain side auxiliary gate electrode DAG2, the memory side auxiliary gate electrode MAG2, and the source side auxiliary gate electrode SAG2 arranged along the straight line in the row direction Y. However, the present invention is not limited to this. For example, it is also possible to arrange that in a top view, the drain side auxiliary gate electrode DAG2, the memory side auxiliary gate electrode MAG2, and the source side auxiliary gate electrode SAG2 are not provided on the other side, and only the drain side auxiliary gate electrode DAG1, the memory side auxiliary gate electrode MAG1, and the source side auxiliary gate electrode SAG1 are arranged on one side.

[0321] In addition, although the top cross-sectional structure of a portion where a plurality of memory cells Ce are arranged in a row along the column direction X is omitted, it is a structure in which the second embodiment is arranged in a row. Fig.26 The auxiliary gate electrode AG shown 11 AG 21 The structure is replaced with the arrangement structure of the drain side auxiliary gate electrodes DAG1 and DAG2, the memory side auxiliary gate electrodes MAG1 and MAG2, and the source side auxiliary gate electrodes SAG1 and SAG2 shown in FIG. 33 .

[0322] (3-3) Data writing operation Next, the operation of writing data into the memory cell Ce shown in FIG. 33 will be described. Fig.33A When data is written into the memory cell Ce shown in FIG. 1 , a source side auxiliary gate voltage V of 0 V to 2 V is applied to the source side auxiliary gate electrode SAG. AssistS , a drain-side auxiliary gate voltage V of 0 V is applied to the drain-side auxiliary gate electrode DAG AssistD , a memory side auxiliary gate voltage V of 0V to 8V is applied to the memory side auxiliary gate electrode MAG AssistM At this time, for example, the source voltage V SL The source side gate voltage Vt is applied to the source line SL, which is smaller than the threshold voltage Vt of the source side selection transistor ST. SGS The voltage is applied to the source side selection gate electrode SG, and the source side selection transistor ST is turned off.

[0323] At this time, a write bit voltage V of 0 V is applied to the bit line BL. BL A drain-side gate voltage Vt greater than the threshold voltage Vt of the drain-side selection transistor DT is applied to the drain-side selection gate electrode DG. SGD, the drain - side selection transistor DT is turned on.

[0324] Furthermore, for example, by applying a write memory gate voltage V of 10V to the memory gate electrode MG CG0 (write - select memory gate voltage), in the memory cell Ce, as Fig.33B shown, the semiconductor layer 17 near the outer periphery of the memory gate structure 10 becomes the same potential as the write - select bit voltage V BL0 . Thus, in the memory cell Ce, charges move from the semiconductor layer 17 and / or the memory gate electrode MG to the charge storage layer 15b included in the multi - layer insulating layer 15 of the memory gate structure 10, and it becomes a state where data is written.

[0325] In addition, in the third embodiment, as also described in the above - mentioned first embodiment Figure 7B , in the multi - layer insulating layer 15 including the charge storage layer 15b, if the distance ta in the plane direction of the first memory gate insulating layer 15a is greater than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta>tc), then charges move from the semiconductor layer 17 around the outer periphery of the second memory gate insulating layer 15c to the charge storage layer 15b. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta<tc), then charges move from the memory gate electrode MG to the charge storage layer 15b.

[0326] Next, as Fig.34A shown, taking a memory array CAd as an example, in which two memory cells Ce1 and Ce2 are arranged along the column direction X in the upper layer, and two memory cells Ce3 and Ce4 are also arranged along the column direction X in the lower layer, a page is composed of the memory cells Ce1 and Ce3 arranged in the vertical direction Z, and another page is composed of the memory cells Ce2 and Ce4 arranged in the vertical direction Z, the write operation of data in this memory array CAd will be described.

[0327] Here, the case of writing data to the memory cell Ce1 as the selected memory cell among the memory cells Ce1, Ce2, Ce3, and Ce4 will be described. At this time, the page including the selected memory cell Ce1 containing the written data is taken as the write - select page, and the page composed only of the non - selected memory cells Ce2 and Ce4 that do not write data is taken as the write - non - select page.

[0328] In addition, without specifically distinguishing between the memory transistors MT1, MT2, MT3, MT4, the drain side selection transistors DT1, DT2, DT3, DT4, and the source side selection transistors ST1, ST2, ST3, ST4, they are simply represented as the memory transistor MT, the drain side selection transistor DT, and the source side selection transistor ST.

[0329] in addition, Fig.34B 2 shows an example of voltages of various parts in the memory array CAd at this time. A non-selected source side gate voltage V SGS2 The drain side auxiliary gate voltage V AssistD (For example, 0 V). In addition, a memory side auxiliary gate voltage V AssistM (e.g., 0V or a positive voltage of 0 to 8V), a source-side auxiliary gate voltage V is applied to the source-side auxiliary gate line SAGL. AssistS (For example, 0V or a positive voltage of 0 to 2V).

[0330] As a result, in the drain side selection transistors DT of the memory cells Ce1, Ce2, Ce3, and Ce4, a drain side auxiliary gate voltage V is applied to the semiconductor layer 17 near the drain side auxiliary gate electrode DAG. AssistD In addition, in the memory transistors MT of the memory cells Ce1, Ce2, Ce3, and Ce4, a memory side auxiliary gate voltage V is applied to the semiconductor layer 17 near the memory side auxiliary gate electrode MAG. AssistM Furthermore, in the source side selection transistors ST of the memory cells Ce1, Ce2, Ce3, and Ce4, a source side auxiliary gate voltage V is applied to the semiconductor layer 17 near the source side auxiliary gate electrode SAG. AssistS .

[0331] In the memory array CAd, a write selection bit voltage V is applied to the bit line BL1 which is the selection bit line connected to the selected memory cell Ce1. BL1 (For example, a low voltage of 0 to 1.5 V) A write selection drain gate voltage V higher than the threshold voltage Vt (preferably a positive value, also expressed as Vt(DT)) of the drain selection transistor DT is applied to the drain selection gate line BGL1 connected to the selected memory cell Ce1. SGD1 As a result, in the selected memory cell Ce1, the drain side selection transistor DT1 becomes conductive, and the selection bit voltage V BL1 Passed to memory transistor MT1.

[0332] In the non - selected memory cell Ce3 that does not write data within the write - select page, the same voltage as that of the selected memory cell Ce1 is applied from the drain - side select gate line BGL1, which is shared with the selected memory cell Ce1, to the drain - side select gate electrode DG of the drain - side select transistor DT3. However, by applying a write non - selected bit voltage V to the bit line BL2 that becomes a non - selected bit line, BL2 , thus, the drain - side select transistor DT3 becomes in an off state.

[0333] In addition, in the memory array CAd, a positive voltage (e.g., 1 - 2V) is uniformly applied to the source line SL. On the source - side select gate line SGL1 connected to the selected memory cell Ce1, a write - select source - side gate voltage V lower than the threshold voltage Vt of the source - side select transistor ST1 (preferably a positive value, also denoted as Vt(ST)) is applied. SGS1 . Thus, in the selected memory cell Ce1, the source - side select transistor ST1 becomes in an off state.

[0334] In addition, a write - select memory gate voltage V CG1 (e.g., a high voltage of 7 - 15V) is applied to the word line WL1 connected to the selected memory cell Ce1. In the selected memory cell Ce1, due to the write - select memory gate voltage V of the word line WL1, CG1 the potential of the memory gate electrode MG becomes a high potential. Similar to the first embodiment, for example, when ta (the distance in the plane direction of the first memory gate insulating layer 15a)>tc (the distance in the plane direction of the second memory gate insulating layer 15c), electrons move from the semiconductor layer 17 to the charge storage layer 15b, or holes move from the charge storage layer 15b to the semiconductor layer 17, and it becomes a state where data is written. Thus, the threshold voltage of the memory transistor MT1 of the selected memory cell Ce1 becomes higher. On the other hand, when ta < tc, electrons escape from the charge storage layer 15b and move to the memory gate electrode MG, or holes move from the memory gate electrode MG to the charge storage layer 15b. Thus, the threshold voltage of the memory transistor MT1 of the selected memory cell Ce1 becomes lower.

[0335] At this time, a write non - selected bit voltage V is applied to other bit lines BL2 that are non - selected bit lines not connected to the selected memory cell Ce1. BL2 The write non - selected bit voltage V BL2 is preferably a positive voltage (e.g., 1.5 - 3V).

[0336] Thus, in the non-selected memory cell Ce3 in which data is not written in the write selected page, the same voltage as that of the selected memory cell Ce1 is applied to the drain side selection gate electrode DG of the drain side selection transistor DT3 from the drain side selection gate line BGL1 shared with the selected memory cell Ce1, but the write non-selected bit voltage V is applied to the bit line BL2 which becomes the non-selected bit line. BL2 , thereby, the drain side selection transistor DT3 becomes in the off state.

[0337] In the write selection page, although the non-selected memory cell Ce3 shares the drain side selection gate line BGL1, the word line WL1, and the source side selection gate line SGL1 with the selected memory cell Ce1, the drain side selection transistor DT3 and the source side selection transistor ST3 of the non-selected memory cell Ce3 are turned off. Therefore, in the non-selected memory cell Ce3, even if the write selection memory gate voltage V CG1 (For example, a high voltage of 7 to 15 V), and since the potential of the semiconductor layer 17 around the memory transistor MT3 rises, the write selection memory gate voltage V CG1 Therefore, in the non-selected memory cell Ce3, the channel current does not flow into the charge storage layer 15b of the memory transistor MT3, and the movement of charges to the charge storage layer 15b can be blocked, thereby preventing the writing of data.

[0338] In addition, Fig.34A Although the non-selected memory cells (i.e., the memory cells arranged on the deeper side of the paper or the front side of the paper relative to the memory cells Ce1 and Ce3) arranged on other columns in the write selection page are not shown in the figure, in the case of the non-selected memory cells, the drain side selection gate line BGL1, the word line WL1 and the source side selection gate line SGL1 are shared with the selected memory cell Ce1, but similarly to the above-mentioned non-selected memory cell Ce3, the same voltage as the bit line BL2 and the source line SL2 is applied to each bit line BL and the source line SL, respectively, so that the drain side selection transistor DT and the source side selection transistor ST can be turned off to prevent the writing of data.

[0339] In addition, similarly to the above, at this time, in the non-selected memory cells configured in other columns in these write selection pages (memory cells configured on the deep side or the front side of the paper relative to the memory cells Ce1 and Ce3), the drain side auxiliary gate voltage V is also applied from the drain side auxiliary gate line DAGL. AssistD , the memory side auxiliary gate voltage V is applied from the memory side auxiliary gate line MAGL AssistM , the source side auxiliary gate voltage V is applied from the source side auxiliary gate line SAGL AssistSTherefore, the potential of the semiconductor layer 17 near the word line WL1 also changes according to the drain side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM And the source side auxiliary gate voltage V AssistS When the drain side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM And the source side auxiliary gate voltage V AssistS When the potential of the semiconductor layer 17 rises, the potential difference between the potential of the semiconductor layer 17 and the word line WL1 decreases. This makes it possible to more effectively prevent data from being written.

[0340] Next, a write non-selected page consisting only of non-selected memory cells Ce2 and Ce4 is described. In this case, since the bit lines BL1 and BL2 and the source lines SL1 and SL2 connected to the non-selected memory cells Ce2 and Ce4 are shared with the memory cells Ce1 and Ce3 in the above-mentioned write selected page, their description is omitted here, and the drain side selection gate line BGL2, the word line WL2 and the source side selection gate line SGL2 are described.

[0341] In writing non-selected pages, a low potential (for example, 0 V) ​​writing non-selected drain side gate voltage V is applied to the drain side selection gate line BGL2, the word line WL2, and the source side selection gate line SGL2. SGD2 , write non-select memory gate voltage V CG2 and write non-selected source side gate voltage V SGS2 Thus, in each non-selected memory cell Ce2, Ce4 in which the non-selected page is written, at both ends of the memory transistors MT2, MT4, the drain side selection transistors DT2, DT4 and the source side selection transistors ST2, ST4 are respectively turned off, so that the channel current does not flow into the charge storage layer 15b of the memory transistors MT2, MT4, and the movement of charges to the charge storage layer 15b can be blocked, thereby preventing the writing of data.

[0342] In addition, similarly to the above, at this time, the drain-side auxiliary gate voltage V is also applied from the drain-side auxiliary gate line DAGL to the non-selected memory cells Ce2 and Ce4 of the non-selected page for writing. AssistD , the memory side auxiliary gate voltage V is applied from the memory side auxiliary gate line MAGL AssistM , the source side auxiliary gate voltage V is applied from the source side auxiliary gate line SAGL AssistS Thus, in the drain side selection transistors DT2 and DT4 and the source side selection transistors ST2 and ST4, the potentials of the semiconductor layer 17 near the drain side auxiliary gate electrode DAG and the semiconductor layer 17 near the source side auxiliary gate electrode SAG are respectively in an increased state.

[0343] In particular, by applying the drain side auxiliary gate voltage V AssistD (e.g., 0 V), a source side auxiliary gate voltage V is applied from the source side auxiliary gate line SAGL AssistS (e.g., 0 V), even when writing to a non-selected page, the drain side selection transistors DT2, DT4 and the source side selection transistors ST2, ST4 can be reliably turned off. In addition, in each memory transistor MT of the non-selected memory cells Ce2, Ce3, Ce4, since the movement of charges to the charge storage layer 15b is blocked, the threshold voltage does not change.

[0344] In this way, in the memory array CAd, it is possible to prevent data from being written into the non-selected memory cells Ce2, Ce3, and Ce4, and to write data only into the selected memory cell Ce1.

[0345] As described above, in the third embodiment, during the data writing operation, the source side auxiliary gate voltage V AssistS , memory side auxiliary gate voltage V AssistM , and the drain side auxiliary gate voltage V AssistD , the potential of the semiconductor layer 17 around the source side selection gate structure 12, the potential of the semiconductor layer 17 around the memory gate structure 10, and the potential of the semiconductor layer 17 around the drain side selection gate structure 11 can be independently adjusted. Therefore, in this embodiment, the leakage current can be suppressed more reliably.

[0346] (3-4) Data clearing action Next, the clearing operation of the data in the memory cell Ce shown in FIG. 33 will be described. Fig.33A When data is cleared in the memory cell Ce shown in the figure, a positive source side auxiliary gate voltage V of 7V to 12V is applied to the source side auxiliary gate electrode SAG. AssistS , a positive voltage of 7V to 12V is applied to the drain side auxiliary gate electrode DAG. AssistD , a positive voltage of 7V to 12V is applied to the memory side auxiliary gate electrode MAG. AssistM .

[0347] As a result, the potential of the semiconductor layer 17 near the drain-side auxiliary gate electrode DAG, the potential of the semiconductor layer 17 near the memory-side auxiliary gate electrode MAG, and the potential of the semiconductor layer 17 near the source-side auxiliary gate electrode SAG rise to substantially the same value. AssistD , memory side auxiliary gate voltage V AssistM And the source side auxiliary gate voltage VAssistS The values ​​of are preferably the same value.

[0348] At this time, for example, a positive high voltage (for example, 7 to 12 V) source voltage V SL Applied to the source line SL, the bit voltage V BL The same clear select source side gate voltage V SGS The voltage is applied to the source side selection gate line SGL connected to the source side selection gate electrode SG of the source side selection transistor ST.

[0349] Similarly, a positive high voltage (e.g., 7 to 12 V) bit voltage V BL Applied to the bit line BL, it will be connected to the bit voltage V BL Same clear select drain side gate voltage V SGD is applied to the drain side selection gate line BGL connected to the drain side selection gate electrode DG of the drain side selection transistor DT. As a result, the potential of the semiconductor layer 17 on the drain side of the source side selection transistor ST becomes V SGS -V t Similarly, the potential of the semiconductor layer 17 on the drain side of the drain side selection transistor DT also becomes V SGD -V t .

[0350] In addition, the clear selection memory gate voltage V CG1 is applied to the word line WL connected to the memory gate electrode MG of the memory transistor MT. As a result, a potential difference is generated between the memory gate electrode MG of the memory transistor MT and the semiconductor layer 17, and charges are moved from the charge storage layer 15b, resulting in a state where data is cleared. At this time, in the third embodiment, due to the drain-side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM , and the source side auxiliary gate voltage V AssistS , the potential of the semiconductor layer 17 rises, thereby increasing the potential difference with the memory gate electrode MG, and the electrons in the charge storage layer 15b move at a higher speed.

[0351] In addition, in the third embodiment, similar to the first embodiment described above, in the multilayer insulating layer 15 including the charge storage layer 15b, if the distance ta in the plane direction of the first memory gate insulating layer 15a is greater than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta > tc), then during the data erasure operation, electrons move from the charge storage layer 15b to the semiconductor layer 17, or holes move from the semiconductor layer 17 to the charge storage layer 15b. As a result, the threshold value of the memory transistor MT decreases. On the other hand, if the distance ta in the plane direction of the first memory gate insulating layer 15a is less than the distance tc in the plane direction of the second memory gate insulating layer 15c (i.e., ta < tc), then electrons move from the charge storage layer 15b to the memory gate electrode MG, or holes move from the memory gate electrode MG to the charge storage layer 15b. As a result, the threshold value of the memory transistor MT increases.

[0352] Next, similar to the above-mentioned "(3-3) Data writing operation", as Fig.35A shown, taking a memory array CAd in which memory cells Ce1 and Ce3 arranged in the vertical direction Z form one page and memory cells Ce2 and Ce4 arranged in the same vertical direction Z form another page as an example, the data erasure operation in this memory array CAd will be described.

[0353] Here, a case where data is erased in units of pages, the data of the page composed of memory cells Ce1 and Ce3 is erased, and the data of the page composed of non-selective memory cells Ce2 and Ce4 that are not erased is not erased will be described. At this time, the page for erasing data is set as the erasure selection page, and the page composed only of non-selective memory cells Ce2 and Ce4 that do not erase data is set as the erasure non-selection page. In addition, the threshold voltages Vt of the drain-side selection transistors DT and the source-side selection transistors ST of the memory cells Ce1, Ce2, Ce3, and Ce4 are preferably positive values.

[0354] In addition, Fig.35B An example of the voltages of each part in the memory array CAd at this time is shown. On the drain-side auxiliary gate line DAGL, the memory-side auxiliary gate line MAGL, and the source-side auxiliary gate line SAGL connected to the memory cells Ce1, Ce2, Ce3, and Ce4, a positive high voltage (for example, 7 to 12 V) of the same value, namely the drain-side auxiliary gate voltage V AssistD , the memory-side auxiliary gate voltage V AssistM , and the source-side auxiliary gate voltage V AssistS are applied respectively. As a result, a predetermined voltage is applied to the semiconductor layer 17 of the memory cells Ce1, Ce2, Ce3, and Ce4.

[0355] In the memory array CAd, an erase bit voltage V is applied to the bit lines BL1 and BL2 common to the erase selected page and the erase non-selected page. BL1 、V BL2 (Also denoted as “V BL1、2 ”. For example, a high voltage of 7 to 12 V is applied to the source lines SL1 and SL2 to clear the bit voltage V BL1 、V BL2 The source voltage V of the same voltage (for example, a high voltage of 7 to 12 V) SL .

[0356] In the clear selection page, for example, the clear bit voltage V BL1 、V BL2 The same 7-12V high voltage clear select drain side gate voltage V SGD1 Applied to the drain side select gate line BGL1, similarly, it will be connected to the clear bit voltage V BL1 、V BL2 The same 7-12V high voltage clear select source side gate voltage V SGS1 is applied to the source side selection gate line SGL1. In addition, in the clear selection page, the clear selection memory gate voltage V CG1 This is applied to the word line WL1. Thus, in the erase selected page, a potential difference is generated between the memory gate electrode MG and the surrounding semiconductor layer 17 in each of the memory cells Ce1 and Ce3, and charges are transferred from the charge storage layer 15b, thereby erasing the data.

[0357] On the other hand, in erasing the non-selected page, the clear bit voltage V BL1 、V BL2 The same voltage (e.g., a high voltage of 7 to 12 V) is used as the clear non-select drain side gate voltage V SGD2 , Clear the non-selected source side gate voltage V SGS2 and clear the non-select memory gate voltage V CG2 , respectively applied to the drain side selection gate line BGL2, the source side selection gate line SGL2 and the word line WL2. Thus, in erasing the non-selected page, in each memory cell Ce2, Ce4, no potential difference is generated between the memory gate electrode MG and the semiconductor layer 17 surrounding it, and the charge does not move from the charge storage layer 15b, which can prevent the data from being erased.

[0358] in addition, Fig.35C An example of voltages of various parts in a data clearing operation according to another embodiment is shown, and Fig.35B Compared to the clear select source side gate voltage V SGS1and clear select drain side gate voltage V SGD1 , drain side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM , source side auxiliary gate voltage V AssistS The voltage value of the other parts is different. Fig.35B same.

[0359] In this case, if Fig.35B As shown, the drain side auxiliary gate line DAGL, the memory side auxiliary gate line MAGL and the source side auxiliary gate line SAGL are respectively applied with the same positive high voltage (eg, 5-10V) of the drain side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM and source side auxiliary gate voltage V AssistS In addition, in the clear selection page, for example, the clear selection drain side gate voltage V is set to a high voltage of 4 to 9 V. SGD1 The drain side select gate line BGL1 is applied to the drain side select gate line. Similarly, the clear select source side gate voltage V SGS1 In the erase selection page, even if such a voltage is applied, in each memory cell Ce1, Ce3, charges are moved from the charge storage layer 15b by utilizing the potential difference generated between the memory gate electrode MG and the surrounding semiconductor layer 17, thereby erasing data.

[0360] As described above, in the third embodiment, during the data clearing operation, a positive drain-side auxiliary gate voltage V is applied to the memory cells Ce1, Ce2, Ce3, and Ce4. AssistD , memory side auxiliary gate voltage V AssistM , and the source side auxiliary gate voltage V AssistS , thereby, the potential of the semiconductor layer 17 of the memory cells Ce1, Ce2, Ce3, and Ce4 becomes high. Therefore, in erasing the non-selected page, the drain side auxiliary gate voltage V is not applied to each memory cell Ce2 or Ce4. AssistD , memory side auxiliary gate voltage V AssistM And the source side auxiliary gate voltage V AssistS Compared with the case of , the potential difference between the memory gate electrode MG and the surrounding semiconductor layer 17 becomes smaller, and data erasure can be suppressed more effectively.

[0361] In the third embodiment, data is erased in units of pages, but the present invention is not limited thereto, and all pages may be set as erase selection pages to erase data in all memory cells Ce constituting the memory array CAd.

[0362] (3-5) Data reading operation Next, the data reading operation in the memory array CAd is described. In addition, here, similarly to the above-mentioned "(3-3) Data writing operation", Fig.36A As shown, taking a memory array CAd in which memory cells Ce1 and Ce3 arranged in the vertical direction Z constitute one page and memory cells Ce2 and Ce4 arranged in the vertical direction Z constitute another page as an example, the data reading operation in the memory array CAd is described.

[0363] Here, the case where, for example, memory cells Ce1 and Ce3 among memory cells Ce1, Ce2, Ce3, and Ce4 are used as selected memory cells Ce1 and Ce3 to read data is described. At this time, the page including the selected memory cells Ce1 and Ce3 whose data are to be read is used as the read selected page, and the page consisting of only the non-selected memory cells Ce2 and Ce4 whose data are not to be read is used as the read non-selected page.

[0364] in addition, Fig.36B The following is an example of the voltage of each part in the memory array CAd at this time. At this time, the same low voltage (for example, 0V) drain side auxiliary gate voltage V is applied to the drain side auxiliary gate line DAGL, the memory side auxiliary gate line MAGL, and the source side auxiliary gate line SAGL connected to the memory cells Ce1, Ce2, Ce3, and Ce4. AssistD , memory side auxiliary gate voltage V AssistM and source side auxiliary gate voltage V AssistS In the memory array CAd, a read bit voltage V is applied to the bit lines BL1 and BL2 shared by the read selected page and the read non-selected page. BL1 、V BL2 (both are the same positive voltage, for example, 1V), and a read source voltage V is applied to the source lines SL1 and SL2 respectively. SL (The source lines SL are all at the same voltage, for example, 0V).

[0365] In addition, in the read selection page, for example, a voltage higher than the threshold voltage Vt(DT) of the drain side selection transistor DT1 (for example, 2V) is set as the read selection drain side gate voltage V SGD1 The drain side selection gate line BGL1 is applied. Similarly, a voltage higher than the threshold voltage Vt(ST) of the source side selection transistor ST1 (for example, 2V) is used as the read selection source side gate voltage V SGS1 The voltage is applied to the source-side selection gate line SGL1 , thereby turning on the drain-side selection transistor DT1 and the source-side selection transistor ST1 of the selected memory cell Ce1 .

[0366] At this time, in the read selection page, by applying a low voltage (for example, 0V) drain side auxiliary gate voltage V AssistD , memory side auxiliary gate voltage V AssistM and source side auxiliary gate voltage V AssistS The potential of the semiconductor layer 17 is lowered, and accordingly, leakage current from the source line SL1 to the bit line BL1 can be suppressed.

[0367] Furthermore, in the read selection page, for example, the read selection memory gate voltage V is set to 0 to 6V. CG1 As a result, in the selected memory cell Ce1, no data is written into the memory transistor MT1, and the threshold voltage Vt of the memory transistor MT1 is lower than the read selected memory gate voltage V CG1 When the voltage is low, current flows from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 changes.

[0368] On the other hand, when data is written into the memory transistor MT1 of the selected memory cell Ce1, the threshold voltage Vt of the memory transistor MT1 is lower than the read selected memory gate voltage Vt. CG1 When the voltage is high, the current does not flow from the source line SL1 to the bit line BL1, and the potential of the bit line BL1 does not change. Then, by using the column decoder 2b ( Figure 1 ) detects the change in the potential of the bit line BL1, and can read the data of the selected memory cell Ce1. In addition, at this time, by using the column decoder 2b ( Figure 1 ) detects the change in the potential of the bit line BL2, and data can also be read from another selected memory cell Ce3 in the read selection page.

[0369] In reading the non-selected page, a voltage lower than the threshold voltage Vt of the drain-side selection transistor DT2 (for example, 0V) is used as the non-selected drain-side gate voltage Vt. SGD2 The drain side selection gate line BGL2 is applied to the drain side selection gate line. Similarly, a voltage lower than the threshold voltage Vt of the source side selection transistor ST2 (for example, 0V) is used as the reading non-selected source side gate voltage V SGS2 Applied to the source side selection gate line SGL2.

[0370] As a result, the drain side selection transistors DT and source side selection transistors ST of the non-selected memory cells Ce2 and Ce4 of the read non-selected page are turned off, and current does not flow from the source lines SL1 and SL2 to the bit lines BL1 and BL2. As described above, data is read only from the selected memory cells Ce1 and Ce3 of the read selected page.

[0371] In addition, when detecting multi-value data using one memory cell Ce, by changing the read selection memory gate voltage V CG1 By detecting the change in the potential of the bit line BL1 at each voltage value, it is possible to detect the fine threshold voltage of the memory transistor MT and read multi-value data.

[0372] Fig.36C An example of voltage at each part in a data read operation according to another embodiment is shown. Fig.36C The voltage during data reading is shown in Fig.36B The difference is that in the read selection page, the read selection memory gate voltage V CG1 (for example, 0V) is applied to the word line WL1 as a fixed voltage, and the voltages of other parts are Fig.36B same.

[0373] The cell current flowing from the source line SL1 to the bit line BL1 through the selected memory cell Ce1 is determined by the read selected memory gate voltage V CG1 The threshold difference (V CG1 The column decoder 2b detects the magnitude of the cell current flowing from the source line SL1 to the bit line BL1 via the selected memory cell Ce1, and in the column decoder 2b, the threshold voltage Vt of the memory transistors MT1 and MT3 is determined to determine whether data is written into the memory transistors MT1 and MT3.

[0374] In this case, the data written into the memory transistors MT1 and MT3 can be distinguished and multi-valued data can be read according to the value of the cell current flowing from the source line SL1 to the bit line BL1 through the selected memory cell Ce1. Fig.36B The same, so the description is omitted here.

[0375] (3-6) Specific Examples of Voltages in Data Writing, Erasing, and Reading Operations Table 5 below shows specific examples (voltage examples) of voltage combinations during the data writing operation, the erasing operation (the erasing operation based on channel current induction and the erasing operation based on junction destruction induction) and the reading operation of the third embodiment. The unit of the voltage values ​​shown in Table 5 is "V".

[0376] In Table 5, "BL column" indicates a column of a memory cell Ce group electrically connected to a bit line BL extending from the column decoder 2b in the column direction X. Figure 1Similarly, the column decoder 2b is configured as a two-dimensional structure of the row direction Y and the vertical direction Z as the paper depth direction in the figure. There are two directions in the BL column, the row direction Y and the vertical direction Z as the paper depth direction. Strictly speaking, they can also be specified. However, in Table 5, in order to simplify the description, the row direction Y and the vertical direction Z as the paper depth direction are not particularly distinguished, and the focus is on Fig.34A , Fig.35A and Fig.36A The actions are organized into selected and non-selected pages as shown. Table 5

[0377] In the nonvolatile semiconductor memory device according to the third embodiment, by applying voltages as shown in Table 5, the voltages can be adjusted in units of pages in the memory array CAd, and data can be selectively written, erased, and read from predetermined memory cells Ce.

[0378] (3-7) Method for Manufacturing Memory Array According to Third Embodiment Next, use Figures 37 to 46 The manufacturing method of the memory array CAd is described below. Fig.37 As shown, an insulating layer 51 is stacked on a substrate 20 made of silicon, for example, and interlayer insulating layers 52 of a type different from that of the insulating layer 51 and silicon layers 53 made of, for example, polycrystalline silicon are alternately stacked on the insulating layer 51. In addition, on the interlayer insulating layer 52 located at the uppermost layer among the interlayer insulating layers 52, the insulating layer 51 and another insulating layer 51a of a type different from that of the interlayer insulating layer 52 are stacked, and a mask layer 54 for masking made of, for example, Al2O3, carbon, SiC, etc. is further formed thereon. Here, the insulating layer 51 and the insulating layer 51a are made of a material different from that of the silicon layer 53, and are layers that are difficult to be etched when the interlayer insulating layer 52 and the silicon layer 53 are etched.

[0379] Then, if Fig.38A and 38B As shown, the mask layer 54 is selectively etched using a predetermined mask layer, for example, by a dry etching method. Fig.38A 2 is a schematic diagram showing the mask layer 54 after etching when viewed from above. Fig.38B Yes means Fig.38A The cross-sectional view of the cross-sectional structure of the MM' part. Fig.38AAs shown, opening portions are formed in accordance with predetermined regions (gate structure formation regions) 54a, 54b, 54c for forming the source side selection gate structure 12, the memory gate structure 10 and the drain side selection gate structure 11, and with predetermined regions (auxiliary gate electrode formation regions) 54d for forming the source side auxiliary gate electrode SAG, the memory side auxiliary gate electrode MAG and the drain side auxiliary gate electrode DAG.

[0380] The openings of the gate structure forming regions 54 a , 54 b , and 54 c and the opening of the auxiliary gate electrode forming region 54 d formed in the mask layer 54 are in a state where the surface of the insulating layer 51 a is exposed.

[0381] Next, a new mask layer is formed on the mask layer 54 to cover the gate structure formation region 54b where the memory gate structure 10 is formed among the gate structure formation regions 54a, 54b, and 54c formed on the mask layer 54. Fig.39A The new mask layer 55a formed in such a manner as to cover the gate structure forming region 54b shows Fig.38A 2 is a cross-sectional view of the cross-sectional structure of the MM′ portion shown in FIG. Then, using the new mask layer 55a as a mask, the gate structure forming region 54a where the source side selection gate structure 12 is formed and the gate structure forming region 54c where the drain side selection gate structure 11 is formed are etched in the vertical direction Z by a dry etching method. Thus, the insulating layer 51a, the interlayer insulating layer 52 and the silicon layer 53 in the gate structure forming regions 54a and 54c are etched along the vertical direction Z from the surface of the insulating layer 51a to the surface of the insulating layer 51.

[0382] Thus, a hole ER15 for forming a source side selection gate structure is formed in the gate structure formation region 54a, and a hole ER16 for forming a drain side selection gate structure is formed in the gate structure formation region 54c. In addition, at this time, even in the auxiliary gate electrode formation region 54d not covered by the mask layer 55a, the insulating layer 51a, the interlayer insulating layer 52, and the silicon layer 53 are etched from the surface of the insulating layer 51a to the surface of the insulating layer 51 by dry etching along the vertical direction Z. Thus, a hole for forming an auxiliary gate electrode (not shown) is formed in the auxiliary gate electrode formation region 54d. Then, the uppermost mask layer 55a is removed.

[0383] Then, if Fig.39BAs shown, insulating materials such as silicon oxide films are deposited in the hole ER15 for forming the source side selection gate structure, in the hole ER16 for forming the drain side selection gate structure, and in the opening of the gate structure forming region 54b. As a result, a source side selection gate insulating layer 14b is formed along the side and bottom surface of the hole ER15 for forming the source side selection gate structure, a drain side selection gate insulating layer 14a is formed along the side and bottom surface of the hole ER16 for forming the drain side selection gate structure, and an insulating layer 56a is also formed in the gate structure forming region 54b. Then, gate materials such as low-resistance polysilicon or tungsten are deposited in the regions surrounded by the source side selection gate insulating layer 14b and the drain side selection gate insulating layer 14a, respectively, so that a source side selection gate electrode SG and a drain side selection gate electrode DG are formed in the regions surrounded by the source side selection gate insulating layer 14b and the drain side selection gate insulating layer 14a. At this time, in the gate structure forming region 54 b , the gate material is also deposited in the region surrounded by the insulating layer 56 a to form a gate material deposited portion 56 b .

[0384] In addition, when the source side selection gate insulating layer 14b and the drain side selection gate insulating layer 14a are formed in the hole ER15 for forming the source side selection gate structure and the hole ER16 for forming the drain side selection gate structure, an auxiliary gate insulating layer 45 is also formed along the side surface and the bottom surface inside the hole for forming the auxiliary gate electrode. Fig.41A ). In addition, when the source side selection gate electrode SG and the drain side selection gate electrode DG are formed, a gate material is also deposited in the area surrounded by the auxiliary gate insulating layer 45 to form an auxiliary gate electrode 58 ( Fig.41A ).

[0385] Next, the insulating material or gate material deposited on the mask layer 54 is removed by surface grinding to expose the upper surface of the mask layer 54. In this way, the source side selection gate structure 12 is formed in the hole ER15 for forming the source gate electrode, and the drain side selection gate structure 11 is formed in the hole ER16 for forming the drain gate electrode.

[0386] In addition, here, Fig.39A The mask layer 55a shown is removed after forming the hole ER15 for forming the source side selection gate structure and the hole ER16 for forming the drain side selection gate structure, but the mask layer 55a may be not removed, and an insulating material and a gate material may be deposited in the hole ER15 for forming the source side selection gate structure and the hole ER16 for forming the drain side selection gate structure, respectively. In this case, the insulating layer 56a and the gate material deposition portion 56b are not formed on the gate structure formation region 54b, and then the mask layer 55a is removed.

[0387] Next, on the mask layer 54, a new mask layer is formed on the mask layer 54, wherein the new mask layer covers the gate structure forming region 54a where the source side selection gate structure 12 is formed, the gate structure forming region 54c where the drain side selection gate structure 11 is formed, and the auxiliary gate electrode forming region 54d where the auxiliary gate insulating layer 45 and the auxiliary gate electrode 58 are formed. Fig.40A The new mask layer 55b formed in such a manner as to cover the gate structure forming regions 54a, 54c and the auxiliary gate electrode forming region 54d is shown. Fig.38A A cross-sectional view of the cross-sectional structure of the MM′ portion is shown.

[0388] Using the mask layer 55b as a mask, the insulating layer 56a, the gate material deposition portion 56b, the insulating layer 51a, the interlayer insulating layer 52, and the silicon layer 53 are etched along the vertical direction Z to the surface of the insulating layer 51 in the gate structure formation region 54b where the memory gate structure 10 is formed and not covered by the mask layer 55b. Fig.40A As shown, a hole ER17 for forming a memory gate structure having the same outer contour shape as that of the gate structure forming region 54b is formed in the gate structure forming region 54b.

[0389] Then, if Fig.40B As shown in the figure, after the multilayer insulating layer 15 is formed along the side and bottom of the hole ER17 for forming the memory gate structure, a gate material of a metal such as low-resistance polysilicon or tungsten is deposited on the multilayer insulating layer 15, thereby forming a memory gate electrode MG in a region surrounded by the multilayer insulating layer 15. Then, the insulating material and gate material deposited on the mask layer 55b, the mask layer 54, etc. are removed by surface grinding, and the memory gate structure 10 is formed in the hole ER17 for forming the memory gate structure.

[0390] In this way, the columnar memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 are respectively provided upright on the substrate 20 via the insulating layer 51 as an insulating layer. As described later, along the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12, the memory cells Ce are formed at predetermined intervals on each level, and the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 are shared by a plurality of memory cells Ce arranged in the vertical direction Z. In addition, since the longitudinal cross-sectional structures of the memory gate structure 10, the drain side selection gate structure 11, and the source side selection gate structure 12 are the same as those in the second embodiment, the description thereof is omitted here.

[0391] In addition, hole ER15, hole ER16 ( Fig.39A ) and hole ER17( Fig.40A ) The order of the formation process is not limited to the above order and may be changed appropriately.

[0392] Next, the mask layer 54 is removed by surface grinding, as shown in FIG. Fig.41A and 41B As shown, the insulating layer 51a is exposed on the surface. Fig.41A 2 is a schematic diagram showing a structure when the insulating layer 51a is exposed on the surface when viewed from above. Fig.41B Yes means Fig.41A In this case, the source side selection gate structure 12, the memory gate structure 10, the drain side selection gate structure 11, and the auxiliary gate electrode 58 surrounded by the auxiliary gate insulating layer 45 are exposed on the surface of the insulating layer 51a.

[0393] Next, a new patterned mask layer (not shown) is formed on the surface of the insulating layer 51a, and the predetermined areas of each auxiliary gate electrode 58 are etched along the vertical direction Z to the surface of the insulating layer 51 using the mask layer to form two holes that penetrate the auxiliary gate electrode 58 along the vertical direction Z. After dividing the auxiliary gate electrode 58 into three, the mask layer is removed. Fig.42A 1 is a schematic diagram showing the structure of two holes ER18a and 18b formed in each auxiliary gate electrode 58 when viewed from above. Fig.42B Yes means Fig.42A A cross-sectional view of the cross-sectional structure of the NN′ part.

[0394] like Fig.42A and Fig.42B As shown, by forming two holes ER18a and 18b at equal intervals in the longitudinal direction of the auxiliary gate electrode 58, each auxiliary gate electrode 58 is divided into three, for example, to form a source side auxiliary gate electrode SAG 21 , memory side auxiliary gate electrode MAG 21 , and the drain side auxiliary gate electrode DAG 21 In the present embodiment, the case where the auxiliary gate insulating layer 45 formed on the periphery of the auxiliary gate electrode 58 is not etched, but only the auxiliary gate electrode 58 is etched to form two holes ER18a and 18b on the auxiliary gate electrode 58 is described, but the present invention is not limited thereto. When the auxiliary gate electrode 58 is etched to form the holes ER18a and 18b, the auxiliary gate insulating layer 45 in the area opposite to the holes ER18a and 18b may also be etched together with the auxiliary gate electrode 58.

[0395] In addition, in this embodiment, along the column direction X, the source side auxiliary gate electrode SAG21 The memory side auxiliary gate electrode MAG is formed to face the source side selection gate structure 12. 21 The drain-side auxiliary gate electrode DAG is formed to face the memory gate structure 10. 21 The drain side selection gate structure 11 is formed to face the drain side selection gate structure 11. In addition, the source side auxiliary gate electrode SAG 21 and memory side auxiliary gate electrode MAG 21 The inside of the hole ER18a between the memory side auxiliary gate electrode MAG 21 and drain side auxiliary gate electrode DAG 21 The surfaces of the insulating layer 51 are exposed inside the holes ER18b.

[0396] Then, if Fig.42C As shown, the auxiliary gate insulating layer 45, the insulating layer 51a, the drain side auxiliary gate electrode DAG are covered. 21 , memory side auxiliary gate electrode MAG 21 and source side auxiliary gate electrode SAG 21 Insulating materials such as silicon oxide film are deposited on the substrate surface to form an insulating layer (mask layer) 62, thereby forming auxiliary gate insulating layers 49a and 49b in the holes ER18a and 18b, respectively. Thus, for example, the auxiliary gate electrode SAG on the source side is formed through the auxiliary gate insulating layer 49a. 21 and memory side auxiliary gate electrode MAG 21 The auxiliary gate electrode MAG on the memory side is electrically isolated through the auxiliary gate insulating layer 49b. 21 and drain side auxiliary gate electrode DAG 21 It becomes electrically isolated.

[0397] In addition, if Fig.42C As shown, the source side auxiliary gate electrode SAG 21 , memory side auxiliary gate electrode MAG 21 , and the drain side auxiliary gate electrode DAG 21 , are respectively extended in a columnar shape in a vertical direction Z relative to the surface of the substrate 20. 21 , memory side auxiliary gate electrode MAG 21 , drain side auxiliary gate electrode DAG 21 , composed of memory cells Ce at each level arranged along the vertical direction Z 211 , Ce 212 ,…,Ce 21k Shared.

[0398] Then, if Fig.43A As shown, for example, in the memory cells Ce arranged along the column direction X 11、Ce 21 、Ce 31 The memory cells Ce arranged along the column direction X 12 、Ce 22 、Ce 32 A new mask layer patterned in such a manner as to form a hole ER19 extending in the column direction X is formed on the mask layer 62, and after etching is performed to form the hole ER19, the new mask layer is removed. 11 、Ce 21 、Ce 31 The memory cells Ce arranged along the column direction X 12 、Ce 22 、Ce 32 A hole ER19 extending along the column direction X is formed between Fig.43A In the figure, the mask layer 62 formed on the uppermost layer is omitted, and the top view structure of the lower layer of the mask layer 62 is shown. The surface of the insulating layer 51 is exposed on the bottom surface of the hole ER19 formed in this way. Fig.43B Yes means Fig.43A The cross-sectional view of the cross-sectional structure of the OO' portion also illustrates the mask layer 62 located at the uppermost layer.

[0399] exist Fig.43A Although only the memory cells Ce arranged along the column direction X are shown in FIG. 11 、Ce 21 、Ce 31 and the memory cells Ce arranged adjacent to them on the right along the column direction X 12 、Ce 22 、Ce 32 The hole ER19 formed between the memory cells Ce and extending in the column direction X is similarly 11 、Ce 21 、Ce 31 The left side and memory cell Ce 12 、Ce 22 、Ce 32 A hole ER19 extending along the column direction X is also formed on the right side.

[0400] Here, if Fig.43B As shown, the hole ER19 passes through the insulating layer 51a, the interlayer insulating layer 52 and the silicon layer 53 between the interlayer insulating layer 52 (see Fig.42C) is formed by etching. In addition, the silicon layer 53 is removed in the hole ER19, and on the other hand, it remains as the semiconductor layer 17 in the region between the memory gate structure 10 and the drain side selection gate structure 11, and between the memory gate structure 10 and the source side selection gate structure 12. At this time, in the hole ER19, when the silicon layer 53 between the interlayer insulating layers 52 is removed, the silicon layer 53 is side-etched until it reaches the drain side selection gate insulating layer 14a of the drain side selection gate structure 11, thereby forming a hollow portion ER20. Therefore, in the hollow portion ER20, the side surface of the drain side selection gate insulating layer 14a of the drain side selection gate structure 11 or the side surface of the source side selection gate insulating layer 14b of the source side selection gate structure 12 is exposed.

[0401] Then, if Fig.44A As shown, a semiconductor material composed of n-type silicon is deposited in the hole ER19, and then, the mask layer 62 is used as a mask to perform etching from the opening 62a of the mask layer 62, so that the semiconductor material remains in the hollow portion ER20. Thus, holes ER21 each having a semiconductor layer 63 formed therein are formed in the hollow portion ER20 from the opening 62a of the mask layer 62 along the vertical direction Z.

[0402] Then, if Fig.44B As shown, the semiconductor layer 63 is side-etched from the side of each hole ER21, so that the semiconductor layer 63 formed between the interlayer insulating layer 52 is partially left, and the source diffusion layer 6 or the drain diffusion layer 7 is formed from the semiconductor layer 63 to the interlayer insulating layer 52. The source diffusion layer 6 and the drain diffusion layer 7 are electrically isolated between the layers by the interlayer insulating layer 52.

[0403] Then, after the metal material is filled in each hole ER21, Fig.45 As shown, in the region where the source diffusion layer 6 or the drain diffusion layer 7 is formed between the interlayer insulating layers 52, etching is performed so that the metal material remains, thereby forming a hole ER22. Thus, the source line SL or the bit line BL is formed by the metal material remaining between the interlayer insulating layers 52. The source line SL and the bit line BL are in a state of being electrically isolated between the layers by the interlayer insulating layer 52.

[0404] Fig.46 The mask layer 62 formed on the uppermost layer is omitted in the figure, and the schematic diagram shows the top view structure of the lower layer of the mask layer 62. Fig.46 As shown, in Fig.45 The hole ER22 between the bit lines BL adjacent to the row direction Y and the hole ER22 between the source lines SL adjacent to the row direction Y (in Fig.45Insulating material is filled in the row (not shown) to form an insulating layer 65a. Thus, the bit lines BL adjacent to each other in the row direction Y are electrically isolated from each other by the insulating layer 65a. Similarly, the source lines SL adjacent to each other in the row direction Y are also electrically isolated from each other by the insulating layer 65a.

[0405] in addition, Fig.46 The region E100 shown indicates a region where a memory cell Ce21 is formed. The memory cell Ce21 has a structure in which a source side selection gate structure 12, a memory gate structure 10, and a drain side selection gate structure 11 are arranged in sequence in the row direction Y. In addition, the structure is such that source side auxiliary gate electrodes SAG are arranged on both sides of the source side selection gate structure 12 in the column direction X, memory side auxiliary gate electrodes MAG are arranged on both sides of the memory gate structure 10 in the column direction X, and drain side auxiliary gate electrodes DAG are arranged on both sides of the drain side selection gate structure 11 in the column direction X.

[0406] A semiconductor layer 17 made of a semiconductor material is provided around the source side selection gate structure 12, the memory gate structure 10, and the drain side selection gate structure 11 so as to surround them. Furthermore, a wall-shaped auxiliary gate insulating layer 45 is provided between the source side auxiliary gate electrode SAG, the memory side auxiliary gate electrode MAG, and the drain side auxiliary gate electrode DAG and the semiconductor layer 17. Thus, the source side auxiliary gate electrode SAG, the memory side auxiliary gate electrode MAG, and the drain side auxiliary gate electrode DAG are electrically isolated from the semiconductor layer 17.

[0407] Next, through the general semiconductor manufacturing process using photolithography technology, film forming technology such as CVD, etching technology, and ion implantation, such as Fig.47 As shown in FIG. 1 , a contact 18 electrically connected to the source side selection gate electrode SG, the memory gate electrode MG, and the drain side selection gate electrode DG is formed on the surface of the insulating layer 65a formed on the surface of the mask layer 62. Next, an insulating layer 65b is formed on the surface, and a source side selection gate line SGL electrically connected to the contact 18 is formed in the insulating layer 65b. 1、2 , word line WL 1、2 and drain side selection gate line BGL 1、2 In addition, a source side auxiliary gate line SAGL is formed on the surface of the insulating layer 65a. 1、2 , memory side auxiliary gate line MAGL 1、2 , and the drain side auxiliary gate line DAGL 1、2 In addition, the source side auxiliary gate line SAGL 1、2 , memory side auxiliary gate line MAGL 1、2 and the drain side auxiliary gate line DAGL1、2 , and are connected to the corresponding source-side auxiliary gate electrode SAG, memory-side auxiliary gate electrode MAG, or drain-side auxiliary gate electrode DAG via contacts (not shown). In this way, the memory array CAd of the third embodiment can be manufactured.

[0408] In addition, about Fig.28 The memory array in which the memory cells Cd of the second embodiment are hierarchically arranged in a matrix can be manufactured in the same manner as the manufacturing method of the memory array CAd of the third embodiment described above.

[0409] That is, in the method for manufacturing the memory array of the second embodiment, Figures 37 to 47 When manufacturing by the process described in Fig.42A , 42B The auxiliary gate electrode 58 can be formed as the auxiliary gate electrode AG of the second embodiment. The other structures of the memory array of the second embodiment can be manufactured in the same manner according to the manufacturing process of the third embodiment.

[0410] (3-8) Actions and Effects In the above structure, in the third embodiment, a three-dimensional structure is also realized for the memory cell Ce having the memory transistor MT, the drain side selection transistor DT and the source side selection transistor ST connected in series. By making the memory cell Ce a three-dimensional structure, the memory cell Ce can be integrated and miniaturized without being restricted by two-dimensional scaling.

[0411] In addition, in the memory cell Ce of the third embodiment, since the source side auxiliary gate electrode SAG, the memory side auxiliary gate electrode MAG, and the drain side auxiliary gate electrode DAG are provided, the potential of the semiconductor layer 17 can be determined by adjusting not only the potential of the source diffusion layer 6, the drain diffusion layer 7, the source side selection gate electrode SG, the memory gate electrode MG, and the drain side selection gate electrode DG, but also respectively adjusting the potential of these source side auxiliary gate electrode SAG, the memory side auxiliary gate electrode MAG, and the drain side auxiliary gate electrode DAG.

[0412] That is, in the third embodiment, the potential of the semiconductor layer 17 around the source side selection gate structure 12 can be controlled by the source side auxiliary gate electrode SAG, the potential of the semiconductor layer 17 around the memory gate structure 10 can be controlled by the memory side auxiliary gate electrode MAG, and the potential of the semiconductor layer 17 around the drain side selection gate structure 11 can be controlled by the drain side auxiliary gate electrode DAG.

[0413] In the data writing operation, the source side gate voltage V can be reduced in the write selection page by increasing the potential of the semiconductor layer 17 using the source side auxiliary gate electrode SAG. SGS1 The potential difference with the semiconductor layer 17 can reliably turn off the source side selection transistors ST1 and ST3, thereby suppressing leakage current. In addition, even when writing to a non-selected page, the potential of the semiconductor layer 17 can be adjusted by using the source side auxiliary gate electrode SAG and the drain side auxiliary gate electrode DAG, thereby reliably turning off the drain side selection transistors DT2 and DT4 and the source side selection transistors ST2 and ST4, thereby suppressing leakage current.

[0414] During the data clearing operation, the voltages of the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, and the source side auxiliary gate electrode SAG are adjusted so that the memory gate voltage V CG1 The potential difference with the semiconductor layer 17 is increased, and data can be erased more efficiently. In addition, when erasing non-selected pages, the potential difference with the memory gate voltage V CG2 The potential difference can more effectively suppress data clearing.

[0415] Furthermore, during the data reading operation, the potential of the semiconductor layer 17 and the read selection drain side gate voltage V can be adjusted by adjusting the voltages of the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, and the source side auxiliary gate electrode SAG. SGD1 The potential difference between the potential of the semiconductor layer 17 and the read selection source side gate voltage V SGS1 The potential difference can suppress leakage current from the source line SL1 to the bit line BL1 near the drain-side auxiliary gate electrode DAG, the memory-side auxiliary gate electrode MAG, and the source-side auxiliary gate electrode SAG.

[0416] (4) Fourth Embodiment (4-1) Structure of Memory Cell of Fourth Embodiment Fig.48 It is a schematic diagram showing the structure of the memory cell Cf of the fourth embodiment when viewed from above. In the memory cell Cf, as in the third embodiment, a drain side auxiliary gate electrode DAG is provided on the drain side selection transistor DT, a memory side auxiliary gate electrode MAG is provided on the memory transistor MT, and a source side auxiliary gate electrode SAG is provided on the source side selection transistor ST.

[0417] The memory cell Cf is different from the third embodiment in the structures of the memory gate structure 10c, the drain side selection gate structure 11c, and the source side selection gate structure 12c. Specifically, the memory gate structure 10c is different from the third embodiment in that the multilayer insulating layer is not provided around the side of the memory gate electrode MG in the circumferential direction, but the memory side multilayer insulating layer 141 is provided in a manner of contacting only one side of the side of the columnar memory gate electrode MG with a quadrangular cross section. In addition, the drain side selection gate structure 11c has the following structure: the drain side selection gate multilayer insulating layer 142 is provided as the drain side selection gate insulating layer, and the drain side selection gate multilayer insulating layer 142 is provided in a manner of contacting only one side of the side of the columnar drain side selection gate electrode DG with a quadrangular cross section. In addition, the source side selection gate structure 12c has the following structure: a source side selection gate multilayer insulation layer 143 is provided as a source side selection gate insulation layer, and the source side selection gate multilayer insulation layer 143 is provided in a manner of contacting only one side of the side surface of the columnar source side selection gate electrode SG having a quadrangular cross section. In the fourth embodiment, these drain side selection gate multilayer insulation layer 142, the memory side multilayer insulation layer 141, and the source side selection gate multilayer insulation layer 143 are linearly connected and provided to form a multilayer insulation layer 151a extending in the row direction Y.

[0418] In the memory cell Cf, the memory gate structure 10c, the drain side selection gate structure 11c, and the source side selection gate structure 12c are provided in a region between the source diffusion layer 6 and the drain diffusion layer 7 in parallel along the column direction X in the plane direction of the surface of the substrate (not shown). Fig.48 In the figure, one direction indicates the column direction X when viewed from above, and another direction orthogonal to the one direction indicates the row direction Y. For example, in the region between the source diffusion layer 6 and the drain diffusion layer 7 which are parallel to the column direction X, a semiconductor layer 17 is provided which extends in the row direction Y in a manner of contacting the side surfaces of the source diffusion layer 6 and the drain diffusion layer 7. On the semiconductor layer 17, on one side surface extending in the row direction Y between the source diffusion layer 6 and the drain diffusion layer 7, a multilayer insulation layer 151a in which the drain side selection gate multilayer insulation layer 142, the memory side multilayer insulation layer 141, and the source side selection gate multilayer insulation layer 143 are linearly connected is provided.

[0419] The multilayer insulating layer 151a is composed of a linear first memory gate insulating layer 15a, a linear charge storage layer 15b, and a linear second memory gate insulating layer 15c, wherein the first memory gate insulating layer 15a is arranged to contact the side surface of each side of the drain side selection gate electrode DG, the memory gate electrode MG, and the source side selection gate electrode SG when viewed from above; the charge storage layer 15b is arranged along the side surface of the first memory gate insulating layer 15a; and the second memory gate insulating layer 15c is arranged along the side surface of the charge storage layer 15b. In addition, similarly to the above-mentioned embodiment, the first memory gate insulating layer 15a and the second memory gate insulating layer 15c are formed of silicon oxide (SiO2) or the like, and the charge storage layer 15b is formed of silicon nitride (Si3N4) or silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), or the like.

[0420] In addition, on the semiconductor layer 17, another linear multilayer insulating layer 151b is formed along another side surface extending in the row direction Y between the source diffusion layer 6 and the drain diffusion layer 7, and the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, and the source side auxiliary gate electrode SAG are arranged via the multilayer insulating layer 151b. The multilayer insulating layer 151b is formed between the source diffusion layer 6 and the drain diffusion layer 7 in parallel with the multilayer insulating layer 151a, and is provided on the side surface extending in the row direction Y so as to contact the side surface of each side of the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, and the source side auxiliary gate electrode SAG.

[0421] Another multilayer insulating layer 151b is composed of a linear first memory gate insulating layer 15a, a linear charge storage layer 15b, and a linear second memory gate insulating layer 15c, wherein the first memory gate insulating layer 15a is arranged to contact the side surface of each side of the columnar drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, and the source side auxiliary gate electrode SAG having a quadrilateral cross section when viewed from above; the charge storage layer 15b is arranged along the side surface of the first memory gate insulating layer 15a; and the second memory gate insulating layer 15c is arranged along the side surface of the charge storage layer 15b. In addition, similarly to the above-mentioned embodiment, the first memory gate insulating layer 15a and the second memory gate insulating layer 15c are formed of silicon oxide (SiO2) or the like, and the charge storage layer 15b is formed of silicon nitride (Si3N4) or silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), or the like.

[0422] In addition, another multilayer insulating layer 151b is used to insulate the semiconductor layer 17 and the drain-side auxiliary gate electrode DAG, the semiconductor layer 17 and the memory-side auxiliary gate electrode MAG, and the semiconductor layer 17 and the source-side auxiliary gate electrode SAG, respectively. In this embodiment, in order to simultaneously manufacture with one multilayer insulating layer 151a to simplify the manufacturing process, the multilayer insulating layer 151b with a three-layer structure similar to the multilayer insulating layer 151a for writing data is used, but the present invention is not limited to this, and a linear insulating layer composed of a single-layer structure may be formed in a process different from the multilayer insulating layer 151a, and only an insulating layer may be provided instead of the multilayer insulating layer 151b.

[0423] Insulating layers 71 are formed between the source diffusion layer 6 and the source side selection gate electrode SG, between the source side selection gate electrode SG and the memory gate electrode MG, between the memory gate electrode MG and the drain side selection gate electrode DG, and between the drain side selection gate electrode DG and the drain diffusion layer 7, respectively, and are insulated from each other by the insulating layers 71.

[0424] In addition, insulating layers 72 are also formed between the source diffusion layer 6 and the source side auxiliary gate electrode SAG, between the source side auxiliary gate electrode SAG and the memory side auxiliary gate electrode MAG, between the memory side auxiliary gate electrode MAG and the drain side auxiliary gate electrode DAG, and between the drain side auxiliary gate electrode DAG and the drain diffusion layer 7, respectively, and they are insulated from each other by the insulating layer 72.

[0425] In the semiconductor layer 17 of the present embodiment, the area of ​​the multilayer insulating layer 151a in contact with the memory gate electrode MG that is opposite to the memory side multilayer insulating layer 141 is the memory peripheral area, the area of ​​the multilayer insulating layer 151a in contact with the drain side selection gate electrode DG that is opposite to the drain side selection gate multilayer insulating layer 142 is the drain side peripheral area, and the area of ​​the multilayer insulating layer 151a in contact with the source side selection gate electrode SG that is opposite to the source side selection gate multilayer insulating layer 143 is the source side peripheral area.

[0426] In addition, the memory cell Cf is insulated from other memory cells (not shown) adjacent to the column direction X by a pair of insulating layers 70 arranged between the source diffusion layer 6 and the drain diffusion layer 7 and arranged in parallel along the row direction Y. Fig.48 The insulating layer 70 on the lower middle side is arranged such that the side surfaces of the drain side selection gate electrode DG, the memory gate electrode MG, the source side selection gate electrode SG and the insulating layer 71 are in contact with the side surfaces of the straight line extending in the row direction Y. Fig.48The other insulating layer 70 located on the upper side is set so that the linear side extending along the row direction Y is in contact with the side of each side of the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG, the source side auxiliary gate electrode SAG and the insulating layer 72.

[0427] In addition, in the above-mentioned fourth embodiment, similarly to the above-mentioned third embodiment, the case where the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG and the source side auxiliary gate electrode SAG are separately provided is described, but the present invention is not limited to this. For example, similarly to the above-mentioned second embodiment, the drain side auxiliary gate electrode DAG, the memory side auxiliary gate electrode MAG and the source side auxiliary gate electrode SAG may be linearly connected and provided as one auxiliary gate electrode.

[0428] (4-2) Structure of Memory Array According to Fourth Embodiment Next, a cross-sectional structure of a memory array in which the memory cells Cf are arranged in a matrix when viewed from above will be described. Fig.49 FIG. 4 is a cross-sectional view showing the cross-sectional structure of the memory array CAf according to the fourth embodiment when viewed from above. Fig.49 In FIG. 1 , one direction in a plan view represents the column direction X, and another direction orthogonal to the one direction represents the row direction Y. For example, in the first layer, the memory cells Cf are arranged in a region of 2 rows and 2 columns. Fig.49 In the figure, each memory cell Cf arranged in the first row and the first column and the second row and the first column on the left side of the figure is represented as memory cell Cf. 11 , Cf 21 , the memory cells Cf arranged in the first row and second column and the second row and second column on the right side of the drawing are respectively represented as memory cells Cf 12 , Cf 22 In addition, there is no need to distinguish these memory cells Cf 11 , Cf 21 , Cf 12 , Cf 22 In this case, it is referred to as memory cell Cf.

[0429] In addition to the memory cells Cf configured in the first column 11 , Cf 21 The structure and configuration of the second column memory cell Cf 12 , Cf 22 The structure is formed to be bilaterally symmetrical, and the other structures are the same. In the region between the source diffusion layer 6 and the drain diffusion layer 7 parallel to the column direction X, the memory cells Cf are arranged in the column direction X. 11 , Cf 21 , each memory cell Cf 11, Cf 21 The side surfaces of the semiconductor layer 17 are in contact with the side surfaces of the source diffusion layer 6 and the drain diffusion layer 7, respectively. 11 , Cf 21 The memory cells Cf each have a common source line SL1, a bit line BL1, a source diffusion layer 6, and a drain diffusion layer 7. 11 , Cf 21 An insulating layer 70 is provided between the memory cells Cf and the memory cells Cf. 11 , Cf 21 insulation.

[0430] The drain side selection gate line BGL1 extending in the row direction Y is connected to the memory cells Cf arranged in the first and second columns on the same row. 11 , Cf 12 The drain side selection gate electrodes DG of the memory cells are connected to the source side selection gate lines SGL1 extending in the row direction Y and connected to the memory cells Cf arranged in the first and second columns on the same row. 11 , Cf 12 The word line WL1 extending in the row direction Y is connected to the first and second memory cells Cf arranged in the same row. 11 , Cf 12 In addition, the drain side selection gate line BGL 0、2 , source side selection gate line SGL 0、2 and word line WL 0、2 It also has the same structure as the drain side selection gate line BGL1, the source side selection gate line SGL1, and the word line WL1.

[0431] In addition, the drain-side auxiliary gate line DAGL1 extending in the column direction X is connected to the memory cells Cf arranged in the first and second rows of the same column. 11 , Cf 21 The drain-side auxiliary gate electrodes DAG are connected to the source-side auxiliary gate lines SAGL1 extending in the column direction X and connected to the memory cells Cf arranged in the first and second rows of the same column. 11 , Cf 21 The memory side auxiliary gate line MAGL1 extending in the column direction X is connected to the memory cells Cf arranged in the first and second rows of the same column. 11 , Cf 21In addition, the drain side auxiliary gate line DAGL2, the source side auxiliary gate line SAGL2 and the memory side auxiliary gate line MAGL2 also have the same structure as the drain side auxiliary gate line DAGL1, the source side auxiliary gate line SAGL1 and the memory side auxiliary gate line MAGL1.

[0432] In addition, the memory cell Cf of the first column 11 , Cf 21 The bit line BL1 connected to the memory cell Cf of the second column 12 , Cf 22 The connected source lines SL2 are arranged in parallel so as to be adjacent to each other with the insulating layer 75 interposed therebetween, and are insulated by the insulating layer 75 .

[0433] Fig.50 Yes means Fig.49 The cross-sectional view of the cross-sectional structure of the RR' portion. Fig.50 It is also shown that the Fig.49 The cross-sectional structure of the memory array CAf shown in the top view includes an upper insulating layer 81 and a drain side selection gate line BGL arranged on the insulating layer 81. 1、2 And the configuration structure of the drain side auxiliary gate line DAGL1. In the memory array CAf, as Fig.50 As shown, the columnar drain side selection gate electrode DG and the drain side auxiliary gate electrode DAG are vertically arranged on the substrate 20 through the insulating layer 24. In addition, the memory gate electrode MG, the source side selection gate electrode SG, the memory side auxiliary gate electrode MAG and the source side auxiliary gate electrode SAG are also vertically arranged on the substrate 20 through the insulating layer 24.

[0434] Between the drain side selection gate electrode DG and the drain side auxiliary gate electrode DAG, layers formed with semiconductor layers 17 and multi-layer insulating layers 151a and 151b and interlayer insulating layers 79 are alternately arranged along the vertical direction Z. Thus, the upper layer formed with semiconductor layers 17 and multi-layer insulating layers 151a and 151b and the lower layer formed with semiconductor layers 17 and multi-layer insulating layers 151a and 151b are insulated by the interlayer insulating layer 79.

[0435] In the memory array CAf, a memory cell Cf is formed at each position (layer) of the semiconductor layer 17 formed along the vertical direction Z. Among the multiple memory cells Cf arranged along the vertical direction Z, there are: a drain side selection gate electrode DG, a memory gate electrode MG, a source side selection gate electrode SG, a drain side auxiliary gate electrode DAG, a memory side auxiliary gate electrode MAG and a source side auxiliary gate electrode SAG.

[0436] In addition, since the data writing operation, data erasing operation, and data reading operation in the memory cell Cf of the fourth embodiment are the same as those of the third embodiment, the description thereof will be omitted here.

[0437] (4-3) Method of Manufacturing Memory Array According to Fourth Embodiment Next, use Figure 51 to Figure 5 7 describes a method for manufacturing the memory array CAf. Fig.51 As shown, for example, an insulating layer 24 is stacked on a substrate 20 made of silicon, and interlayer insulating layers 79 of a type different from the insulating layer 24 and silicon layers 80 made of, for example, polysilicon are alternately stacked on the insulating layer 24. In addition, on the interlayer insulating layer 79 located at the uppermost layer among the interlayer insulating layers 79, the insulating layer 24 and another insulating layer 81 of a type different from the interlayer insulating layer 79 are stacked, and a mask layer 82 for masking made of, for example, Al2O3, carbon, SiC, etc. is further formed thereon. Here, the insulating layer 24 and the insulating layer 81 are made of a material different from the silicon layer 80, and are layers that are difficult to be etched when the interlayer insulating layer 79 and the silicon layer 80 are etched.

[0438] Then, if Fig.52A and Fig.52A The cross-sectional structure of the SS′ part Fig.52B As shown, a predetermined mask layer (not shown) is used, for example, the mask layer 82 is selectively etched by a dry etching method to form mask layers 82a and 82b of a predetermined pattern, and the underlying interlayer insulating layer 79 and silicon layer 80 are etched using the mask layers 82a and 82b as masks.

[0439] Here, Fig.52A 1 is a schematic diagram showing a structure when viewed from above after etching the lower interlayer insulating layer 79 and the silicon layer 80 using mask layers 82a and 82b of a predetermined pattern. The mask layer 82a is formed at a predetermined formation region where the multilayer insulating layers 151a and 151b and the semiconductor layer 17 are formed. The mask layer 82b is formed at a predetermined formation region where the source line SL and the source diffusion layer 6 are formed, and at a predetermined formation region where the bit line BL and the drain diffusion layer 7 are formed.

[0440] Thus, the interlayer insulating layer 79 and the silicon layer 80 are etched until the surface of the insulating layer 24 is exposed between the mask layers 82b adjacent to each other in the row direction Y, thereby forming a hole ER32. In addition, the interlayer insulating layer 79 and the silicon layer 80 are etched until the surface of the insulating layer 24 is exposed between the mask layers 82a adjacent to each other in the column direction X, thereby forming a hole ER31.

[0441] Next, an insulating material is deposited in the spaces of the holes ER31 and ER32 where the insulating layer 24 is exposed, and after the insulating layer is formed, the surface is polished to form a mask layer (not shown) with a predetermined pattern on the mask layers 82a and 82b on the surface. Fig.53A and Fig.53B As shown, until the surface of the lower insulating layer 24 is exposed, the insulating layer 84 at the predetermined forming positions is etched to form holes ER32a and ER32b, wherein the predetermined forming positions are formed with: a drain side selection gate electrode DG, a memory gate electrode MG, a source side selection gate electrode SG, a drain side auxiliary gate e...

Claims

1. A non-volatile memory cell, wherein: include: A drain diffusion layer is extended along the surface direction of the substrate and is electrically connected to the bit line; A source diffusion layer extending in parallel with the drain diffusion layer along the surface direction and electrically connected to an active line; One or more columnar memory gate electrodes, the memory gate electrodes are vertically arranged on the substrate through an insulating layer, and are arranged in a region between the parallel drain diffusion layer and the source diffusion layer; a columnar drain-side selection gate electrode, which is vertically arranged on the substrate via an insulating layer and is arranged in a region between the drain diffusion layer and the memory gate electrode; a columnar source-side selection gate electrode, which is vertically disposed on the substrate via an insulating layer and is disposed in a region between the source diffusion layer and the memory gate electrode; A multi-layer insulating layer is arranged in contact with the memory gate electrode; A drain-side selection gate insulating layer, arranged in contact with the drain-side selection gate electrode; A source side selection gate insulating layer, arranged in contact with the source side selection gate electrode; as well as a semiconductor layer disposed in a region between the parallel drain diffusion layer and the source diffusion layer, and respectively contacting the drain side selection gate insulation layer, the source side selection gate insulation layer, the multi-layer insulation layer, the drain diffusion layer and the source diffusion layer, The multilayer insulating layer has a first memory gate insulating layer in contact with the memory gate electrode, a charge storage layer in contact with the first memory gate insulating layer, and a second memory gate insulating layer in contact with the charge storage layer and the semiconductor layer.

2. The nonvolatile memory cell according to claim 1, wherein: The multi-layer insulating layer is arranged on the side of the memory gate electrode, The drain side selection gate insulating layer is arranged on the side of the drain side selection gate electrode, The source side selection gate insulating layer is arranged on the side of the source side selection gate electrode, The semiconductor layer is in contact with the side surfaces of the drain side selection gate insulating layer, the source side selection gate insulating layer, the multi-layer insulating layer, the drain diffusion layer, and the source diffusion layer, respectively. In the multilayer insulating layer, the first memory gate insulating layer contacts the side of the memory gate electrode, the charge storage layer contacts the side of the first memory gate insulating layer, and the second memory gate insulating layer contacts the side of the charge storage layer and the side of the semiconductor layer.

3. The non-volatile memory cell according to claim 2, wherein: The drain side selection gate insulating layer is arranged around the side surface of the drain side selection gate electrode along the circumferential direction. The source side selection gate insulating layer is arranged on the side surface of the source side selection gate electrode along the circumferential direction. The multi-layer insulating layer is disposed around the side surface of the memory gate electrode along a circumferential direction.

4. The nonvolatile memory cell according to claim 3, wherein: The semiconductor layer has a drain side peripheral region surrounding the side of the drain side selection gate insulation layer, a source side peripheral region surrounding the side of the source side selection gate insulation layer, and a memory peripheral region surrounding the side of the multilayer insulation layer, wherein the drain side peripheral region, the source side peripheral region and the memory peripheral region are connected.

5. The non-volatile memory cell according to claim 4, wherein: In the top view, the distance from the drain side selection gate insulation layer to the outer surface of the drain side peripheral area, the distance from the source side selection gate insulation layer to the outer surface of the source side peripheral area, and the distance from the multilayer insulation layer to the outer surface of the memory peripheral area are respectively less than 40nm.

6. The non-volatile memory cell according to claim 5, wherein: The semiconductor layer comprises: a memory-drain region connection setting portion, connecting and setting the adjacent memory peripheral region and the drain side peripheral region; and The memory-source region connection setting portion connects and sets the adjacent memory peripheral region and the source side peripheral region.

7. The nonvolatile memory cell according to claim 4, wherein: In the semiconductor layer, In a plan view, a distance from the drain-side selection gate insulating layer to the multi-layer insulating layer adjacent to the drain-side selection gate insulating layer is greater than or equal to 25 nm and less than or equal to 100 nm, In a plan view, a distance from the source-side selection gate insulating layer to the multi-layer insulating layer adjacent to the source-side selection gate insulating layer is greater than or equal to 25 nm and less than or equal to 100 nm.

8. The nonvolatile memory cell according to claim 1, wherein: Among the drain side selection gate electrode, the source side selection gate electrode and the memory gate electrode, The expanded diameter portion and the reduced diameter portion having a smaller diameter than the expanded diameter portion are alternately formed along the axial direction. On the side of the expanded diameter portion, the semiconductor layer is arranged respectively via the drain side selection gate insulation layer, the source side selection gate insulation layer or the multi-layer insulation layer, and on the side of the reduced diameter portion, an interlayer insulation layer is arranged respectively via the drain side selection gate insulation layer, the source side selection gate insulation layer or the multi-layer insulation layer.

9. The nonvolatile memory cell according to claim 1, wherein: include: A columnar auxiliary gate electrode, which is vertically arranged on the substrate through the insulating layer; as well as an auxiliary gate insulating layer which is provided on a side of the auxiliary gate electrode and electrically isolates the auxiliary gate electrode from the semiconductor layer, the drain diffusion layer and the source diffusion layer, The auxiliary gate electrode is arranged on each side of the drain side selection gate electrode, the source side selection gate electrode and the memory gate electrode, respectively separated by the drain side selection gate insulation layer, the source side selection gate insulation layer or the multi-layer insulation layer, the semiconductor layer and the auxiliary gate insulation layer.

10. The non-volatile memory cell according to claim 9, wherein: The auxiliary gate electrode is: a drain-side auxiliary gate electrode arranged opposite to the drain-side selection gate electrode, a source-side auxiliary gate electrode arranged opposite to the source-side selection gate electrode, and a memory-side auxiliary gate electrode arranged opposite to the memory gate electrode. The drain-side auxiliary gate electrode, the source-side auxiliary gate electrode, and the memory-side auxiliary gate electrode are formed separately.

11. The non-volatile memory cell according to claim 1, wherein: A plurality of columnar memory gate electrodes are provided between the drain-side selection gate electrode and the source-side selection gate electrode.

12. A nonvolatile semiconductor memory device, wherein a plurality of nonvolatile memory cells arranged in a matrix in a plane direction on a surface of a substrate are arranged hierarchically in a vertical direction orthogonal to the plane direction, wherein: The nonvolatile memory cell is the nonvolatile memory cell according to any one of claims 1 to 11.

13. The nonvolatile semiconductor memory device according to claim 12, wherein: Has the following structure: Semiconductor layers and interlayer insulating layers are alternately stacked on the substrate along the vertical direction. A plurality of holes are formed in the vertical direction through the stacked semiconductor layer and the interlayer insulating layer, The hole is provided with: a columnar drain side selection gate electrode erected on the substrate via an insulating layer and a drain side selection gate insulating layer provided on the side of the drain side selection gate electrode; In the other hole, there are provided: a columnar source side selection gate electrode erected on the substrate via an insulating layer, and a source side selection gate insulating layer provided on a side surface of the source side selection gate electrode, and A columnar memory gate electrode and a multi-layer insulating layer are provided in the other hole different from the hole and the other hole, wherein the columnar memory gate electrode is vertically provided on the substrate through the insulating layer, and the multi-layer insulating layer is provided on the side of the memory gate electrode, Among them, in the multiple non-volatile memory cells of different levels arranged in the vertical direction, there are respectively: the drain side selection gate electrode and the drain side selection gate insulation layer, the source side selection gate electrode and the source side selection gate insulation layer, and the memory gate electrode and the multi-layer insulation layer.

14. The nonvolatile semiconductor memory device according to claim 12, comprising: A plurality of drain side selection gate lines are respectively arranged on each row and connected to the drain side selection gate electrodes arranged in the same row including different levels; A plurality of source side selection gate lines are respectively arranged on each row and connected to the source side selection gate electrodes arranged in the same row including different levels; and A plurality of word lines are respectively arranged on each row and connected to the memory gate electrodes arranged in the same row including different levels.

15. The nonvolatile semiconductor memory device according to claim 14, wherein: In the nonvolatile memory unit, A plurality of memory gate electrodes are vertically arranged between a pair of the drain side selection gate electrodes and the source side selection gate electrodes, The word line is provided on each of the memory gate electrodes which are respectively provided on each row of the nonvolatile memory cells and are arranged in the same row.

16. The nonvolatile semiconductor memory device according to claim 12, wherein: include: A plurality of drain diffusion layers are respectively arranged to extend along the column direction in each layer and connected to the semiconductor layers of the nonvolatile memory cells in the same column; A plurality of source diffusion layers, each of which is arranged in parallel with the drain diffusion layer and extends along the column direction, and is connected to the semiconductor layer of the nonvolatile memory cell in the same column; A plurality of bit lines are respectively arranged to extend along the column direction at each level and connected to the drain diffusion layer of the same column; as well as A plurality of source lines are respectively arranged in parallel with the bit lines in each level and extend along the column direction and are connected to the source diffusion layers in the same column; Wherein, on the substrate, the following are alternately stacked along the vertical direction: a layer provided with the semiconductor layer, the drain diffusion layer, the source diffusion layer, the bit line, and the source line; and an interlayer insulating layer.

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