Semiconductor device and semiconductor module

Abstract

The present invention provides a semiconductor device and a semiconductor module, the semiconductor device comprising: a semiconductor substrate having an active portion provided with a transistor portion; the emission electrode is arranged above the front surface of the semiconductor substrate; and a protective film provided above the emitter electrode, the active portion having an emitter region of a first conductivity type provided on the front surface of the semiconductor substrate, a contact region of a second conductivity type, and a plurality of trench portions, and the emitter electrode having an exposed portion not covered by the protective film. The active portion has a first region and a second region in a region where the exposed portion is provided, the second region being provided on an outer periphery of the first region and having a channel density lower than that of the first region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a semiconductor module. Background Art

[0002] Patent Document 1 describes the use of soldering to electrically connect element electrodes and lead terminals using a connecting conductor.

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2009-38140 Summary of the invention

[0004] Technical issues It is desired to suppress local concentration of current when the transistor portion is operating.

[0005] Technical Solution In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device comprises: a semiconductor substrate having an active portion provided with a transistor portion; an emitter electrode provided above the front surface of the semiconductor substrate; and a protective film provided above the emitter electrode, the active portion having an emitter region of a first conductivity type provided on the front surface of the semiconductor substrate, a contact region of a second conductivity type, and a plurality of groove portions, the emitter electrode having an exposed portion not covered by the protective film, the active portion having a first region and a second region in a region provided with the exposed portion, the second region being provided at the periphery of the first region and having a channel density lower than that of the first region.

[0006] The second region may be provided so as to surround the entire periphery of the first region when the semiconductor substrate is viewed in plan.

[0007] In a plan view of the semiconductor substrate, an area of ​​the first region may be greater than or equal to 0.5 times and less than or equal to 10 times an area of ​​the second region.

[0008] In a plan view of the semiconductor substrate, the first region may be separated from an end portion of the exposed portion by at least 0 μm or more and 1500 μm or less.

[0009] A channel density of a mesa portion of the transistor portion in the second region may be smaller than a channel density of a mesa portion of the transistor portion in the first region.

[0010] In the mesa portion of the transistor portion, the emitter region and the contact region are alternately arranged in the trench extension direction, and when looking down at the semiconductor substrate, the ratio of the emitter region to the contact region in the mesa portion of the transistor portion in the first region can be larger than the ratio of the emitter region to the contact region in the mesa portion of the transistor portion in the second region.

[0011] When the semiconductor substrate is viewed from above, a trench extension length of the contact region provided at the mesa portion of the transistor portion in the second region may be greater than a trench extension length of the contact region provided at the mesa portion of the transistor portion in the first region.

[0012] When looking down on the semiconductor substrate, the emitter region of the transistor portion in the second region can be arranged correspondingly to the emitter region of the transistor portion in the first region in the groove arrangement direction. When looking down on the semiconductor substrate, the emitter region of the transistor portion in the first region can be arranged correspondingly to any one of the emitter region and the contact region of the transistor portion in the second region in the groove arrangement direction.

[0013] A channel density of the mesa portion of the transistor portion in the second region may be 50% or less of a channel density of the mesa portion of the transistor portion in the first region.

[0014] The active portion has a diode portion alternately arranged with the transistor portion in the groove arrangement direction, and when looking down at the semiconductor substrate, the ratio of the diode portion to the transistor portion in the second region can be larger than the ratio of the diode portion to the transistor portion in the first region.

[0015] In a plan view of the semiconductor substrate, in the second region, an area of ​​the transistor portion may be larger than an area of ​​the diode portion.

[0016] According to a second aspect of the present invention, there is provided a semiconductor module including any one of the semiconductor devices according to the first aspect.

[0017] The semiconductor module may include: a solder portion provided above the emitter electrode; and a lead frame provided on the solder portion and electrically connected to the emitter electrode.

[0018] When the semiconductor substrate is viewed in plan, the boundary between the first region and the second region may be provided at a position further inside than an end portion of the lead frame.

[0019] A distance between a boundary between the first region and the second region and an end portion of the lead frame may be 400 μm or more and 800 μm or less.

[0020] The outer peripheral end of the second region may be provided at a position further outward than an end portion of the solder portion.

[0021] A distance between an outer peripheral end of the second region and an end of the solder portion may be greater than or equal to 0 μm and less than or equal to 1500 μm.

[0022] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 FIG. 1 is a plan view showing an example of the semiconductor device 100 according to the embodiment.

[0024] Figure 2 This is an example of an enlarged view of the active portion 120 .

[0025] Figure 3 It is shown Figure 2 FIG. 1 is a diagram of an example of the aa section in FIG.

[0026] Figure 4 1 is a diagram showing an example of the configuration of the first region 121 and the second region 122 .

[0027] Figure 5 1 is a plan view showing an example of the mesa portion 60 .

[0028] Figure 6 is another example of an enlarged view of the active portion 120 .

[0029] Figure 7 It is shown Figure 6 FIG. 1 is a diagram of an example of a bb section in FIG.

[0030] Figure 8 2 is a diagram showing an example of the arrangement of the transistor section 70 and the diode section 80 .

[0031] Fig. 9 FIG. 1 is a plan view showing an example of a semiconductor module 300 according to the embodiment.

[0032] Fig.10 It is a side view of the semiconductor substrate 10 in a state of being mounted on the mounting substrate 200 .

[0033] Explanation of symbols 10···semiconductor substrate, 11···well region, 12···emitter region, 14···base region, 15···contact region, 16···accumulation region, 18···drift region, 20···buffer region, 21···front surface, 22···collector region, 23···back surface, 24···collector electrode, 25···connecting portion, 29···extension portion, 30···dummy trench portion, 31···front end portion, 32···dummy insulating film, 34···dummy conductive portion, 38···interlayer insulating film, 39···extension portion, 40···gate trench portion, 41···front end portion, 42···gate insulating film, 44···gate conductive portion, 48···gate runner, 50···pad, 5 2···Emitter electrode, 53···Exposure portion, 54···Contact hole, 56···Contact hole, 60···Mesa portion, 70···Transistor portion, 80···Diode portion, 82···Cathode region, 86···Main terminal, 88···Casing, 99···Control terminal, 100···Semiconductor device, 102···End side, 120···Active portion, 121···First region, 122···Second region, 150···Protective film, 160···Connection portion, 162···Solder portion, 163···Lead frame, 172···Current detection pad, 174···Anode pad, 176···Cathode pad, 200···Mounting substrate, 300···Semiconductor module DETAILED DESCRIPTION

[0034] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily all essential to the technical means of the invention.

[0035] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0036] In this specification, sometimes the orthogonal coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The orthogonal coordinate axes are only used to determine the relative positions of the components and are not limited to specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite directions to each other. When the Z-axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z-axis and the -Z-axis. In addition, in this specification, sometimes viewing from the +Z-axis direction is referred to as looking down.

[0037] In the present specification, when described as “same” or “equal”, this may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0038] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. However, the conductivity type of each doped region may be of opposite polarity. In addition, in this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of the P type or N type, and when it is described as P-type or N-type, it means that the doping concentration is lower than the doping concentration of the P type or N type.

[0039] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between donors and acceptors is sometimes set to the concentration of the donor or acceptor, whichever is greater. This concentration difference can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by diffusion resistance measurement (SR) can be used as the concentration of the donor or acceptor. In addition, in the case where the concentration distribution of the donor or acceptor has a peak, the peak value can be used as the concentration of the donor or acceptor in the region. In the case where the concentration of the donor or acceptor in the region where the donor or acceptor is present is almost uniform, the average value of the donor or acceptor concentration in the region can be used as the donor or acceptor concentration.

[0040] Figure 1 1 is a top view showing an example of a semiconductor device 100 of an embodiment. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has an edge 102 when viewed from above. The semiconductor substrate 10 of this example has two sets of edge 102 that are opposite to each other when viewed from above. Figure 1 In FIG. 1 , a set of first end edges 102-1 and second end edges 102-2 opposite to each other are shown. Figure 1 In the figure, a direction parallel to the first end side 102-1 and the second end side 102-2 is set as a Y-axis direction, and a direction perpendicular to the first end side 102-1 and the second end side 102-2 is set as an X-axis direction.

[0041] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where the main current flows between the front surface and the back surface of the semiconductor substrate 10 in the depth direction when the semiconductor device 100 is controlled to be in the on state. In this example, the region corresponding to the emitter electrode 52 is set as the active portion 120. The active portion 120 may be provided with a transistor portion including a transistor element such as an IGBT (insulated gate bipolar transistor). The active portion 120 may be provided with a diode portion including a diode element such as a FWD (freewheeling diode).

[0042] The semiconductor device 100 includes an emitter electrode 52 and a pad 50 provided above the front surface of the semiconductor substrate 10. The emitter electrode 52 and the pad 50 are electrodes made of a metal such as aluminum. An insulating film is provided between the emitter electrode 52 and the pad 50 and the semiconductor substrate 10. The emitter electrode 52 and the pad 50 are connected to the semiconductor substrate 10 via a contact hole provided in the insulating film. Figure 1 In the embodiment, the insulating film and the contact holes are omitted.

[0043] The emitter electrode 52 is arranged above the active portion 120. The emitter electrode 52 is connected to the active portion 120 via the contact hole. The emitter electrode 52 has an exposed portion 53 that is not covered by a protective film described later. The exposed portion 53 is a region including the center Ac of the active portion 120. The center Ac of the active portion 120 refers to the geometric center of gravity of the active portion 120 when viewed from above. A lead frame described later is arranged on the upper surface of the exposed portion 53. The emitter electrode 52 is electrically connected to the lead frame, and a predetermined emitter voltage is applied thereto.

[0044] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium and / or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. The emitter electrode 52 may also have a plug formed of tungsten, etc., filled in the contact hole in a manner contacting the barrier metal and aluminum, etc. A plating layer may be provided on the upper surface of the emitter electrode 52. The plating layer may be a metal material different from the emitter electrode 52, such as nickel or gold.

[0045] The pad 50 is, for example, a gate pad. The emitter electrode 52 and the pad 50 are arranged so as to be separated from each other in a plan view. A wire or the like is connected to the upper surface of the pad 50, and a predetermined gate voltage is applied thereto. The gate voltage applied to the pad 50 is supplied to the transistor portion of the active portion 120 through a gate flow channel or the like described later. The pad 50 of this example is arranged near the end side 102-1.

[0046] In addition to the structure of the semiconductor device 100, it also has an anode pad 174, a cathode pad 176, and a current detection pad 172. The semiconductor device 100 may also have a current sensor, which has the same structure as the transistor portion of the semiconductor substrate, simulates the operation of the transistor portion, and detects the current flowing between the front and back surfaces of the semiconductor substrate. The anode pad 174, the cathode pad 176, and the current detection pad 172 of this example are arranged near the edge 102-2, and the area where these pads are arranged is sometimes referred to as a pad area.

[0047] The semiconductor device 100 includes a protective film 150 disposed above the front surface of the semiconductor substrate 10. The protective film 150 is formed of polyimide or the like, covers the front surface side of the semiconductor substrate 10, and protects the front device structure. Figure 1 In the figure, the area where the protective film 150 is provided is indicated by oblique hatching. The protective film 150 has an opening corresponding to the exposed portion 53 on the emitter electrode 52. The protective film 150 may also have openings at positions and pad regions corresponding to the pad 50, the anode pad 174, the cathode pad 176, and the current detection pad 172.

[0048] exist Figure 1 In the embodiment, additional active portions may be provided above and below the pad 50 and the pad region (in the +Y axis direction and the -Y axis direction). In this case, the emitting electrode 52 may be provided so as to extend upward from the additional active portion.

[0049] Figure 2 This is an example of an enlarged view of the active portion 120. The active portion 120 of this example includes a transistor portion 70. Figure 2 The region centered on the end portion of the active portion 120 on the −Y axis direction side is shown.

[0050] The semiconductor device 100 may include a gate channel 48 arranged to surround the active portion 120 in a plan view. The gate channel 48 is a wiring formed of a conductive material such as polysilicon or metal to which impurities are added. The gate channel 48 supplies a gate voltage applied to the gate pad 50 to the transistor portion 70. The gate channel 48 may be arranged above the well region 11 described later.

[0051] The semiconductor device 100 of this example includes a gate trench portion 40 , a dummy trench portion 30 , a well region 11 , an emitter region 12 , a base region 14 , and a contact region 15 , which are provided inside the front surface side of a semiconductor substrate 10 .

[0052] exist Figure 2 , the range where the emitter electrode 52 is provided is shown. The emitter electrode 52 of this example is provided in a range that does not overlap with the gate flow channel 48, but it may overlap with the gate flow channel 48. In this case, an insulating film is provided between the emitter electrode 52 and the gate flow channel 48. An interlayer insulating film is provided between the emitter electrode 52 and the front surface of the semiconductor substrate 10, but Figure 2 In the interlayer insulating film of this example, the contact hole 56 and the contact hole 54 are provided so as to penetrate the interlayer insulating film.

[0053] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the front surface of the semiconductor substrate 10 through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. Between the emitter electrode 52 and the dummy conductive portion, a connection portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided. The connection portion 25 is provided above the front surface of the semiconductor substrate 10. An insulating film is provided between the connection portion 25 and the front surface of the semiconductor substrate 10.

[0054] An insulating film is provided between the gate flow channel 48 and the front surface of the semiconductor substrate 10. The gate flow channel 48 is connected to the gate conductive portion in the gate groove portion 40 on the front surface of the semiconductor substrate 10. The gate flow channel 48 is not connected to the dummy conductive portion in the dummy groove portion 30. The gate flow channel 48 of this example is provided so as to overlap with the front end portion 41 of the gate groove portion 40. The front end portion 41 is the end closest to the gate flow channel 48 in the gate groove portion 40. At the front end portion 41 of the gate groove portion 40, the gate conductive portion is exposed on the front surface of the semiconductor substrate 10 and is in contact with the gate flow channel 48.

[0055] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction in the transistor portion 70. The arrangement direction (also referred to as the trench arrangement direction) in this example is the X-axis direction. In this example, one or more gate trench portions 40 and one or more dummy trench portions 30 may be alternately arranged along the arrangement direction.

[0056] The gate groove portion 40 of this example may have two extension portions 39 (portions of the groove in a straight line along the extension direction) extending along an extension direction perpendicular to the arrangement direction (also referred to as a groove extension direction) and a front end portion 41 connecting the two extension portions 39. The extension direction in this example is the Y-axis direction. Preferably, at least a portion of the front end portion 41 is set to be curved. In the two extension portions 39 of the gate groove portion 40, since the front end portion 41 connects the ends of the straight line shape along the extension direction, i.e., the ends, to each other, the electric field concentration at the ends of the extension portion 39 can be alleviated.

[0057] The dummy trench portions 30 of this example are provided between the respective extending portions 39 of the gate trench portions 40. These dummy trench portions 30 may have a linear shape extending along the extending direction.

[0058] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is disposed within a predetermined range separated from the contact hole 54. The diffusion depth of the well region 11 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction are disposed in the well region 11.

[0059] The base region 14 is provided in the mesa portion 60 sandwiched by the adjacent groove portions. The mesa portion is a region of the semiconductor substrate 10 sandwiched by the groove portions that is closer to the front side than the deepest bottom of the groove portion. The base region 14 is of the second conductivity type with a doping concentration lower than that of the well region 11. In this example, the base region 14 is of the P- type, and the well region 11 is of the P+ type.

[0060] A second conductive type contact region 15 having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 in this example is of P+ type. The well region 11 can be formed from the contact region 15 disposed closest to the end portion in the trench extension direction (at Figure 2 The contact region 15 (in the -Y axis direction) is separated from the gate flow channel 48. In addition, in the transistor portion 70, an emitter region 12 of the first conductivity type having a doping concentration higher than that of the drift region 18 described later is selectively provided on the upper surface of the base region 14. The emitter region 12 in this example is of N+ type.

[0061] The contact region 15 and the emitter region 12 are provided from one adjacent trench portion to the other trench portion. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are provided to be exposed alternately on the upper surface of the mesa portion 60 along the extending direction of the trench portion.

[0062] In another example, in the mesa portion 60 in the transistor portion 70, the contact region 15 and the emitter region 12 may be arranged in stripes along the extension direction. For example, the emitter region 12 is arranged in a region adjacent to the groove portion, and the contact region 15 is arranged in a region sandwiched by the emitter region 12.

[0063] In the transistor portion 70, the contact hole 54 is provided above each region of the contact region 15 and the emitter region 12. The contact hole 54 is not provided in a region corresponding to the base region 14 and the well region 11.

[0064] Figure 3 It is shown Figure 2 1 is a diagram showing an example of the aa cross section in FIG. The aa cross section is an XZ plane passing through the emitter region 12. In this cross section, the semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surfaces of the semiconductor substrate 10 and the interlayer insulating film 38.

[0065] The collector electrode 24 is provided on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is provided with a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction. The depth direction in this example is the Z-axis direction.

[0066] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. A P-type base region 14 is provided on the front side 21 of the semiconductor substrate 10 in this cross section.

[0067] In this cross section, on the front surface 21 side of the semiconductor substrate 10 in the transistor portion 70 , an N+ type emitter region 12 , a P− type base region 14 , and an N+ type accumulation region 16 are provided in order from the front surface 21 side of the semiconductor substrate 10 .

[0068] In transistor section 70, N-type drift region 18 is provided below accumulation region 16. Providing accumulation region 16 with a higher concentration than drift region 18 between drift region 18 and base region 14 can enhance carrier injection enhancement effect (IE effect) and reduce on-voltage.

[0069] The accumulation region 16 of this example is provided in each mesa portion 60 of the transistor portion 70. The accumulation region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. An N+ type buffer region 20 is provided under the drift region 18. In addition, a plurality of accumulation regions 16 may be provided in the depth direction.

[0070] The buffer region 20 is disposed on the lower side of the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82. A P+ type collector region 22 is disposed below the buffer region 20.

[0071] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21 side of the semiconductor substrate 10. Each trench portion is provided so as to penetrate the base region 14 from the front surface 21 of the semiconductor substrate 10 and reach the drift region 18. In a region where at least any one of the emitter region 12, the contact region 15, and the storage region 16 is provided, each trench portion also penetrates these regions and reaches the drift region 18.

[0072] The method of forming a groove portion through a doped region is not limited to the method of forming the groove portion after forming the doped region. The method of forming a groove portion through a doped region includes the method of forming a groove portion through a doped region after forming the groove portion.

[0073] The gate trench portion 40 includes a gate insulating film 42 and a gate conductive portion 44 provided on the front surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided in a manner covering the inner wall of the gate trench portion 40. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is provided inside the gate trench portion 40 at a position further inside than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0074] The gate conductive portion 44 includes a region opposed to the base region 14 via a gate insulating film 42. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 at the front surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel consisting of an inversion layer of electrons is formed in the surface layer of the interface in contact with the gate groove in the base region 14.

[0075] In this cross section, the dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove provided on the front surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0076] Figure 4 1 is a diagram showing an example of the structure of the first region 121 and the second region 122. The protective film 150 has an opening corresponding to the exposed portion 53 on the emitter electrode 52. Figure 4 In the figure, the region where the protective film 150 is provided is indicated by oblique hatching. A lead frame is arranged on the upper surface of the exposed portion 53, and the emitter electrode 52 is electrically connected to the lead frame. The size of the exposed portion 53 is determined by the size of the arranged lead frame.

[0077] The first region 121 of this example is a region including the center Ac of the active portion 120 in the region corresponding to the exposed portion 53 of the exposed portion 53. The center Ac of the active portion 120 is the geometric center of gravity of the active portion 120 in a plan view. The lead frame is arranged so as to cover the first region 121. In a plan view, the distance W between the first region 121 and the end of the exposed portion 53 is at least 0 μm or more and 1500 μm or less.

[0078] The second region 122 is a region provided on the periphery of the first region 121 in the region corresponding to the exposed portion 53 of the active portion 120, and has a channel density lower than that of the first region 121. In a plan view, the second region 122 of this example is provided to surround the entire periphery of the first region 121, and the peripheral end of the second region 122 coincides with the end of the exposed portion 53. However, in other examples, the second region 122 may be provided only in a partial region of the periphery of the first region 121. The end of the lead frame is arranged in the second region 122.

[0079] When the transistor section 70 is operating, in the semiconductor substrate 10, since the current generated around the region where the lead frame is arranged flows toward the lead frame, the current is particularly concentrated in the region from the vicinity of the end of the lead frame to the end of the solder portion that joins the lead frame to the upper surface of the emitter electrode 52. The current density increases in this region, which may lead to a decrease in turn-off tolerance and a decrease in reliability due to heat generation.

[0080] According to the semiconductor device 100 of this example, the channel density of the second region 122 where the end of the lead frame is arranged is made lower than the channel density of the first region 121 located directly below the lead frame, thereby suppressing the generation of current in the second region 122. As a result, when the transistor portion 70 is operating, the current concentration in the second region 122 is alleviated, and a decrease in turn-off tolerance and a decrease in reliability due to heat generation can be suppressed.

[0081] In a plan view, the area of ​​the first region 121 is 0.5 to 10 times the area of ​​the second region 122. By setting the area ratio within this range, current concentration in the second region 122 can be alleviated, and a sufficient amount of current can be ensured in the entire semiconductor device 100.

[0082] The outer peripheral end of the second region 122 in this example coincides with the end of the exposed portion 53, but in other examples, it may be located further inside than the end of the exposed portion 53. In this case, the outer side of the second region 122 may have the same front element structure as the first region 121. Thus, the generation of current in the entire active portion 120 can be promoted, and the current concentration in the second region 122 can be alleviated.

[0083] Figure 5 FIG. 6 is a top view showing an example of the table portion 60. Figure 2 and Figure 3 As shown, the active portion 120 of this example includes a transistor portion 70. In the mesa portion 60 of the transistor portion 70, the emitter regions 12 and the contact regions 15 are alternately arranged in the trench extending direction.

[0084] In this example, the channel density of the mesa portion 60 of the transistor portion 70 in the second region 122 is smaller than the channel density of the mesa portion 60 of the transistor portion 70 in the first region 121. The channel density in the transistor portion 70 is determined by the ratio of the contact region 15 to the emitter region 12 in the trench extension direction. In a plan view, the ratio of the emitter region 12 to the contact region 15 in the mesa portion 60 of the transistor portion 70 in the first region 121 is larger than the ratio of the emitter region 12 to the contact region 15 in the mesa portion 60 of the transistor portion 70 in the second region 122.

[0085] In a plan view, a trench extending length L2 of the contact region 15 provided in the mesa portion 60 of the transistor portion 70 in the second region 122 is greater than a trench extending length L1 of the contact region 15 provided in the mesa portion 60 of the transistor portion 70 in the first region 121 .

[0086] When viewed from above, the emitter region 12 of the transistor portion 70 in the second region 122 can be arranged correspondingly to the emitter region 12 of the transistor portion 70 in the first region 121 in the trench arrangement direction, and the emitter region 12 of the transistor portion 70 in the first region 121 can be arranged correspondingly to any one of the emitter region 12 of the transistor portion 70 in the second region 122 and the contact region 15 in the trench arrangement direction.

[0087] The emitter region 12 of this example is arranged in a manner extending over a plurality of table portions 60 in the first region 121 in the groove arrangement direction, but a portion of the emitter region 12 also extends over a plurality of table portions 60 in the second region 122, and other emitter regions 12 do not extend to the second region 122 but terminate in the first region 121.

[0088] That is, in the second region 122, a portion of the emitter region 12 is thinned out compared to the first region 121, so that the channel density is reduced. For example, the channel density of the mesa portion 60 of the transistor portion 70 in the second region is 50% or less of the channel density of the mesa portion 60 of the transistor portion 70 in the first region 121. Thus, the current generation in the second region 122 is suppressed.

[0089] Figure 6 1 is another example of an enlarged view of the active portion 120. The active portion 120 of this example has transistor portions 70 and diode portions 80 alternately arranged in the trench arrangement direction. Figure 2 The description will focus on the differences between the examples, and the description of the common contents will be omitted.

[0090] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the back surface of the semiconductor substrate 10. Figure 6In FIG. 1 , a region where the cathode region 82 is provided is indicated by a dotted line. In the active portion 120 , a P+ type collector region may be provided in a region on the back side of the semiconductor substrate 10 where the cathode region 82 is not provided.

[0091] In the active portion 120, the projection area overlapping with the cathode region 82 in the Z-axis direction is set as the diode portion 80. That is, the projection area when the cathode region 82 is projected onto the front surface of the semiconductor substrate 10 along the direction perpendicular to the back surface of the semiconductor substrate 10 is set as the diode portion 80. In addition, the area where the projection area is extended to the well region along the Y-axis direction can also be set as the diode portion 80. In addition, in the active portion 120, the projection area when the collector region 22 is projected onto the front surface of the semiconductor substrate 10 along the direction perpendicular to the back surface of the semiconductor substrate 10 and the area where a predetermined unit structure is regularly arranged is set as the transistor portion 70, and the predetermined unit structure includes the emitter region 12 and the contact region 15.

[0092] exist Figure 6 , one mesa portion 60 of the diode portion 80 is shown, but the diode portion 80 may have a plurality of mesa portions 60 in the X-axis direction. The mesa portion 60 of the diode portion 80 is provided with a contact region 15, and in a region where the contact region 15 is not provided, the base region 14 is exposed on the front surface of the semiconductor substrate 10. The emitter region 12 may not be provided in the mesa portion 60 of the diode portion 80. The contact region 15 is provided on the front surface of the semiconductor substrate 10 in the mesa portion 60 adjacent to the transistor portion 70. The contact hole 54 is provided above the contact region 15 and the base region 14.

[0093] In the diode portion 80, one or more dummy groove portions 30 are arranged at predetermined intervals along the X-axis direction. The dummy groove portion 30 of the diode portion 80 may have an extension portion 29 and a front end portion 31. The front end portion 31 and the extension portion 29 have the same shape as the front end portion 41 and the extension portion 39. The length of the dummy groove portion 30 having the front end portion 31 in the extension direction may be the same as the length of the dummy groove portion 30 in the straight line shape in the extension direction.

[0094] In the transistor section 70, an intermediate region in which no emitter region is provided on the surface may be provided at the boundary adjacent to the diode section 80. In the mesa portion 60 in the intermediate region, the contact region 15 may be provided in a manner that covers an area larger than the area of ​​the mesa portion 60 of the transistor section 70. In addition, in the transistor section 70, a plurality of dummy groove portions 30 may be continuously arranged in a portion adjacent to the intermediate region. The dummy groove portion 30 provided in the portion adjacent to the intermediate region may also have an extension portion 29 and a front end portion 31.

[0095] Figure 7 It is shown Figure 6FIG. 1 is a diagram showing an example of a bb cross section in FIG. In this cross section, a base region 14 is provided on the front surface 21 side of the semiconductor substrate 10 in the diode portion 80. In the diode portion 80 of this example, the accumulation region 16 is not provided. In other examples, the accumulation region 16 may also be provided in the diode portion 80. In addition, a plurality of accumulation regions 16 may be provided in the depth direction.

[0096] In the diode portion 80 , the drift region 18 is provided below the base region 14 . In the diode portion 80 , the N+ type cathode region 82 is provided below the buffer region 20 .

[0097] Figure 8 is a diagram showing an example of the configuration of the transistor unit 70 and the diode unit 80. Figure 8 In the example, the transistor portion 70 is marked with I, and the diode portion 80 is marked with F. In the active portion 120 of this example, Figure 6 and Figure 7 The transistor portions 70 and the diode portions 80 shown are arranged alternately in the X-axis direction. In a plan view, the area of ​​each transistor portion 70 is larger than the area of ​​each diode portion 80.

[0098] In a plan view, the ratio of the diode portion 80 to the transistor portion 70 in the second region 122 is greater than the ratio of the diode portion 80 to the transistor portion 70 in the first region 121. In the first region 121 of this example, the width 1i of the transistor portion 70 in the X-axis direction is greater than the width of the diode portion 80 in the X-axis direction. In the second region 122 of this example, a portion of the diode portion 80 has the same width as the diode portion 80 in the first region 121, but the width of the other diode portions 80 is greater than the width of the diode portion 80 in the first region 121.

[0099] Thus, in the second region 122, the area ratio of the diode portion 80 to the transistor portion 70 is higher than that of the first region 121, so the channel density is lower than that of the first region 121. Thus, the current generation in the second region 122 is suppressed.

[0100] In plan view, even in the second region 122 where the area ratio of the diode portion 80 is high, the area of ​​the transistor portion 70 is larger than that of the diode portion 80. This can alleviate current concentration in the second region 122 and ensure sufficient current in the entire semiconductor device 100.

[0101] Fig. 9 1 is a top view showing an example of a semiconductor module 300 of the embodiment. The semiconductor module 300 includes a first semiconductor device 100-1 and a second semiconductor device 100-2. The first semiconductor device 100-1 and the second semiconductor device 100-2 are Figures 1 to 8 The semiconductor module 300 may include a plurality of sets of the first semiconductor device 100 - 1 and the second semiconductor device 100 - 2 .

[0102] The semiconductor module 300 of this example includes a housing 88. The housing 88 accommodates each semiconductor device 100. A refrigerant for cooling the semiconductor device 100 flows inside the housing 88. The semiconductor module 300 further includes at least one of a temperature sensor and a current sensor.

[0103] The housing 88 has a main terminal 86 and a control terminal 99. At least a portion of the main terminal 86 is electrically connected to the emitter electrode 52 of the semiconductor device 100. At least a portion of the control terminal 99 is electrically connected to the pad 50 of the semiconductor device 100. In addition, at least a portion of the control terminal 99 is electrically connected to the sensor of the semiconductor device 100.

[0104] Fig.10 FIG. 1 is a side view of the semiconductor substrate 10 mounted on the mounting substrate 200. Fig.10 , the collector electrode 24, the interlayer insulating film 38, etc. are omitted. The semiconductor substrate 10 is fixed to the mounting substrate 200 by a connection portion 160 such as solder. A solder portion 162 and a lead frame 163 are provided above the exposed portion 53 of the emitter electrode 52. The lead frame 163 is provided on the solder portion 162 and is electrically connected to the emitter electrode 52. In addition, a protective film 150 having an opening corresponding to the exposed portion 53 is provided above the front surface 21 of the semiconductor substrate 10 and the emitter electrode 52.

[0105] like Fig.10 As shown, the solder portion 162 has a cross-sectional shape that expands downward to improve the bonding strength with the emitter electrode 52. By providing the protective film 150, the solder portion 162 can be prevented from expanding to the pad 50 provided around the emitter electrode 52 or the pad region.

[0106] In addition, the protective film 150 can suppress the positional deviation of the solder portion 162 by limiting the extension range of the solder portion 162. If the position of the solder portion 162 is deviated, the center of gravity of the semiconductor device 100 is deviated, so that in the process of mounting the semiconductor substrate 10 on the mounting substrate 200 via the connection portion 160, the semiconductor substrate 10 may be fixed in a tilted state. By providing the protective film 150, the positional deviation of the solder portion 162 can be suppressed, thereby suppressing the tilt of the semiconductor substrate 10 during mounting.

[0107] As described above, when the transistor portion 70 operates, a current generated in the semiconductor substrate 10 around the region where the lead frame 163 is disposed flows into the lead frame 163. Therefore, the current is particularly concentrated in the region from the vicinity of the end of the lead frame 163 to the end of the solder portion 162. The current density increases in this region, which may cause a decrease in the turn-off withstand capability and a decrease in reliability due to heat generation.

[0108] Therefore, in this example, the region from the vicinity of the end of the lead frame 163 to the end of the solder portion 162, where current is concentrated when the transistor portion 70 is operated, is arranged in the second region 122 having a low channel density. In this example, the boundary between the first region 121 and the second region 122 is set at a position further inside than the end of the lead frame 163. The distance D1 between the boundary between the first region 121 and the second region 122 and the end of the lead frame 163 is 400 μm or more and 800 μm or less.

[0109] In addition, the outer peripheral end of the second region 122 of this example is set at a position further outward than the end of the solder portion 162. The distance D2 between the outer peripheral end of the second region 122 and the end of the solder portion 162 is greater than 0 μm and less than 1500 μm. In this way, in this example, by suppressing the generation of current in the second region 122, the current concentration in the second region 122 is alleviated when the transistor portion 70 is operated, and the reduction in turn-off tolerance and the reduction in reliability due to heat can be suppressed.

[0110] It should be noted that Figures 1 to 10 In the example described above, the first region 121 and the second region 122 are provided in the exposed portion 53 as the region including the center Ac of the active portion, corresponding to the lead frame. However, in the case where the additional active portion is provided above and below the pad 50 and the pad region (in the +Y axis direction and the -Y axis direction), the exposed portion 53 for arranging the lead frame may also be provided in the emitter electrode 52, and the first region 121 and the second region 122 may be provided in each exposed portion 53, and the emitter electrode 52 may be provided in a manner extending upward from the additional active portion.

[0111] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It can be clearly known from the description of the claims that such changes or improvements can also be included in the technical scope of the present invention.

[0112] It should be noted that the execution order of the actions, sequences, steps, stages, etc. in the devices, systems, programs, and methods shown in the claims, specifications, and drawings can be implemented in any order unless it is specifically stated that "before...", "prior to...", etc., and the output of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor substrate having an active portion provided with a transistor portion; an emitting electrode disposed above the front surface of the semiconductor substrate; and a protective film disposed above the emitting electrode, The active portion includes an emitter region of a first conductivity type, a contact region of a second conductivity type, and a plurality of trench portions disposed on the front surface of the semiconductor substrate. The emitter electrode has an exposed portion not covered by the protective film, The active portion includes a first region and a second region in a region where the exposed portion is provided, the second region being provided at an outer periphery of the first region and having a channel density lower than that of the first region.

2. The semiconductor device according to claim 1, wherein: The second region is provided so as to surround the entire periphery of the first region when the semiconductor substrate is viewed in plan.

3. The semiconductor device according to claim 1, wherein: In a plan view of the semiconductor substrate, an area of ​​the first region is not less than 0.5 times and not more than 10 times an area of ​​the second region.

4. The semiconductor device according to claim 1, wherein: In a plan view of the semiconductor substrate, the first region is separated from an end portion of the exposed portion by at least 0 μm or more and 1500 μm or less.

5. The semiconductor device according to claim 1, wherein: A channel density of a mesa portion of the transistor portion in the second region is smaller than a channel density of a mesa portion of the transistor portion in the first region.

6. The semiconductor device according to claim 1, wherein: In the mesa portion of the transistor portion, the emitter regions and the contact regions are alternately arranged in a trench extending direction, In a plan view of the semiconductor substrate, a ratio of the emitter region to the contact region in a mesa portion of the transistor portion in the first region is greater than a ratio of the emitter region to the contact region in a mesa portion of the transistor portion in the second region.

7. The semiconductor device according to claim 6, wherein: In a plan view of the semiconductor substrate, a trench extending length of the contact region provided in the mesa portion of the transistor portion in the second region is greater than a trench extending length of the contact region provided in the mesa portion of the transistor portion in the first region.

8. The semiconductor device according to claim 7, wherein: When the semiconductor substrate is viewed from above, the emitter region of the transistor portion in the second region is arranged to correspond to the emitter region of the transistor portion in the first region in the trench arrangement direction. When the semiconductor substrate is viewed in plan, the emitter region of the transistor portion in the first region is provided to correspond to any one of the emitter region and the contact region of the transistor portion in the second region in the trench arrangement direction.

9. The semiconductor device according to claim 5, wherein: A channel density of the mesa portion of the transistor portion in the second region is 50% or less of a channel density of the mesa portion of the transistor portion in the first region.

10. The semiconductor device according to claim 1, wherein: The active portion has diode portions that are alternately arranged with the transistor portions in the trench arrangement direction. When the semiconductor substrate is viewed in plan, a ratio of the diode portion to the transistor portion in the second region is greater than a ratio of the diode portion to the transistor portion in the first region.

11. The semiconductor device according to claim 10, wherein: In a plan view of the semiconductor substrate, in the second region, an area of ​​the transistor portion is larger than an area of ​​the diode portion.

12. A semiconductor module, characterized in that: A semiconductor device according to any one of claims 1 to 11.

13. The semiconductor module according to claim 12, characterized in that have: a solder portion disposed above the emitter electrode; and A lead frame is disposed on the solder portion and is electrically connected to the emitter electrode.

14. The semiconductor module according to claim 13, characterized in that When the semiconductor substrate is viewed in plan, a boundary between the first region and the second region is provided at a position inside an end portion of the lead frame.

15. The semiconductor module according to claim 14, characterized in that A distance between a boundary between the first region and the second region and an end portion of the lead frame is greater than or equal to 400 μm and less than or equal to 800 μm.

16. The semiconductor module according to claim 14, characterized in that The outer peripheral end of the second region is provided at a position further outward than an end portion of the solder portion.

17. The semiconductor module according to claim 16, characterized in that A distance between an outer peripheral end of the second region and an end of the solder portion is greater than or equal to 0 μm and less than or equal to 1500 μm.

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