Optoelectronic semiconductor device and method for manufacturing optoelectronic semiconductor device
By covering the side surface of the semiconductor layer stack with a regrown semiconductor layer, the efficiency reduction caused by etching marks is solved, and more efficient optoelectronic semiconductor device performance is achieved.
Patent Information
- Application Number
- CN202380040611.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-05-17
- Filing Date
- 2023-05-03
- Publication Date
- 2025-01-10
AI Technical Summary
In existing technologies, step-like etching marks are present on the side surfaces of the semiconductor layer stack during the etching process, which leads to reduced device efficiency, especially the uneven slopes that affect device performance during subsequent layer growth.
By covering the side surface of the semiconductor layer stack with a regenerated semiconductor layer, direct etching is avoided, and a smooth slope is formed using epitaxial growth technology, reducing etching marks.
It improves the efficiency of optoelectronic semiconductor devices, reduces device defects, and achieves better radiation performance.
Smart Images
Figure CN119302058A_ABST
Abstract
Description
[0001] An optoelectronic semiconductor component and a production method for producing such an optoelectronic semiconductor component are described in detail. The optoelectronic semiconductor component is suitable, for example, for emitting electromagnetic radiation, in particular in the infrared, visible or ultraviolet spectral range.
[0002] In an exemplary method for producing an optoelectronic semiconductor device, a semiconductor layer stack of an optoelectronic semiconductor device can be produced by patterning a semiconductor layer sequence by means of an etching process. In this context, the problem may arise that some layers of a semiconductor layer sequence having a heterogeneous structure are etched at different etching rates and therefore suffer from under-etching, which results in steps between layers of different material compositions at the side surfaces of the semiconductor layer stack. However, for subsequent layers applied to the side surfaces of the semiconductor layer stack, it is essential that the slope of the semiconductor layer stack is fairly smooth. In particular, a smooth slope is important if the subsequent layers are grown on the side surfaces. Otherwise, it may have many defects that reduce the efficiency of the device.
[0003] One object is in particular to specify an optoelectronic semiconductor component which provides an improved efficiency. This object is achieved in particular by an optoelectronic semiconductor component according to the independent claim. Further embodiments and further developments of the optoelectronic semiconductor component are the subject matter of the dependent claims.
[0004] Another object is in particular to specify a production method for producing an optoelectronic semiconductor component which provides improved efficiency. This object is achieved in particular by a production method according to the independent claim. Further embodiments and further developments of the production method are the subject matter of the dependent claims.
[0005] According to at least one embodiment of the optoelectronic semiconductor component, it comprises at least one semiconductor layer stack including an active region. The active region can be configured to generate and emit electromagnetic radiation. For example, the optoelectronic semiconductor component is suitable for emitting electromagnetic radiation with a wavelength in the infrared, visible or ultraviolet spectral range.
[0006] Furthermore, the semiconductor layer stack may include one or more side surfaces. Depending on the geometry of the semiconductor layer stack, the semiconductor layer stack has one side surface (e.g., if cylindrical) or several side surfaces (e.g., if polyhedral). The one or more side surfaces delimit the semiconductor layer stack in a lateral direction.
[0007] Furthermore, the active region may extend to one or more side surfaces. In other words, one or more side surfaces of the active region may form part of one or more side surfaces of the semiconductor layer stack.
[0008] According to at least one embodiment, the optoelectronic semiconductor device includes a regrown semiconductor layer covering the active region at one or more side surfaces. In other words, the regrown semiconductor layer can be arranged on one or more side surfaces of the semiconductor layer stack so that it covers the active region or the side surface of the active region. By means of the regrown semiconductor layer covering the active region, the number of traps at one or more side surfaces can be reduced, and thus the radiation efficiency of the active region can be improved.
[0009] According to at least one embodiment, at least one semiconductor layer stack has no etching marks at one or more side surfaces. Etching marks are recognizable in the surface structure of the semiconductor layer stack, for example in the form of steps between layers of different material compositions at the side surfaces of the semiconductor layer stack. The manufacturing method proposed here does not require any direct etching process for structuring the semiconductor layer stack, and thus the semiconductor layer stack can have a relatively smooth slope and fewer defects occur in the regrown semiconductor layer than in the case of an etching process.
[0010] According to at least one embodiment of the optoelectronic semiconductor component, it comprises:
[0011] at least one semiconductor layer stack comprising an active region and having one or more side surfaces, wherein the active region extends to the one or more side surfaces,
[0012] - a regrown semiconductor layer covering the active region at one or more side surfaces, wherein
[0013] At least one semiconductor layer stack has no etching marks at one or more side surfaces.
[0014] According to at least one embodiment or configuration, the regrown semiconductor layer is applied directly onto the semiconductor layer stack.Thus, the regrown semiconductor layer and the semiconductor layer stack may be in contact with each other.
[0015] According to at least one embodiment or configuration, the regrown semiconductor layer covers at least a majority of each side surface. In other words, the semiconductor layer stack may be at least mostly laterally surrounded by the regrown semiconductor layer.
[0016] According to at least one embodiment or configuration, the regrown semiconductor layer extends from one or more side surfaces to the main surface of at least one semiconductor layer stack. In other words, the regrown semiconductor layer may also cover the main surface. The main surface may be arranged obliquely to each side surface. For example, the main surface may delimit the semiconductor layer stack in a vertical direction, wherein the vertical direction extends perpendicular to the lateral direction. For example, the vertical direction is the direction in which the semiconductor layers of the semiconductor layer sequence follow each other.
[0017] According to at least one embodiment or configuration, the regrown semiconductor layer comprises an opening at the main surface. Thus, the regrown semiconductor layer partially covers the main surface. The electrical contact layer may be arranged in the opening and may be in electrical contact with at least one semiconductor layer stack. The electrical contact layer may include a metal layer and / or a layer of a transparent conductive oxide such as ITO. Alternatively, the regrown semiconductor layer may not form any openings at the main surface. And in this case the electrical contact layer may electrically contact the regrown semiconductor layer.
[0018] According to at least one embodiment or configuration, the semiconductor material system of the semiconductor layer stack and / or the regrown semiconductor layer is InGaAlP or AlInGaAsP. However, the semiconductor layer stack and / or the regrown semiconductor layer may also be based on an AlInGaN material system or on an AlInGaAs material system. For example, in the case of an InGaAlP material system or an AlInGasAsP material system, the regrown semiconductor layer may include an undoped InGaAlP layer or a p-doped InAlP layer. In addition, in the case of an AlInGaN material system, the regrown semiconductor layer may include an undoped InGaAlN layer or a p-doped InGaAlN layer. In particular, the semiconductor layer stack and the regrown semiconductor layer are based on the same semiconductor material system.
[0019] According to at least one embodiment or configuration, the semiconductor layer stack includes a first semiconductor region of a first conductivity type, for example a p-doped semiconductor region, and a second semiconductor region of a second conductivity type, for example an n-doped semiconductor region.
[0020] The active region may be arranged between the first semiconductor region and the second semiconductor region.The active region may include a series of single layers, which form a quantum well structure, in particular a single quantum well (SQW) structure or a multiple quantum well (MQW) structure.
[0021] Furthermore, the first semiconductor region and the second semiconductor region may each have a series of monolayers, some of which may be undoped or lightly doped.The monolayers of the semiconductor region may be epitaxially deposited on a patterned growth substrate.
[0022] Furthermore, the regrown semiconductor layer may be a single layer and may be made of a single material that is homogeneously distributed throughout the regrown semiconductor layer. However, the regrown semiconductor layer may also be a multilayer and include two or more sublayers. Adjacent sublayers or all sublayers may differ from each other in material composition and / or in doping concentration and / or in doping type.
[0023] According to at least one embodiment or configuration, at least one semiconductor layer stack has a cross section similar to an acute trapezoid, wherein the value of each acute angle is in the range between 15° and 60°. The manufacturing method proposed here does not require any direct etching process, allowing a relatively free choice of angles.
[0024] According to at least one embodiment or configuration, the optoelectronic semiconductor device comprises a plurality of semiconductor layer stacks as described above, wherein each semiconductor layer stack comprises an active region and has one or more side surfaces. The semiconductor layer stacks may be arranged on a common carrier. In particular, the optoelectronic semiconductor device comprises a regrown semiconductor layer covering each active region at one or more side surfaces of the semiconductor layer stack.
[0025] According to at least one embodiment or configuration, the optoelectronic semiconductor component is a MicroLed, also referred to as, for example, microLED, μLED, μ-LED, uLED, u-LED or micro light emitting diode. In this embodiment or configuration, the optoelectronic semiconductor component has particularly small dimensions.
[0026] The method described below is suitable for producing the optoelectronic semiconductor component described here. Features described in conjunction with the optoelectronic semiconductor component can therefore also be applied to the method, and vice versa.
[0027] According to at least one embodiment of the manufacturing method for producing an optoelectronic semiconductor component as described above, the method comprises the following steps, preferably in the order stated:
[0028] - providing a patterned growth substrate comprising at least one opening,
[0029] - growing, in particular epitaxially growing, a semiconductor layer sequence on the patterned growth substrate such that the semiconductor layer sequence is arranged in the at least one opening, wherein the semiconductor layer sequence in the at least one opening forms a semiconductor layer stack comprising an active region and having one or more side surfaces,
[0030] - removing portions of the patterned growth substrate covering one or more side surfaces of the at least one semiconductor layer stack,
[0031] - Depositing, in particular epitaxially growing, a regrown semiconductor layer on one or more side surfaces of the at least one semiconductor layer stack, wherein the regrown semiconductor layer covers the active region at the one or more side surfaces.
[0032] Due to the growth in the at least one opening, the semiconductor layer stack formed therein has substantially (i.e. within common production tolerances) the same three-dimensional shape as the at least one opening. And the semiconductor layer stack can grow in a desired three-dimensional shape. Therefore, there is no need to pattern the semiconductor layer sequence, for example by etching, to create a semiconductor layer stack with a desired three-dimensional shape. And therefore, at least one semiconductor layer stack can be produced without etching marks at one or more side surfaces. For example, the three-dimensional shape of the semiconductor layer stack and the opening can be a truncated cone or a truncated pyramid.
[0033] According to at least one embodiment or configuration, at least one semiconductor layer stack is formed at a height lower than the depth of at least one opening. This results in a portion of the patterned growth substrate protruding beyond the main surface of the at least one semiconductor layer stack, the main surface facing away from the bottom of the opening. The portion protruding beyond the main surface facilitates the removal of a portion of the patterned growth substrate. For example, the height of the at least one semiconductor layer stack is at least 0.2 μm and at most 10 μm. The height and depth can be determined along the vertical direction.
[0034] According to at least one embodiment or configuration, the step of removing portions of the patterned growth substrate comprises an etching process.Before the step of removing portions of the patterned growth substrate, a step of removing the semiconductor layer sequence on the portions to be removed, for example by chemical mechanical polishing, may be performed.
[0035] According to at least one embodiment or configuration, the step of providing a patterned growth substrate includes providing a growth substrate layer, and removing material from the growth substrate layer to form at least one opening of the patterned growth substrate, wherein the growth substrate layer includes a semiconductor material. For example, the growth substrate layer may include or consist of GaAs. For example, the growth substrate layer may be patterned by photolithography using a resist mask and an etching process (e.g., a wet chemical etching process).
[0036] Alternatively, the step of providing a patterned growth substrate may include providing a growth substrate layer, which includes or consists of a semiconductor material (e.g., GaAs), and forming a patterned layer on the growth substrate layer, wherein the patterned layer includes at least one opening of the patterned growth substrate.
[0037] According to at least one configuration, the step of forming the patterned layer may include:
[0038] - providing a resist mask on the growth substrate layer in a region where at least one opening is to be formed,
[0039] - depositing a patterned layer of material on the growth substrate layer around the resist mask, and
[0040] - removing the resist mask, wherein at least one opening is formed. The patterned layer may comprise a dielectric material, such as Al2O3.
[0041] The step of depositing the material of the patterned layer on the growth substrate layer may include a sputtering process or any low temperature process that does not cause damage to the resist mask.
[0042] Furthermore, before the step of removing the resist mask, the step of removing the material of the patterned layer on the upper surface of the resist mask facing away from the growth substrate layer, for example by chemical mechanical polishing or dry etching, and then removing the resist mask, for example by a solvent, may be performed.
[0043] Alternatively, the step of forming a patterned layer may include:
[0044] - providing a resist mask on the growth substrate layer in a region where the patterned layer is to be formed,
[0045] - depositing a dielectric material, such as SiO2, on the growth substrate layer around the resist mask,
[0046] - removing the resist mask,
[0047] - depositing a patterned layer of material (16') on the growth substrate layer in the areas where the resist mask has been removed, and
[0048] - Removing the dielectric material, wherein at least one opening is formed. For example, the patterned layer may comprise a semiconductor material, such as GaAs. The patterned layer may be grown, in particular epitaxially, on a growth substrate layer.
[0049] The step of depositing the dielectric material on the growth substrate layer may include a sputtering process or any low temperature process that does not cause damage to the resist mask.
[0050] Furthermore, before the step of removing the resist mask, a step of removing the dielectric material on the upper surface of the resist mask together with the resist mask by a lift-off technique or by chemical mechanical polishing and resist stripping may be performed.
[0051] Furthermore, the step of removing the dielectric material to create the at least one opening may include an etching process.
[0052] In the described embodiment, the step of providing a resist mask may include applying a resist layer on the growth substrate layer and patterning the resist layer by photolithography.
[0053] The optoelectronic semiconductor device proposed here can be a MicroLed and is suitable for AR (augmented reality), VR (virtual reality) and display applications. MicroLed or multiple MicroLeds can form pixels or sub-pixels of a display device and emit light of a defined color. The small pixel size and high density with close distance make MicroLed particularly suitable for small monolithic displays for AR applications, especially data glasses. In addition, MicroLed can be used for communication and lighting applications.
[0054] Further preferred embodiments and further developments of the optoelectronic semiconductor component and the production method for producing the optoelectronic semiconductor component are described below in combination with Figure 1 The exemplary embodiments described through FIG. 9 will become apparent.
[0055] Figure 1 shows a schematic cross-sectional view of an exemplary embodiment of an optoelectronic semiconductor component,
[0056] Figure 2 shows a schematic cross-sectional view of a comparative example of an optoelectronic semiconductor device,
[0057] FIG. 3A to FIG. 3F Schematic cross-sectional views showing method steps of a first exemplary embodiment of a method for producing an optoelectronic semiconductor component described herein,
[0058] FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4C Schematic cross-sectional illustrations showing method steps of a second exemplary embodiment of a method for producing an optoelectronic semiconductor component described herein,
[0059] Figures 5 to 7 shows schematic cross-sectional views of patterned growth substrates according to various exemplary embodiments,
[0060] FIG. 8A to FIG. 8H Schematic cross-sectional views showing method steps of a third exemplary embodiment of a method for producing an optoelectronic semiconductor component described herein,
[0061] FIG. 9A to FIG. 9I Schematic cross-sectional illustrations show method steps for a fourth exemplary embodiment of a method for producing an optoelectronic semiconductor component described here.
[0062] Identical, equivalent or equivalently acting elements may be indicated by the same reference numerals in the drawings. The drawings are schematic and therefore not necessarily true to scale. For the purpose of better illustration, relatively small elements, and in particular layer thicknesses, may be shown exaggeratedly.
[0063] Figure 1An exemplary embodiment of an optoelectronic semiconductor device 1 is shown. The optoelectronic semiconductor device 1 comprises two or more semiconductor layer stacks 2. However, as indicated by the separation lines, the optoelectronic semiconductor device 1 may also comprise only one semiconductor layer stack 2. The semiconductor layer stacks 2 are arranged on a common carrier 3 which may be part of a patterned growth substrate 14 for depositing a semiconductor layer sequence 15 in order to produce a semiconductor layer stack 2 as described in more detail below (see, for example, Figures 3D to 3F ).
[0064] The semiconductor layer stack 2 comprises in each case an active region 5 which serves in particular to generate and emit electromagnetic radiation. For example, the optoelectronic semiconductor component 1 is suitable for emitting electromagnetic radiation having a wavelength in the infrared, visible or ultraviolet spectral range.
[0065] Furthermore, the semiconductor layer stack 2 comprises in each case a first semiconductor region 4 of a first conductivity type, for example a p-doped semiconductor region, and a second semiconductor region 6 of a second conductivity type, for example an n-doped semiconductor region.
[0066] The active region 5 is arranged between the first semiconductor region 4 and the second semiconductor region 6, and may include a series of single layers forming a quantum well structure, in particular a single quantum well (SQW) structure or a multiple quantum well (MQW) structure. In addition, the first semiconductor region 4 and the second semiconductor region 6 may each have a series of single layers, some of which may be undoped or lightly doped (not shown).
[0067] The semiconductor layer stack 2 has in each case a three-dimensional shape similar to a truncated pyramid and at least three, preferably at least four side surfaces 2C, which delimit the respective semiconductor layer stack 2 in a lateral direction L and extend obliquely to the main extension plane of the carrier 3. The lateral direction L can be parallel to the main extension plane of the carrier 3. The semiconductor layer stack 2 has in each case a cross section similar to an acute trapezoid, wherein the value of each acute angle α is in the range between 15° and 60°. The angle α is the angle between the respective side surface 2C and the second main surface 2B.
[0068] The active regions 5 extend in each case substantially (ie within customary production tolerances) parallel to a main extension plane of the carrier 3 and to the side surface 2C. In other words, the side surfaces of the active regions 4 can in each case form part of the side surface 2C of the semiconductor layer stack 2 .
[0069] The optoelectronic semiconductor device 1 further comprises a regrown semiconductor layer 7 covering the active region 5 at the side surface 2C of each semiconductor layer stack 2. In other words, the regrown semiconductor layer 7 is arranged on the side surface 2C of each semiconductor layer stack 2 so that it covers the active region 5 or the side surface of the active region 5. In particular, the regrown semiconductor layer 7 covers at least a large part of each side surface 2C so that the semiconductor layer stack 2 is in each case at least largely surrounded laterally by the regrown semiconductor layer 7. The regrown semiconductor layer 7 can be applied directly on the semiconductor layer stack 2 and thereby contacts the semiconductor layer stack 2. Preferably, the regrown semiconductor layer 7 is epitaxially grown on the semiconductor layer stack 2.
[0070] By means of the regrown semiconductor layer 7 covering the active region 5 , the number of traps at the side surface 2C can be reduced, and thus the radiation efficiency of the active region 5 can be improved.
[0071] The regrown semiconductor layer 7 extends in each case from the side surface 2C to a first main surface 2A of the semiconductor layer stack 2, wherein the first main surface 2A is arranged in each case on the side opposite to the carrier 3 and is inclined to each side surface 2C. The main surface 2A delimits the semiconductor layer stack 2 in each case in a vertical direction V, wherein the vertical direction V extends perpendicular to the lateral direction L. Furthermore, the second main surface 2B delimits the semiconductor layer stack 2 on the side facing the carrier 3 in each case.
[0072] The regrown semiconductor layer 7 comprises an opening 8 at each first main surface 2A and thus partially covers the corresponding first main surface 2A. An electrical contact layer 9 is arranged on the side of the regrown semiconductor layer 7 facing away from the semiconductor layer stack 2 and extends in the opening 8. The electrical contact layer 9 is in electrical contact with the semiconductor layer stack 2 in each case. The electrical contact layer 9 may comprise a metal layer and / or a layer of a transparent conductive oxide such as ITO. Alternatively, the regrown semiconductor layer 7 may not form any openings at the first main surface 2A. And in this case the electrical contact layer 9 may electrically contact the regrown semiconductor layer 7.
[0073] Suitable semiconductor material systems for the semiconductor layer stack 2 and / or the regrown semiconductor layer 7 are InGaAlP or AlInGaAsP. However, the semiconductor layer stack 2 and / or the regrown semiconductor layer 7 may also be based on an AlInGaN material system or on an AlInGaAs material system. For example, in the case of an InGaAlP material system or an AlInGasAsP material system, the regrown semiconductor layer 7 may include an undoped InGaAlP layer or a p-doped InAlP layer. Furthermore, in the case of an AlInGaN material system, the regrown semiconductor layer 7 may include an undoped InGaAlN layer or a p-doped InGaAlN layer. In particular, the semiconductor layer stack 2 and the regrown semiconductor layer 7 are based on the same semiconductor material system.
[0074] The regrown semiconductor layer 7 may be a single layer and may be made of a single material that is homogeneously distributed throughout the regrown semiconductor layer 7. However, the regrown semiconductor layer 7 may also be a multilayer and include two or more sublayers (not shown). Adjacent sublayers or all sublayers may differ from each other in material composition and / or in doping concentration and / or in doping type.
[0075] The height h of the semiconductor layer stack 2 , ie the maximum extension in the vertical direction V, can in each case be at least 0.2 μm and at most 10 μm.
[0076] Furthermore, the width w of the semiconductor layer stack 2 , ie the maximum extension in at least one lateral direction L, can in each case be at least 200 nm and at most 100 μm.
[0077] The optoelectronic semiconductor component 1 can be embodied as a MicroLed having particularly small dimensions, including, for example, a maximum extension in the vertical direction V in the range from 1.5 μm to 10 μm and a maximum extension in the lateral direction L of less than or equal to 100 μm, or less than or equal to 70 μm, or less than or equal to 50 μm.
[0078] The semiconductor layer stack 2 has no etching traces at the side surfaces 2C in each case. Etching traces are recognizable in the surface structure of the semiconductor layer stack 2 , for example, as described in accordance with Figure 2 This becomes apparent in the form of steps between layers of different material composition at the side surface 2C' of the semiconductor layer stack 2'.
[0079] For example, by patterning a semiconductor layer sequence by means of an etching process Figure 20 . The semiconductor layer stack 2 ′ of the comparative example shown in , wherein some layers of the semiconductor layer sequence having a heterogeneous structure are etched at different etching rates and are therefore subject to under-etching, which results in steps between layers of different material compositions at the side surface 2C′ of the semiconductor layer stack 2 ′.
[0080] However, if Figure 1 The semiconductor layer stack 2 shown in each case has a rather smooth slope and therefore fewer defects occur in the regrown semiconductor layer 7 applied on the side surface 2C of the semiconductor layer stack 2 than in the case of an etching process. This leads to improved device efficiency.
[0081] Combination FIG. 3A to FIG. 3F , more detailed description for producing e.g. combined Figure 1 A first exemplary embodiment of a method for producing an optoelectronic semiconductor component is described.
[0082] from Figure 3A Initially, the method comprises the step of providing a growth substrate layer 10 comprising or consisting of a semiconductor material such as GaAs.
[0083] continue Figure 3B , the method further comprises the steps of providing a resist layer (not shown) on the growth substrate layer 10, patterning the resist layer by photolithography and producing a resist mask 11. In a further step, the growth substrate layer 10 is patterned by means of the resist mask 11 using an etching process (e.g. a wet chemical etching process) and material is removed from the growth substrate layer 10, so that one or several openings 12 are produced in the growth substrate layer 10. The patterned growth substrate layer 10 comprises a raised portion 13, which laterally surrounds the opening 12, wherein the angle α between a side surface 13C of the raised portion 13 and a corresponding bottom surface 10B at the bottom of the opening 12 is in each case substantially (i.e. within common production tolerances) identical to the angle α between a side surface 2C and the second main surface 2B of the semiconductor layer stack 2 to be produced (see Figure 1 ).
[0084] like Figure 3C As shown in FIG. 1 , the resist mask 11 is removed after the patterned growth substrate layer 10 is patterned. The patterned growth substrate layer 10 constitutes a patterned growth substrate 14 including at least one opening 12.
[0085] continue Figure 3DThe method further comprises the step of growing a semiconductor layer sequence 15 on the patterned growth substrate 14, such that the semiconductor layer sequence 15 is arranged in the opening 12, wherein the semiconductor layer sequence 15 in the opening 12 in each case forms a semiconductor layer stack 2 comprising an active region 5 and having one or more side surfaces 2C. The semiconductor layer sequence 15 is formed from a semiconductor material as mentioned above in conjunction with the semiconductor layer stack 2.
[0086] In particular, the semiconductor layer sequence 15 is epitaxially grown on the patterned growth substrate 14. Although parasitic growth occurs in each case on the main surface 13A of the raised portion 13, the growth conditions can be controlled in such a way that growth on the edge of the main surface 13A is prevented.
[0087] continue Figure 3E The method further comprises the step of removing parasitic growth portions on main surface 13A of raised portion 13 by, for example, chemical mechanical polishing. Here, semiconductor layer stack 2 is formed with a height h similar to the height of raised portion 13 or depth d of opening 12 in each case.
[0088] continue Figure 3F , the method further comprises a step of removing portions of the patterned growth substrate 14 covering one or more side surfaces 2C of the semiconductor layer stack 2. In particular, the raised portions 13 are removed in this step. The removal process is, for example, an etching process. After the removal process, the side surfaces 2C may be subjected to a cleaning process to reduce defects. The semiconductor layer stack 2 produced in this way is arranged on a common carrier 3, which is part of the patterned growth substrate 14, and is laterally spaced apart from each other by gaps originating from the removed portions of the patterned growth substrate 14.
[0089] The method further comprises the step of depositing, in particular epitaxially growing, a regrown semiconductor layer 7 on the side surface 2C of the semiconductor layer stack, wherein the regrown semiconductor layer 7 in each case covers the active region 5 at the side surface 2C.
[0090] The method may also comprise the step of producing an electrical contact layer (not shown).
[0091] Due to the growth in the opening 12, the semiconductor layer stack 2 formed therein has in each case substantially (i.e. within common production tolerances) the same three-dimensional shape as the opening 12. And the semiconductor layer stack 2 can be grown in a desired three-dimensional shape. Therefore, there is no need to pattern the semiconductor layer sequence 15, for example by an etching process, to create a semiconductor layer stack 2 with a desired three-dimensional shape. And therefore, the semiconductor layer stack 2 can be produced without etching marks at the side surface 2C, thereby providing a smoother slope and thereby providing a better quality regrown semiconductor layer 7. For example, the three-dimensional shape of the opening 12 can be a truncated pyramid in each case.
[0092] Additionally, the method may have any features, characteristics, and advantages mentioned in conjunction with other exemplary embodiments.
[0093] Combination FIG. 4A to FIG. 4C , explain in more detail, for example, combining Figure 1 A second exemplary embodiment of a production method for producing an optoelectronic semiconductor component is described.
[0094] exist FIG. 4A to FIG. 4C The method steps shown in FIG. 3A to FIG. 3C Before the method steps described.
[0095] like Figure 4A , when growing the semiconductor layer sequence 15 , the semiconductor layer stack 2 in the opening 12 is formed with a height h lower than the depth d of the opening 12 . This results in a raised portion 13 which in each case projects beyond the first main surface 2A of the semiconductor layer stack 2 .
[0096] The raised portion 13 higher than the semiconductor layer stack 2 is easier to remove. The parasitic growth portion of the semiconductor layer sequence 15 on the main surface 13A of the raised portion 13 can be removed together with the raised portion 13 or a portion of the patterned growth substrate 14 by etching, for example (see Figure 4B ). Therefore, the step of chemical mechanical polishing can be omitted.
[0097] The subsequent steps of the manufacturing method (see Figure 4C ) can be combined as Figure 3F Proceed as described.
[0098] Additionally, the method may have any features, characteristics, and advantages mentioned in conjunction with other exemplary embodiments.
[0099] Figures 5 to 7Different exemplary embodiments of patterned growth substrates 14 are shown. As becomes apparent from these figures, the angle α between the side surface 13C of the raised portion 13 and the bottom surface 10B at the bottom of the opening 12 can be selected quite freely, for example between 0° and 90°, preferably between 15° and 60°, independently of the material of the semiconductor layer sequence and in a manner best suited to the deposition of the regrown layer.
[0100] Combination FIG. 8A to FIG. 8H , more detailed description for producing e.g. combined Figure 1 A third exemplary embodiment of a method for producing an optoelectronic semiconductor component is described.
[0101] from Fig. 8A Initially, a growth substrate layer 10 is provided, which includes or consists of a semiconductor material (eg, GaAs).
[0102] continue Figure 8B On the growth substrate layer 10, a patterned growth substrate 14 is formed (see Fig. 8E ) is provided in the region of the opening 12. The shape of the resist mask 11 can be adjusted according to the photolithography conditions.
[0103] continue Figure 8C , a patterned layer 16 is deposited on the growth substrate layer 10 around the resist mask 11 (see Fig. 8E ) material 16'. The material 16' may cover the upper surface 11A and the side surface 11C of the resist mask 11. The material 16' of the patterned layer 16 may be a dielectric material, such as Al2O3. The material 16' of the patterned layer 16 may be deposited by a sputtering process or any low temperature process that does not cause damage to the resist mask 11.
[0104] continue Fig.8D , for example, the material 16 ′ of the patterned layer 16 on the upper surface 11A of the resist mask 11 facing away from the growth substrate layer 10 is removed by chemical mechanical polishing or dry etching.
[0105] continue Fig. 8E The resist mask 11 is removed, for example, by a solvent, and thereby a patterned layer 16 including the opening 12 is formed. The growth substrate layer 10 having the patterned layer 16 constitutes a patterned growth substrate 14.
[0106] continue Fig.8F, a semiconductor layer sequence 15 is grown on a patterned growth substrate 14 so that the semiconductor layer sequence 15 is arranged in the opening 12, wherein the semiconductor layer sequence 15 in the opening 12 in each case forms a semiconductor layer stack 2 comprising an active region 5 and having one or more side surfaces 2C. The growth process may be an MOCVD (metal organic chemical vapor deposition) process. The semiconductor layer stack 2 is at most as high as the depth of the opening 12.
[0107] continue Figure 8G , the portion of the patterned growth substrate 14 covering the side surface 2C of the semiconductor layer stack 2 is removed. In particular, the removed portion is the raised portion 13 of the patterned growth substrate 14 formed by the patterned layer 16. After the removal process, the side surface 2C can be subjected to a cleaning process to reduce defects. The semiconductor layer stack 2 produced in this way is arranged on a common carrier 3, which is a part of the patterned growth substrate 14, and is laterally spaced apart from each other by gaps originating from the removed portion of the patterned growth substrate 14.
[0108] The subsequent steps of the manufacturing method (see Figure 8H ) can be combined as Figure 3F Proceed as described.
[0109] Additionally, the method may have any features, characteristics, and advantages mentioned in conjunction with other exemplary embodiments.
[0110] Combination FIG. 9A to FIG. 9I , more detailed description for producing e.g. combined Figure 1 A fourth exemplary embodiment of a method for producing an optoelectronic semiconductor component is described.
[0111] from Fig.9A Initially, a growth substrate layer 10 is provided, which includes or consists of a semiconductor material (eg, GaAs).
[0112] continue Fig. 9B , a resist mask 11 is provided on the growth substrate layer 10 in a region where the patterned layer 16 is to be formed (see Fig.9F ). The shape of the resist mask 11 can be adjusted according to the photolithography conditions.
[0113] continue Fig. 9C , a dielectric material 17, such as SiO2, is deposited on the growth substrate layer 10 around the resist mask 11. The material 17 may cover the upper surface 11A and the side surface 11C of the resist mask 11. The material 17 may be deposited by a sputtering process or any low temperature process that does not cause damage to the resist mask 11.
[0114] continue Fig.9DBefore removing the resist mask 11, the stripping technique or the like is combined with Fig.8D The described chemical mechanical polishing and resist stripping remove the dielectric material 17 on the upper surface 11A of the resist mask 11 together with the resist mask 11 .
[0115] continue Fig.9E , patterned layer 16 (see Fig.9F ) material 16' is deposited on the growth substrate layer 10 and the resist mask 11 has been removed (see Fig. 9C ). The deposition process may be an epitaxial growth process with controlled conditions to avoid parasitic growth on the dielectric material 17. The material 16' of the patterned layer 16 may be a semiconductor material such as GaAs.
[0116] continue Fig.9F , removing the dielectric material 17 , wherein the opening 12 is formed. The removal process may be an etching process. The growth substrate layer 10 with the patterned layer 16 constitutes a patterned growth substrate 14 .
[0117] continue Figure 9G , a semiconductor layer sequence 15 is grown on the patterned growth substrate 14 such that the semiconductor layer sequence 15 is arranged in the opening 12 , wherein the semiconductor layer sequence 15 in the opening 12 in each case forms a semiconductor layer stack 2 comprising an active region 5 and having one or more side surfaces 2C.
[0118] Although parasitic growth occurs on main surface 13A of convex portion 13 in each case, the growth conditions can be controlled in such a manner as to prevent growth on the edge of main surface 13A.
[0119] continue Figure 9H , for example, by chemical mechanical polishing to remove the parasitic growth portion on the main surface 13A of the raised portion 13. And, portions of the patterned growth substrate 14 covering one or more side surfaces 2C of the semiconductor layer stack 2 are removed. In particular, the raised portion 13 is removed in this step. The removal process is, for example, an etching process. After the removal process, the side surface 2C may be subjected to a cleaning process to reduce defects. The semiconductor layer stack 2 produced in this way is arranged on a common carrier 3, which is part of the patterned growth substrate 14, and is laterally spaced apart from each other by gaps originating from the removed portions of the patterned growth substrate 14.
[0120] continue Fig.9I , a regrown semiconductor layer 7 is deposited or grown on the side surface 2C of the semiconductor layer stack 2 , wherein the regrown semiconductor layer 7 in each case covers the active region 5 at the side surface 2C.
[0121] Additionally, the method may have any features, characteristics, and advantages mentioned in conjunction with other exemplary embodiments.
[0122] By describing based on the embodiments, the present invention is not limited to these embodiments. Instead, the present invention includes any new features and any combination of features, and any combination of features particularly includes any combination of features in the patent claims, even if the feature or the combination itself is not explicitly indicated in the patent claims or embodiments.
[0123] This patent application claims the priority of German patent application 102022112344.8, the disclosure content of which is incorporated herein by reference.
[0124] Reference numerals
[0125] 1Optoelectronic semiconductor devices
[0126] 2.2'Semiconductor layer stacking
[0127] 2A first main surface
[0128] 2B Second main surface
[0129] 2C, 2C' side surface
[0130] 3 Carrier
[0131] 4First semiconductor region
[0132] 5 Active Area
[0133] 6 Second semiconductor region
[0134] 7 Regrowth of semiconductor layer
[0135] 8. Opening of regrowth semiconductor layer
[0136] 9Electrical contact layer
[0137] 10 Growth substrate layer
[0138] 10B bottom
[0139] 11Resist mask
[0140] 11A upper surface
[0141] 11C side surface
[0142] 12 Opening of patterned growth substrate
[0143] 13 Raised part
[0144] 13A Main surface
[0145] 13C side surface
[0146] 14Patterned Growth Substrate
[0147] 15 Semiconductor layer sequence
[0148] 16 Patterned Layers
[0149] 16' Material of patterned layer
[0150] 17 Dielectric Materials
[0151] α angle
[0152] dDepth
[0153] hHeight
[0154] wWidth
[0155] L Horizontal direction
[0156] VVertical direction
Claims
1. An optoelectronic semiconductor device (1), comprising: at least one semiconductor layer stack (2), the at least one semiconductor layer stack (2) comprising an active region (5) and having one or more side surfaces (2C), wherein the active region (5) extends to the one or more side surfaces (2C), - a regrown semiconductor layer (7), said regrown semiconductor layer (7) covering said active area (5) at said one or more side surfaces (2C), wherein: The at least one semiconductor layer stack (2) has no etching marks at the one or more side surfaces (2C).
2. The optoelectronic semiconductor component (1) according to claim 1, wherein: The regrown semiconductor layer (7) covers at least a majority of each side surface (2C).
3. The optoelectronic semiconductor component (1) according to claim 1, wherein: The regrown semiconductor layer (7) extends from the one or more side surfaces (2C) to the main surface (2A) of the at least one semiconductor layer stack (2), wherein the main surface (2A) is arranged obliquely to each side surface (2C).
4. The optoelectronic semiconductor component (1) according to the preceding claim, wherein: The regrown semiconductor layer (7) comprises an opening (8) at the main surface (2A), and an electrical contact layer (9) is arranged in the opening (8) and is in electrical contact with the at least one semiconductor layer stack (2).
5. The optoelectronic semiconductor component (1) according to claim 1, wherein: The semiconductor material system of the at least one semiconductor layer stack (2) and / or the regrown semiconductor layer (7) is InGaAlP or AlInGaAsP.
6. The optoelectronic semiconductor component (1) according to claim 1, wherein: The at least one semiconductor layer stack (2) has a cross section similar to an acute trapezoid, wherein the value of each acute angle (α) is in the range between 15° and 60°. 7 . The optoelectronic semiconductor component ( 1 ) according to claim 1 , which is a MicroLed.
8. A manufacturing method for producing an optoelectronic semiconductor component (1) according to any one of the preceding claims, comprising the following steps: - providing a patterned growth substrate (14) comprising at least one opening (12), - growing a semiconductor layer sequence (15) on the patterned growth substrate (14) such that the semiconductor layer sequence (15) is arranged in the at least one opening (12), wherein the semiconductor layer sequence (15) in the at least one opening (12) forms a semiconductor layer stack (2), the semiconductor layer stack (2) comprising an active region (5) and having one or more side surfaces (2C), - removing portions of the patterned growth substrate (14) covering the one or more side surfaces (2C) of the at least one semiconductor layer stack (2), - depositing a regrown semiconductor layer (7) on the one or more side surfaces (2C) of the at least one semiconductor layer stack (2), wherein the regrown semiconductor layer (7) covers the active area (5) at the one or more side surfaces (2C).
9. The manufacturing method according to the preceding claim, wherein: The at least one semiconductor layer stack (2) is formed at a height (h) lower than a depth (d) of the at least one opening (12).
10. The manufacturing method according to any one of the two preceding claims, wherein: The step of removing portions of the patterned growth substrate (14) comprises an etching process.
11. The manufacturing method according to claims 8 to 10, wherein: The step of providing a patterned growth substrate (14) comprises providing a growth substrate layer (10) and removing material from the growth substrate layer (10) to form the at least one opening (12) of the patterned growth substrate (14), wherein the growth substrate layer (10) comprises a semiconductor material.
12. The manufacturing method according to claims 8 to 10, wherein: The step of providing a patterned growth substrate (14) comprises providing a growth substrate layer (10) comprising a semiconductor material and forming a patterned layer (16) on the growth substrate layer (10), wherein the patterned layer (16) comprises the at least one opening (12) of the patterned growth substrate (14).
13. The manufacturing method according to the preceding claim, wherein: The patterned layer (16) includes a dielectric material.
14. The manufacturing method according to the preceding claim, wherein: The step of forming the patterned layer (16) comprises: - providing a resist mask (11) on the growth substrate layer (10) in a region where the at least one opening (12) is to be formed, - depositing the material (16') of the patterned layer (16) around the resist mask (11) on the growth substrate layer (10), and - removing the resist mask (11), wherein the at least one opening (12) is formed.
15. The manufacturing method according to claim 12, wherein: The patterned layer (16) comprises a semiconductor material.
16. The manufacturing method according to the preceding claim, wherein: The step of forming the patterned layer (16) comprises: - providing a resist mask (11) on the growth substrate layer (10) in a region where the patterned layer (16) is to be formed, - depositing a dielectric material (17) on the growth substrate layer (10) around the resist mask (11), - removing the resist mask (11), - depositing the material (16') of the patterned layer (16) on the growth substrate layer (10) in the areas where the resist mask (11) has been removed, and - removing the dielectric material (17), wherein the at least one opening (12) is formed.