Array substrate, display panel and display panel motherboard

Abstract

This application relates to an array substrate, a display panel, and a display panel motherboard. The array substrate includes a substrate, scan lines, a gate driving circuit, gate test pads, and intermediate redundant gate test pads. The substrate has a display area and a non-display area. The non-display area surrounds the display area and includes a bonding area. In a first direction, the bonding area is located on one side of the display area. The bonding area includes two outer bonding areas and a middle bonding area. In a second direction, the middle bonding area is located between the two outer bonding areas. The first direction intersects the second direction. The scan lines are located on the substrate of the display area. The gate driving circuit is connected to the scan lines. The gate test pads are located in the non-display area and adjacent to at least one outer bonding area, and are connected to the gate driving circuit. The intermediate redundant gate test pads are located in the non-display area and adjacent to the intermediate bonding area, and are insulated from the gate driving circuit. This array substrate design can reduce the number of photomask exposures during the manufacturing of the array substrate and the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display panel motherboard. Background Technology

[0002] With the development of the TV panel industry and market demand, the industry is continuously trending towards larger sizes. For large-size TV panels, due to limitations in mask size, a splicing method is required to complete the exposure process. Therefore, a significant amount of exposure capacity is needed to support the production of large-size panels. Summary of the Invention

[0003] This application provides an array substrate, a display panel, and a display panel motherboard, which helps to reduce the number of exposures of the photomask during the manufacturing process of the array substrate and the display panel, thereby at least partially solving the above-mentioned technical problems.

[0004] To achieve the above objectives, according to a first aspect of this application, an array substrate is provided, comprising:

[0005] A substrate has a display area and a non-display area, the non-display area being disposed around the display area and including a bonding area, the bonding area being located on one side of the display area in a first direction, the bonding area including two outer bonding areas and a middle bonding area, the middle bonding area being located between the two outer bonding areas in a second direction, the first direction intersecting the second direction;

[0006] Scan lines are located on the substrate of the display area;

[0007] A gate driving circuit is located on the substrate and connected to the scan line;

[0008] A gate test pad is located on the substrate in the non-display area and is adjacent to at least one of the outer bonding areas, and is connected to the gate drive circuit.

[0009] An intermediate redundant gate test pad is located on the substrate in the non-display area and adjacent to the intermediate bonding area, and is insulated from the gate drive circuit.

[0010] According to a second aspect of this application, an embodiment of this application provides a display panel, the display panel including the array substrate described above.

[0011] According to a third aspect of this application, embodiments of this application provide a display panel motherboard, comprising:

[0012] The motherboard has multiple panel areas, each panel area including a display area and a non-display area. The non-display area is arranged around the display area and includes a binding area. In a first direction, the binding area is located on one side of the display area. The binding area includes two outer binding areas and a middle binding area. In a second direction, the middle binding area is located between the two outer binding areas. The second direction intersects with the first direction.

[0013] Scan lines are located on the motherboard of the display area;

[0014] A gate driving circuit is located on the motherboard and connected to the scan line;

[0015] A gate test pad is located on the motherboard of the non-display area and is adjacent to at least one of the outer bonding areas, and is connected to the gate drive circuit.

[0016] The intermediate redundant gate test pad is located on the motherboard of the non-display area and adjacent to the intermediate bonding area, and is insulated from the gate drive circuit.

[0017] In some embodiments of the array substrate, display panel, and display panel motherboard of this application, when gate test pads are provided around the outer bonding region, intermediate redundant gate test pads are added around the middle bonding region. Thus, the pattern around the middle bonding region is similar to the pattern around the outer bonding region. The patterns around the outer bonding region and the pattern around the middle bonding region can be prepared by splicing photomasks, reducing the number of photomask exposures during the manufacturing of the array substrate and display panel. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the planar structure of the array substrate provided in an exemplary embodiment of this application;

[0019] Figure 2 This is provided in an exemplary embodiment of this application. Figure 1 A partially enlarged schematic diagram of an outer bonding region and its surrounding area on the array substrate shown.

[0020] Figure 3 This is provided in an exemplary embodiment of this application. Figure 1 A magnified schematic diagram of the central bonding area and its surrounding area on the array substrate shown.

[0021] Figure 4 The exemplary embodiments provided in this application are along Figure 3 A schematic diagram of the cross-sectional structure intercepted by the tangent line A-A' shown;

[0022] Figure 5 This is provided in an exemplary embodiment of this application. Figure 1A partially enlarged schematic diagram of another outer bonding area and its surroundings on the array substrate shown.

[0023] Figure 6 The manufacturing process provided in the exemplary embodiments of this application Figure 1 A schematic diagram of the process of the array substrate shown;

[0024] Figure 7 This is a schematic diagram of the planar structure of the display panel provided in an exemplary embodiment of this application;

[0025] Figure 8 This is a schematic diagram of the planar structure of the display panel motherboard provided in an exemplary embodiment of this application;

[0026] Figure 9 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shows a partially enlarged view of the outer bonding area and its surroundings of the display panel motherboard.

[0027] Figure 10 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shows a partially enlarged view of the central binding area and its surroundings of the display panel motherboard.

[0028] Figure 11 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shows another enlarged view of the central binding area and its surroundings of the display panel motherboard.

[0029] Explanation of reference numerals in the attached figures:

[0030] 100, Array substrate; 200, Display panel; 300, Display panel motherboard;

[0031] 11. Substrate; 111. Motherboard; 111A. Panel area; 11A. Display area; 11B. Non-display area; 11C. Bonding area; 11C1. Outer bonding area; 11C2. Middle bonding area;

[0032] 20. Scan lines;

[0033] 211. Gate test pad; 212. First gate test pad; 213. Second gate test pad; 214. Intermediate redundant gate test pad; 215. First outer redundant gate test pad; 216. Second outer redundant gate test pad;

[0034] 220. Gate test line; 221. First gate test section; 222. Second gate test section;

[0035] 223. Intermediate redundant gate test line; 224. First redundant gate test segment; 225. Second redundant gate test segment; 226. First outer redundant gate test line; 227. Second outer redundant gate test line;

[0036] 241. First gate array test pad; 242. Second gate array test pad; 243. Third gate array test pad;

[0037] 251. First connection trace; 252. Second connection trace; 253. Third connection trace; 254. Fourth connection trace; 255. Fifth connection trace;

[0038] 26. External wiring;

[0039] 30. Data cable;

[0040] 31. Data short circuit trace; 311. First data short circuit segment; 312. Second data short circuit segment;

[0041] 32. Data test pad;

[0042] 331. First data array test pad; 332. Second data array test pad;

[0043] 34. Data array test connection cable;

[0044] M1, first conductive layer; M2, second conductive layer;

[0045] 41. Gate driving circuit; 51. Pixel driving circuit; 52. Pixel electrode;

[0046] 61. First outer binding pad; 62. Second outer binding pad; 63. First intermediate binding pad; 64. Second intermediate binding pad; 65. Third outer binding pad;

[0047] 71. Drive unit;

[0048] S1, First mask template; S2, Second mask template; Q1, First cutting line; Q2, Second cutting line; Q3, Third cutting line;

[0049] X, the first direction; Y, the second direction. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0051] Figure 1 This is a schematic diagram of the planar structure of the array substrate provided in an exemplary embodiment of this application. Figure 2 This is provided in an exemplary embodiment of this application. Figure 1 A magnified schematic diagram of an outer bonding area and its surroundings on the array substrate shown. Figure 3 This is provided in an exemplary embodiment of this application. Figure 1 A magnified schematic diagram of the central bonding area and its surroundings of the array substrate shown. Figure 4 The example embodiments provided in this application are along Figure 3 The diagram shows a cross-sectional structure taken by the tangent line A-A'. Figure 5 This is provided in an exemplary embodiment of this application. Figure 1 A partially enlarged schematic diagram of another outer bonding area of ​​the array substrate and its surroundings.

[0052] like Figures 1 to 5 As shown, the array substrate 100 includes a substrate 11, a gate driving circuit 41, a gate test pad 211, and an intermediate redundant gate test pad 214.

[0053] like Figure 1 As shown, substrate 11 has a display area 11A and a non-display area 11B. The non-display area 11B is disposed around the display area 11A. Substrate 11 may include a flexible substrate or a rigid substrate. Flexible substrates include organic materials. Rigid substrates include rigid materials such as glass.

[0054] like Figures 1 to 3 as well as Figure 5 As shown, the display area 11A is provided with multiple signal lines. These signal lines include multiple data lines 30 extending along a first direction X and arranged along a second direction Y, and multiple scan lines 20 extending along the second direction Y and arranged along the first direction X. The first direction X and the second direction Y intersect.

[0055] The first direction X is perpendicular to the second direction Y, but is not limited to this. It can be understood that the angle between the first direction X and the second direction Y can be acute or obtuse.

[0056] like Figure 1 As shown, in some embodiments, the display area 11A is further provided with a pixel driving circuit 51. The pixel driving circuit 51 is connected to the data line 30 and the scan line 20. In some embodiments, the display area 11A is further provided with a pixel electrode 52 of the liquid crystal display element. The pixel driving circuit 51 is connected to the pixel electrode 52 of the liquid crystal display element, and the pixel driving circuit 51 includes a thin-film transistor. In other embodiments, the pixel driving circuit 51 may be connected to an organic light-emitting diode.

[0057] like Figure 1As shown, the non-display area 11B includes a bonding area 11C, which is provided with bonding pads for bonding driving units. In the first direction X, the bonding area 11C is located on one side of the display area 11A. The bonding area 11C includes two outer bonding areas 11C1 and a middle bonding area 11C2. In the second direction Y, the middle bonding area 11C2 is located between the two outer bonding areas 11C1. In other words, the two outer bonding areas 11C1 are located at the edges of the bonding area 11C in the second direction Y. Exemplarily, a plurality of middle bonding areas 11C2 are located between the two outer bonding areas 11C1.

[0058] A gate driving circuit 41 is located on the substrate 11. The gate driving circuit 41 is connected to multiple scan lines 20 to output valid and invalid scan signals to the scan lines 20. When each scan line 20 receives a high-level valid scan signal, the pixel driving circuit 51 connected to that scan line 20 can receive the data signal transmitted by the data line 30. When each scan line 20 receives a low-level invalid scan signal, the pixel driving circuit 51 connected to that scan line 20 may not be able to receive the data signal transmitted by the data line 30.

[0059] In some embodiments, the gate driving circuit 41 can be integrated on the substrate 11, i.e., formed on the substrate 11 by the manufacturing process of the display panel 200. In other embodiments, the gate driving circuit 41 can also be a gate driving chip, which is bonded to the substrate 11. In still other embodiments, the gate driving circuit 41 can also be disposed on a flexible base film, which is bonded to the substrate 11.

[0060] In some embodiments, the gate driving circuit 41 is located in the non-display area 11B and at least on one side of the display area 11A in the second direction Y. In one exemplary embodiment, as Figure 1 , Figure 2 as well as Figure 5 As shown, in the second direction Y, the two gate driving circuits 41 are located on opposite sides of the display area 11A, i.e., dual-sided driving scan line 20. In another exemplary embodiment, a single gate driving circuit 41 may be located on one side of the display area 11A, i.e., single-sided driving scan line 20.

[0061] In other embodiments, when the gate driving circuit 41 is formed on the substrate 11 by the manufacturing process of the display panel, at least a portion of the gate driving circuit 41 may be located in the display area 11A to reduce the bezel of the array substrate 100.

[0062] like Figure 2 and Figure 5As shown, the gate test pad 211 is located on the substrate 11 of the non-display area 11B. The gate test pad 211 is adjacent to at least one outer bonding area 11C1 and connected to the gate driving circuit 41. A gate test signal is applied to the gate test pad 211, and the gate test signal is transmitted to the gate driving circuit 41, causing the gate driving circuit 41 to output valid scan signals and invalid scan signals to multiple scan lines 20. In this way, the detection of the displayed image can be realized during the testing phase of the display panel 200.

[0063] In one exemplary embodiment, such as Figure 1 , Figure 2 as well as Figure 5 As shown, in the second direction Y, with the two gate driving circuits 41 located on opposite sides of the display area 11A, the plurality of gate test pads 211 include a first gate test pad 212 and a second gate test pad 213. The first gate test pad 212 is located on the side of an outer bonding area 11C1 facing away from the middle bonding area 11C2 in the second direction Y, and is connected to one gate driving circuit 41. The second gate test pad 213 is located on the side of another outer bonding area 11C1 facing away from the middle bonding area 11C2 in the second direction Y, and is connected to another gate driving circuit 41. Thus, during the testing phase of the display panel, gate test signals are applied to the first gate test pad 212 and the second gate test pad 213 respectively to facilitate the detection of the display image.

[0064] In some embodiments, there are multiple first gate test pads 212 and multiple second gate test pads 213. The number of first gate test pads 212 and the number of second gate test pads 213 are the same. Multiple first gate test pads 212 are spaced apart along the second direction Y and are located on the side of an outer bonding region 11C1 opposite to the middle bonding region 11C2, and are connected to a gate drive circuit 41. Multiple second gate test pads 213 are spaced apart along the second direction Y and are located on the side of another outer bonding region 11C1 opposite to the middle bonding region 11C2, and are connected to another gate drive circuit 41. The multiple first gate test pads 212 and multiple second gate test pads 213 can be loaded with various different input signals from the gate drive circuit 41, such as clock signals and DC signals.

[0065] like Figure 3As shown, the intermediate redundant gate test pad 214 is located in the non-display area 11B. The intermediate redundant gate test pad 214 is adjacent to the intermediate bonding area 11C2 and is insulated from the gate drive circuit 41. Thus, with the gate test pad 211 disposed around the outer bonding area 11C1, the intermediate redundant gate test pad 214 is added around the intermediate bonding area 11C2. The pattern around the intermediate bonding area 11C2 is similar to the pattern around the outer bonding area 11C1. The pattern around the outer bonding area 11C1 and the pattern around the intermediate bonding area 11C2 can be prepared by splicing photomasks, that is, the pattern around the outer bonding area 11C1 is prepared by splicing photomasks, saving photomask space, reducing the number of photomask exposures during the fabrication of the array substrate 100, and supporting the splicing of photomasks in different repeated exposure areas.

[0066] In some embodiments, at least one intermediate redundant gate test pad 214 is the same as the gate test pad 211, so that the intermediate redundant gate test pad 214 and the gate test pad 211 are formed in the same exposure process. The pattern around the outer bonding region 11C1 and the pattern around the intermediate bonding region 11C2 can be formed by splicing multiple photomasks.

[0067] In some embodiments, the shape of the intermediate redundant gate test pad 214 is the same as the shape of at least one gate test pad 211. Thus, the gate test pad 211 and the intermediate redundant gate test pad 214 tend to be the same.

[0068] In some embodiments, when the shape of the intermediate redundant gate test pad 214 is the same as the shape of at least one gate test pad 211, the area of ​​the intermediate redundant gate test pad 214 is equal to the area of ​​at least one gate test pad 211. This makes it advantageous for the intermediate redundant gate test pad 214 to be identical to the gate test pad 211.

[0069] In some embodiments, the shape of the gate test pad 211 and the shape of the intermediate redundant gate test pad 214 are both at least one of rectangle and trapezoid, but are not limited thereto. Exemplarily, the shape of the gate test pad 211 and the shape of the intermediate redundant gate test pad 214 are both rectangles.

[0070] The relative position between the gate test pad 211 and the outer bonding region 11C1 is the same as the relative position between the intermediate redundant gate test pad 214 and the intermediate bonding region 11C2. For example, the distance between the gate test pad 211 and the outer bonding region 11C1 is equal to the distance between the intermediate redundant gate test pad 214 and the intermediate bonding region 11C2.

[0071] In some embodiments, such as Figure 1 , Figure 2 as well as Figure 5As shown, when the two gate driving circuits 41 are located on opposite sides of the display area 11A, and the multiple gate test pads 211 include the first gate test pad 212 and the second gate test pad 213, the array substrate 100 also includes the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216.

[0072] like Figure 2 As shown, the first outer redundant gate test pad 215 is adjacent to an outer bonding region 11C1, and in the second direction Y, an outer bonding region 11C1 is located between the first outer redundant gate test pad 215 and the first gate test pad 212. Figure 5 As shown, the second outer redundant gate test pad 216 is adjacent to another outer bonding region 11C1, and in the second direction Y, the other outer bonding region 11C1 is located between the second outer redundant gate test pad 216 and the second gate test pad 213. Figure 3 As shown, intermediate redundant gate test pads 214 are provided on both sides of each intermediate binding region 11C2.

[0073] With the two gate driving circuits 41 located on opposite sides of the display area 11A, and the multiple gate test pads 211 including a first gate test pad 212 and a second gate test pad 213, a first outer redundant gate test pad 215 is added to the side of one outer bonding area 11C1 away from the first gate test pad 212, and a second outer redundant gate test pad 216 is added to the side of another outer bonding area 11C1 away from the second gate test pad 213. Furthermore, intermediate redundant gate test pads 214 are added to both sides of each intermediate bonding area 11C2. The patterns around the two outer bonding areas 11C1 and the patterns around each intermediate bonding area 11C2 are the same or nearly the same, and can be formed by splicing multiple photomasks.

[0074] In some embodiments, the first gate test pad 212, the second gate test pad 213, the intermediate redundant gate test pad 214, the first outer redundant gate test pad 215, and the second outer redundant gate test pad 216 are the same.

[0075] Figure 6 The manufacturing process provided in the exemplary embodiments of this application Figure 1 The diagram shows the process of the array substrate.

[0076] When a gate test pad 211 is placed around the outer bonding region 11C1, but not around the middle bonding region 11C2, the pattern around the outer bonding region 11C1 differs from the pattern around the middle bonding region 11C2. The pattern around the outer bonding region 11C1 requires a separate mask and exposure process, and cannot be fabricated using the same mask as the pattern around the middle bonding region 11C2. This makes it difficult to fabricate the pattern around the outer bonding region 11C1 using a combined mask.

[0077] like Figure 2 , Figure 3 as well as Figure 5 As shown, an intermediate redundant gate test pad 214 is added around the intermediate bonding region 11C2, which helps the pattern around the intermediate bonding region 11C2 to be similar to the pattern around the outer bonding region 11C1, and the two can be formed in the exposure process of a single mask. The pattern around the outer bonding region 11C1 and the pattern around the intermediate bonding region 11C2 can be formed by splicing multiple masks, reducing the number of mask exposures.

[0078] Specifically, such as Figure 6 As shown, when the first mask S1 and the second mask S2 are spliced ​​together, the overlapping area between the first mask S1 and the second mask S2 is the repeated exposure area H. In order to ensure that the pattern located in the repeated exposure area H is similar to the pattern around the outer binding area 11C1, the pattern around the middle binding area 11C2 located in the repeated exposure area H is controlled to be similar to or similar to the pattern around the outer binding area 11C1.

[0079] In some embodiments, N1 gate test pads 211 are located on at least one side of each of at least one outer bonding region 11C1 in the second direction Y and are adjacent to each of at least one outer bonding region 11C1, where N1 is an integer greater than or equal to 1. N2 intermediate redundant gate test pads 214 are located on at least one side of an intermediate bonding region 11C2 in the second direction Y and are adjacent to an intermediate bonding region 11C2, where N2 is an integer greater than or equal to 1 and N2 is less than or equal to N1. Thus, it is advantageous that the pattern and its number around the intermediate bonding region 11C2 tend to be the same as the pattern and its number around the outer bonding region 11C1.

[0080] In one exemplary embodiment, the number of first gate test pads 212 and the number of second gate test pads 213 are the same as the number of intermediate redundant gate test pads 214, the number of first outer redundant gate test pads 215 and the number of second outer redundant gate test pads 216 on each side of the intermediate bonding region 11C2 in the second direction.

[0081] In another exemplary embodiment, the number of first gate test pads 212 is the same as the number of second gate test pads 213. The number of intermediate redundant gate test pads 214, the number of first outer redundant gate test pads 215, and the number of second outer redundant gate test pads 216 on each side of the intermediate bonding region 11C2 in the second direction are the same. The number of first gate test pads 212 is greater than the number of intermediate redundant gate test pads 214 on each side of the intermediate bonding region 11C2 in the second direction.

[0082] It should be noted that when intermediate redundant gate test pads 214 are added around the intermediate bonding region 11C2, the number of intermediate redundant gate test pads 214 on each side of the intermediate bonding region 11C2 in the second direction Y depends on the number of intermediate redundant gate test pads 214 in the repeated exposure region.

[0083] In some embodiments, such as Figure 4 As shown, the gate test pad 211 and the intermediate redundant gate test pad 214 are located in the first conductive layer M1. Thus, when the first conductive layer M1 is formed using an exposure process with multiple spliced ​​photomasks, the gate test pad 211 and the intermediate redundant gate test pad 214 are formed.

[0084] In some embodiments, the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216 are also located in the first conductive layer M1.

[0085] In some embodiments, the first conductive layer M1 may further include multiple data lines 30. Therefore, the gate test pad 211 and the intermediate redundant gate test pad 214 are located on the same layer as the multiple data lines 30.

[0086] In some embodiments, the first conductive layer M1 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0087] In some embodiments, such as Figure 2 , Figure 3 as well as Figure 5As shown, the array substrate 100 further includes a first outer bonding pad 61, a first intermediate bonding pad 63, a gate test line 220, and an intermediate redundant gate test line 223. The first outer bonding pad 61 is located on the substrate 11 of at least one outer bonding region 11C1 and is connected to the gate driving circuit 41. The first intermediate bonding pad 63 is located in the intermediate bonding region 11C2. The gate test line 220 is adjacent to at least one outer bonding region 11C1 and is connected to the first outer bonding pad 61 and the gate test pad 211. The intermediate redundant gate test line 223 is adjacent to the intermediate bonding region 11C2 and is insulated from at least one of the first intermediate bonding pad 63 and the intermediate redundant gate test pad 214. Thus, when the gate test pad 211 is connected to the first outer bonding pad 61 through the gate test line 220 around the outer bonding region 11C1, the additional intermediate redundant gate test line 223 around the intermediate bonding region 11C2 further makes the pattern around the intermediate bonding region 11C2 more similar to the pattern around the outer bonding region 11C1.

[0088] In some embodiments, such as Figure 2 and Figure 5 As shown, the array substrate 100 also includes a peripheral trace 26 located in the non-display area 11B, which connects the first outer bonding pad 61 and the gate driving circuit 41. Thus, the gate test pad 211 is connected to the gate driving circuit 41 through the gate test line 220, the first outer bonding pad 61, and the peripheral trace 26.

[0089] In some embodiments, such as Figure 3 As shown, the intermediate redundant gate test line 223 is connected to the first intermediate bonding pad 63 and is insulated from the intermediate redundant gate test pad 214. This reduces the risk of the redundant gate test pad 211 interfering with the display process of the display panel, including the array substrate.

[0090] In other embodiments, the intermediate redundant gate test line 223 is insulated from the first intermediate bonding pad 63 and connected to the intermediate redundant gate test pad 214. In still other embodiments, the intermediate redundant gate test line 223 is insulated from both the first intermediate bonding pad 63 and the intermediate redundant gate test pad 214.

[0091] It should be noted that the insulation between the intermediate redundant gate test line 223 and either the first intermediate bonding pad 63 or the intermediate redundant gate test pad 214 means that the intermediate redundant gate test line 223 is not connected to either the first intermediate bonding pad 63 or the intermediate redundant gate test pad 214. The intermediate redundant gate test line 223 can be disconnected using a laser, thus preventing it from being connected to either the first intermediate bonding pad 63 or the intermediate redundant gate test pad 214.

[0092] In some embodiments, the first intermediate bonding pad 63 may be connected to a common electrode block (not shown in the figure).

[0093] In some embodiments, at least a portion of the intermediate redundant gate test line 223 and at least a portion of the gate test line 220 are non-linear. This improves the layout flexibility of the intermediate redundant gate test line 223 and the gate test line 220 and reduces the risk of short circuits between them and other structures.

[0094] In some embodiments, the intermediate redundant gate test line 223 is identical to at least a portion of the gate test line 220. Thus, the pattern around the intermediate bonding region 11C2 is identical to or nearly identical to the pattern around the outer bonding region 11C1.

[0095] In some embodiments, such as Figure 2 and Figure 3 As shown, gate test line 220 includes a first gate test segment 221. Intermediate redundant gate test line 223 includes a first redundant gate test segment 224. The first gate test segment 221 is adjacent to the outer bonding region 11C1 and connected to the first outer bonding pad 61. The first redundant gate test segment 224 is adjacent to the intermediate bonding region 11C2 and connected to the first intermediate bonding pad 63. The first gate test segment 221 and the first redundant gate test segment 224 are identical. Thus, the portion of the intermediate redundant gate test line 223 connected to the first intermediate bonding pad 63 is the same as the portion of the gate test line 220 connected to the first outer bonding pad 61.

[0096] In some embodiments, the first gate test segment 221 and the first redundant gate test segment 224 are in a zigzag shape. In other embodiments, the first gate test segment 221 and the first redundant gate test segment 224 may also be in a straight line shape.

[0097] In some embodiments, such as Figure 2 As shown, the gate test line 220 also includes a second gate test segment 222. The second gate test segment 222 is connected between the first gate test segment 221 and the gate test pad 211.

[0098] In some embodiments, such as Figure 2 As shown, at least a portion of the first gate test segment 221 and at least a portion of the second gate test segment 222 both extend along the second direction Y and are offset in the first direction X, so that the first gate test segment 221 is connected to the first outer bonding pad 61 and the second gate test segment 222 is connected to the gate test pad 211.

[0099] In some embodiments, such as Figure 3As shown, the intermediate redundant gate test line 223 includes a second redundant gate test segment 225. The second redundant gate test segment 225 is connected to the intermediate redundant gate test pad 214 and disconnected from the first redundant gate test segment 224.

[0100] In some embodiments, such as Figure 4 As shown, with the gate test pad 211 located in the first conductive layer M1, the intermediate redundant gate test line 223 and the gate test line 220 are located in the second conductive layer M2. The second conductive layer M2 is located between the first conductive layer M1 and the substrate 11. Thus, the gate test line 220 and the gate test pad 211 are located in different conductive layers, improving the layout flexibility of the intermediate gate test line 220 and the gate test pad 211. Furthermore, the intermediate redundant gate test line 223 and the gate test line 220 are formed when the second conductive layer M2 is formed using an exposure process with multiple spliced ​​photomasks.

[0101] In some embodiments, the second conductive layer M2 further includes a plurality of scan lines 20. The plurality of scan lines 20 are located in the same layer as the intermediate redundant gate test line 223 and the gate test line 220. In some embodiments, the second conductive layer M2 includes at least one of molybdenum, aluminum, titanium, copper, and silver.

[0102] In some embodiments, such as Figure 2 and Figure 5 As shown, when the array substrate 100 includes a first outer redundant gate test pad 215 and a second outer redundant gate test pad 216, the array substrate 100 may also include a first outer redundant gate test line 226, a second outer redundant gate test line 227 and a third outer bonding pad 65.

[0103] The first outer redundant gate test line 226 is adjacent to an outer bonding region 11C1. In the second direction Y, at least a portion of the first outer redundant gate test line 226 and at least a portion of the gate test line 220 are located on the opposite side of the outer bonding region 11C1. The first outer redundant gate test line 226 is insulated from at least one of the third outer bonding pad 65 and the first outer redundant gate test pad 215 located in the outer bonding region 11C1. In an exemplary embodiment, the first outer redundant gate test line 226 is connected to the third outer bonding pad 65 located in the outer bonding region 11C1, but not connected to the first outer redundant gate test pad 215.

[0104] The second outer redundant gate test line 227 is adjacent to another outer bonding region 11C1. In the second direction Y, at least a portion of the second outer redundant gate test line 227 and at least a portion of the gate test line are located on the opposite side of the other outer bonding region 11C1. The second outer redundant gate test line 227 is insulated from at least one of the third outer bonding pad 65 and the second outer redundant gate test pad 216 located in the other outer bonding region 11C1. In an exemplary embodiment, the second outer redundant gate test line 227 is connected to the third outer bonding pad 65 located in the other outer bonding region 11C1, but not connected to the second outer redundant gate test pad 216.

[0105] In some embodiments, the first outer redundant gate test line 226 and the second outer redundant gate test line 227 are the same as the intermediate redundant gate test line.

[0106] In some embodiments, reference Figure 2 , Figure 3 as well as Figure 5 As shown, the array substrate 100 also includes a second outer bonding pad 62, a second intermediate bonding pad 64, and a data short-circuit trace 31. The second outer bonding pad 62 is located in the outer bonding region 11C1 and is connected to the data line 30. The second intermediate bonding pad 64 is located in the intermediate bonding region 11C2 and is connected to the data line 30. The data short-circuit trace 31 is connected to the second outer bonding pad 62 and the second intermediate bonding pad 64. The orthographic projection of the data short-circuit trace 31 on the substrate 11 is offset from the orthographic projections of the gate test pad 211 and the intermediate redundant gate test pad 214 on the substrate 11. This reduces the risk of short circuits between the data short-circuit trace 31 and the gate test pad 211 and the intermediate redundant gate test pad 214.

[0107] In some embodiments, when the array substrate 100 further includes a first outer redundant gate test pad 215 and a second outer redundant gate test pad 216, the orthogonal projection of the data short-circuit trace 31 on the substrate 11 is offset from the orthogonal projections of the first outer redundant gate test pad 215 and the second outer redundant gate test pad 216 on the substrate 11.

[0108] In some embodiments, such as Figure 2 , Figure 3 as well as Figure 5 As shown, at least a portion of the data short-circuit trace 31 is non-linear. This increases the flexibility of the data short-circuit trace 31's layout and helps it avoid the gate test pad 211 and the intermediate redundant gate test pad 214.

[0109] In some embodiments, such as Figure 2 , Figure 3 as well as Figure 5As shown, the data short-circuit trace 31 includes multiple first data short-circuit segments 311. These multiple first data short-circuit segments 311 are adjacent to and staggered from the gate test pad 211 and the intermediate redundant gate test pad 214, respectively. Thus, at least a portion of the data short-circuit trace 31 is staggered from the gate test pad 211 and the intermediate redundant gate test pad 214.

[0110] In some embodiments, multiple first data short circuit segments 311 extend along the second direction Y and are adjacent to and staggered from the gate test pad 211 and the intermediate redundant gate test pad 214 in the first direction X, respectively.

[0111] In some embodiments, the data short-circuit trace 31 further includes multiple second data short-circuit segments 312. The multiple second data short-circuit segments 312 are adjacent to the outer bonding region 11C1 and the intermediate bonding region 11C2, respectively, and are connected to the second outer bonding pad 62, the second intermediate bonding pad 64, and the multiple first data short-circuit segments 311. The multiple second data short-circuit segments 312 are staggered from the multiple first data short-circuit segments 311. Thus, the data short-circuit trace 31 adopts a non-linear segmented structure to avoid the gate test pad 211 and the intermediate redundant gate test pad 214, and is also connected to multiple data lines 30 through the second outer bonding pad 62 and the second intermediate bonding pad 64.

[0112] In some embodiments, the plurality of second data short-circuit segments 312 may be in a polygonal shape. Each second data short-circuit segment 312 includes interconnected data short-circuit straight segments and data short-circuit inclined segments. The data short-circuit straight segments extend along the second direction Y and are connected to the second outer bonding pad 62 and the second intermediate bonding pad 64, and are offset from the first data short-circuit segment 311 in the first direction X. The data short-circuit inclined segments connect the first data short-circuit segment 311 and the data short-circuit straight segments. The extension direction of the data short-circuit straight segments intersects the first direction X and the second direction Y.

[0113] In some embodiments, the data short-circuit trace 31, the redundant gate test pad 211, and the gate test pad 211 are located in the first conductive layer M1. Thus, the data short-circuit trace 31, the redundant gate test pad 211, and the gate test pad 211 can be formed simultaneously, simplifying the manufacturing process of the array substrate 100. Furthermore, when the orthographic projection of the data short-circuit trace 31 on the substrate 11 is misaligned with the orthographic projections of the gate test pad 211 and the intermediate redundant gate test pad 214 on the substrate 11, the interference problem caused by mask splicing between the data short-circuit trace 31, the gate test pad 211, and the intermediate redundant gate test pad 214 is mitigated.

[0114] In some embodiments, such as Figure 2 , Figure 3 as well as Figure 5As shown, the array substrate 100 also includes a data test pad 32. The data test pad 32 is connected to the data short-circuit trace 31. Thus, by applying a data test signal to the data test pad 32, the data test signal can be transmitted to multiple data lines 30 through the data short-circuit trace 31 to realize the detection of the image during the testing phase of the display panel.

[0115] In some embodiments, a plurality of data test pads 32 are adjacent to two outer binding regions 11C1 and a plurality of intermediate binding regions 11C2, respectively.

[0116] In some embodiments, such as Figure 2 and Figure 5 As shown, when the array substrate 100 also includes a gate test line 220, and the gate test line 220 and the data short-circuit trace 31 are located in different conductive layers, at least a portion of the orthographic projection of the gate test line 220 on the substrate 11 is misaligned with the orthographic projection of the data short-circuit trace 31 on the substrate 11. For example, the second data short-circuit segment 312 is misaligned with the first gate test segment 221. This reduces the overlap area between the gate test line 220 and the data short-circuit trace 31 located in different layers, mitigating the risk of damage to insulating layers such as the planarization layer on the array substrate 100 due to a large overlap area.

[0117] In some embodiments, such as Figure 3 As shown, when the array substrate 100 also includes an intermediate redundant gate test line 223, the intermediate redundant gate test line 223 and the data short-circuit trace 31 are located in different conductive layers. At least a portion of the orthographic projection of the intermediate redundant gate test line 223 onto the substrate 11 is offset from the orthographic projection of the data short-circuit trace 31 onto the substrate 11; for example, the second data short-circuit segment 312 is offset from the first redundant gate test segment 224. This reduces the overlap area between the intermediate redundant gate test line 223 and the data short-circuit trace 31 located in different layers, mitigating the risk of damage to insulating layers such as the planarization layer on the array substrate 100 due to a large overlap area.

[0118] In some embodiments, such as Figure 2 , Figure 3 as well as Figure 5 As shown, the intermediate redundant gate test line 223 and gate test line 220 overlap with the data short-circuit trace 31. In this way, the space occupied by the intermediate redundant gate test line 223, gate test line 220 and data short-circuit trace 31 in the non-display area 11B is reduced, ensuring that the display panel 200 including the array substrate 100 achieves a narrow bezel.

[0119] In some embodiments, the area of ​​overlap between the gate test line 220 and the data short-circuit trace 31 is greater than the area of ​​overlap between the intermediate redundant gate test line 223 and the data short-circuit trace 31. This accommodates situations where the intermediate redundant gate test line 223 is connected to the first intermediate bonding pad 63 and not connected to the intermediate redundant gate test pad 214.

[0120] Figure 7 This is a schematic diagram of the planar structure of the display panel provided in an exemplary embodiment of this application.

[0121] Based on the same inventive concept, and referring to Figure 7 As shown, this application also provides a display panel 200, which is an array substrate 100 of any of the above embodiments.

[0122] In some embodiments, such as Figure 7 As shown, the display panel 200 also includes a plurality of driving units 71. The plurality of driving units 71 are respectively bound to two outer binding areas 11C1 and a middle binding area 11C2.

[0123] In some embodiments, the driving unit 71 may be a driving chip. In other embodiments, the driving unit 71 may include a flexible thin film and a driving chip located on the flexible thin film, that is, the driving unit 71 is a flip-chip film.

[0124] In some embodiments, the display panel 200 may further include an opposing substrate 11 and a liquid crystal layer. The opposing substrate 11 is disposed opposite to the array substrate 100, and a liquid crystal layer is disposed between the opposing substrate 11 and the array substrate 100.

[0125] Figure 8 This is a schematic diagram of the planar structure of the display panel motherboard provided in an exemplary embodiment of this application. Figure 9 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shows a partially enlarged view of the outer bonding area and its surroundings of the display panel motherboard. Figure 10 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shows a magnified view of the central binding area and its surroundings of the display panel motherboard. Figure 11 This is provided in an exemplary embodiment of this application. Figure 8 The diagram shown is another enlarged view of the central binding area and its surroundings of the display panel motherboard.

[0126] Reference Figures 8 to 11 As shown, this application embodiment also provides a display panel motherboard 300. Along Figure 9 and Figure 10 Cut along the first cutting line Q1, or along... Figure 11The display panel 200 is obtained by cutting with the second cutting line Q2 and the third cutting line Q3. The display panel 200 includes the array substrate 100.

[0127] The display panel motherboard 300 includes a motherboard 111, a gate drive circuit 41, a gate test pad 211, and an intermediate redundant gate test pad 214.

[0128] The motherboard 111 has multiple panel areas 111A. Each panel area 111A includes a display area 11A and a non-display area 11B. The non-display area 11B is disposed around the display area 11A and includes a bonding area 11C. In a first direction X, the bonding area 11C is located on one side of the display area 11A. The bonding area 11C includes two outer bonding areas 11C1 and a middle bonding area 11C2. In a second direction Y, the middle bonding area 11C2 is located between the two outer bonding areas 11C1, and the second direction Y intersects the first direction X. A scan line 20 is located on the motherboard 111 of the display area 11A. A gate drive circuit 41 is located on the motherboard 111. A gate test pad 211 is located in the non-display area 11B, adjacent to at least one outer bonding area 11C1 in the second direction Y, and connected to the gate drive circuit 41. An intermediate redundant gate test pad 214 is located in the non-display area 11B, adjacent to the intermediate bonding area 11C2, and insulated from the gate drive circuit 41.

[0129] In some embodiments of the display panel motherboard 300 of this application, when gate test pads 211 are provided around the outer bonding region 11C1, intermediate redundant gate test pads 214 are added around the middle bonding region 11C2. Thus, the pattern around the middle bonding region 11C2 is similar to the pattern around the outer bonding region 11C1. The patterns around the outer bonding region 11C1 and the middle bonding region 11C2 can be obtained by splicing a mask, reducing the number of exposures of the mask during the manufacturing of the display panel 200 template.

[0130] Since the display panel motherboard 300 is cut to obtain the display panel 200 including the array substrate 100 mentioned above, the relevant content of the array substrate 100 also applies to the display panel 200 motherboard, and will not be repeated here.

[0131] In some embodiments, such as Figure 9 and Figure 10As shown, the display panel motherboard 300 also includes a first gate array test pad 241 and a second gate array test pad 242. The first gate array test pad 241 is located in the non-display area 11B and is adjacent to the outer bonding area 11C1, and is connected to the gate drive circuit 41. The second gate array test pad 242 is located in the non-display area 11B and is adjacent to the middle bonding area 11C2. Thus, with the first gate array test pad 241 disposed around the outer bonding area 11C1, the second gate array test pad 242 is also added around the middle bonding area 11C2, making the pattern around the middle bonding area 11C2 similar to the pattern around the outer bonding area 11C1.

[0132] During the testing of the array substrate 100, a gate array test signal is applied to the first gate array test pad 241 to test the gate drive circuit 41.

[0133] In some embodiments, the second gate array test pad 242 is insulated from the gate driving circuit 41. When the second gate array test pad 242 is insulated from the gate driving circuit 41, the second gate array test pad 242 is not connected to the gate driving circuit 41. When the second gate array test pad 242 is insulated from the gate driving circuit 41, no gate array test signal is applied to the second gate array test pad 242 during the testing of the array substrate 100.

[0134] In some embodiments, the first gate array test pad 241 is the same as the second gate array test pad 242, that is, the shape and area of ​​the first gate array test pad 241 are the same as the shape and area of ​​the second gate array test pad 242.

[0135] In some embodiments, the first gate array test pad 241 and the second gate array test pad 242, together with the intermediate redundant gate test pad 214, are located in the first electrical layer M1.

[0136] In some embodiments, such as Figure 9 and Figure 10 As shown, the display panel motherboard 300 also includes a first connection trace 251 and a second connection trace 252. The first connection trace 251 and the second connection trace 252 are located on the motherboard 111 of the non-display area 11B. The first connection trace 251 is adjacent to the outer bonding area 11C1 and connects the first gate array test pad 241 and the gate test pad 211. The second connection trace 252 is adjacent to the middle bonding area 11C2 and connects the second gate array test pad 242 and the middle redundant gate test pad 214. Thus, when the first connection trace 251 is provided in the outer bonding area 11C1, the second connection trace 252 is added around the middle bonding area 11C2, and the pattern around the middle bonding area 11C2 is similar to the pattern around the outer bonding area 11C1.

[0137] In some embodiments, such as Figure 9 As shown, when the display panel motherboard 300 includes the first outer redundant gate test pad 215, the display panel motherboard 300 also includes a third gate array test pad 243 and a third connection trace 253. The third connection trace 253 connects the third gate array test pad 243 and the first outer redundant gate test pad 215.

[0138] In some embodiments, the first connection trace 251 to the third connection trace 253, the first gate array test pad 241 to the third gate array test pad 243, the gate test pad 211, the intermediate redundant gate test pad 214, and the first outer redundant gate test pad 215 are located in the first electrical layer M1. This allows the first connection trace 251 to connect the first gate array test pad 241 and the gate test pad 211, the second connection trace 252 to connect the second gate array test pad 242 and the intermediate redundant gate test pad 214, and the third connection trace 253 to connect the third gate array test pad 243 and the first outer redundant gate test pad 215.

[0139] In some embodiments, refer to Figure 9 and Figure 10 As shown, the display panel motherboard 300 also includes multiple data lines 30, data short-circuit traces 31, a first data array test pad 331, and a second data array test pad 332. The multiple data lines 30 are located on the motherboard 111 of the display area 11A. The data short-circuit traces 31 are located on the motherboard 111 of the non-display area 11B and are connected to the multiple data lines 30. The first data array test pad 331 is located in the non-display area 11B, adjacent to the outer bonding area 11C1, and connected to the data short-circuit traces 31. The second data array test pad 332 is located in the non-display area 11B, adjacent to the middle bonding area 11C2. Thus, when the first data array test pad 331 is provided around the outer bonding area 11C1, the second data array test pad 332 is added around the middle bonding area 11C2, making the pattern around the middle bonding area 11C2 similar to the pattern around the outer bonding area 11C1.

[0140] During the testing of the array substrate 100, a data test signal is applied to the first data array test pad 331 to detect multiple data lines 30.

[0141] In some embodiments, the second data array test pad 332 may be connected to or insulated from multiple data lines 30.

[0142] In some embodiments, such as Figure 9 and Figure 10As shown, the display panel motherboard 300 also includes a data array test connection cable 34 and a data test pad 32. The data array test connection cable 34 is connected to the first data array test pad 331 via a fourth connection trace 254. The data array test connection cable 34 is connected to the second data array test pad 332 via a fifth connection trace 255. The data array test connection cable 34 is connected to the data test pad 32, and the data test pad 32 is connected to multiple data lines 30 via a data shorting trace 31.

[0143] In some embodiments, the first data array test pad 331 and the second data array test pad 332, the fourth connection trace 254, the fifth connection trace 255, the gate test pad 211, and the intermediate redundant gate test pad 214 are all located in the first conductive layer M1.

[0144] In some embodiments, the data array test connection line 34 is located on the second conductive layer M2. The data array test connection line 34 intersects with the first connection traces 251 to the fifth connection traces 255. Thus, the data array test connection line 34 and the first connection traces 251 to the fifth connection traces 255 are located on different conductive layers, reducing the risk of short circuits between the data array test connection line 34 and the first connection traces 251 and the second connection traces 252.

[0145] In some embodiments, such as Figure 11 As shown, the data array test connection line 34 can also be reused as a data short-circuit trace 31. The data array test connection line 34 is connected to multiple data lines 30 through the second outer bonding pad 62 of the outer bonding area 11C1 and the second intermediate bonding pad 64 of the middle bonding area 11C2. In this way, the wiring in the non-display area 11B is reduced.

[0146] It should be noted that after the array test is completed, the data array test connection line 34 is cut along the second cutting line Q2, and the remaining data array test connection line 34 is used as the data short-circuit trace 31. After the display panel test is completed, the data array is cut along the third cutting line Q3 to obtain the display panel.

[0147] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0148] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0149] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0150] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. An array substrate, characterized in that, include: A substrate has a display area and a non-display area, the non-display area being disposed around the display area and including a bonding area, the bonding area being located on one side of the display area in a first direction, the bonding area including two outer bonding areas and a middle bonding area, the middle bonding area being located between the two outer bonding areas in a second direction, the first direction intersecting the second direction; Scan lines are located on the substrate of the display area; A gate driving circuit is located on the substrate and connected to the scan line; A gate test pad is located on the substrate in the non-display area and is adjacent to at least one of the outer bonding areas, and is connected to the gate drive circuit. An intermediate redundant gate test pad is located on the substrate in the non-display area and adjacent to the intermediate bonding area, and is insulated from the gate drive circuit.

2. The array substrate according to claim 1, characterized in that, At least one of the intermediate redundant gate test pads is the same as the gate test pad.

3. The array substrate according to claim 1, characterized in that, N1 of the gate test pads are located on at least one side of each of the at least one of the outer bonding regions in the second direction and are adjacent to each of the at least one of the outer bonding regions, where N1 is an integer greater than or equal to 1; N2 intermediate redundant gate test pads are located on at least one side of each of at least one intermediate bonding region in the second direction and are adjacent to each of at least one intermediate bonding region, where N2 is an integer greater than or equal to 1 and N2 is less than or equal to N1.

4. The array substrate according to claim 1, characterized in that, The gate test pad and the intermediate redundant gate test pad are located in the first conductive layer.

5. The array substrate according to claim 1, characterized in that, Also includes: A first outer bonding pad is located on the substrate of at least one of the outer bonding regions and is connected to the gate drive circuit. A first intermediate bonding pad is located on the substrate of the intermediate bonding region; A gate test line is adjacent to at least one of the outer bonding regions and connected to the first outer bonding pad and the gate test pad; An intermediate redundant gate test line is adjacent to the intermediate bonding region, connected to the first intermediate bonding pad, and insulated from at least one of the intermediate redundant gate test pads.

6. The array substrate according to claim 5, characterized in that, The intermediate redundant gate test line is the same as at least a portion of the gate test line.

7. The array substrate according to claim 5, characterized in that, The gate test pad is located on the first conductive layer, the intermediate redundant gate test line and the gate test line are located on the second conductive layer, and the second conductive layer is located between the first conductive layer and the substrate.

8. The array substrate according to claim 1, characterized in that, Also includes: Multiple data lines are located on the substrate of the display area; The second outer bonding pad is located on the substrate of the outer bonding area and is connected to the data line; The second intermediate bonding pad is located on the substrate of the intermediate bonding area and is connected to the data line; The data short-circuit trace is connected to the second outer bonding pad and the second intermediate bonding pad. The orthographic projection of the data short-circuit trace on the substrate is offset from the orthographic projection of the gate test pad and the intermediate redundant gate test pad on the substrate.

9. The array substrate according to claim 8, characterized in that, At least some of the data short-circuit traces are non-linear.

10. The array substrate according to claim 8 or 9, characterized in that, The data short-circuit trace includes a first data short-circuit segment, and multiple first data short-circuit segments are adjacent to and staggered with the gate test pad and the intermediate redundant gate test pad, respectively.

11. The array substrate according to claim 10, characterized in that, The data short-circuit trace also includes multiple second data short-circuit segments. These multiple second data short-circuit segments are adjacent to the outer binding area and the middle binding area, respectively, and are connected to the second outer binding pad, the second middle binding pad, and the multiple first data short-circuit segments. The multiple second data short-circuit segments are staggered from the multiple first data short-circuit segments.

12. The array substrate according to claim 8, characterized in that, The data short-circuit trace, the redundant gate test pad, and the gate test pad are located in the first conductive layer.

13. The array substrate according to claim 8, characterized in that, Also includes: A first outer binding pad is located in at least one of the outer binding areas; A gate test line is adjacent to at least one of the outer bonding regions and connected to the first outer bonding pad and the gate test pad. The gate test line and the data short circuit trace are located in different conductive layers. At least a portion of the orthographic projection of the gate test line on the substrate is offset from the orthographic projection of the data short circuit trace on the substrate.

14. The array substrate according to claim 13, characterized in that, Also includes: A first intermediate bonding pad is located in the intermediate bonding area; An intermediate redundant gate test line is adjacent to the intermediate bonding region and insulated from at least one of the first intermediate bonding pad and the intermediate redundant gate test pad. The intermediate redundant gate test line and the data short-circuit trace are located in different conductive layers. At least a portion of the orthographic projection of the intermediate redundant gate test line on the substrate is offset from the orthographic projection of the data short-circuit trace on the substrate.

15. The array substrate according to claim 1, characterized in that, The two gate driving circuits are respectively located on opposite sides of the display area in the second direction; The plurality of gate test pads include a first gate test pad and a second gate test pad, wherein the first gate test pad is located on the side of one of the outer bonding regions opposite to the intermediate bonding region in the second direction and is connected to one of the gate driving circuits, and the second gate test pad is located on the side of another outer bonding region opposite to the intermediate bonding region in the second direction and is connected to another gate driving circuit.

16. The array substrate according to claim 15, characterized in that, Also includes: A first outer redundant gate test pad is adjacent to an outer bonding region, and in the second direction, an outer bonding region is located between the first outer redundant gate test pad and the first gate test pad; The second outer redundant gate test pad is adjacent to another said outer bonding region, and in the second direction, the other said outer bonding region is located between the second outer redundant gate test pad and the second gate test pad; Each of the intermediate binding regions has at least one intermediate redundant gate test pad disposed on the opposite side in the second direction.

17. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1 to 16.

18. A display panel motherboard, characterized in that, include: The motherboard has multiple panel areas, each panel area including a display area and a non-display area. The non-display area is arranged around the display area and includes a binding area. In a first direction, the binding area is located on one side of the display area. The binding area includes two outer binding areas and a middle binding area. In a second direction, the middle binding area is located between the two outer binding areas. The second direction intersects with the first direction. Scan lines are located on the motherboard of the display area; A gate driving circuit is located on the motherboard and connected to the scan line; A gate test pad is located on the motherboard of the non-display area and is adjacent to at least one of the outer bonding areas, and is connected to the gate drive circuit. The intermediate redundant gate test pad is located on the motherboard of the non-display area and adjacent to the intermediate bonding area, and is insulated from the gate drive circuit.

19. The display panel motherboard according to claim 18, characterized in that, Also includes: The first gate array test pad is located in the non-display area and adjacent to the outer bonding area, and is connected to the gate driving circuit. The second gate array test pad is located in the non-display area and is adjacent to the intermediate bonding area.

20. The display panel motherboard according to claim 18, characterized in that, Also includes: Multiple data lines are located on the motherboard of the display area; The data short-circuit trace is located on the motherboard in the non-display area and is connected to multiple data lines; The first data array test pad is located in the non-display area and adjacent to the outer binding area, and is connected to the data short-circuit trace; The second data array test pad is located in the non-display area and adjacent to the intermediate binding area.

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