Electrical test structure for detecting offset of lithography process

Abstract

The invention discloses an electrical test structure for detecting the offset of a lithography process, which is characterized in that the electrical test structure is initially in an open circuit, and when the lithography of a first through hole layer is normal, the current measured by the electrical test structure is I1; when the first through hole layer is offset in the lithography process, the first metal layer and the first through hole layer of the electrical test structure are in bridge connection, and the measured current is I2 different from I1. According to the electrical test structure for detecting the offset of the lithographic process, a traditional conduction circuit is changed into a circuit breaking structure, when the lithographic process of a certain layer of contact window deviates, the circuit is changed into a short circuit from a short circuit, so that an electrical measurement result is changed drastically, obvious abnormity can be detected, and the measurement sensitivity is improved.

Description

Technical Field

[0001] The present invention relates to the field of lithography process, and in particular to an electrical test structure for detecting offset of lithography process. Background Art

[0002] In the prior art, the general contact window stack test structure is a series conduction circuit. Only when the lithography process produces a serious offset, the electrical measurement results will be clearly represented, and the electrical results are reflected in the gradual change of resistance from small to large. When an abnormality occurs, the result is not obvious.

[0003] The current structure is M1+V1+M2+V2+M3+…, and the initial state is a through state. When the metal layer or through hole layer has a small offset, the resistance value of the entire structure changes slightly. Only when the metal layer or through hole layer lithography process has a serious offset can obvious abnormalities be detected from an electrical perspective, that is, from a through state to an open circuit or a situation similar to an open circuit. Since the resistance value changes slightly, the main problem with the current structure is that the detection sensitivity is not high.

[0004] Therefore, how to make the electrical measurement results have obvious representation, that is, how to improve the sensitivity of detection, has become an urgent problem to be solved. Summary of the invention

[0005] In order to solve the existing technical problems, the present invention proposes an electrical test structure for detecting the offset of the lithography process. The front and rear layer structures of the present application are in an open circuit state by default. When a certain layer of the contact window lithography process is offset, the circuit changes from open circuit to short circuit, thereby causing a drastic change in the electrical measurement result. Different from the conventional contact window stack electrical test structure, this structure can more sensitively detect whether the contact window lithography process is offset and determine the size of the offset.

[0006] According to one aspect of the present invention, there is provided an electrical test structure for detecting the offset of a lithography process, comprising: the electrical test structure is initially open circuited, and when the lithography state of the first via layer is normal, the current measured by the electrical test structure is I1; when the lithography of the first via layer is offset, the first metal layer / first via layer of the electrical test structure is bridged, and the measured current is I2 which is different from I1.

[0007] According to one embodiment of the present invention, I2>I1.

[0008] According to an embodiment of the present invention, changing the distance between the first via layer and the first metal layer can change the test sensitivity.

[0009] According to one embodiment of the present invention, the electrical test structure can detect a dimensional deviation greater than zero.

[0010] According to an embodiment of the present invention, the minimum size of the metal layer is 0.15 um, and the minimum size of the via layer is 0.2 um.

[0011] According to one embodiment of the present invention, the electrical test structure includes a first metal layer + a first through-hole layer + a second metal layer + a second through-hole layer + ... + an nth through-hole layer + an nth metal layer, wherein n is a positive integer greater than 1 and the nth through-hole layer is perpendicular to the nth metal layer and the n+1th metal layer. In an initial state, the first metal layer and the first through-hole layer are not connected, that is, they are open circuited.

[0012] Due to the adoption of the above technical solution, the present invention has the following advantages compared with the prior art: it can more sensitively detect whether the contact window lithography process is offset and determine the magnitude of the offset. The front and rear layer structures are in an open circuit state by default. When a certain layer of the contact window lithography process is offset, the circuit changes from open circuit to short circuit, thereby causing a drastic change in the electrical measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the drawings required for use in the embodiment will be briefly introduced below. Obviously, the drawings described below are only some implementation cases of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0014] Figure 1 A schematic diagram showing a normal process and a first via layer process abnormally shifted to the right according to an exemplary embodiment of the present invention;

[0015] Figure 2 A top view showing a normal process and a first via layer process abnormally shifted to the right according to an exemplary embodiment of the present invention;

[0016] Figure 3 A top view showing a normal process and a first via layer process abnormally shifted to the left according to an exemplary embodiment of the present invention;

[0017] Figure 4 A top view showing a normal process and a first via layer process abnormally shifted upward according to an exemplary embodiment of the present invention is shown;

[0018] Figure 5 A top view showing a normal process and a first via layer process with an abnormal downward shift according to an exemplary embodiment of the present invention is shown;

[0019] Figure 6 A schematic diagram showing a normal process of a conventional stacked electrical test structure according to the present invention and an abnormal leftward shift of the first via layer process is shown.

[0020] Description of reference numerals:

[0021] 1. First metal layer; 2. First through-hole layer; 3. Second metal layer; 4. Second through-hole layer; 5. Third metal layer. DETAILED DESCRIPTION

[0022] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0023] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0024] like Figure 1-6 As shown, the present invention provides an electrical test structure for detecting the offset of the lithography process, which includes: the electrical test structure is initially open-circuited, and when the lithography state of the first through-hole layer 2 is normal, the current measured by the electrical test structure is I1; when the lithography of the first through-hole layer 2 is offset, the first metal layer 1 / first through-hole layer 2 of the electrical test structure is bridged, and the measured current is I2 which is different from I1.

[0025] like Figure 6 As shown, in the prior art, the traditional stacked electrical test structure is the first metal layer 1+first via layer 2+second metal layer 3+second via layer 4+third metal layer 5+…, and the current measurement structure has a small change in the resistance of the entire structure when the metal layer or via layer offset is not large. Only when the metal layer or via layer lithography process is seriously offset can an obvious abnormality be detected from the electrical properties, that is, from a path to an open circuit or a situation similar to an open circuit. Since the resistance change is small, the main problem with the current structure is that the detection sensitivity is not high.

[0026] In order to improve the sensitivity of detection, the present application adjusts the default state of the test structure to open circuit. In the open circuit state, the process is in a normal state and a current I1 can be measured. That is, when the lithography of the first via layer is normal, the current measured by the electrical test structure is I1; when an offset occurs in the process, the test structure changes from an open circuit to a pass circuit, that is, when the first via layer is offset, the first metal layer 1 / first via layer of the electrical test structure is bridged, and the measured current is I2 which is different from I1.

[0027] The current in the open circuit is much smaller than the current in the open circuit, that is, I2>I1.

[0028] Taking the abnormal shift of the first via layer 2 process to the right as an example, the present application adjusts the default state of the test structure to open circuit. When an abnormal process occurs, the metal layer of the electrical test structure is bridged with the via layer adjacent to it, and the measured current changes dramatically. When the lithography of the first via layer 2 is normal, the current measured by the test structure is only 1E-13A. When the lithography of the first via layer 2 is slightly shifted to the right, the first via layer 2 of the test structure is bridged with the first metal layer 1, and the test current exceeds 1E-6A.

[0029] In some embodiments, the default offset of the first through-hole layer 2 may be changed according to actual needs to adjust the test sensitivity.

[0030] Changing the distance between the first via layer and the first metal layer 1 can also change the test sensitivity:

[0031] When the distance is 0.1um, the first via layer 2 is shifted to the right by 0.1um, and the circuit is turned on, and the power supply voltage / ground leakage increases from 1E-13A to 1E-6A;

[0032] When the distance is 0.2um, the first via layer 2 is shifted to the right by 0.2um, and the circuit is turned on, and the power supply voltage / ground leakage increases from 1E-13A to 1E-6A;

[0033] And so on…

[0034] In theory, the electrical test structure can detect any dimensional deviation greater than zero.

[0035] The minimum size of the metal layer is 0.15um, and the minimum size of the via layer is 0.2um.

[0036] like Figure 1-6 As shown, the electrical test structure includes a first metal layer 1+a first via layer 2+a second metal layer 3+a second via layer 4+…+an nth via layer+an nth metal layer, wherein n is a positive integer greater than 1 and the nth via layer is perpendicular to the nth metal layer and the n+1th metal layer in pairs, that is, the first via layer 2 is perpendicular to the first metal layer 1 and the second metal layer 3 in pairs, and the second via layer 4 is perpendicular to the second metal layer 3 and the third metal layer 5 in pairs.

[0037] In the initial state, there is an obvious disconnection between the first metal layer 1 and the first through-hole layer 2 , that is, a disconnected structure, or an open circuit.

[0038] The new stacking test provided by the present application changes the traditional on-circuit to an off-circuit structure. When the lithography process of a certain layer of contact window is offset, the circuit changes from an open circuit to a short circuit, causing a drastic change in the electrical measurement results. This allows for detection of obvious anomalies with high measurement sensitivity.

[0039] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. An electrical test structure for detecting a lithography process offset, characterized in that: The electrical test structure is initially open circuit. When the lithography state of the first via layer is normal, the current measured by the electrical test structure is I1. When the lithography of the first via layer is offset, the first metal layer / first via layer of the electrical test structure is bridged, and the measured current is I2 which is different from I1.

2. The electrical test structure for detecting the offset of the lithography process according to claim 1, characterized in that: Said I2>I1.

3. The electrical test structure for detecting the offset of the lithography process according to claim 2, characterized in that: Changing the distance between the first via layer and the first metal layer can change the test sensitivity.

4. The electrical test structure for detecting the offset of a lithography process according to claim 1, characterized in that: The electrical test structure can detect dimensional deviations greater than zero.

5. The electrical test structure for detecting lithography process offset according to claim 1, characterized in that: The minimum size of the metal layer is 0.15um, and the minimum size of the through-hole layer is 0.2um.

6. The electrical test structure for detecting lithography process offset according to claim 1, characterized in that: The electrical test structure includes a first metal layer + a first through-hole layer + a second metal layer + a second through-hole layer + ... + an nth through-hole layer + an nth metal layer, wherein n is a positive integer greater than 1 and the nth through-hole layer is perpendicular to the nth metal layer and the n+1th metal layer. In an initial state, the first metal layer and the first through-hole layer are not connected, that is, they are open circuited.

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