Semiconductor device, integrated circuit (IC) manufacturing system and photoetching method thereof

Abstract

The embodiment of the invention provides a semiconductor device. The semiconductor device includes a substrate having a plurality of chip regions. In some embodiments, the semiconductor device also includes a plurality of scribe lines between the plurality of chip regions. In some examples, the semiconductor device further includes a first plurality of alignment mark regions distributed within the plurality of scribe lines. In some embodiments, the semiconductor device further includes a second plurality of alignment mark regions distributed within each of the plurality of chip regions. Embodiments of the invention provide an integrated circuit (IC) manufacturing system. The embodiment of the invention also provides a photoetching method.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the semiconductor field, and more specifically, to a semiconductor device, an integrated circuit (IC) manufacturing system and a photolithography method thereof. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC dimensions (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] As just one example, and as part of the lithography process, overlay includes the ability of a lithography tool to accurately align and print the stacked layers of a semiconductor IC. As the complexity and number of layers used to form advanced ICs increase, overlay remains a key manufacturing issue. The overlay raw data can be described as the movement distance (or offset distance) between the ideal (or target) position and the actual position of the alignment mark patterned on the substrate. Based on the determined offset distance, the lithography tool can be positionally adjusted (or offset) according to the offset distance to minimize the overlay error between the layers of the continuous patterning. If the determined offset distance is inaccurate, the position adjustment of the lithography tool will also be inaccurate. Therefore, the prior art is not completely satisfactory in all aspects. Summary of the invention

[0004] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, comprising multiple chip regions; multiple scribe lines, the scribe lines being between the multiple chip regions; a first plurality of alignment mark regions, distributed within the multiple scribe lines; and a second plurality of alignment mark regions, distributed within each of the multiple chip regions.

[0005] Another embodiment of the present invention provides an integrated circuit (IC) manufacturing system, comprising: a lithography system configured to form a pattern on a substrate comprising a plurality of chip regions, wherein the pattern comprises a plurality of alignment mark regions, and the plurality of alignment mark regions are distributed within each of the plurality of chip regions and within scribe lines between the plurality of chip regions; one or more metrology tools configured to inspect the pattern to provide overlay data; and a lithography correction system coupled to receive the overlay data from the one or more metrology tools; wherein the lithography correction system is configured to make one or more adjustments to the lithography system based on the received overlay data.

[0006] Another embodiment of the present invention provides a lithography method, comprising: on a substrate including multiple chip areas, forming a first plurality of alignment marks in each chip area, and forming a second plurality of alignment marks within a scribe line between the multiple chip areas; determining an offset distance based on overlay data corresponding to the first plurality of alignment marks and the second plurality of alignment marks; providing adjustment to a lithography system based on the determined offset distance; and after performing the adjustment to the lithography system, performing a lithography process to pattern a target component on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 illustrates a top view of a semiconductor substrate according to some embodiments;

[0009] Figure 2 According to some embodiments, Figure 1 an enlarged view of a portion of a substrate;

[0010] Figure 3 provides an enlarged view of an example alignment mark area according to some embodiments;

[0011] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G shows example pattern types that may be used to provide alignment marks within cells of an alignment mark region according to some embodiments;

[0012] Figure 5 shows a functional flow of an IC manufacturing system including a lithography correction system according to some embodiments;

[0013] Figure 6 A schematic diagram of a lithography system according to some embodiments is provided;

[0014] Figure 7 is a flow chart of a method for reducing overlay error according to one or more aspects of the present disclosure; and

[0015] Figure 8 is a schematic diagram illustrating an embodiment of a computer system. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments or examples for realizing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the present invention. Such as, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein likewise interpreted accordingly. Furthermore, in the present disclosure, the terms "mask," "photomask," and "reticle" may be used interchangeably to refer to a photolithography template, such as an EUV mask.

[0018] In the photolithography process, overlay includes the ability of the photolithography tool to accurately align and print the stacked layers of the semiconductor IC. As more and more complex patterns and a large number of layers are used to form advanced ICs, overlay remains a key manufacturing issue. Overlay raw data can be described as the movement distance (or offset distance) between the ideal (or target) position and the actual position of the alignment mark patterned on the substrate, which may include the distance measured between the ideal (or target) position and the actual position of the alignment mark patterned on the substrate. Based on the determined offset distance, the photolithography tool can be positionally adjusted (or offset) according to the offset distance to minimize the overlay error between consecutive patterned layers. If the determined offset distance is inaccurate, the position adjustment of the photolithography tool will also be inaccurate. In some cases, the error in the determined offset distance may be caused by the presence of an undesirably low number of alignment marks on the wafer. A small number of alignment marks will result in a limited overlay raw data set. Therefore, due to inaccurate position adjustment of the photolithography tool, much overlay error information may be lost, and subsequent photolithography processes may have poor overlay performance (e.g., increased overlay error). Therefore, existing techniques for reducing overlay errors are not completely satisfactory in all aspects.

[0019] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all advantages must be discussed herein, and not all embodiments require specific advantages. For example, embodiments of the present disclosure provide a semiconductor device and related methods for increasing the amount of retrieved overlay raw data, thereby mitigating the loss of overlay error information and reducing overlay errors by ensuring that the position adjustment of the lithography tool is more accurate. In various embodiments, the increased amount of overlay raw data is provided by using a high density of alignment marks. In particular, in various embodiments, the alignment marks are distributed both in the wafer scribe lines (e.g., between chips) and in the individual chips themselves. In some embodiments, the alignment marks are located at the corners of the scribe lines between the chips and are positioned according to a regular distribution along the scribe lines (e.g., one every 4 mm in the X and Y directions). In addition, in various instances, a plurality of alignment marks (e.g., at least 4) are located within the region of each chip, and these alignment marks are evenly distributed throughout the region of each chip. Of course, in various embodiments, the exact location and / or number of alignment marks within the chip may vary depending on the specific layer being patterned. By implementing the techniques described herein, overlay errors may be reduced by approximately 50% compared to at least some prior art processes.

[0020] In various embodiments, different types of cells (e.g., including squares, rectangles, lines, arrays thereof, or combinations thereof) may be used to define each alignment mark in a plurality of alignment marks. For each type of cell, the duty cycle may be defined as the pattern width divided by the pattern spacing (W / S). In some embodiments, the duty cycle may be in the range of about 0.5 to about 3. In addition, the X and Y directions used to determine the duty cycle may vary according to different embodiments. In some instances, the cell type used in the chip may be the same or different from the cell type in the scribe line. Within each cell, the pattern may generally include a repeating array that follows a defined duty cycle. In addition, in some cases, a dummy pattern (e.g., at least 1 micron away from the cell) may be provided to prevent pattern density loading. In some embodiments, the total number of alignment marks is between about 950 and about 1000. Those skilled in the art will recognize other benefits and advantages of the methods and devices described herein, and the embodiments are not meant to be limited to the scope specifically cited in the following claims.

[0021] Reference now Figure 1 , which shows a top view of a semiconductor substrate 100 (or substrate 100). The substrate 100 includes a plurality of chip regions 110 in which semiconductor devices and / or circuits may be formed. As shown, the chip regions 110 are isolated from each other by scribe lines 120 disposed between adjacent chip regions in the plurality of chip regions 110. After the device and / or circuit manufacturing process is completed, the scribe lines 120 define the regions where the substrate 100 will be cut, so that the plurality of chip regions 110 can be divided into a plurality of separate chips.

[0022] Figure 2 Provided Figure 1 FIG. 1 is an enlarged view of a portion of substrate 100 , which more clearly shows some of the plurality of chip regions 110 , as well as scribe lines 120 surrounding and / or between chip regions 110 . Figure 2 Also shown are multiple alignment mark areas 202, which may include alignment mark areas 202A located at one or more exposure field corners and within the scribe line 120, alignment mark areas 202B located between adjacent chip areas 110 and within the scribe line 110, and alignment mark areas 202C located within each of the multiple chip areas 110.

[0023] When patterning multiple material layers formed on substrate 100, multiple alignment mark areas 202 can be used to align the upper and lower layers in these material layers. In other words, multiple alignment mark areas 202 can be used to ensure that the components in a given layer are accurately aligned with the components in one or more lower layers. For example, in the IC manufacturing process, multiple material layers can be patterned by repeating a photolithography process and an etching process. For example, a photoresist (resist) layer can be formed on the material layer to be patterned, and the photoresist layer can be exposed using a photolithography system according to a pattern (e.g., defined by a photomask), and developed to provide a patterned photoresist layer. Before exposure, the alignment marks on the photomask (e.g., in the alignment area 202) can be aligned with the corresponding alignment marks on or in the material layer. After the exposure pattern is developed, a post-development inspection (ADI) can be performed to provide overlay data. Thereafter, an etching process can be performed so that the pattern provided by the patterned photoresist layer is transferred to the material layer below. After the etching process, a post-etching inspection (AEI) can be performed to provide additional overlay data, such as overlay changes caused by etching. In various instances, the ADI and AEI processes can be performed using metrology tools that employ an image-based overlay (IBO) method, a diffraction-based overlay (DBO) method, or a combination thereof. Based on the collected overlay data (e.g., from ADI and AEI), adjustments can be made to the lithography system, and in some cases one or more etching systems can be adjusted to improve (reduce) overlay errors. In some instances, the adjustments made to the lithography system can correct translation errors, rotation errors, and / or higher-order errors. Thereafter, patterning and etching of additional material layers can be similarly performed on some or all subsequent material layers sequentially stacked on the patterned underlying material layer. In addition, the formation of each subsequent material layer can be inspected (e.g., collecting overlay data) and adjusted (e.g., to the lithography system) as needed.

[0024] Still reference Figure 2And alignment mark area 202, alignment mark area 202A and 202B can be distributed at regular intervals along scribe line 120. As an example, alignment mark area 202 in scribe line 120 can be spaced at intervals of 4mm in X and Y directions. In other examples, alignment mark area 202 in scribe line 120 can be spaced at other intervals in X and Y directions, such as 1mm, 2mm, 2.5mm, 5mm or other suitable intervals. In addition, multiple alignment mark areas 202C are located in each of multiple chip areas 110. In some embodiments, at least four alignment mark areas 202C are located in each of multiple chip areas 110. In various cases, alignment mark area 202C can be evenly distributed in the entire area of ​​each chip area of ​​multiple chip areas 110. For example, in the case of four alignment mark areas 202C, one alignment mark area 202C can be located in each quadrant of each chip area 110. Of course, in some embodiments, the exact location and / or number of alignment mark regions 202C within chip region 110 may vary based on the specific layer being patterned. Figure 2 In the example of FIG. 1 , four alignment mark areas 202C are shown in each chip area 110, but other numbers of alignment mark areas 202C may be used without departing from the scope of the present disclosure. In some cases, a greater number of alignment mark areas 202C may be included in each chip area 110 when patterning critical layers rather than non-critical layers. Therefore, in some embodiments, two or more alignment mark areas 202C may be located in one or more quadrants of each chip area 110. More generally, although a specific number of alignment mark areas 202 are shown as being formed within the scribe line 120 (alignment mark areas 202A, 202B) and within the chip area 110 (alignment mark areas 202C), these examples are not meant to be limiting, and different numbers and / or distributions of alignment mark areas 202A, 202A, 202C may be used without departing from the scope of the present disclosure.

[0025] Reference now Figure 3 , where an enlarged view of an exemplary alignment mark region 202 is shown. Figure 3 The exemplary alignment mark region 202 of can be used to provide alignment mark region 202A, alignment mark region 202B and / or alignment mark region 202C. As shown, alignment mark region 202 includes cells 302, which include alignment marks for alignment mark region 201. In some embodiments, the cell length "cell-L" of cell 302 is in the range of about 200 microns to 250 microns, and the cell width "cell-W" is in the range of about 38 microns to 100 microns. Figure 3In the example of , the cells 302 include an array of rectangular patterns 304. However, more generally, the cells 302 may include any of a number of different types of cells having different types of patterns (e.g., including squares, rectangles, lines, arrays thereof, or combinations thereof), some of which will be referenced below. FIG. 4A to FIG. 4G It should be noted that in various cases, the type of cells (and the type of patterns generated thereby) used to provide alignment marks for the alignment mark regions 202A, 202B in the scribe line 120 may be the same as or different from the type of cells (and the type of patterns generated thereby) used to provide alignment marks for the alignment mark region 202C in the chip region 110.

[0026] In addition, in the present example, the duty cycle (along the X direction) of the rectangular pattern array 304 is defined as the width 'W1' of a single rectangular pattern 304 divided by the pattern spacing 'S1' (W1 / S1). In various embodiments, the duty cycle W1 / S1 may be in the range of about 0.5 to about 3. In some embodiments, a dummy pattern 306 adjacent to one or more sides of the cell 302 is also provided. Thus, as an example, the exemplary alignment mark region 202 may include a cell 302 and a dummy pattern 306, the cell 302 including an alignment mark of the alignment mark region 202. As shown, the dummy pattern 306 may include an array of components 308, such as an array of rectangular components, square components, circular components, line components, combinations thereof, or other suitable components. In addition, to prevent pattern density loading, the dummy pattern 306 may be spaced a distance "D" from the corresponding side of the adjacent cell 302. In some embodiments, the distance "D" is equal to or greater than 1 micron.

[0027] FIG. 4A to FIG. 4G Exemplary pattern types that may be used to provide alignment marks within a cell (eg, cell 302 ) of an alignment mark region (eg, alignment mark regions 202A, 202B, 202C) are shown. Figure 4A The example of shows a first pattern type 402 that can be used to provide a first cell type. In particular, the first pattern type 402 has no duty cycle. In other words, the first pattern type 402 can include a single pattern that substantially fills a cell (eg, cell 302). Figure 4BThe example shows a second pattern type 404 that can be used to provide a second unit type. Specifically, the second pattern type 404 includes an array of rectangular patterns 405. In some embodiments, the duty cycle (along the Y direction) of the array of rectangular patterns 405 is defined as the width 'W2' of a single rectangular pattern 405 divided by the pattern spacing 'S2' (W2 / S2). In various embodiments, the duty cycle W2 / S2 can be in the range of about 0.5 to about 3. In some cases, the duty cycle of the array of rectangular patterns 405 can remain constant along the Y direction of the unit (e.g., when the width 'W2' and the spacing 'S2' remain constant). However, in some embodiments, the duty cycle of the array of rectangular patterns 405 can vary along the Y direction of the unit (e.g., when the width 'W2' and / or the spacing 'S2' vary along the Y direction).

[0028] Figure 4C The example of FIG. 4 illustrates a third pattern type 406 that can be used to provide a third unit type. Specifically, the third pattern type 406 includes an array of rectangular patterns 407. In some embodiments, the array of rectangular patterns 407 has a duty cycle (along the X direction) defined as the width "W3" of a single rectangular pattern 407 divided by the pattern spacing "S3" (W3 / S3). In various embodiments, the duty cycle W3 / S3 can be in the range of about 0.5 to about 3. In one embodiment, the third pattern type 406 can be Figure 3 The array of rectangular patterns 304 in the cell 302 is substantially the same. In some cases, the duty cycle of the array of rectangular patterns 407 may be constant along the X direction of the cell (e.g., when the width "W3" and the spacing "S3" are constant). However, in some embodiments, the duty cycle of the array of rectangular patterns 407 may vary along the X direction of the cell (e.g., when the width "W3" and / or the spacing "S3" vary along the X direction).

[0029] Figure 4DThe example of illustrates a fourth pattern type 408 that can be used to provide a fourth cell type. Specifically, the fourth pattern type 408 includes an array of square patterns 409. In some embodiments, the array of square patterns 409 has a first duty cycle (along the x-direction), which is defined as the width 'W4' of a single square pattern 409 divided by the pattern spacing 'S4' in the x-direction (W4 / S4), and a second duty cycle (along the y-direction), which is defined as the width 'W4' of a single square pattern 409 divided by the pattern spacing 'S5' in the y-direction (W4 / S5). . In this example, the spacing 'S5' in the Y-direction is less than the spacing 'S4' in the X-direction, resulting in the second duty cycle (along the Y-direction) being greater than the first duty cycle. In other examples, the first duty cycle (along the X-direction) can be greater than the second duty cycle (along the Y-direction), or the first duty cycle is equal to the second duty cycle. In general, the duty cycle can be defined independently for each direction (e.g., the X-direction and the Y-direction). Even though the duty cycle may vary, in various embodiments, each of the first duty cycle W4 / S4 and the second duty cycle W1 / S5 may be in the range of about 0.5 to about 3. In some cases, the first duty cycle and the second duty cycle may remain constant along the respective X and Y directions of the cell (e.g., when the width and spacing in the respective X and Y directions remain constant). However, in some embodiments, the first duty cycle and the second duty cycle may vary along the respective X and Y directions of the cell (e.g., when the width and / or spacing in the respective X and / or Y directions vary).

[0030] Figure 4E The example of illustrates a fifth pattern type 410 that can be used to provide a fifth unit type. Specifically, the fifth pattern type 410 includes an array of rectangular patterns 411. In some aspects, the fifth pattern type 410 is similar to the second pattern type 404 and the third pattern type 406, as long as they each include an array of rectangular patterns. However, as shown, the fifth pattern type 410 is rotated by an angle θ relative to the X direction. Therefore, in some embodiments, the array of rectangular patterns 411 has a duty cycle (along a direction N perpendicular to a plane parallel to the angle θ), which is defined as the width 'W6' of a single rectangular pattern 411 divided by the pattern spacing 'S6' (W6 / S6). In various embodiments, the duty cycle W6 / S6 can be in the range of about 0.5 to about 3. In some cases, the duty cycle of the array of rectangular patterns 411 can be constant along the direction N of the unit (for example, when the width 'W6' and the spacing 'S6' are constant). However, in some embodiments, the duty cycle of the array of rectangular patterns 411 may vary along the direction N of the cell (eg, when the width ' W6 ' and / or the spacing ' S6 ' vary along the direction N).

[0031] Figure 4FThe example of the sixth pattern type 412 that can be used to provide the sixth unit type is illustrated. Specifically, the sixth pattern type 412 includes an array of rectangular patterns 413. In some embodiments, the sixth pattern type 412 is similar to the third pattern type 406 described above. However, due to the change in the pattern spacing, the sixth pattern type 412 has a variable duty cycle. Of course, in other cases, different duty cycles may be the result of changes in pattern width. In the example shown, the array of rectangular patterns 413 has a first duty cycle (along the X direction, for the first portion of the sixth pattern type 412) and a second duty cycle (along the X direction, for the second portion of the sixth pattern type 412), the first duty cycle is defined as a single rectangular pattern 413 width 'W7' divided by the first pattern spacing 'S7' (W7 / S7), and the second duty cycle is defined as a single rectangular pattern 413 width 'W7' divided by the second pattern spacing 'S8' (W7 / S8). In this example, the first pattern spacing 'S7' is greater than the second pattern spacing 'S8', resulting in the second duty cycle being greater than the first duty cycle. In other examples, for example, when the second pattern pitch 'S8' is greater than the first pattern pitch 'S7'", the first duty cycle can be greater than the second duty cycle. In other cases, along the entire X direction of the sixth pattern type 412, one of the first duty cycle and the second duty cycle can be alternatingly greater than the other (optionally, in a periodic manner). Although the duty cycle can vary, each of the first duty cycle W7 / S7 and the second duty cycle W3 / S8 can be in the range of about 0.5 to about 3.

[0032] Figure 4GThe example of FIG. 4 illustrates a seventh pattern type 414 that can be used to provide a seventh unit type. In particular, the seventh pattern type 414 includes an array of square patterns 415. In some embodiments, the seventh pattern type 414 is similar to the fourth pattern type 408 described above. However, due to the variation in pattern spacing, the seventh pattern type 414 has a varying duty cycle. Of course, in other cases, different duty cycles may be the result of varying pattern widths. In the example shown, the array of square patterns 415 has: a first duty cycle (along the x-direction and in the first region of the seventh pattern type 414), which is defined as the width 'W9' of a single square pattern 415 divided by the first pattern pitch in the x-direction 'S9' (W9 / S9); a second duty cycle (along the x-direction and in the second region of the seventh pattern type 414), which is defined as the width 'W9' of a single square pattern 415 divided by the second pattern pitch 'S10' in the x-direction (W9 / S10); a third duty cycle (along the y-direction and in the first region of the seventh pattern type 414), which is defined as the width 'W4' of a single square pattern 415 divided by the first pattern pitch 'S11' in the y-direction (W4 / S11); and a fourth duty cycle (along the y-direction and in the second region of the seventh pattern type 414), which is defined as the width 'W4' of a single square pattern 415 divided by the second pattern pitch 'S12' in the y-direction (W4 / S12). In some cases, the second region of the seventh pattern type 414 can be described as having a gap without any separate square pattern 415, resulting in a second pattern spacing in the X direction and the Y direction. In this example, the first pattern spacing 'S11' in the Y direction is less than the second pattern spacing 'S9' in the X direction, resulting in the third duty cycle W4 / S11 (along the Y direction) being greater than the first duty cycle W9 / S9 (along the X direction). In other examples, the first duty cycle W9 / S9 (along the X direction) can be greater than the third duty cycle W4 / S11 (along the Y-axis direction), or the first and third duty cycles can be the same. In addition, the second pattern spacing 'S10' in the X direction is greater than the first pattern spacing 'S9' in the X direction, resulting in the first duty cycle W9 / S9 (along the X-axis direction) being greater than the second duty cycle W9 / S10 (along the X-axis direction). In addition, the second pattern pitch 'S12' in the Y direction is greater than the first pattern pitch 'S11' in the Y direction, resulting in the third duty cycle W4 / S11 (along the Y-axis direction) being greater than the fourth duty cycle W4 / S12 (along the Y-axis direction). In general, as discussed with respect to the fourth pattern type 408, the duty cycle can be independently defined for each direction (e.g., the X direction and the Y direction). Although the duty cycle can vary, each of the first duty cycle W9 / S9, the second duty cycle W9 / S10, the third duty cycle W4 / S11, and the fourth duty cycle W4 / S12 can be in the range of about 0.5 to about 3.

[0033] Although referenced FIG. 4A to FIG. 4G Some exemplary types of patterns that may be used to provide alignment marks within a cell (e.g., cell 302) of an alignment mark region (e.g., alignment mark regions 202A, 202B, 202C) are discussed, but these examples are illustrative only and are not meant to be limiting. It should be understood that other types of patterns may be used in addition to and / or in addition to the above-described patterns without departing from the scope of the present disclosure. Furthermore, in various embodiments, a combination of two or more pattern types may be combined within a particular cell (e.g., cell 302) to provide alignment marks for an alignment mark region (e.g., alignment mark regions 202A, 202B, 202C).

[0034] Reference now Figure 5 , which shows the functional flow of an IC manufacturing system 500 including a lithography correction system 502. In the example shown, in some cases, a substrate (e.g., substrate 100) is provided to a lithography system 504 after the substrate has been previously processed. According to some embodiments, Figure 6 A schematic diagram of a lithography system 504 is provided in FIG.

[0035] The lithography system 504 may also be collectively referred to as a scanner, which is operable to perform a lithography process including exposure with a corresponding radiation source and a specific exposure mode. In at least some of the present embodiments, the lithography system 504 includes an extreme ultraviolet (EUV) lithography system, which is designed to expose a photoresist layer by EUV light. Therefore, in various embodiments, the photoresist layer includes a material that is sensitive to EUV light (e.g., EUV photoresist). The lithography system 504 includes a plurality of subsystems, such as a radiation source 602, an illuminator 604, a mask stage 606 configured to receive a mask 608, a projection optical device 610, and a substrate stage 618 configured to receive a substrate 616 (which may include the substrate 100). A general description of the operation of the lithography system 504 can be given as follows: EUV light from the radiation source 602 is directed to the illuminator 604 (which includes a set of mirrors) and projected onto a reflective mask 608. The reflected mask image is directed toward projection optics 610, which focuses the EUV light and projects the EUV light onto substrate 616 to expose the EUV photoresist layer deposited thereon. Additionally, in various examples, each subsystem of lithography system 504 can be housed in a high vacuum environment and thus operated therein, for example, to reduce atmospheric absorption of EUV light.

[0036] In the embodiments described herein, radiation source 602 may be used to generate EUV light. In some embodiments, radiation source 602 includes a plasma source, such as a discharge plasma (DPP) or a laser plasma (LPP). In some instances, EUV light may include light having a wavelength range of about 1 nm to about 100 nm. In a specific instance, radiation source 602 generates EUV light having a wavelength center of about 13.5 nm. Therefore, radiation source 602 may also be referred to as EUV radiation source 602. In some embodiments, radiation source 602 also includes a collector, which may be used to collect EUV light generated from the plasma source and direct the EUV light to an imaging optical device, such as illuminator 604.

[0037] As described above, light from the radiation source 602 is directed to the illuminator 604. In some embodiments, the illuminator 604 may include reflective optics (e.g., for EUV lithography system 504), such as a single mirror or a mirror system having multiple mirrors, to direct light from the radiation source 602 onto the mask stage 606, and in particular onto the mask 608 fixed to the mask stage 606. In some instances, the illuminator 604 may include a zone plate, for example, to improve the focusing of the EUV light. In some embodiments, the illuminator 604 may be configured to shape the EUV light passing therethrough according to a particular pupil shape, and include, for example, a dipole shape, a quadrupole shape, a toroidal shape, a single beam shape, a multi-beam shape, and / or a combination thereof. In some embodiments, the illuminator 604 is operable to configure a mirror (i.e., a mirror of the illuminator 604) to provide the desired illumination to the mask 608. In one instance, the mirror of the illuminator 604 may be configured to reflect the EUV light to different illumination positions. In some embodiments, the stage prior to the illuminator 604 may additionally include other configurable mirrors that can be used to direct EUV light to different illumination positions within the mirror of the illuminator 604. In some embodiments, the illuminator 604 is configured to provide on-axis illumination (ONI) to the mask 608. In some embodiments, the illuminator 604 is configured to provide off-axis illumination (OAI) to the mask 608. It should be noted that the optics employed in the EUV lithography system 504, particularly for the illuminator 604 and the projection optics 610, may include mirrors with multilayer thin-film coatings known as Bragg reflectors. For example, such multilayer thin-film coatings may include alternating layers of Mo and Si, which provide high reflectivity at EUV wavelengths (e.g., about 13 nm).

[0038] As described above, the lithography system 504 also includes a mask stage 606 configured to hold a mask 608. Since the lithography system 504 can be housed and operated in a high vacuum environment, the mask stage 606 can include an electrostatic chuck (e-chuck) to hold the mask 608. The mask stage 606 can also be connected to one or more motors that provide translation and rotation adjustment of the mask stage 602. Like the optical devices of the EUV lithography system 504, the mask 608 is also reflective. Figure 6 As shown in the example of , light reflects from mask 608 and is directed to projection optics 610, which collects EUV light reflected from mask 608. For example, the EUV light (reflected from mask 608) collected by projection optics 610 carries an image of the pattern defined by mask 608. In various embodiments, projection optics 610 provides imaging of the pattern of mask 608 onto substrate 616 fixed on substrate stage 618 of lithography system 504. In particular, in various embodiments, projection optics 610 focuses the collected EUV light and projects the EUV light onto substrate 616 to expose a layer of EUV photoresist deposited on substrate 616. As described above, projection optics 610 may include reflective optics, such as used in EUV lithography systems (such as lithography system 504). In some embodiments, illuminator 604 and projection optics 610 are collectively referred to as an optical module of lithography system 504.

[0039] In some embodiments, the lithography system 504 further includes a pupil phase modulator 612 for modulating the optical phase of EUV light directed from the mask 608 so that the light has a phase distribution along a projection pupil plane 614. In some embodiments, the pupil phase modulator 612 includes a mechanism for tuning a mirror of the projection optics 610 for phase modulation. For example, in some embodiments, the mirror of the projection optics 610 may be configured to reflect the EUV light through the pupil phase modulator 612, thereby modulating the phase of the light passing through the projection optics 610. In some embodiments, the pupil phase modulator 612 utilizes a pupil filter placed on the projection pupil plane 614. For example, a pupil filter may be employed to filter out specific spatial frequency components of the EUV light reflected from the mask 608. In some embodiments, the pupil filter may be used as a phase pupil filter that modulates the phase distribution of the light passing through the projection optics 610.

[0040] As described above, the lithography system 504 also includes a substrate stage 618 for fixing a semiconductor substrate 616 to be patterned. The substrate stage 618 can also be connected to one or more motors that provide translation and rotation adjustment of the substrate stage 618. In various embodiments, the semiconductor substrate 616 includes a semiconductor wafer, such as a silicon wafer, a germanium wafer, a silicon germanium wafer, a III-V wafer, or other types of wafers as described above or known in the art. The semiconductor substrate 616 can be coated with a photoresist layer (e.g., an EUV resist layer) that is sensitive to EUV light. EUV photoresists may have strict performance standards. For illustrative purposes, EUV photoresists can be designed to provide a resolution of at least about 22nm, a line width roughness (LWR) of at least about 2nm, and a sensitivity of at least about 15mJ / cm2. In the embodiments described herein, the various subsystems of the lithography system 504, including the above-mentioned subsystems, are integrated together and can be used to perform lithography exposure processes, including EUV lithography processes. Of course, the lithography system 504 may also include other modules or subsystems, which may be integrated (or coupled) with one or more subsystems or components described herein.

[0041] In addition, in some embodiments, the photolithography system 504 can be used to pattern one or more types of patterns that can be used to provide alignment marks within a cell (e.g., cell 302) in an alignment mark area (e.g., alignment mark areas 202A, 202B, 202C) within a semiconductor layer and / or a photoresist layer. More generally, the photolithography system 504 can be used to form a pattern (e.g., including a patterned photoresist layer) on an underlying material layer to be patterned. For example, a photoresist layer can be formed on a material layer to be patterned (a material layer of a provided substrate), and the photoresist layer can be exposed and developed using the photolithography system 504 according to a pattern (e.g., defined by a mask 608) to provide a patterned photoresist layer. Prior to exposure, the alignment marks on the mask 608 can be aligned with corresponding alignment marks on or within the material layer.

[0042] Back to Figure 5 In the functional flow of FIG. 5 , after the exposure pattern on the substrate is developed, one or more metrology tools 506 may be used to perform post-development inspection (ADI) to provide overlay data to the lithography correction system 502. In some embodiments, the lithography correction system 502 may be implemented using any of a plurality of systems (e.g., Figure 8800 shown in FIG. 8 ). In addition, in some cases, the lithography correction system 502 can be integrated within the lithography system 504. Thereafter, an etching process can be performed using one or more etching tools 508 so that the pattern provided by the patterned lithography layer is transferred to the underlying material layer on the substrate. After the etching process, a post-etch inspection (AEI) can be performed using one or more metrology tools 506 to provide additional overlay data (e.g., overlay changes caused by etching) to the lithography correction system 502. In some embodiments, the substrate can be subsequently processed.

[0043] Based on the overlay data collected from the ADI and / or AEI using one or more metrology tools 506, the lithography correction system 502 can adjust the lithography system 504 to improve (reduce) overlay errors. In some cases, one or more etching tools 508 can also be adjusted. In some instances, the adjustments made to the lithography system 504 can correct translation errors, rotation errors, and / or higher-order errors. Therefore, in some embodiments, the adjustments made by the lithography correction system 502 can include adjustments to one or more motors coupled to the mask stage 606 and / or the substrate stage 618, adjustments to the illuminator 604, adjustments to the projection optical device 610, and / or adjustments to other modules or subsystems that can be integrated (or coupled) with the lithography system 504. In various embodiments, patterning and etching of additional material layers can be performed similarly for some or all subsequent material layers on the patterned lower material layer stacked sequentially on the substrate. Furthermore, the formation of each subsequent material layer may be inspected (eg, collecting overlay data) and adjusted (eg, adjusting the lithography system 504 via the lithography correction system 502 ) as needed.

[0044] Reference now Figure 7 , which shows a flowchart of a method 700 for reducing overlay error according to an embodiment of the present disclosure. Figures 1 to 3 , FIG. 4A to FIG. 4G , Figure 5 and Figure 6 Method 700 is described. It should be understood that additional process steps may be performed before, during, and after method 700, and that some of the process steps described may be replaced or eliminated according to various embodiments of method 700. It should also be noted that the steps of method 700, including any description given, are merely exemplary and are not intended to limit what is specifically recited in the following claims.

[0045] The method 700 begins at block 702, where alignment marks are formed on a substrate (e.g., substrate 100). In various embodiments, the alignment marks may include alignment mark regions (e.g., alignment mark regions 202A, 202B, 202C) formed in the scribe line 120 and / or within the chip region 110. In addition, as previously described, each alignment mark region formed may include a reference FIG. 4A to FIG. 4G A cell of one or more pattern types discussed (e.g., such as cell 302), while a dummy pattern (e.g., such as dummy pattern 306) is formed adjacent to one or more sides of the cell. Typically, the formation of alignment marks may include depositing a photoresist layer over a target film (or a material layer to be patterned), exposing the photoresist (e.g., using a photolithography system 504), and etching the target film (e.g., using one or more etching tools 508) to form alignment marks in the target film. In various embodiments, the alignment marks formed at box 702 may be formed before a target component to be patterned in the target layer. In various instances, the target component may include a source / drain contact, a source / drain electrode via, a gate via, a backside via, an interconnect line, a gate stack component, or other semiconductor device component.

[0046] After forming the alignment marks, the method 700 proceeds to block 704, where measurements are taken using the alignment marks to obtain offset distances. The movement distance (or offset distance) can be extracted from or provided by the overlay data, which can be measured by one or more metrology tools 506. In some embodiments, the offset distance can be described as the distance between the ideal (or target) position and the actual position of the alignment marks patterned on the substrate. The overlay data and / or the offset distance can be provided to the lithography correction system 502 to adjust the lithography system 504.

[0047] After determining the offset distance, the method 700 continues to block 706, where the lithography correction system 502 uses the overlay data and / or the offset distance to correct or provide adjustments to the lithography system 504. As described above, the adjustments made by the lithography correction system 502 to the lithography system 504 may correct translation errors, rotation errors, and / or higher order errors. Thus, in some embodiments, the adjustments made by the lithography correction system 502 may include adjustments to one or more motors coupled to the mask stage 606 and / or the substrate stage 618, adjustments to the illuminator 604, adjustments to the projection optics 610, and / or adjustments to other modules or subsystems that may be integrated (or coupled) with the lithography system 504. In particular, due to the high density of alignment marks provided, more overlay raw data will be provided to the lithography correction system 502, and thus the adjustments to the lithography system 504 will be highly accurate and significantly reduce overlay errors.

[0048] Once the lithography system 504 is adjusted (or once the lithography system 504 is calibrated), the method 700 continues to box 708, where the target component is patterned within the target layer using the lithography tool 504. As described above, the target component may include a source / drain contact, a source / drain electrode via, a gate via, a backside via, an interconnect line, a gate stack component, or other semiconductor device component. According to an embodiment of the present disclosure, by calibrating the lithography system 504 using a high density of alignment marks, there is almost no offset between the target component and the underlying feature to which the target component is to be aligned. For example, in various embodiments, the overlay error can be reduced by about 50% compared to at least some existing processes, and the 3-standard deviation limit of the overlay error can be in the range of about 10nm to 10.6nm.

[0049] As described above, the lithography correction system 502 may be implemented using the computer system 800, such as Figure 8 As shown. According to various embodiments of the present disclosure, a computer system 800, such as a computer and / or a network server, includes a bus 802 or other communication mechanism for communicating information, which interconnects subsystems and components, such as a processing component 804 (e.g., a processor, a microcontroller, a digital signal processor (DSP), etc.), a system memory component 806 (e.g., a RAM), a static storage component 808 (e.g., a ROM), a disk drive component 810 (e.g., a magnetic or optical), a network interface component 812 (e.g., a modem or an Ethernet card), a display component 814 (e.g., a CRT or LCD), an input component 818 (e.g., a keyboard, a keypad, or a virtual keyboard), a cursor control component 820 (e.g., a mouse, a pointer, or a trackball), a position determination component 822 (e.g., a global positioning system (GPS) device as shown, a cellular base station triangulation positioning device, and / or various other position determination devices known in the art) and / or a camera component 823. In one embodiment, the disk drive component 810 may include a database having one or more disk drive components.

[0050] According to an embodiment of the present disclosure, computer system 800 performs specific operations by processor 804 executing one or more sequences of instructions contained in memory component 806, such as described herein with respect to IC manufacturing system 500 and method 700. Such instructions may be read into system memory component 806 from another computer-readable medium, such as static storage component 808 or disk drive component 810. In other embodiments, hard-wired circuitry may be used in place of or in combination with software instructions to implement the present disclosure.

[0051] The logic may be encoded in a computer readable medium, where computer readable media may refer to any medium that participates in providing instructions to processor 804 for execution. Such media may take a variety of forms, including, but not limited to, non-volatile media, volatile media, and transmission media. In one embodiment, the computer readable medium is non-transitory. In various implementations, non-volatile media include optical or magnetic disks, such as disk drive component 810, volatile media include dynamic memory, such as system memory component 806, and transmission media include coaxial cables, copper wire, and optical fiber, including the wires that make up bus 802. In one example, the transmission medium may take the form of sound or light waves, such as those generated during radio wave and infrared data communications.

[0052] Some common forms of computer readable media include, for example, a floppy disk, a diskette, a hard disk, a magnetic tape, any other magnetic medium, a CD-ROM, any other optical medium, a punch card, a paper tape, any other physical medium having a pattern of holes, a RAM, a PROM, an EPROM, a FLASH-EPROM, any other memory chip or cassette, a carrier wave, or any other medium suitable for reading by a computer. In one embodiment, the computer readable medium is non-transitory.

[0053] In various embodiments of the present disclosure, execution of instruction sequences for practicing the present disclosure may be performed by a computer system 800. In various other embodiments of the present disclosure, multiple computer systems 800 coupled to a network 815 (e.g., such as a LAN, WLAN, PTSN, and / or various other wired or wireless networks, including telecommunications, mobile, and cellular telephone networks) via a communication link 824 may execute instruction sequences to practice the present disclosure in coordination with one another.

[0054] Computer system 800 may send and receive messages, data, information, and instructions, including one or more programs (i.e., application code), via communication link 824 and network interface component 812. Network interface component 812 may include a separate or integrated antenna to enable transmission and reception via communication link 824. Received program code may be executed by processor 804, such as received and / or stored in disk drive component 810 or some other non-volatile storage component for execution.

[0055] Where applicable, the various embodiments provided by the present disclosure may be implemented using hardware, software, or a combination of hardware and software. In addition, where applicable, the various hardware components and / or software components described herein may be combined into composite components including software, hardware, and / or both, without departing from the scope of the present disclosure. Where applicable, the various hardware components and / or software components described herein may be divided into subcomponents including software, hardware, or both, without departing from the scope of the present disclosure. In addition, where applicable, it is conceivable that software components may be implemented as hardware components, and vice versa.

[0056] Software according to the present disclosure, such as program code and / or data, can be stored on one or more computer-readable media. It is also contemplated that the software described herein can be implemented using one or more general or special-purpose computers and / or computer systems, networks, and / or other means. Where applicable, the order of the various steps described herein can be changed, combined into composite steps, and / or separated into sub-steps to provide the components described herein.

[0057] The various embodiments described herein provide several advantages over the prior art. It should be understood that not all advantages are necessarily discussed herein, not all embodiments require specific advantages, and other embodiments may provide different advantages. For example, the embodiments discussed herein provide a semiconductor device and a related method for increasing the amount of retrieved overlay raw data, thereby alleviating the loss of overlay error information, and reducing overlay errors by ensuring that the position adjustment of the lithography tool is more accurate. In various embodiments, an increased amount of overlay raw data is provided by using a high density of alignment marks. In particular, in various embodiments, the alignment marks are distributed both in the wafer scribing (e.g., between the chips) and in the single chip itself. In some embodiments, the exact position and / or number of the alignment marks within the chip can vary depending on the specific layer being patterned. In addition, in some embodiments, different types of cells with patterns of various duty cycles can be used to define each of a plurality of alignment marks.

[0058] Therefore, one embodiment of the present disclosure describes a semiconductor device, including a substrate having a plurality of chip regions. In some embodiments, the semiconductor device further includes a plurality of scribe lines between the plurality of chip regions. In some instances, the semiconductor device further includes a first plurality of alignment mark regions distributed within the plurality of scribe lines. In some embodiments, the semiconductor device further includes a second plurality of alignment mark regions distributed within each of the plurality of chip regions.

[0059] In some embodiments, the first plurality of alignment mark regions are located both at one or more exposure field corners and between adjacent chip regions of the plurality of chip regions.

[0060] In some embodiments, the second plurality of alignment mark regions are evenly distributed in the entire area of ​​each chip region of the plurality of chip regions.

[0061] In some embodiments, the second plurality of alignment mark areas includes at least one alignment mark area within each quadrant of each chip area of ​​the plurality of chip areas.

[0062] In some embodiments, each of the first plurality of alignment mark regions and the second plurality of alignment mark regions includes cells having a pattern defining an alignment mark.

[0063] In some embodiments, a dummy pattern is disposed adjacent to the cell within each of the first plurality of alignment mark regions and the second plurality of alignment mark regions.

[0064] In some embodiments, first cells within the first plurality of alignment mark areas have a first pattern, and second cells within the second plurality of alignment mark areas have a second pattern different from the first pattern.

[0065] In some embodiments, the pattern comprises an array of patterns having a constant duty cycle.

[0066] In some embodiments, the pattern comprises an array of patterns having a varying duty cycle, and the varying duty cycle is provided by at least one of varying widths of individual patterns of the array of patterns and varying pitches of adjacent patterns of the array of patterns.

[0067] In some embodiments, the pattern comprises an array of patterns having a first duty cycle along a first direction and a second duty cycle along a second direction different from the first direction.

[0068] In some embodiments, the pattern comprises an array of patterns having a duty cycle ranging from about 0.5 to about 3.

[0069] In another embodiment, an IC manufacturing system is discussed, including a lithography system, one or more metrology tools, and a lithography correction system. In some embodiments, the lithography system is configured to form a pattern on a substrate including a plurality of chip regions, wherein the pattern includes a plurality of alignment mark regions distributed within each of the plurality of chip regions and within scribe lines between the plurality of chip regions. In some cases, one or more metrology tools are configured to inspect the pattern to provide overlay data. In some embodiments, the lithography correction system is coupled to receive overlay data from the one or more metrology tools. In various instances, the lithography correction system is configured to make one or more adjustments to the lithography system based on the received overlay data.

[0070] In some embodiments, the lithography correction system is integrated into the lithography system.

[0071] In some embodiments, the IC manufacturing system further includes: one or more etching tools configured to etch the substrate so that the pattern is transferred to an underlying material layer; wherein the one or more metrology tools are configured to inspect the pattern transferred to the underlying material layer to provide additional overlay data; wherein the lithography correction system is also coupled to receive the additional overlay data from the one or more metrology tools; and wherein the lithography correction system is configured to perform the one or more adjustments to the lithography system based on the received additional overlay data.

[0072] In some embodiments, the one or more adjustments are configured to correct one or more of translation errors, rotation errors, and higher-order errors.

[0073] In some embodiments, each of the plurality of alignment mark regions includes a cell having a pattern defining an alignment mark, and a dummy pattern is disposed adjacent to the cell.

[0074] In some embodiments, the cells within the alignment mark region disposed in each of the plurality of chip regions have a first pattern, and the cells within the alignment mark region disposed in each of the scribe lines have a second pattern different from the first pattern. In another embodiment, a method is discussed, the method comprising, on a substrate having a plurality of chip regions, forming a first plurality of alignment marks in each chip region, and forming a second plurality of alignment marks in the scribe lines between the plurality of chip regions. In some embodiments, the method further comprises determining an offset distance based on overlay data corresponding to the first and second plurality of alignment marks. In some instances, the method further comprises providing an adjustment to the lithography system based on the determined offset distance. In some embodiments, the method further comprises, after adjusting the lithography system, performing a lithography process to pattern a target component on the substrate.

[0075] In some embodiments, the first plurality of alignment marks are evenly distributed in the entire area of ​​each chip region of the plurality of chip regions, and the second plurality of alignment marks are located both at one or more exposure field corners and between adjacent chip regions of the plurality of chip regions.

[0076] In some embodiments, the first plurality of alignment marks have a first pattern and the second plurality of alignment marks have a second pattern different from the first pattern.

[0077] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate including a plurality of chip regions; a plurality of scribe lines, wherein the scribe lines are located between the plurality of chip regions; a first plurality of alignment mark areas distributed within the plurality of scribe lines; as well as A second plurality of alignment mark regions are distributed within each of the plurality of chip regions.

2. The semiconductor device according to claim 1, wherein The first plurality of alignment mark regions are located at one or more exposure field corners and between adjacent chip regions of the plurality of chip regions.

3. The semiconductor device according to claim 1, wherein The second plurality of alignment mark regions are uniformly distributed throughout an entire region of each of the plurality of chip regions.

4. The semiconductor device according to claim 1, wherein: The second plurality of alignment mark areas includes at least one alignment mark area within each quadrant of each chip area of ​​the plurality of chip areas.

5. The semiconductor device according to claim 1, wherein Each of the first plurality of alignment mark regions and the second plurality of alignment mark regions includes cells having a pattern defining an alignment mark.

6. An integrated circuit IC manufacturing system, comprising: A photolithography system configured to form a pattern on a substrate including a plurality of chip regions, wherein the pattern includes a plurality of alignment mark regions distributed within each of the plurality of chip regions and within scribe lines between the plurality of chip regions; one or more metrology tools configured to inspect the pattern to provide overlay data; and a lithography correction system coupled to receive the overlay data from the one or more metrology tools; The photolithography correction system is configured to adjust the photolithography system one or more times based on the received overlay data.

7. The IC manufacturing system according to claim 6, wherein: The lithography correction system is integrated into the lithography system.

8. The IC manufacturing system according to claim 6, further comprising: one or more etching tools configured to etch the substrate so that the pattern is transferred to an underlying material layer; wherein the one or more metrology tools are configured to inspect the pattern transferred to the underlying material layer to provide additional overlay data; wherein the lithography correction system is further coupled to receive the additional overlay data from the one or more metrology tools; and The lithography correction system is configured to perform the one or more adjustments to the lithography system based on the received additional overlay data.

9. The IC manufacturing system according to claim 6, wherein: The one or more adjustments are configured to correct one or more of translation errors, rotation errors, and higher-order errors.

10. A photolithography method comprising: On a substrate including a plurality of chip regions, forming a first plurality of alignment marks in each chip region, and forming a second plurality of alignment marks in scribe lines between the plurality of chip regions; determining an offset distance based on overlay data corresponding to the first plurality of alignment marks and the second plurality of alignment marks; providing an adjustment to a lithography system based on the determined offset distance; as well as After the adjustments are made to the lithography system, a lithography process is performed to pattern a target feature on the substrate.

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