Memory device and control method for controlling memory device

Abstract

The present disclosure provides a memory device and a control method for the memory device. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit performs access to the memory array. The control logic circuit counts the number of accesses performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an access memory cell row among the memory cell rows is greater than or equal to a threshold value generated using a random number corresponding to the access memory cell row, the control logic circuit arranges memory cell rows in the vicinity of the access memory cell row into a mitigation operation.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a control method for controlling the memory device, and more particularly, to a memory device and a control method for mitigating row-hammer attacks. Background Art

[0002] Generally, a memory device performs a mitigation operation on a memory cell row in a memory array to prevent a row hammering event. When the number of accesses to a memory cell row reaches a threshold, the memory device performs a mitigation operation to refresh memory cell rows near a memory cell row that is frequently accessed within a short period of time.

[0003] However, an external attacker (e.g., a hacker or a malicious program) obtains mitigation operations based on a threshold. Therefore, based on the threshold, the external attacker can target a specific row of memory cells for writing, or cause a large number of accesses to reach the threshold in a very short period. The above-mentioned row-hammer attack can make the memory device busy, thereby reducing the performance of the memory device or disturbing specific memory cells. Therefore, how to mitigate row-hammer attacks is one of the research and development focuses of technicians in the field. Summary of the invention

[0004] The present disclosure provides a memory device and a control method of the memory device for mitigating row hammer attacks on the memory device.

[0005] The memory device includes a storage array and a control logic circuit. The storage array includes a plurality of storage cell rows. The control logic circuit is coupled to the storage array. The control logic circuit performs access to the storage array. The control logic circuit includes a counter, a random value generator, and a comparator. The counter counts the number of accesses performed on the storage cell row to generate a count value corresponding to an access storage cell row among the plurality of storage cell rows. The random value generator generates a threshold using a random value corresponding to the access storage cell row. The comparator compares the threshold with the count value. When the count value corresponding to the access storage cell row is greater than or equal to the threshold, the control logic circuit arranges the storage cell row near the access storage cell row into a mitigation operation.

[0006] The control method is used to control a memory device. The control method includes: providing a count value corresponding to an access memory cell row among a plurality of memory cell rows; reading the count value stored in the access memory cell row; generating a threshold using a random number corresponding to the access memory cell row; comparing the count value with the threshold; and arranging a memory cell row near the access memory cell row to a mitigation operation when the count value is greater than or equal to the threshold.

[0007] Based on the above, the threshold values ​​are random values. An external attacker (e.g., a hacker or a malicious program) cannot obtain the threshold values. An external attacker cannot obtain the mitigation operation disclosed herein. Therefore, the memory device can mitigate the row hammer attack.

[0008] In order to make the above contents easier to understand, several embodiments accompanied by drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0010] Figure 1 A schematic diagram showing a memory device according to a first embodiment of the present disclosure;

[0011] Figure 2 A schematic diagram showing a memory device according to a second embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram showing a threshold segment according to an embodiment of the present disclosure;

[0013] Figure 4 A schematic diagram showing a memory array according to an embodiment of the present disclosure;

[0014] Figure 5 A schematic diagram showing a memory array according to an embodiment of the present disclosure;

[0015] Figure 6 A circuit diagram showing an input / output circuit, a sense amplifier, a voltage balancing circuit, and a count value register according to an embodiment of the present disclosure;

[0016] Figure 7 Show according to Figure 6 Operation diagram of reading the count value of the count value register in the precharge phase;

[0017] Figure 8 Show according to Figure 6 Operation diagram for reading the count value of the count value register;

[0018] Fig. 9 A flow chart of a control method according to an embodiment of the present disclosure is shown.

[0019] Description of Reference Numerals

[0020] 100, 200: Memory device

[0021] 110, 310, 310': Storage array

[0022] 120, 220: Control logic circuit

[0023] 121, 122: Comparator

[0024] 223: Value register

[0025] 224: Random Value Generator

[0026] 330_1~330_n、330_1'~330_n':Count value register

[0027] 440_1: Input / output circuit

[0028] 450_1: Sense amplifier

[0029] 460_1: Voltage balancing circuit

[0030] 2231: Threshold segment

[0031] B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14: bits

[0032] BF1, BF2: Buffer

[0033] BL1: bit line

[0034] BL1B: Reverse Phase Line

[0035] CMC, CMC1_1, CMC1_2, CMC1_n, CMC2_1, CMC2_2, CMC2_n, CMC3_1, CMC3_2, CMC3_n, MC: Storage unit

[0036] CS: Column select signal

[0037] CV1, CV2, CV3~CVm, CVn: count value

[0038] DB: Bit data

[0039] DR1: Reset data

[0040] DR1B: Inverted reset data

[0041] DW1: Write data

[0042] DW1B: write data in reverse phase

[0043] EQ: Equalize the signal

[0044] H: High voltage level

[0045] L: Low voltage level

[0046] MR_1, MR_2, MR_3, MR_4, MR_5~MR_(m-2), MR_(m-1), MR_(m+1), MR_(m+2)~MR_n: storage unit row

[0047] S100: Control Methods

[0048] S110, S120, S130, S140, S150, S160: Steps

[0049] SA: Output sense voltage

[0050] SAN: First sensing voltage

[0051] SAP: Second sensing voltage

[0052] SC1, SC2: Selection circuit

[0053] SS: Mode selection signal

[0054] SW1, SW2, SW3: switches

[0055] SWL1: word line signal

[0056] TCS1, TCS2: select transistor

[0057] TD: Time Length

[0058] TN1, TN2: N-type transistor

[0059] TP1, TP2: Time point / P-type transistor

[0060] TR1: First readout terminal

[0061] TR2: Second readout terminal

[0062] TV1: First threshold / threshold

[0063] TV2: Second threshold / threshold

[0064] TV3~TVm, TVn: Threshold

[0065] TWE1: Write enable transistor / first write enable transistor

[0066] TWE2: Write enable transistor / second write enable transistor

[0067] VREF: reference voltage

[0068] WE: Write enable signal

[0069] WL1: word line DETAILED DESCRIPTION

[0070] The present disclosure may be understood by referring to the following detailed description in conjunction with the drawings described below. It should be noted that, for the sake of clarity of illustration and ease of understanding by the reader, the various drawings of the present disclosure illustrate a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. In addition, the number and size of each device shown in the drawings are merely illustrative and are not intended to limit the scope of the present disclosure.

[0071] Certain terms are used throughout the description and the appended claims to refer to specific components. As will be understood by those skilled in the art, electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components that have different names but the same function. In the following description and in the claims, the terms "include", "comprise", and "have" are used in an open-ended manner and should therefore be interpreted to mean "but the disclosure is not limited thereto". Therefore, when the terms "include", "comprises", and / or "have" are used in the description of the present disclosure, it will indicate the presence of corresponding features, regions, steps, operations, and / or components, but is not limited to the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0072] It should be understood that when an element is said to be “coupled to”, “connected to” or “conducted to” another element, the element may be directly connected to the other element and a direct electrical connection may be established, or an intermediate element may exist between the element and the other element for relaying the electrical connection (indirect electrical connection). In contrast, when an element is said to be “directly coupled to”, “directly conducted to” or “directly connected to” another element, there are no intermediate elements.

[0073] Figure 1 FIG. 2 is a schematic diagram showing a memory device according to a first embodiment of the present disclosure. Figure 1In the present embodiment, the memory device 100 includes a memory array 110 and a control logic circuit 120. The memory array 110 may be a dynamic random access memory (DRAM) memory array, but the present disclosure is not limited thereto. The memory array 110 includes memory cell rows MR_1 to MR_n. The control logic circuit 120 is coupled to the memory array 110. The control logic circuit performs accesses on the memory array. In the present embodiment, the control logic circuit 120 includes a counter 121 and a comparator 122. The counter 121 counts the number of accesses performed on the memory cell rows to generate count values ​​CV1 to CVn corresponding to the memory cell rows MR_1 to MR_n. For example, the count value CV1 is the number of accesses performed on the memory cell row MR_1. The count value CV2 is the number of accesses performed on the memory cell row MR_2, and so on.

[0074] The comparator 122 compares the threshold values ​​TV1 to TVn corresponding to the memory cell rows and the count values ​​CV1 to CVn. For example, the threshold value TV1 corresponds to the memory cell row MR_1. The comparator 122 compares the threshold value TV1 with the count value CV1 to generate a first result. The threshold value TV2 corresponds to the memory cell row MR_2. The comparator 122 compares the threshold value TV2 with the count value CV2 to generate a second result, and so on.

[0075] In the present embodiment, the control logic circuit 120 resets the count values ​​CV1 to CVn based on the time length TD, and sets the threshold values ​​TV1 to TVn based on the time length TD. In the present embodiment, the threshold values ​​TV1 to TVn are random values, respectively.

[0076] For example, the time length TD is associated with the refresh cycle of the memory array 110. For example, the time length TD may be 32 milliseconds, but the present disclosure is not limited thereto. Therefore, the time length TD is the refresh cycle of the memory array 110. The count values ​​CV1 to CVn are reset according to the time length TD. In addition, the thresholds TV1 to TVn are reset based on the time length TD.

[0077] It should be noted that the thresholds TV1 to TVn are random values ​​and are set again based on the time length TD. An external attacker (e.g., a hacker or a malicious program) cannot obtain the thresholds TV1 to TVn. An external attacker cannot obtain the mitigation operation of row hammering. Therefore, the memory device 100 mitigates row hammering attacks from external attackers.

[0078] In this embodiment, each count value CV1 to CVn is stored in a corresponding row. For example, the count value CV1 is stored in the memory cell row MR_1, the count value CV2 is stored in the memory cell row MR_2, and so on.

[0079] The control logic circuit 120 performs access to the memory array 110 and reads the count values ​​CV1 to CVn. Taking the count value CV3 as an example, when the memory cell row MR_3 (i.e., the access memory cell row) is accessed and written (e.g., an internal write operation), the counter 121 increments the count value CV3. On the contrary, when the memory cell row MR_3 is not accessed and written, the counter 121 stops incrementing the count value CV3. The comparator 122 compares the count value CV3 with the threshold TV3. When the count value CV3 is greater than or equal to the threshold TV3, the comparator 122 notifies the control logic circuit 120. Therefore, the control logic circuit 120 arranges the memory cell rows MR_1, MR_2, MR_4, and MR_5 near the memory cell row MR_3 into a mitigation operation (e.g., recharging the memory cell row within an appropriate time period). When the count value CV3 is less than the threshold value TV3, the counter 121 increments the count value CV3 when the memory cell row MR_3 is accessed. In addition, when the memory cell rows MR_1, MR_2, MR_4, and MR_5 near the memory cell row MR_3 are arranged in the mitigation operation, the control logic circuit 120 resets the count value CV3 to an initial value (e.g., "0").

[0080] Taking the count value CVm (not shown, the number "m" is at least "2" less than the number "n") as an example, when the count value CVm is greater than or equal to the threshold TVm, the control logic circuit 120 arranges the storage cell rows MR_(m-2), MR_(m-1), MR_(m+1) and MR_(m+2) into the mitigation operation.

[0081] In the present embodiment, the counter 121 is a per-row-hammer-tracking (PRHT) counter.

[0082] In this embodiment, the control logic circuit 120 generates a threshold value when reading the corresponding count value. For example, the control logic circuit 120 generates a threshold value TV1 when reading the count value CV1. For example, the control logic circuit 120 generates a threshold value TV2 when reading the count value CV2.

[0083] Figure 2 FIG. 2 is a schematic diagram showing a memory device according to a second embodiment of the present disclosure. Figure 2In this embodiment, the memory device 200 includes a memory array 110 and a control logic circuit 220. The control logic circuit 220 includes a counter 121, a comparator 122, a value register 223, and a random value generator 224. The operations between the memory array 110, the counter 121, and the comparator 122 have been described in detail. Figure 1 This is clearly explained in the illustrated embodiment and therefore will not be repeated here.

[0084] In the present embodiment, the random value generator 224 is coupled to the value register 223. The random value generator 224 generates threshold values ​​TV1 to TVn. In the present embodiment, when the control logic circuit 220 reads the count value CV1 from the access storage cell row MR_1, the random value generator 224 generates a first threshold value TV1 corresponding to the access storage cell row MR_1. When the control logic circuit 220 reads the count value CV2 from the access storage cell row MR_2, the random value generator 224 generates a second threshold value TV2 corresponding to the access storage cell row MR_2, and so on. Therefore, an external attacker cannot obtain the threshold value. The threshold values ​​TV1 to TVn are random values, respectively.

[0085] For example, the random value generator 224 uses a linear feedback shift register (LFSR) to generate the threshold values ​​TV1 to TVn. For example, the random value generator 224 includes a Fibonacci-type LFSR or a Galois-type LFSR. Therefore, each of the threshold values ​​TV1 to TVn is a random value having a number of bits. In the present embodiment, the value register 223 stores the threshold values ​​TV1 to TVn. For example, the value register 223 includes a threshold value segment for storing the threshold values ​​TV1 to TVn.

[0086] Figure 3 A schematic diagram showing a threshold segment according to an embodiment of the present disclosure is shown. Figure 2 and Figure 3In the present embodiment, the threshold segment 2231 of the value register 223 is used to store the threshold TV1. The threshold TV1 includes a first number of bits. For example, the threshold segment 2231 is a segment having 15 bits B0 to B14, but the present disclosure is not limited thereto. Therefore, the threshold TV1 is a value of 15 bits (i.e., the first number is "15"), but the present disclosure is not limited thereto. In addition, the threshold TV1 includes a second number of bits in the first number generated by the random value generator 224. For example, the threshold TV1 includes 9 random value bits (i.e., the second number is "9"), but the present disclosure is not limited thereto. The first number is greater than or equal to the second number. In addition, the second number is greater than zero. Each of the bit values ​​of the random value bits is a random value. At the time point TP1, bits B2 to B10 are set as random value bits. For example, the time point TP1 is a time point for reading the count value CV1.

[0087] At time point TP2, bits B4 to B12 are set to random value bits. For example, the random value bits of the threshold value TV1 in the threshold segment 2231 are shifted based on the time length TD. For example, the random value bits of the threshold value TV1 in the threshold segment 2231 are shifted based on the refresh cycle of the memory device. In addition, the threshold value TV1 is a changing random value. Therefore, it is not easy for an external attacker to know the threshold value TV1. For another example, the time point TP2 may be another time point for reading the count value CV1.

[0088] In addition, bits B13 and B14 are not set to random value bits. Therefore, the threshold TV1 is not too low. For example, each bit value of bits B13 and B14 is "1".

[0089] Figure 4 A schematic diagram of a storage array according to an embodiment of the present disclosure is shown. Figure 4 In the present embodiment, the memory array 310 includes memory cell rows MR_1 to MR_n. The memory cell row MR_1 includes a memory cell MC and a count value register 330_1. The count value register 330_1 includes memory cells CMC1_1 to CMC3_1 for storing a count value CV1. The memory cells CMC1_1 to CMC3_1 are adjacent to each other. The memory cell row MR_2 includes a memory cell MC and a count value register 330_2. The count value register 330_2 includes memory cells CMC1_2 to CMC3_2 for storing a count value CV2. The memory cells CMC1_2 to CMC3_2 are adjacent to each other. Similarly, the memory cell row MR_n includes a memory cell MC and a count value register 330_n. The count value register 330_n includes memory cells CMC1_n to CMC3_n for storing a count value CVn. The memory cells CMC1_n to CMC3_n are adjacent to each other.

[0090] In this embodiment, each of the memory cell rows MR_1 to MR_n corresponds to a different word line. For example, when the memory cell row MR_1 is asserted by a word line signal on the first word line, the count value CV1 stored in the count value register 330_1 can be read.

[0091] Furthermore, the memory cells CMC1_1 to CMC1_n are formed as a first memory cell column. The memory cells CMC2_1 to CMC2_n are formed as a second memory cell column. The memory cells CMC3_1 to CMC3_n are formed as a third memory cell column.

[0092] In this embodiment, each of the count value registers 330_1 to 330_n includes three storage units for storing the corresponding count value, but the present disclosure is not limited thereto. Figure 3 In the threshold segment 2231, each of the count value registers 330_1 to 330_n may include a 15-bit storage unit.

[0093] Taking the count value register 330_1 and the memory cell row MR_1 as an example, the control logic circuit resets the count value register 330_1 by overwriting the reset data based on the preset time length TD, and provides write data to the memory cells in the memory cell row MR_1 in the write operation. For another example, the control logic circuit resets the count value register 330_1 after arranging the memory cell rows near the memory cell row MR_1 in the mitigation operation.

[0094] Figure 5 A schematic diagram of a storage array according to an embodiment of the present disclosure is shown. Figure 5In the present embodiment, the memory array 310' includes memory cell rows MR_1 to MR_n. The memory cell row MR_1 includes a memory cell MC and a count value register 330_1'. The count value register 330_1' includes memory cells CMC1_1 to CMC3_1 for storing a count value CV1. The memory cells CMC1_1 to CMC3_1 are not adjacent to each other. The memory cell row MR_2 includes a memory cell MC and a count value register 330_2. The count value register 330_2 includes memory cells CMC1_2 to CMC3_2 for storing a count value CV2. The memory cells CMC1_2 to CMC3_2 are not adjacent to each other. Similarly, the memory cell row MR_n includes a memory cell MC and a count value register 330_n. The count value register 330_n includes memory cells CMC1_n to CMC3_n for storing a count value CVn. The memory cells CMC1_n to CMC3_n are not adjacent to each other. Furthermore, the memory cells CMC1_1 to CMC1_n are formed as a first memory cell column. The memory cells CMC2_1 to CMC2_n are formed as a second memory cell column. The memory cells CMC3_1 to CMC3_n are formed as a third memory cell column.

[0095] Figure 6 FIG. 1 is a circuit diagram showing an input / output circuit, a sense amplifier, a voltage balancing circuit, and a count value register according to an embodiment of the present disclosure. Figure 1 and Figure 6 The memory device includes a plurality of sense amplifiers, a plurality of voltage equalization circuits, and a plurality of count value registers corresponding to the memory cell columns of the memory array (not shown). In this embodiment, Figure 6 An input / output circuit 440_1 among a plurality of input / output circuits of the memory device 100 , a sense amplifier 450_1 among a plurality of sense amplifiers, a voltage equalizing circuit 460_1 among a plurality of voltage equalizing circuits, and a count value register 330_1 ′ among a plurality of count value registers are shown.

[0096] In the present embodiment, the input / output circuit 440_1 is coupled to the memory cell row MR_1 and the control logic circuit 120. The input / output circuit 440_1 is coupled to the count value register 330_1′ arranged in the memory cell row MR_1 and the control logic circuit 120. The input / output circuit 440_1 includes selection circuits SC1 and SC2, write enable transistors TWE1 and TWE2, and selection transistors TCS1 and TCS2. The selection circuit SC1 is coupled to the control logic circuit 120. The selection circuit SC1 outputs one of the reset data DR1 and the write data DW1 in response to the mode selection signal SS. The selection circuit SC2 is coupled to the control logic circuit 120. The selection circuit SC2 outputs one of the inverted reset data DR1B and the inverted write data DW1B in response to the mode selection signal SS. When the count value register 330_1′ is reset, the control logic circuit 120 provides the reset data DR1 to the selection circuit SC1, and provides the inverted reset data DR1B to the selection circuit SC2. The reset data DR1 and the inverted reset data DR1B are complementary to each other. When a write operation is performed on the memory cell row MR_1, the control logic circuit 120 provides the write data DW1 to the selection circuit SC1 and provides the inverted write data DW1B to the selection circuit SC2. The write data DW1 and the inverted write data DW1B are complementary to each other. The selection circuit SC1 outputs the reset data DR1 to the bit line BL1 in response to the mode selection signal SS having a first value. The selection circuit SC2 outputs the inverted reset data DR1B to the inverted bit line BL1B in response to the mode selection signal SS having a first value. The selection circuit SC1 outputs the write data DW1 to the bit line BL1 in response to the mode selection signal SS having a second value. The selection circuit SC2 outputs the inverted write data DW1B to the inverted bit line BL1B in response to the mode selection signal SS having a second value. Each of the selection circuits SC2 and SC1 can be implemented by a multiplexer (MUX).

[0097] A first terminal of the write enable transistor TWE1 is coupled to an output terminal of the selection circuit SC1. A second terminal of the write enable transistor TWE1 is coupled to a first readout terminal TR1. A control terminal of the write enable transistor TWE1 receives a write enable signal WE. A first terminal of the write enable transistor TWE2 is coupled to an output terminal of the selection circuit SC2. A second terminal of the write enable transistor TWE2 is coupled to a second readout terminal TR2. A control terminal of the write enable transistor TWE2 receives a write enable signal WE.

[0098] A first terminal of the selection transistor TCS1 is coupled to a first readout terminal TR1. A second terminal of the selection transistor TCS1 is coupled to a bit line BL1. A control terminal of the selection transistor TCS1 receives a column selection signal CS. A first terminal of the selection transistor TCS2 is coupled to a second readout terminal TR2. A second terminal of the selection transistor TCS2 is coupled to an inverted bit line BL1B. A control terminal of the selection transistor TCS2 receives a column selection signal CS.

[0099] In this embodiment, the input / output circuit 440_1 further includes buffers BF1 and BF2. The input terminal of the buffer BF1 is coupled to the output terminal of the selection circuit SC1. The output terminal of the buffer BF1 is coupled to the first terminal of the first write enable transistor TWE1. The input terminal of the buffer BF2 is coupled to the output terminal of the selection circuit SC2. The output terminal of the buffer BF2 is coupled to the first terminal of the second write enable transistor TWE2.

[0100] In the present embodiment, the sense amplifier 450_1 includes N-type transistors TN1 and TN2 and P-type transistors TP1 and TP2. The first terminal of the N-type transistor TN1 is coupled to the bit line BL1. The second terminal of the N-type transistor TN1 receives the first sense voltage SAN. The control terminal of the N-type transistor TN1 is coupled to the inverted bit line BL1B. The first terminal of the N-type transistor TN2 is coupled to the second terminal of the N-type transistor TN1. The second terminal of the N-type transistor TN2 is coupled to the inverted bit line BL1B. The control terminal of the N-type transistor TN2 is coupled to the bit line BL1. The first terminal of the P-type transistor TP1 is coupled to the bit line BL1. The second terminal of the P-type transistor TP1 receives the second sense voltage SAP. The control terminal of the P-type transistor TP1 is coupled to the inverted bit line BL1B. The first terminal of the P-type transistor TP2 is coupled to the second terminal of the P-type transistor TP1. The second terminal of the P-type transistor TP2 is coupled to the inverted bit line BL1B. The control terminal of the P-type transistor TP2 is coupled to the bit line BL1.

[0101] In the present embodiment, the voltage equalization circuit 460_1 includes switches SW1 to SW3. A first terminal of the switch SW1 is coupled to the bit line BL1. A second terminal of the switch SW1 receives a reference voltage VREF. A control terminal of the switch SW1 receives an equalization signal EQ. A first terminal of the switch SW2 receives the reference voltage VREF. A second terminal of the switch SW2 is coupled to the inverted bit line BL1B. A control terminal of the second switch receives the equalization signal EQ. A first terminal of the switch SW3 is coupled to the bit line BL1. A second terminal of the switch SW3 is coupled to the inverted bit line BL1B. A control terminal of the switch SW3 receives the equalization signal EQ.

[0102] In the present embodiment, each of the write enable transistors TWE1 and TWE2, the selection transistors TCS1 and TCS2, the N-type transistors TN1 and TN2, and the switches SW1 to SW3 may be implemented by an N-type metal-oxide-semiconductor (NMOS) transistor. Each of the P-type transistors TP2 and TP1 may be implemented by a P-type metal-oxide-semiconductor (PMOS) transistor.

[0103] In the present embodiment, when the control logic circuit 120 resets the count value stored in the memory cell CMC, the write enable signal WE and the column select signal CS have a high voltage level "H". The equalization signal EQ has a low voltage level "L". Therefore, the write enable transistors TWE1, TWE2 and the selection transistors TCS1, TCS2 are turned on in response to the high voltage level "H" of the write enable signal WE and the high voltage level "H" of the column select signal CS. The input / output circuit 440_1 provides the reset data DR1 to the bit line BL1 and provides the inverted reset data DR1B to the inverted bit line BL1B. The switches SW1 to SW3 are turned off in response to the low voltage level "L" of the equalization signal EQ. Therefore, the voltage equalization circuit 460_1 is disabled in response to the low voltage level "L" of the equalization signal EQ.

[0104] In addition, the memory cell CMC of the count value register 330_1' receives the word line signal SWL1 having a high voltage level "H" through the word line WL1. The memory cell CMC is selected. Therefore, the reset data DR1 is written into the memory cell CMC. The memory cell CMC is reset. The reset data DR1 in the memory cell CMC is the initial data before the count value register 330_1' counts the write operation of the access performed on the memory cell row MR_1.

[0105] In this embodiment, the mode selection signal SS, the column selection signal CS, the write enable signal WE and the equalization signal EQ may be provided by the control logic circuit 120 .

[0106] Figure 7 Show according to Figure 6 The operation diagram of reading the count value of the count value register in the precharge phase. Figure 1 and Figure 7In the present embodiment, when the control logic circuit 120 reads the bit data of the count value of the count value register 330_1', the equalization signal EQ has a high voltage level "H" in the precharge phase. The switches SW1 to SW3 are turned on in response to the high voltage level "H" of the equalization signal EQ. The voltage equalization circuit 460_1 is enabled in the precharge phase. In the precharge phase, the voltage equalization circuit 460_1 precharges the bit line BL1 and the inverted bit line BL1B using the reference voltage VREF. Therefore, the voltage value of the voltage on the bit line BL1 and the inverted bit line BL1B is substantially equal to the voltage value of the reference voltage VREF. For example, the voltage value of the reference voltage VREF is half of the system voltage of the memory device, but the present disclosure is not limited thereto.

[0107] The memory cell CMC of the count value register 330_1 ′ receives the word line signal SWL1 having a low voltage level “L” through the word line WL1 . Therefore, the memory cell CMC cannot output the bit data of the count value.

[0108] Furthermore, when the control logic circuit 120 reads the bit data of the count value of the count value register 330_1 ′, the write enable signal WE has a low voltage level “L.” Therefore, when the control logic circuit 120 reads the bit data of the count value of the count value register 330_1 ′, the input / output circuit 440_1 stops transmitting any data.

[0109] Figure 8 Show according to Figure 6 The operation diagram of reading the count value of the count value register in the access phase and the sensing phase. Figure 6 and Figure 8 In the present embodiment, after the precharge phase, the voltage equalization circuit 460_1 is disabled in response to the low voltage level "L" of the equalization signal EQ in the access phase. The memory cell CMC receives the word line signal SWL1 having the low voltage level "L" through the word line WL1, and outputs the bit data DB to the bit line BL1 in the access phase. When the bit line BL1 is "1", the voltage value on the bit line BL1 is higher than the voltage value of the reference voltage VREF. When the bit line BL1 is "0", the voltage value on the bit line BL1 is lower than the voltage value of the reference voltage VREF.

[0110] The sense amplifier 450_1 selects one of the first sensing voltage SAN and the second sensing voltage SAP as the output sensing voltage SA according to the bit data DB of the count value in the sensing phase. The first sensing voltage SAN has a low voltage level “L”. The second sensing voltage SAP has a high voltage level “H”.

[0111] For example, when the bit line BL1 is "1", the voltage value on the bit line BL1 is higher than the voltage value of the reference voltage VREF. The P-type transistor TP2 is turned off. The N-type transistor TN2 is turned on and transmits the first sensing voltage SAN to the inverting bit line BL1B. The voltage value on the inverting bit line BL1B has a low voltage level "L". Therefore, the N-type transistor TN1 is turned off. The P-type transistor TP1 is turned on and transmits the second sensing voltage SAP to the bit line BL1. The voltage value on the bit line BL1 has a high voltage level "H". Therefore, when the bit line BL1 is "1", the voltage value on the inverting bit line BL1B has a low voltage level "L". The voltage value on the bit line BL1 has a high voltage level "H". In the sensing phase, the column selection signal CS has a high voltage level "H". In other words, when the bit line BL1 is "0", the sense amplifier 450_1 selects the second sensing voltage SAP as the output sensing voltage SA. When the bit line BL1 is “0”, the input / output circuit 440_1 outputs a high voltage level “H” to the first readout terminal TR1 , and outputs a low voltage level “L” to the second readout terminal TR2 .

[0112] In addition, the sense amplifier 450_1 recovers the memory cell CMC with the second sense voltage SAP. Therefore, when the control logic circuit 120 reads the bit data of the count value of the count value register 330_1 ′, the bit data DB stored in the memory cell CMC does not change.

[0113] For example, when the bit line BL1 is "0", the voltage value on the bit line BL1 is lower than the voltage value of the reference voltage VREF. The N-type transistor TN2 is turned off. The P-type transistor TP2 is turned on and transmits the second sensing voltage SAP to the inverting bit line BL1B. The voltage value on the inverting bit line BL1B has a high voltage level "H". Therefore, the P-type transistor TP1 is turned off. The N-type transistor TN1 is turned on and transmits the first sensing voltage SAN to the bit line BL1. The voltage value on the bit line BL1 has a low voltage level "L". Therefore, when the bit line BL1 is "0", the voltage value on the inverting bit line BL1B has a low voltage level "L". The voltage value on the bit line BL1 has a high voltage level "H". In other words, when the bit line BL1 is "0", the sense amplifier 450_1 selects the first sensing voltage SAN as the output sensing voltage SA. When the bit line BL1 is “0”, the input / output circuit 440_1 outputs a low voltage level “L” to the first readout terminal TR1 , and outputs a high voltage level “H” to the second readout terminal TR2 .

[0114] In addition, the sense amplifier 450_1 recovers the memory cell CMC with the first sensing voltage SAN. Therefore, when the control logic circuit 120 reads the bit data of the count value of the count value register 330_1 ′, the bit data DB stored in the memory cell CMC does not change.

[0115] Fig. 9 A flow chart of a control method according to an embodiment of the present disclosure is shown. Figure 1 and Fig. 9 In the present embodiment, the control method S100 is applicable to the memory device 100. The control method S100 includes steps S110 to S160. In step S110, a count value corresponding to an access memory cell row among the memory cell rows MR_1 and MR_n is provided. In step S120, the control logic circuit 120 reads the count value stored in the access memory cell row. In step S130, the control logic circuit 120 generates a threshold using a random number corresponding to the access memory cell row. In the present embodiment, for example, when comparing the count value CV1 corresponding to the access memory cell row MR_1, the control logic circuit 120 generates a threshold TV1. When comparing the count value CV2 corresponding to the access memory cell row MR_2, the control logic circuit 120 generates a threshold TV2. It should be noted that the thresholds TV1 to TVn are random values, respectively. In addition, for example, the threshold TV1 includes a first number of bits. The threshold TV1 includes a second number of random bits in the first number. The first number is greater than or equal to the second number. The random value bits of the threshold value TV1 in the threshold segment 2231 are shifted based on the time length TD (eg, a refresh cycle of the memory device).

[0116] In step S140, the comparator 122 compares the count value with the threshold. When the count value is greater than or equal to the threshold, in step S150, the control logic circuit 120 arranges the memory cell row near the access memory cell row to the mitigation operation. Then, the control logic circuit 120 returns to step S110.

[0117] On the contrary, when the count value is lower than the threshold value, the count value is incremented when the access memory cell row is accessed. Then, in step S120, the control logic circuit 120 performs access to the memory array 110. The detailed operations of steps S110 to S160 have been described in detail. Figures 1 to 8 The above is clearly explained in the embodiments of the present invention, so it will not be repeated here.

[0118] In summary, the threshold values ​​are random values. The threshold values ​​are generated when the corresponding count values ​​are read. The threshold values ​​are set again based on the length of time. The threshold values ​​cannot be obtained by an external attacker. The mitigation operation disclosed herein cannot be obtained by an external attacker. Therefore, the memory device mitigates the row hammering attack from an external attacker. In addition, the random value bits of the threshold values ​​are shifted in the threshold value segments. Therefore, it is not easy for an external attacker to know the threshold values.

[0119] It will be apparent to those skilled in the art that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the present disclosure. In summary, the present disclosure is intended to cover various modifications and variations as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A memory device, comprising: A storage array including a plurality of storage cell rows; as well as A control logic circuit is coupled to the memory array and configured to access the memory array, wherein the control logic circuit comprises: a counter configured to count the number of accesses performed on the plurality of memory cell rows to generate a count value corresponding to an access memory cell row among the plurality of memory cell rows; a random value generator configured to generate a threshold using a random value corresponding to the access memory cell row; and a comparator configured to compare the threshold value with the count value; When the count value corresponding to the access memory cell row is greater than or equal to the threshold, the control logic circuit arranges memory cell rows adjacent to the access memory cell row to a mitigation operation. 2 . The memory device according to claim 1 , wherein the counter increments the count value of the accessed memory cell row when the count value is less than the threshold value.

3. The memory device according to claim 1, wherein when the control logic circuit reads the count value from the access memory cell row, the random value generator generates the threshold value corresponding to the access memory cell row for comparison with the count value.

4. The memory device of claim 1, wherein the random value generator generates the threshold using a linear feedback shift register.

5. The memory device of claim 1 , wherein the threshold comprises a first number of bits, wherein a second number of bits of the first number of bits of the threshold is generated by the random value generator, and The first number is greater than or equal to the second number, and the second number is greater than zero.

6. The memory device of claim 5, wherein the second number of bits is shifted in the first number of bits based on a length of time.

7. The memory device of claim 1 , wherein the control logic circuit resets the count values ​​stored in the plurality of memory cells of the access memory cell row by overwriting reset data based on a time length or after arranging a memory cell row adjacent to a first memory cell row into the mitigation operation.

8. The memory device of claim 7, further comprising: a plurality of input / output circuits, wherein a first input / output circuit among the plurality of input / output circuits is coupled to a memory cell of the access memory cell row and the control logic circuit, and When the control logic circuit resets the count value stored in the storage unit, the first input / output circuit transmits the reset data to the storage unit through a write operation.

9. The memory device of claim 8, wherein the first input / output circuit comprises: A selection circuit, coupled to the control logic circuit, is configured to selectively output the reset data in response to a mode selection signal.

10. A control method for controlling a memory device, comprising: providing a count value corresponding to an accessed memory cell row among a plurality of memory cell rows; reading the count value stored in the access storage unit row; generating a threshold using a random number corresponding to the access memory cell row; comparing the count value with the threshold; as well as When the count value is greater than or equal to the threshold, a memory cell row adjacent to the access memory cell row is arranged to a mitigation operation.

11. The control method according to claim 10, further comprising: When the count value is greater than or equal to the threshold, the count value is reset to an initial value. 12 . The control method according to claim 10 , wherein a portion of bits of the threshold value is generated by the random number. 13 . The control method according to claim 12 , wherein the part of the bits of the threshold generated by the random number is shifted within a range of the bits of the threshold based on a time length. The control method according to claim 13 , wherein the time length is a refresh period of the memory device.

15. The control method according to claim 10, further comprising: The memory cell row adjacent to the access memory cell row is refreshed in the mitigation operation.

Images