SSD (Solid State Disk) based on chiplet and implementation scheme thereof

Abstract

The invention provides an SSD (Solid State Disk) based on a chiplet technology. The SSD comprises a master chip and a slave chip, the master chip comprises a master front-end module, a read-write distribution hardware module and a master rear-end module, and the slave chip comprises a slave rear-end module; the master front-end module is used for receiving data and requests of the host, replying processing results to the host and the read-write distribution hardware module, segmenting read-write requests and distributing the segmented read-write requests to the master rear-end module and the slave rear-end module; the main rear-end module is used for processing the received partial read-write request and replying a processing result to the main front-end module; and the slave rear-end module is used for processing the received partial read-write request and replying a processing result to the master front-end module. According to the method, the number of rear-end channels of the main control chip of the SSD can be flexibly expanded, more flash memory particles are connected, the SSD capacity and the read-write speed are effectively improved, and meanwhile, the development tape-out cost and risk of the main control chip are controlled.

Description

Technical Field

[0001] The present invention relates to the field of solid-state hard disk storage, and more specifically to a chiplet-based SSD solid-state hard disk and an implementation solution thereof. Background Art

[0002] Today, SSDs continue to develop in terms of speed and capacity. The interface protocol with the host has evolved from SATA to the currently popular PCIE3.04.05.0, and the industry has planned PCIE6.0. The capacity has evolved from the early 128GB-1TB to 2TB, 4TB, and 8TB, which has gradually become the mainstream. Especially in the field of server SSDs, the capacity requirements are higher, and 16TB-128TB ultra-large capacity specifications have appeared. Higher speeds and capacities place higher and higher demands on SSD controllers and SSD solutions, requiring SSD controller chips to adopt higher-level processes, and SSD solution designs are more complex. The improvement of the SSD controller chip process has led to an increase in development costs and tape-out costs, especially because the chips have to be redesigned due to the above-mentioned speed and capacity increases, which consumes huge manpower and financial resources, and also increases the risks of product development and solution implementation.

[0003] Existing SSD solutions include Figure 1 As shown in the figure, the SSD main control chip is responsible for communicating with the host. At the same time, the SSD main control chip is responsible for saving the data written by the host into the flash particles and reading the data from the flash particles back to the host. The SSD main control chip uses DRAM and other resources, and cooperates with the FTL algorithm in the SSD main control to complete the above data read and write operations.

[0004] The existing SSD main control chip is composed of Figure 2 As shown in the figure, the SSD main control chip can be divided into the front end and the back end. The front end is responsible for communicating with the host, and the back end is responsible for communicating with the FTL algorithm and flash memory particles. The SSD speed is limited by the interface protocol between the front end of the main control chip and the host, and the number of flash memory channels at the back end. The SSD capacity is first limited by the number of flash memory particles connected to the back end of the main control chip. The back end of the main control chip requires more flash memory channels to connect more flash memory particles, thereby increasing the SSD capacity. At the same time, a larger capacity also requires a CPU with more powerful computing power, larger and faster DRAM and other resources. The increase and increase of the above resources require more circuit area on the main control chip, and will also increase the power consumption of a single main control chip.

[0005] The existing technical solutions can be summarized into two types. One is not to improve the chip process and technology, but to increase the chip area by adding more computing, storage and flash memory channels. This solution leads to an increase in the single chip area and increased power consumption. The other is to continue to improve the chip process and technology. While adding more computing, storage and flash memory channels, the chip area and power consumption can be controlled to a certain extent, but it also requires greater design and tape-out costs, higher design complexity, and greater tape-out risk.

[0006] The continuous improvement of semiconductor process level has significantly enhanced chip performance, but Moore's Law is gradually approaching the physical limit. In the post-Moore's Law era, the performance benefits brought by process technology improvement are very limited. Constrained by the scaling law, chip power consumption has risen sharply, the performance of a single core has approached the limit, and the performance improvement of multi-core architecture is also slowing down. Summary of the invention

[0007] The purpose of the present invention is to provide an SSD solid state drive and its implementation scheme based on chiplet technology that can support various capacities and scenarios.

[0008] According to one aspect of the present invention, there is provided a chiplet-based SSD solid state drive, comprising a master chip and a slave chip;

[0009] The master chip includes a master front-end module, a read-write distribution hardware module, and a master back-end module, and the slave chip includes a slave back-end module;

[0010] The main front-end module receives data and requests from the host and returns the processing results to the host.

[0011] The read / write distribution hardware module divides the read / write request and distributes it to the master backend module and the slave backend module;

[0012] The main back-end module processes some of the received read and write requests and returns the processing results to the main front-end module;

[0013] The slave back-end module processes part of the received read and write requests, and replies the processing results to the master front-end module.

[0014] In some implementations, the master chip communicates with the slave chip via a high-speed interconnect hardware interface.

[0015] In some implementations, the communication between the master chip and the slave chip is in full-duplex mode, and data can be sent to and received from the opposite end at the same time.

[0016] In some implementations, the main chip communicates with the host via a PCIE front-end interface or a SATA front-end interface.

[0017] In some embodiments, flash memory particles are also included;

[0018] The main back-end module is configured with a plurality of flash memory channels, and the flash memory particles correspond to the flash memory channels one by one;

[0019] The slave backend module is configured with a plurality of flash memory channels, and the flash memory particles correspond to the flash memory channels one by one.

[0020] In some embodiments, a dynamic random access memory is also included.

[0021] According to another aspect of the present invention, there is provided an implementation scheme of an SSD solid state drive based on the chiplet of the claim, wherein the host reads the SSD including:

[0022] The main front-end module receives a read request from the host;

[0023] The read-write distribution hardware module divides the read request and distributes it;

[0024] The main backend module receives a partial read request and reads data from the connected flash memory particles to the memory through the FTL algorithm;

[0025] The receiving of a partial read request from the back-end module reads data from the connected flash memory particles to the memory through the FTL algorithm;

[0026] The main back-end module replies the read data completion status and all data to the main front-end module;

[0027] The slave back-end module replies to the master front-end module with the completion status of the read data and all the data;

[0028] The main front-end module collects and merges the read completion status and all data of the main back-end module and the slave back-end module to reply to the host.

[0029] According to another aspect of the present invention, a chiplet-based SSD solid state drive implementation solution is provided, where a host writes to the SSD including:

[0030] The main front-end module receives a host write request;

[0031] The read-write distribution hardware module divides and distributes the write request according to the set rules;

[0032] The main backend module manages the FTL algorithm and writes to the connected flash memory particles after receiving the partial write request and host data;

[0033] After receiving the partial write request and host data from the back-end module, the FTL algorithm is managed and written into the connected flash memory particles;

[0034] The main back-end module replies to the main front-end module with the completion status of the write operation;

[0035] The slave back-end module replies to the master front-end module with the completion status of the write operation;

[0036] The main front-end module collects and merges the writing completion status of the main back-end module and the slave back-end module and then replies to the host.

[0037] The beneficial effects are as follows: the present invention decouples chip performance from chip process based on chiplet technology. A single-chip solution can be used for scenarios with small capacity and low speed requirements, and dual chips can be used to achieve expansion for scenarios with large capacity and high speed requirements. In this way, support for various capacities and scenarios can be achieved through one chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a schematic diagram of an existing SSD solid state drive;

[0039] Figure 2 A schematic diagram of a main control chip of an existing SSD solid state drive;

[0040] Figure 3 A schematic diagram of a main control chip of a chiplet-based SSD solid state hard disk according to an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of a chiplet-based SSD solid state drive according to an embodiment of the present invention;

[0042] Figure 5 A schematic diagram of an implementation method of a chiplet-based SSD solid state drive host reading data according to an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of an implementation method of a host writing data to an SSD solid state drive based on a chiplet according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the accompanying drawings.

[0045] Figure 3-Figure 4 The chiplet-based SSD solid state drive of the present invention is schematically shown. Figure 3 As shown, the chiplet-based solid-state hard disk includes a main control chip, and the main control chip includes a master chip 1 and a slave chip 2.

[0046] The main chip 1 includes a main front-end module 11, a read-write distribution hardware module 12, a main back-end module 13 and a main high-speed interconnect hardware interface 14 for communication. The main chip 1 is responsible for communicating with the host 5 to receive data and read-write requests from the host 5, and reply the processed data to the host 5. Specifically, the main chip 1 communicates with the host 5 through a PCIE front-end interface or a SATA front-end interface. The main front-end module 11 receives data from the host 5 and replies the processed data to the host 5. The read-write distribution hardware module 12 splits the read-write request and distributes it to the main back-end module 13 and the slave back-end module 21 of the slave chip 2. The main front-end module 11 replies the processing result to the host 5. The main back-end module 13 is configured with a plurality of flash memory channels 131.

[0047] The slave chip 2 is the same as the master chip 1. The slave chip 2 includes a slave backend module 21 and a slave high-speed interconnect interface 22 for communication. The read-write distribution hardware module 12 divides the read-write request and distributes it to the slave backend module 21. The slave backend module 21 processes part of the received read-write request and replies the processing result to the master front-end module 11. The slave backend module 21 processes part of the received read-write request and replies the processing result to the master front-end module 11. The master front-end module 11 replies the processing structure to the host 5. The slave backend module 21 is configured with a plurality of flash memory channels 221.

[0048] The master chip 1 communicates with the slave chip 2 through a high-speed interconnect hardware interface. Specifically, the master backend module 13 communicates with the slave backend module 21 through a high-speed interconnect hardware interface. The communication between the master chip 1 and the slave chip 2 is completed by the read-write distribution hardware module 12. The communication between the master chip 1 and the slave chip 2 is in full-duplex mode, and data can be sent to and received from the opposite end at the same time.

[0049] like Figure 4 As shown, the chiplet-based SSD solid state drive also includes flash memory particles 3 and dynamic random access memory DRAM. The main back-end module 13 is configured with a plurality of flash memory channels 131, and the flash memory particles 3 correspond to the flash memory channels 131 one by one. The slave back-end module 21 is configured with a plurality of flash memory channels 211, and the flash memory particles 4 correspond to the flash memory channels 211 one by one. In this way, the number of back-end channels of the main control chip of the SSD can be flexibly expanded, and more flash memory particles 3 can be connected, which effectively improves the capacity and read and write speed of the SSD, while controlling the cost and risk of the main control chip development tape-out.

[0050] Figure 5-Figure 6A chiplet-based SSD solid state drive implementation scheme is schematically shown, including: the main front-end module 11 of the main chip 1 receives a write request or a read request from the host 5. The data read and write request of the host 5 received by the main chip 1 is distributed according to the rules by the read and write distribution hardware module 12 of the main chip 1, and the read and write distribution hardware module 12 of the main chip 1 divides the read request or the write request according to the set rules and distributes it. The main back-end module 13 of the main chip 1 receives the data of the host 5 and part of the write request or part of the read request, and reads the data from the connected flash memory particle 3 to the internal storage through the FTL algorithm. The data read and write request of the host 5 received by the slave chip 2 is distributed according to the rules by the read and write distribution hardware module 12 of the main chip 1. The slave back-end module 21 of the slave chip 2 receives the data of the host 5 and part of the write request or part of the read request, and reads the data from the connected flash memory particle 4 to the internal storage through the FTL algorithm. The main back-end module 13 of the main chip 1 replies to the main front-end module 11 of the main chip 1 with the completion of the write operation or the completion of the read operation and the read data. The slave backend module 21 of the slave chip 2 replies to the master frontend module 11 of the master chip 1 with the completion of the write operation or the completion of the read operation and the data read. The master frontend module 11 of the master chip 1 collects and merges the read completion status and all data or the write completion status of the master backend module 13 of the master chip 1 and the slave backend module 21 of the slave chip 2 and replies to the host 5.

[0051] like Figure 5 As shown, the host 5 reads the SSD solid state drive including: the main front-end module 11 of the main chip 1 accepts the read request of the host 5, and the read-write distribution hardware module 12 of the main chip 1 divides the read request according to the set rules and distributes it to the main back-end module 13 and the slave back-end module 21. The main back-end module 13 of the main chip 1 receives part of the read request and reads data from the connected flash memory particles 3 to the memory through the FTL algorithm. The memory here includes DRAM and other storage elements in the SSD. The slave back-end module 21 of the slave chip 2 receives part of the read and write request and reads data from the connected flash memory particles 4 to the memory through the FTL algorithm. The main back-end module 13 of the main chip 1 replies the read operation completion status and the read data to the main front-end module 11 of the main chip 1, and the slave back-end module 21 of the slave chip 2 replies the read operation completion status and the read data to the main front-end module 11. The main front-end module 11 of the main chip 1 replies the collected read operation completion status and the read data to the host 5.

[0052] like Figure 6As shown, the host 5 writes to the SSD solid state drive including: the main front-end module 11 of the main chip 1 receives the write request and data of the host 5, and the read-write distribution hardware module 12 divides the write request and data according to the set rules and distributes them to the main back-end module 13 and the slave back-end module 21. After receiving part of the write request and data of the host 5, the main back-end module 13 manages the FTL algorithm and writes to the connected flash memory particles 3. After receiving part of the read-write request and data of the host 5, the slave back-end module 21 manages the FTL algorithm and writes to the connected flash memory particles 4. The main back-end module 13 replies to the main front-end module 11 with the completion status of the write operation, and the slave back-end module 21 replies to the main front-end module 11 with the completion status of the write operation. The main front-end module 11 collects and merges the completion status of the write operation and replies to the host 5.

[0053] The above are only some embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, but not to limit them. For those skilled in the art, without departing from the creative concept of the present invention, the technical solutions recorded in the above embodiments are modified, or some or all of the technical features are replaced by equivalents, which all belong to the protection scope of the present invention.

Claims

1. A chiplet-based SSD solid state drive, characterized in that: Including master chip and slave chip; The master chip includes a master front-end module, a read-write distribution hardware module, and a master back-end module, and the slave chip includes a slave back-end module; The main front-end module receives data and requests from the host and returns the processing results to the host. The read / write distribution hardware module divides the host data and the read / write request and distributes them to the master backend module and the slave backend module; The main back-end module processes some of the received read and write requests and returns the processing results to the main front-end module; The slave back-end module processes part of the received read and write requests, and replies the processing results to the master front-end module.

2. The chiplet-based SSD solid state drive according to claim 1, characterized in that: The master chip communicates with the slave chip via a high-speed interconnect hardware interface.

3. The chiplet-based SSD solid state drive according to claim 1, characterized in that: The communication between the master chip and the slave chip is in full-duplex mode, and data can be sent to and received from the opposite end at the same time.

4. The chiplet-based SSD solid state drive according to claim 1, characterized in that: The main chip communicates with the host through a PCIE front-end interface or a SATA front-end interface.

5. The chiplet-based SSD solid state drive according to claim 1, characterized in that: Also includes flash memory particles; The main back-end module is configured with a plurality of flash memory channels, and the flash memory particles correspond to the flash memory channels one by one; The slave backend module is configured with a plurality of flash memory channels, and the flash memory particles correspond to the flash memory channels one by one.

6. The chiplet-based SSD solid state drive according to claim 1, characterized in that: Dynamic random access memory is also included.

7. An implementation scheme of a chiplet-based SSD solid state drive according to claims 1-6, characterized in that: The host reads the SSD including: The main front-end module receives a read request from the host; The read-write distribution hardware module reads the request and distributes it after segmentation; The main backend module receives a partial read request and reads data from the connected flash memory particles into the memory through the FTL algorithm; The receiving of a partial read request from the back-end module reads data from the connected flash memory particles into the memory through the FTL algorithm; The main back-end module replies the read data completion status and all data to the main front-end module; The slave back-end module replies to the master front-end module with the completion status of the read data and all the data; The main front-end module collects and merges the read completion status and all data of the main back-end module and the slave back-end module to reply to the host.

8. An implementation scheme of a chiplet-based SSD solid state drive according to claims 1-6, characterized in that: The host writes to the SSD including: The main front-end module receives a host write request; The read-write distribution hardware module divides and distributes the write request according to the set rules; The main backend module manages the FTL algorithm and writes to the connected flash memory particles after receiving the partial write request and host data; After receiving the partial write request and host data from the back-end module, the FTL algorithm is managed and written into the connected flash memory particles; The main back-end module replies to the main front-end module with the completion status of the write operation; The slave back-end module replies to the master front-end module with the completion status of the write operation; The main front-end module collects and merges the writing completion status of the main back-end module and the slave back-end module and then replies to the host.

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