A scheduling method, apparatus, system, and computing device

Abstract

The application provides a scheduling method, which is executed by a computing device including a plurality of processors, at least one of the plurality of processors supports a type of at least one instruction set in an instruction set collection, which is different from a type of instruction set in an instruction set collection supported by other processors, and the scheduling method comprises: obtaining an instruction set type of an application; and selecting a target processor from the plurality of processors, wherein the instruction set type of the application is a subset of a plurality of instruction set types in an instruction set collection supported by the target processor; and then distributing the application to the target processor for execution. The method can effectively support high-performance computing data processing under a homogeneous multi-instruction set architecture.

Description

[0001] Cross-references to related applications

[0002] This application is a divisional application. The original application has the application number 202110770860.3 and the original application date is July 8, 2021. The entire contents of the original application are incorporated herein by reference.

[0003] This application claims priority to Chinese Patent Application No. 202110558600.X, filed on May 21, 2021, entitled "A method, apparatus and computer device for data processing", the entire contents of which are incorporated herein by reference. Technical Field

[0004] This application relates to the field of computers, and more particularly to a scheduling method, apparatus, system and computing device. Background Technology

[0005] Traditional server processors employ symmetric multi-processing (SMP) or non-uniform memory architecture (NUMA). This means that multiple processors on the server share identical instruction set architectures and microarchitectures. The operating system samples the performance of specific tasks to determine the appropriate computing power required and then schedules the task to run on the appropriate processor core. Integrating floating-point accelerators within general-purpose computing processors and driving them through specific acceleration instructions is a trend in the development of general-purpose processor architectures in the era of diverse computing. Compared to general-purpose processors, this type of processor has slightly different microarchitectures and instruction set architectures due to its support for high-performance floating-point acceleration. When a general-purpose processor and a processor with floating-point acceleration form a homogeneous multi-instruction set architecture computing system within a server via an interconnect bus, traditional schedulers may encounter unrecognized instruction exceptions when scheduling tasks with floating-point acceleration instructions to general-purpose processor cores, leading to abnormal task termination. Current solutions involve using a programming framework where the user calls an interface provided by the framework to send the application to a user-specified processor for execution. This requires the user to have a certain understanding of the processor's supported instruction set types and involves complex programming. Therefore, how to provide a task scheduling method that supports high performance under a homogeneous multi-instruction set architecture has become an urgent problem to be solved. Summary of the Invention

[0006] This application provides a scheduling method, apparatus, system, and computing device that can support data processing for high-performance computing under a homogeneous multi-instruction set architecture.

[0007] In a first aspect, a scheduling method is provided, which is executed by a computing device including a plurality of processors, at least one of which supports a type of instruction set that is different from a type of instruction set supported by the other processors. The scheduling method includes first obtaining a type of instruction set of an application, and selecting a target processor from the plurality of processors, wherein the type of instruction set of the application is a subset of the types of the plurality of instruction sets supported by the target processor. Then the application is assigned to the target processor for execution. Through the above method, the new scheduling method identifies the type of instruction set of the application and the instruction set collection supported by the processor before scheduling, so that the operating system has the ability to schedule the mixed system of processors with different instruction set collections.

[0008] In a possible implementation, the method of selecting the target processor from the plurality of processors can specifically select the target processor from the plurality of processors according to the type of instruction set of the application, wherein the type of instruction set of the application is a subset of the types of the plurality of instruction sets supported by the target processor. Through the above method, the application can be scheduled to the processor supporting the type of instruction set of the application, so as to avoid application execution exceptions.

[0009] In another possible implementation, the target processor belongs to a target scheduling domain, wherein the instruction set collection supported by the target scheduling domain is the same as the instruction set collection supported by the target processor, and before selecting the target processor, a target scheduling domain is selected from a plurality of scheduling domains, wherein the type of instruction set of the application is a subset of the types of the plurality of instruction sets supported by the target scheduling domain. Through the above method, the target processor can be selected by using the scheduling domain, so as to improve the efficiency of scheduling.

[0010] In another possible implementation, the target scheduling domain only includes the target processor, or includes the target processor and other processors, wherein the instruction set collection supported by the other processors is the same as the instruction set collection supported by the target processor. Through the above method, the processors supporting the same instruction set collection can be uniformly managed as a scheduling domain, so as to improve the efficiency of scheduling.

[0011] In another possible implementation, the application includes at least one task, and the scheduling method further includes writing a type of instruction set of the task into a task control block of the task, wherein the type of instruction set of the task is the same as the type of instruction set of the application. Then obtaining the type of instruction set of the application specifically includes obtaining the type of instruction set of the task from the task control block. Through the above method, the application can be divided into a plurality of tasks, and each task can be assigned to a different processor for execution, so as to improve the execution efficiency of the application.

[0012] In another possible implementation, the application is assigned to the target processor for execution, and specifically, the task can be assigned to the target processor for execution.

[0013] In another possible implementation, the target processor includes at least one processing unit, and the task is assigned to the target processor for execution, and specifically, when the target processor supports multi-thread parallel processing, the task is assigned to one processing unit of the target processor for execution. Through the above method, the multi-thread parallel processing technology of the processor can be used to execute multiple tasks on one processor simultaneously, and the execution efficiency of the application is improved.

[0014] In another possible implementation, the target processor includes at least one processing core, and the task is assigned to the target processor for execution, and specifically, when the target processor does not support multi-thread parallel processing, the task is assigned to one processing core of the target processor for execution. Through the above method, the multi-core technology of the processor can be used to execute multiple tasks on one processor simultaneously, and the execution efficiency of the application is improved.

[0015] In another possible implementation, when the processor fails to execute the task, the identifier of the target scheduling domain is stored in the first storage unit of the task control block of the task, and the identifier stored in the first storage unit is used to indicate that the processor included in the target scheduling domain cannot be assigned to execute the application. Through the above method, the same task of the same application can be prevented from being scheduled to the processor that does not support execution again, and the probability of successful execution of the application is increased.

[0016] In another possible implementation, when the processor successfully executes the task, the identifier of the target scheduling domain is stored in the second storage unit of the task control block of the task, and the identifier stored in the second storage unit is used to indicate that the processor included in the target scheduling domain can be assigned to execute the application. Through the above method, the time for the scheduler to determine whether the scheduling domain supports task execution is reduced, and the execution efficiency of the application is improved.

[0017] In another possible implementation, the instruction set type of the application to be executed is acquired, and specifically, when the application is compilable, the instruction set type of the application is acquired through a compilation option; or when the application is not compilable, the instruction set type of the application is acquired through an exception instruction. The type of the instruction set of the application can be acquired in two ways, and the scheduling method proposed in the application can not only schedule a new application to be executed but also schedule an old application that already has an executable file.

[0018] In another possible implementation, the instruction set type of the application is obtained through a compilation option, specifically including: directly obtaining the type of the instruction set of the application executed by the user through the compilation option; or first obtaining the type of the processor of the application executed by the user through the compilation option, and then determining the type of the instruction set of the application according to the relationship between the processor type and the instruction set type.

[0019] In another possible implementation, after obtaining the instruction set type of the application through the compilation option, the application can also be compiled into a binary file, where the binary file includes the type of the instruction set of the application.

[0020] In another possible implementation, after obtaining the instruction set type of the application through the exception instruction, the binary code of the exception instruction can also be parsed to obtain the type of the instruction set to which the exception instruction belongs, and then the instruction set type of the application is set to the type of the exception instruction set.

[0021] In another possible implementation, the task is a process generated by the device for executing the application.

[0022] In another possible implementation, the task is a thread generated by the device for executing the application.

[0023] In a second aspect, the present application provides a computing device, including a plurality of processors, wherein at least one instruction set type in an instruction set collection supported by at least one processor in the plurality of processors is different from an instruction set type in an instruction set collection supported by other processors. A main processor in the plurality of processors is configured to implement the operation steps of the scheduling method in the first aspect or any possible implementation manner of the first aspect.

[0024] In a third aspect, a scheduling apparatus is provided, including various modules for executing the scheduling method in the first aspect or any possible implementation manner of the first aspect. The scheduling apparatus is deployed in a computing device, wherein the computing device includes a plurality of processors, and at least one instruction set type in an instruction set collection supported by at least one processor in the plurality of processors is different from an instruction set type in an instruction set collection supported by other processors.

[0025] In a fourth aspect, the present application provides a scheduling system, including a scheduling apparatus for executing the scheduling method in the first aspect or any possible implementation manner of the first aspect, and a plurality of processors, wherein at least one instruction set type in an instruction set collection supported by at least one processor in the plurality of processors is different from an instruction set type in an instruction set collection supported by other processors. The scheduling apparatus can be located in a different computing device from the plurality of processors, and at least one processor in the plurality of processors can also be located in a different computing device from other processors.

[0026] In a fifth aspect, a computer readable storage medium is provided, wherein the computer readable storage medium stores instructions which, when executed on a computer, cause the computer to perform the operation steps of the method in the first aspect or any possible implementation manner of the first aspect.

[0027] In a sixth aspect, a computer program product is provided, which contains instructions which, when executed on a computer, cause the computer to perform the operation steps of the method in the first aspect or any possible implementation manner of the first aspect.

[0028] On the basis of the implementation manners of the above aspects, the present application can be further combined to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 Fig. 1 is a structural schematic diagram of a device 100 provided by an embodiment of the present application;

[0030] Figure 2 Fig. 3 is a schematic diagram of an operating system 13 provided by the present application;

[0031] Figure 3 Fig. 5 is a schematic diagram of a dispatch domain provided by the present application;

[0032] Figure 4 Fig. 7 is a schematic diagram of a two-level dispatch domain structure stored in a memory provided by the present application;

[0033] Figure 5 Fig. 9 is a flow schematic diagram of a dispatch method provided by an embodiment of the present application;

[0034] Figure 6 Fig. 11 is a schematic diagram of a task control block provided by an embodiment of the present application;

[0035] Figure 7 Fig. 13 is a flow schematic diagram of another dispatch method provided by an embodiment of the present application;

[0036] Figure 8 Fig. 15 is a method of setting a "black list" provided by the present application;

[0037] Figure 9 Fig. 17 is a method of setting a "white list" provided by the present application;

[0038] Figure 10 Fig. 19 is a schematic diagram of another task control block provided by the present application;

[0039] Figure 11 Fig. 21 is a schematic diagram of a dispatch device 1100 provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present application will be described below with reference to the drawings. Figure 1 is a structural schematic diagram of a device 100 provided in an embodiment of the present application. The device 100 can be any computing device (for example, a server) having at least two processors. A device having multiple processors can adopt a symmetric multi-processing (SMP) architecture or a non-uniform memory access (NUMA) architecture. For ease of description, the following embodiments of the present application are described by taking the device 100 adopting the NUMA architecture as an example. It should be noted that the task scheduling method provided in the present application is also applicable to a device adopting the SMP architecture and a device having other multi-processor architectures.

[0041] The device 100 includes a processing node 14 and a processing node 15, wherein a plurality of processing nodes and a memory 16 are connected through a bus. The bus can be a data bus, and can also be a power bus, a control bus, a status signal bus and the like. The bus can also be a bus for implementing the connection between devices in a computing device, such as an intel quick path interconnect (QPI). It should be noted that the number of processing nodes in the device 100 does not constitute a limitation to the present application, Figure 1 The device 100 is taken as an example including only two processing nodes for description.

[0042] Each processing node in the device 100 has a structure of a single processing node as shown in Figure 1 The following takes one processing node (the processing node 14) as an example to describe the components and connection mode in each processing node. The processing node 14 includes a processor 140, a memory 144 and a memory manager 143. The processor 140, the memory 144 and the memory manager 143 are interconnected through an on-chip bus.

[0043] Processors 140 are chips of physical central processing units (CPUs). Processors on one processing node can access the local memory of that node through an on-chip bus quickly, and can also access the memory of other nodes through a high-speed interconnection network. For example, processor 141 of processing node 14 can access memory 144 of processing node 14, and can also access memory 154 of processing node 15. Accessing the memory of other processing nodes by a processor will take more time than accessing the memory of the same processing node by the processor. Therefore, for a NUMA system, the memory of the same processing node as a processor should ideally contain information most relevant to the processor. In some embodiments, processors 140 can further include multiple cores, such as processor core 141 and processor core 142, which are integrated on the chip of processor 140, and each processor core can have an independent Ll cache, and different processor cores in the same processor can share an L2 cache. In some embodiments, each processor core can further execute multiple threads or processes in parallel through techniques such as simultaneous multithreading. The hardware unit processing each thread or process is logically a CPU, and can also be referred to as a processing unit, such as processing unit 1411 and processing unit 1412. The processing units of the same processor share all the resources of the processor, including the Ll cache and the logical operation unit.

[0044] The memory 144 or the memory 154 refers to an internal memory that directly exchanges data with the processing unit, which can read and write data at any time and at a very fast speed, as temporary data storage of the operating system or other programs running at the moment. The memory 144 or the memory 154 includes at least two types of memories, such as random access memory and read-only memory (ROM). For example, the random access memory is dynamic random access memory (DRAM) or storage class memory (SCM). DRAM is a semiconductor memory, which, like most random access memory (RAM), is a type of volatile memory device. SCM is a hybrid storage technology that combines the characteristics of traditional storage devices and memory. Storage class memory can provide faster read and write speeds than hard drives, but slower access speeds than DRAM, and is more cost-effective than DRAM. However, DRAM and SCM are only exemplary in this embodiment, and the memory can also include other random access memories, such as static random access memory (SRAM), etc. For read-only memory, for example, it can be programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), etc. In addition, the memory 144 or the memory 154 can also be a dual in-line memory module (DIMM), i.e. a module composed of dynamic random access memory (DRAM), and can also be a solid state disk (SSD). In practical applications, multiple memories and different types of memories can be configured in a NUMA system. This embodiment does not limit the number and type of memories. In addition, the memory can be configured to have a power retention function. The power retention function refers to the data stored in the memory will not be lost when the system is powered off and then powered on. The memory with the power retention function is called non-volatile memory.

[0045] The memory manager is used to manage and plan data transmission between the memory and the processing unit, which can be a separate chip or integrated into the chip of the processor.

[0046] The device 100 supports a processor mixed with different instruction set versions to form a homogeneous multi-instruction set architecture, which can include the following two scenarios.

[0047] Scenario one: general-purpose processor and general-purpose instruction heterogeneous processor mixed.

[0048] The general-purpose instruction heterogeneous processor refers to the integration of accelerators including floating point accelerators into the general-purpose processor, and the addition of specific acceleration instructions to drive the accelerators, so that the accelerators can reuse various resources on the processor to support the needs of floating point number calculation with different precision. Exemplarily, Figure 1 The processor 140 can be a general-purpose processor, and the processor 150 can be a general-purpose processor integrated with a floating point accelerator.

[0049] Scenario two: mixed processors produced at different times.

[0050] With the advancement of chip manufacturing processes, the complexity of the hardware circuits of processors produced at different times is different, so the supported instruction set versions are slightly different. Exemplarily, Figure 1 The processor 140 can be a general-purpose processor version 9, and the processor 150 can be a general-purpose processor version 8.6.

[0051] In the device 100, the operating system 13 is used to run an application and convert tasks generated by the application into instructions to assign to a processor capable of successfully executing the tasks for execution. In an embodiment, the operating system 13 can run on the main processor of the device 100, and when the remaining processors receive a request to run an application, the request is sent to the main processor, and the operating system 13 converts tasks generated by the application into instructions to assign to a processor capable of successfully executing the tasks for execution. Wherein, the main processor can be pre-designated by the user from the multiple processors of the device 100, and the application does not limit the designation manner, for example, the main processor can be the processor 140 or the processor 150. In another embodiment, the operating system 13 can also run on multiple processors of the device 100, for example, the operating system 13 runs on the processor 140 and the processor 150 at the same time. When a processor receives a request to run an application, the operating system 13 on the processor converts tasks generated by the application into instructions to assign to a processor capable of successfully executing the tasks for execution. At this time, the processor executing the operating system 13 can be referred to as the main processor.

[0052] Figure 2 is a schematic diagram of an operating system 13 provided by the application, taking the operating system stored in the memory 144 as an example, as shown in Figure 2As shown, the operating system 13 includes a compiler 131, a loader 132 and a scheduler 133. The compiler 131 is configured to compile the code of an application into a binary file executable by a processor. When the binary file is executed, the loader 132 creates a process or a thread for loading the instructions of the binary file. In one aspect, a new process can be created for each loading of a binary file, and when a process is created, the loader 132 also allocates a memory space for the process to store the context of the process, including a process identifier, scheduling information of the process, control information of the process, and an address of a next instruction to be executed, etc. This memory space can also be referred to as a process control block. In another aspect, the loader 132 can also create multiple threads for a process to execute multiple sub-tasks in the process, and the multiple threads can share the software and hardware resources of the process. When a thread is created, the loader 132 allocates a memory space for the thread in the memory space of the process control block to store the context of the thread, including a thread identifier, scheduling information of the thread, control information of the thread, and an address of a next instruction to be executed, etc. The memory space allocated for the thread can also be referred to as a thread control block. Finally, the scheduler 133 schedules the processes or threads of an application to different processing units for execution. For ease of description, the processes or threads are collectively referred to as tasks, and the process control blocks or thread control blocks are collectively referred to as task control blocks in the following embodiments.

[0053] The operating system 13 can also include a parser 134 configured to parse the binary code of an instruction to obtain the instruction set type of the instruction.

[0054] When scheduling tasks, the scheduler 133 can employ a multi-level scheduling domain management method, and each scheduling domain includes one or more hardware. For example, referring to Figure 3 , the hardware can be a processor, and thus a scheduling domain including one or more processors can be referred to as a physical domain (PHY domain); the hardware can also be a processor core, and thus a scheduling domain including one or more processor cores can be referred to as a core domain (MC domain); and the hardware can also be a processor unit, and thus a scheduling domain including one or more processor units can be referred to as a super-thread domain (SMT domain). The scheduling domain represents the range of the scheduler 133 to execute a scheduling policy, and the scheduler 133 can execute different scheduling policies in each scheduling domain. The hardware in each scheduling domain can be further divided into one or more scheduling groups (CPU groups), and each scheduling group can be regarded as an independent execution unit. The scheduler executes scheduling policies between different scheduling groups in a scheduling domain. For example, referring to Figure 3When the scheduling domain is the physical domain, each processor can be taken as a scheduling group; when the scheduling domain is the core domain, each processor core can be taken as a scheduling group; and when the scheduling domain is the hyper-thread domain, each processing unit can be taken as a group. When the operating system 13 is started, the scheduler 133 can establish scheduling domains of different levels, and establish corresponding scheduling groups on each level of the scheduling domain.

[0055] Exemplarily, the processor structure of the device 100 is taken as an example, Figure 1 Figure 3 is a schematic diagram of a scheduling domain provided by the present application, as shown in Figure 3 As shown in the figure, the scheduling domain can be divided into the hyper-thread domain, the core domain and the physical domain. Specifically, the hyper-thread domain is the lowest level of the scheduling domain, and each processor core can be taken as a hyper-thread domain, for example, the processor core 141 is the hyper-thread domain 1. Each hyper-thread domain is associated with two processing units, for example, the hyper-thread domain 1 is associated with the processing unit 1411 and the processing unit 1412. Each processing unit is taken as a scheduling group in the hyper-thread domain, for example, the scheduling group 0 is the processing unit 1411. The higher level of the scheduling domain is the core domain, and each processor can be taken as a core domain, for example, the processor 140 is the core domain 1. Each core domain is associated with two processor cores, for example, the core domain 1 is associated with the processor core 141 and the processor core 142. Each processor core is taken as a scheduling group in the core domain, for example, the scheduling group 00 is the processor core 141. The higher level of the physical domain is composed of multiple processors in the system, and each physical domain is associated with multiple processors, for example, the physical domain 1 is associated with the processor 140 and the processor 1250. In the physical domain, each processor is taken as a scheduling group, for example, the scheduling group 000 is the processor 140.

[0056] Optionally, when the multi-core processor does not support multi-thread parallel processing, the scheduling domain can be divided into two levels of the physical domain and the core domain.

[0057] Optionally, when the processor only has one core and supports multi-thread parallel processing, the scheduling domain can be divided into two levels of the physical domain and the hyper-thread domain.

[0058] Optionally, when the processor only has one core and does not support multi-thread parallel processing, the scheduling domain is the physical domain.

[0059] The retriever 133 can save the topological relationship diagram of the scheduling domain in the memory in the form of a structure body, Figure 4 is a schematic diagram of a two-level scheduling domain provided by the present application, as shown in Figure 4 ​As shown, the scheduling domains present a tree topology, and the scheduling domains at different levels are connected by pointers, and the scheduling domains at lower levels can be regarded as scheduling groups in the scheduling domains at higher levels. For example, scheduling domain 2 and scheduling domain 3 are scheduling group 1 and scheduling group 2 of scheduling domain 1 respectively. The scheduler can first perform the scheduling strategy of scheduling domain 1 between scheduling group 1 and scheduling group 2 in scheduling domain 1. After selecting a scheduling group, for example, scheduling group 1, the scheduler allocates tasks to scheduling domain 2, and then performs the scheduling strategy of scheduling domain 2 between scheduling group 3-5 in scheduling domain 2. After selecting a scheduling group, for example, scheduling group 3, the scheduler allocates tasks to scheduling group 3. The structure of the scheduling domain includes the number of the scheduling domain (which can also be referred to as the scheduling domain identifier, and is NULL when the structure is only a scheduling group), the number of the scheduling group (which can also be referred to as the scheduling group identifier, and is NULL when the structure is not a scheduling group of another scheduling domain), the scheduling strategy, the number of the hardware included in the scheduling domain, and the pointer of the scheduling group (which is NULL when the structure is only a scheduling group). The scheduling strategy can be set by a user, and the user can set different scheduling strategies for scheduling domains at different levels, and the method for setting is not limited by the present application.

[0060] When multiple scheduling groups in a device form a computing system of a homogeneous multi-instruction set architecture, by the task scheduling method provided in the present application, the scheduler 133 can identify different instruction sets in the tasks of an application, and schedule the tasks to processing units that can execute the instruction sets, thereby avoiding the generation of instruction exceptions that cannot be identified by the processing units, and causing the tasks to exit abnormally.

[0061] The following will be described in combination with Figures 5 to 10 The data processing method provided in the embodiments of the present application will be described, Figure 5 is a flowchart of a scheduling method provided in the embodiments of the present application, and the method can be executed by Figure 2 the operating system 13 shown, and specifically, the method can be executed by a main processor running the operating system 13, which can be a processor specified by a user or a processor running the operating system 13, for example, the processor 140 or the processor 150 in Figure 1 . As shown in Figure 5 , the specific method includes the following steps.

[0062] S501, the compiler 131 obtains the type of the instruction set of the application.

[0063] Before an application is executed, the code needs to be compiled into a binary executable file, and then the scheduler schedules the binary executable file to the processor for execution. When compiling the code of the application, the compiler 131 can obtain the type of the instruction set of the application by using the following two ways through a compilation option.

[0064] Method one: the user specifies the processor type of executing the application in the compilation option.

[0065] The user can specify the processor type of executing the application in the compilation option, for example:

[0066] -march=cpu-type;

[0067] Wherein, the right side of the equal sign represents the processor type of executing the application, and the application can be compiled into a binary file executable on the processor of the type.

[0068] After the compiler 131 obtains the processor type, it can determine the instruction set collection supported by the processor according to the processor type, and the instruction set collection includes all types of instruction sets supported by the processor. The relationship between the processor type and the instruction set collection supported by the processor can be pre-stored in the device in the form of a table. For example, Table 1 is a list of the relationship between the processor type and the instruction set collection provided by the embodiment of the application, which records the type (also called identifier) of each processor and the instruction set collection supported by the processor of the type.

[0069] Table 1, relationship between processor type and instruction set collection

[0070]

[0071] Method two: the user directly specifies the type of instruction set of executing the application in the compilation option.

[0072] The user can directly specify the type of instruction set of executing the application in the compilation option "-m-xxx", which means that the application can be compiled into a binary file executable on the processor of the instruction set type, for example:

[0073] -mmmx–msse;

[0074] The type of instruction set of the application is MMX and SSE.

[0075] S502, the compiler 131 writes the type of instruction set into the executable binary file of the application.

[0076] During the compilation process, the compiler 131 writes the type of instruction set into the executable binary file generated by the compilation. For example, the compiler 131 can write the type of instruction set into the.comment field of the executable binary file.

[0077] S503, running the executable binary file, the loader 132 puts the type of instruction set into the task control block.

[0078] When the binary file is executed, the loader 132 creates corresponding tasks according to the instructions of the binary file, and creates corresponding task control blocks in the memory for saving the context related to the process. The loader 132 also stores the type of the instruction set in the task control blocks of all the tasks corresponding to the binary file. Figure 6 is a schematic diagram of a task control block provided by the present application. As shown in Figure 6 , the application running generates a plurality of tasks, each task corresponding to a task control block, and a space is allocated in each task control block for saving the type of the instruction set.

[0079] S504, the scheduler 133 acquires the instruction set collection of the processor.

[0080] When the operating system is started, the scheduler 133 can acquire the supported instruction set collection of the processor deployed on the device, for example, the scheduler 133 can acquire the model number of each processor by calling the cpuinfo instruction and reading the modelnade field, and then acquire the type of the instruction set supported by each processor according to the list of the relationship between the processor model number and the instruction set collection. For another example, the scheduler 133 can also directly acquire the type of the instruction set supported by each processor by calling the cpuinfo instruction and reading the flag field.

[0081] S505, the scheduler 133 sets the scheduling domain according to the instruction set collection of the processor.

[0082] The scheduler 133 sets the processors with the same instruction set collection as one physical domain according to the instruction set collection of the processor, and writes all the types of the instruction sets in the instruction set collection into the structure body of the physical domain in the form of the instruction set collection.

[0083] S506, the scheduler 133 schedules the task to the processing unit that can execute the task.

[0084] When the clock interrupt triggers the task scheduling of the physical domain once, the scheduler 133 judges whether the instruction set collection of the physical domain includes all the types of the instruction sets in the task control block of the task that needs to be scheduled. According to the scheduling strategy of the physical domain, one scheduling group, i.e., one processor, is selected in the physical domain that can execute the task. Then, according to the scheduling strategy of the core domain, one scheduling group, i.e., one processor core, is selected from the core domain, and according to the scheduling strategy of the hyperthreading domain, one scheduling group, i.e., one processing unit, is selected from the hyperthreading domain to execute the task.

[0085] Alternatively, when the multi-core processor does not support multi-thread parallel processing, the scheduler 133 can select one scheduling group, i.e., one processing core, from the core domain to execute the task according to the scheduling strategy of the core domain.

[0086] Optionally, when there is only one core and multi-thread parallel processing is supported, the scheduler 133 can directly select a scheduling group from the hyper-threading domain according to the scheduling policy of the hyper-threading domain, i.e., one processing unit executes the task.

[0087] Optionally, when there is only one core and multi-thread parallel processing is not supported, the scheduler 133 directly selects the scheduling group, i.e., the processor executes the task.

[0088] Optionally, when all the physical domains cannot execute the task, the scheduler 133 directly reports an error and stops executing the application.

[0089] The task scheduling method provided in the present application can be applied to a homogeneous multi-instruction set structure, and through the cooperation of the compiler and the scheduler, a multi-processor system composed of scheduling groups of different instruction set versions can be flexibly scheduled in a unified operating system.

[0090] For a large number of existing binary executable files and dynamic link libraries, the instruction set type cannot be written into the executable binary file of the application because it cannot be recompiled by the compiler. The following method can be used for task scheduling, Figure 7 is another scheduling method provided in the present application, which is similar to Figure 5 , can be executed by using Figure 2 the operating system 13, specifically, can be executed by using a main processor running the operating system 13, which can be a processor specified by a user or a processor running the operating system 13, for example, the processor 140 or the processor 150 in Figure 1 . As shown in Figure 7 , the specific method includes:

[0091] S701, running an executable binary file of an application, and judging whether the execution of an instruction in the task is abnormal.

[0092] S702, when the instruction is abnormal, the parser 134 reads the binary code of the abnormal instruction and parses the type of the instruction set of the instruction.

[0093] S703, similar to S403, the loader 132 puts the type of the instruction set into the task control block.

[0094] S704, the scheduler 133 puts the task corresponding to the abnormal instruction into the waiting queue.

[0095] S705, the scheduler 133 schedules the task to a processing unit that can execute the task.

[0096] Specifically, similar to S504 to S506, the scheduler 133 sets the instruction set collection of the scheduling domain and schedules the task to the processing unit that can execute.

[0097] By the above method, the instruction set type of the application can be identified by dynamically identifying the abnormal instruction, and the problem that the task of the old application program or the dynamic link library is scheduled to the inappropriate processor to cause the repeated error can be solved.

[0098] In order to reduce the time of the scheduler to judge whether the instruction set types are the same and improve the accuracy of the scheduler to execute the scheduling, a "blacklist" or a "whitelist" can be added in the task control block of the task, wherein the "blacklist" is used to store the scheduling domain associated with the processor that appears the exception when executing the task. The "whitelist" is used to store the scheduling domain associated with the processor that successfully executes the task. Figure 8 is a method provided by the present application to set the "blacklist", which can be executed by the operating system 13 as shown in Figure 2 , specifically, the main processor running the operating system 13 can be used to execute, which can be the processor specified by the user or the processor running the operating system 13, for example, the processor 140 or the processor 150 in Figure 1 . As shown in Figure 8 , the method can be executed after step S506 in the method as shown in Figure 5 , or can be executed after step S702 in the method as shown in Figure 7 , and the method is as follows:

[0099] S801, execute the executable binary file of the application, and judge whether the execution of the instruction in the task appears an exception.

[0100] S802, when the instruction appears the exception, the scheduler 133 acquires the number of the physical domain where the processor that appears the exception is located.

[0101] S803, the loader 132 sets the "blacklist" in the task control block.

[0102] A storage area is allocated in the task control block to store the "blacklist" of the scheduling domain, and in order to facilitate description, the storage area can also be called the first storage unit, and the loader 132 stores the number of the physical domain into the first storage unit of the task control block of all tasks of the application.

[0103] After adding the "blacklist", the scheduler 133 will not schedule the task to the scheduling domain corresponding to the number stored in the "blacklist" when scheduling next time. Optionally, when the "blacklist" of the task includes all the physical domains on the device 100, it indicates that all the processors cannot support the execution of the instructions of the task, and the scheduler 133 can directly report an error and stop executing the application.

[0104] By using the methods described above, we can prevent the same application's tasks from being rescheduled to processors that do not support execution, thereby increasing the probability of successful application execution.

[0105] Figure 9 This application provides a "whitelist" method that can be used. Figure 2 The operating system 13 shown is executed. Specifically, it can be executed using the main processor running the operating system 13. This main processor can be a user-specified processor or a processor running the operating system 13, for example... Figure 1 The processor is either 140 or 150. For example... Figure 8 As shown, this method can be used Figure 5 The method shown is executed after step S506, and the specific method is as follows:

[0106] S901. Run the executable binary file of the application and determine whether there are any abnormalities in the execution of instructions in the task.

[0107] S902. When no exception occurs in the instruction, the scheduler 133 obtains the number of the physical domain where the processor is located.

[0108] S903, loader 132 sets a "whitelist" in the task control block.

[0109] A storage area is allocated in the task control block to store the "whitelist" of scheduling domains. For ease of description, this storage area can also be called the second storage unit. The loader 132 stores the physical domain number into the second storage unit of the task control block of all tasks of the application.

[0110] After adding the "whitelist", scheduler 133 can directly schedule tasks to the scheduling domain corresponding to the number stored in the "whitelist" during the next scheduling.

[0111] By using the above methods, the time spent by the scheduler in determining whether the scheduling domain supports the instruction set required to execute the task can be reduced, thereby improving the efficiency of application execution.

[0112] It should be noted that you can add either a "blacklist" or a "whitelist" to the task control block of a task, or you can add both "blacklist" and "whitelist" to the task control block of a task. Figure 10 This is a schematic diagram of a task control block with added "blacklist" and "whitelist" provided in this application.

[0113] It should be noted that, for the above method embodiments, in order to simply describe, they are all expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the action sequence described, and those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the present application.

[0114] Other reasonable combinations of steps that those skilled in the art can think of based on the above description are also within the protection scope of the present application. In addition, those skilled in the art should know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the present application.

[0115] The above describes in detail the task scheduling method provided by the embodiments of the present application, and the following will describe a task scheduling device provided by the embodiments of the present application in conjunction with Figures 5 to 10 Figure 11

[0116] Figure 11 A schematic diagram of a scheduling device 1100 provided by the embodiments of the present application includes an obtaining unit 1101 and a scheduling unit 1102. The scheduling device 1100 is used to implement the functions of the operating system 13 shown in Figure 2

[0117] The obtaining unit 1101 is used to obtain the type of the instruction set of the application, and the specific implementation can refer to the steps of S501 in Figure 5 , which will not be repeated here. In the implementation process of the product, the obtaining unit 1101 can be the compiler 131 shown in Figure 2 , or other compilers, and the embodiments of the present application do not limit the form of the obtaining unit 1101.

[0118] The scheduling unit 1102 is used to select a target processor from a plurality of processors of a computing device, wherein at least one instruction set in the instruction set collection supported by at least one processor is different from the type of the instruction set in the instruction set collection supported by other processors, and the type of the instruction set of the application is a subset of the types of a plurality of instruction sets in the instruction set collection supported by the target processor. The scheduling unit 1102 is also used to assign the application to the target processor for execution. The specific implementation of the scheduling unit 1102 can refer to the steps of S504 to S506 in Figure 5 , which will not be repeated here. In the implementation process of the product, the obtaining unit 1101 can be the scheduler 133 shown in Figure 2 , or other schedulers, and the embodiments of the present application do not limit the form of the scheduling unit 1102.

[0119] ​​​Optionally, the scheduling unit 1102 is further configured to select the target processor from a plurality of processors according to a type of the instruction set of the application.

[0120] Optionally, before the target processor is selected, the scheduling unit 1101 is further configured to select a target scheduling domain from a plurality of scheduling domains, and the type of the instruction set of the application is a subset of types of a plurality of instruction sets in a set of instruction sets supported by the target scheduling domain. The target processor belongs to the target scheduling domain, and the set of instruction sets supported by the target scheduling domain is the same as a set of instruction sets supported by the target processor.

[0121] Optionally, the target scheduling domain only includes the target processor, or the target scheduling domain includes the target processor and other processors, and the set of instruction sets supported by the other processors is the same as the set of instruction sets supported by the target processor.

[0122] Optionally, the scheduling apparatus 1100 further includes a loading unit 1103 configured to write a type of an instruction set of a task into a task control block of the task, the type of the instruction set of the task being the same as the type of the instruction set of the application; and the obtaining unit 1101 is further configured to obtain the type of the instruction set of the task from the task control block. The application includes at least one task. The loading unit 1103 can be specifically implemented by referring to the step S503 in the method 1000, which will not be repeated here. In the implementation of the product, the loading unit 1103 can be the loader 132 shown in Figure 5 , or can be another loader, and the embodiment does not limit the form of the loading unit 1103. Figure 2

[0123] Optionally, the scheduling unit 1102 is further configured to assign the task to the target processor for execution.

[0124] Optionally, the scheduling unit 1102 is further configured to assign the task to one processing unit of the target processor for execution when the target processor supports multi-thread parallel processing. The target processor includes at least two processing units.

[0125] Optionally, the scheduling unit 1102 is further configured to assign the task to one processor core of the target processor for execution when the target processor does not support multi-thread parallel processing. The target processor includes at least one processor core.

[0126] Optionally, the loading unit 1103 is further configured to store an identifier of the target scheduling domain into a first storage unit of the task control block of the task when the target processor fails to execute the task, and the identifier stored in the first storage unit is used to indicate that a processor included in the target scheduling domain cannot be assigned to execute the application. The loading unit 1103 can be specifically implemented by referring to the step S803 in the method 1000, which will not be repeated here. Figure 8 ​​

[0127] Optionally, the loading unit 1103 is further configured to store the identifier of the target scheduling domain into a second storage unit of a task control block of the task when the target processor successfully executes the task, wherein the identifier stored in the second storage unit is used to indicate that the processors included in the target scheduling domain can be assigned to execute the application. For details, refer to the step S903 in the method. Figure 9

[0128] Optionally, the task is a process or a thread generated by the application.

[0129] Optionally, the obtaining unit 1101 further comprises a compiling unit 1104 and an analyzing unit 1105. When the application is compilable, the compiling unit 1104 is configured to obtain the instruction set type of the application through a compiling option. For details, refer to the steps S501-S502 in the method. Figure 5 When the application is not compilable, the analyzing unit 1105 is configured to obtain the instruction set type of the application through an abnormal instruction. For details, refer to the step S702 in the method. Figure 7 In the implementation of the product, the compiling unit 1104 can be the compiler 131 shown in Figure 2 , or can be another compiler. The embodiment does not limit the form of the compiling unit 1104. The analyzing unit 1105 can be the parser 134 shown in Figure 2 , or can be another parser. The embodiment does not limit the form of the analyzing unit 1105.

[0130] To sum up, the scheduling device 1100 provided by the embodiment of the application can identify the different instruction sets in the task of the application, and schedule the task to the processing unit that can execute the instruction set, thereby improving the success probability of the execution of the application.

[0131] The application further provides a scheduling system comprising a scheduling device configured to execute the scheduling method provided by the application and a plurality of processors, wherein at least one processor in the plurality of processors supports at least one instruction set type different from the instruction set types supported by other processors.

[0132] Optionally, the scheduling device and the plurality of processors can be located in different computing devices.

[0133] Optionally, at least one processor in the plurality of processors can also be located in a different computing device from other processors.

[0134] ​The above-described embodiments can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented by software, the above-described embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are wholly or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. containing one or more available medium sets. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid state drive (SSD).

[0135] The above is only a specific embodiment of the present application. Those skilled in the art can think of changes or replacements based on the specific embodiments provided by the present application, which should be covered within the protection scope of the present application.

Claims

1. A scheduling method, characterized in that, The method is executed by a computing device comprising a plurality of processors, wherein at least one of the processors supports an instruction set whose type differs from the instruction set types supported by the other processors. The method includes: Get the type of instruction set used by the application; A target processor is selected from the plurality of processors based on the type of the instruction set of the application, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the set of instruction sets supported by the target processor; The application is assigned to the target processor for execution. The types of instruction sets obtained from the application include: When the application is compileable, the type of instruction set for executing the application can be obtained directly through compilation options; or, the type of processor for executing the application can be obtained first through compilation options, and then the type of instruction set for the application can be determined based on the relationship between processor type and instruction set type. Alternatively, when the application cannot be compiled, the binary code of the exception instruction is parsed to obtain the instruction set type to which the exception instruction belongs, and then the instruction set type of the application is set to the type of the exception instruction set.

2. The method according to claim 1, characterized in that, The target processor belongs to the target scheduling domain, and the instruction set supported by the target scheduling domain is the same as the instruction set supported by the target processor. Before selecting the target processor, the method further includes: The target scheduling domain is selected from multiple scheduling domains, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set supported by the target scheduling domain.

3. The method according to claim 2, characterized in that, The target scheduling domain may include only the target processor, or the target scheduling domain may include the target processor and other processors, wherein the instruction set supported by the other processors is the same as the instruction set supported by the target processor.

4. The method according to any one of claims 1-3, characterized in that, The application includes at least one task, and the method further includes: Write the instruction set type of the task into the task control block of the task, wherein the instruction set type of the task is the same as the instruction set type of the application; The specific type of obtaining the application's instruction set includes: obtaining the type of the task's instruction set from the task control block.

5. The method according to claim 4, characterized in that, The step of assigning the application to the target processor for execution specifically includes: The task is assigned to the target processor for execution.

6. The method according to claim 5, characterized in that, The target processor includes at least two processing units, and the step of assigning the task to the target processor for execution specifically includes: When the target processor supports multi-threaded parallel processing, the task is assigned to one processing unit of the target processor for execution.

7. The method according to claim 5, characterized in that, The target processor includes at least one processor core, and the step of assigning the task to the target processor for execution specifically includes: When the target processor does not support multi-threaded parallel processing, the task is assigned to one processor core of the target processor.

8. The method according to any one of claims 5-7, characterized in that, The target processor belongs to a target scheduling domain, and the instruction set supported by the target scheduling domain is the same as the instruction set supported by the target processor. The method further includes: When the target processor fails to execute the task, the identifier of the target scheduling domain is stored in the first storage unit of the task's task control block. The identifier stored in the first storage unit is used to indicate that the processor included in the target scheduling domain cannot be allocated to execute the application.

9. The method according to any one of claims 5-7, characterized in that, The target processor belongs to a target scheduling domain, and the instruction set supported by the target scheduling domain is the same as the instruction set supported by the target processor. The method further includes: When the target processor successfully executes the task, the identifier of the target scheduling domain is stored in the second storage unit of the task's task control block. The identifier stored in the second storage unit is used to indicate that the processors included in the target scheduling domain can be allocated to execute the application.

10. The method according to claim 4, characterized in that, The task refers to a process or thread generated by the application.

11. A computing device, characterized in that, The computing device includes multiple processors, and at least one of the processors supports an instruction set whose type differs from the instruction sets supported by the other processors. The main processor among the plurality of processors is used for: Get the type of instruction set used by the application; A target processor is selected from the plurality of processors based on the type of the instruction set of the application, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the set of instruction sets supported by the target processor; The application is assigned to the target processor for execution. When the main processor obtains the instruction set type of the application, it specifically performs the following functions: When the application is compileable, the type of instruction set for executing the application can be obtained directly through compilation options; or, the type of processor for executing the application can be obtained first through compilation options, and then the type of instruction set for the application can be determined based on the relationship between processor type and instruction set type. Alternatively, when the application cannot be compiled, the binary code of the exception instruction is parsed to obtain the instruction set type to which the exception instruction belongs, and then the instruction set type of the application is set to the type of the exception instruction set.

12. The computing device according to claim 11, characterized in that, The target processor belongs to the target scheduling domain, and the instruction set supported by the target scheduling domain is the same as the instruction set supported by the target processor. Before selecting the target processor, the main processor is further configured to: The target scheduling domain is selected from multiple scheduling domains, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set supported by the target scheduling domain.

13. The computing device according to claim 12, characterized in that, The target scheduling domain may include only the target processor, or the target scheduling domain may include the target processor and other processors, wherein the instruction set supported by the other processors is the same as the instruction set supported by the target processor.

14. The computing device according to any one of claims 11-13, characterized in that, The application includes at least one task, and the main processor is further configured to: Write the instruction set type of the task into the task control block of the task, wherein the instruction set type of the task is the same as the instruction set type of the application; Obtain the type of the instruction set for the task from the task control block.

15. The computing device according to claim 14, characterized in that, The main processor is also used for: The task is assigned to the target processor for execution.

16. The computing device according to claim 15, characterized in that, The target processor includes at least two processing units, and the main processor is further configured to: When the target processor supports multi-threaded parallel processing, the task is assigned to one processing unit of the target processor for execution.

17. The computing device according to claim 16, characterized in that, The target processor includes at least one processor core, and the main processor is further configured to: When the target processor does not support multi-threaded parallel processing, the task is assigned to one processor core of the target processor.

18. A scheduling device, characterized in that, The scheduling device includes an acquisition unit and a scheduling unit: The acquisition unit is used to acquire the type of the application's instruction set; The scheduling unit is configured to select a target processor from multiple processors of the computing device according to the type of the instruction set of the application, wherein at least one of the processors supports an instruction set whose type is different from the instruction set types in the instruction set sets supported by other processors, and the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set set supported by the target processor; and to allocate the application to the target processor for execution. The acquisition unit is specifically used for: When the application is compileable, the type of instruction set for executing the application can be obtained directly through compilation options; or, the type of processor for executing the application can be obtained first through compilation options, and then the type of instruction set for the application can be determined based on the relationship between processor type and instruction set type. Alternatively, when the application cannot be compiled, the binary code of the exception instruction is parsed to obtain the instruction set type to which the exception instruction belongs, and then the instruction set type of the application is set to the type of the exception instruction set.

19. The scheduling device according to claim 18, characterized in that, The target processor belongs to the target scheduling domain, and the instruction set supported by the target scheduling domain is the same as the instruction set supported by the target processor. Before selecting the target processor, the scheduling unit is further configured to: The target scheduling domain is selected from multiple scheduling domains, wherein the type of the instruction set of the application is a subset of the types of multiple instruction sets in the instruction set supported by the target scheduling domain.

20. The scheduling device according to claim 18 or 19, characterized in that, The application includes at least one task, and the scheduling device further includes a loading unit, the loading unit being used for: Write the instruction set type of the task into the task control block of the task, wherein the instruction set type of the task is the same as the instruction set type of the application; The acquisition unit is further configured to: acquire the type of the instruction set of the task from the task control block.

21. A scheduling system, characterized in that, The scheduling system includes a scheduling device as described in any one of claims 18 to 20 and a plurality of processors, wherein at least one of the processors supports an instruction set whose type is different from the instruction sets supported by the other processors.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes instructions that, when executed on a computer, cause the computer to perform the operational steps of the method described in any one of claims 1 to 10.

Images