Backup partition multi-step checking and upgrading method of data chain system

Abstract

The invention discloses a backup partition multi-step checking and upgrading method for a data chain system, which comprises the following steps of: checking an upgrading file package corresponding to firmware to be upgraded through a multi-step checking method in a process of carrying out backup partition upgrading on firmware of air equipment and ground equipment through terminal equipment; the multi-step verification method comprises the following steps: step 1, performing double verification on a version number of an upgrade file package acquired by terminal equipment through a flag bit I, and performing third verification on an acquired corresponding equipment type through a flag bit II; and 2, summing all characters of the upgrade file package passing the triple verification according to a hexadecimal system, taking low eight bits, comparing the sums with a verification sum calculated by a running program of the equipment board card, and if the sums are consistent with the verification sum, carrying out file upgrade operation in the backup partition. The invention provides a data chain system backup partition upgrading method. According to the method, the reliability and safety of the upgrading process are effectively guaranteed through a multi-step verification mechanism.

Description

Technical Field

[0001] The present invention relates to the technical field of data backup, and in particular to a multi-step verification and upgrading method for backup partitions of a data link system. Background Art

[0002] The data link system consists of airborne equipment and ground equipment. During the upgrade of the data link system, if the upgrade firmware of the ground equipment is mistakenly upgraded to the airborne equipment or the upgrade firmware of the airborne equipment is upgraded to the ground equipment, the upgrade fails and the equipment cannot work normally after restarting; or special circumstances occur during the upgrade process (sudden power failure due to power failure, or human error, mistakenly thinking that the upgrade has been completed when the upgrade is not completed, and restarting the operation) resulting in the upgrade being incomplete, the equipment cannot work normally after restarting. In the existing data link system, the firmware upgrade of the airborne equipment and the ground equipment is usually carried out through the terminal device. However, during the firmware upgrade process, due to problems such as instability of network transmission, file corruption or version mismatch, the upgrade may fail or the equipment may be abnormal. Traditional firmware upgrade methods often lack sufficient verification mechanisms and cannot effectively ensure the integrity and correctness of the upgrade file package, thereby increasing the risk during the upgrade process.

[0003] For example, patent number CN201911298741.1 discloses a single system upgrade method with backup function and a system. During the upgrade process, if the upgrade file package has an error or version mismatch, it may cause the system to crash or malfunction. Therefore, how to ensure the correctness and integrity of the upgrade file package has become an urgent problem to be solved. Summary of the invention

[0004] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0005] In order to achieve these purposes and other advantages according to the present invention, a backup partition upgrade method for a data link system is provided, characterized in that, in the process of performing backup partition upgrade on the firmware of an aerial device and a ground device through a terminal device, an upgrade file package corresponding to the firmware to be upgraded is verified by a multi-step verification method, and the multi-step verification method includes the following steps:

[0006] Step 1: Double check the version number of the upgrade file package obtained by the terminal device through flag bit Ⅰ, and perform a third check on the corresponding device type through flag bit Ⅱ;

[0007] Step 2: All characters of the upgrade file package that has passed the triple check are summed in hexadecimal, the lower eight bits are taken, and compared with the checksum calculated by the device board running program. If the two are consistent, the file upgrade operation inside the backup partition is performed. Preferably, the firmware of the aerial device and the ground device are both upgraded by an incremental upgrade method.

[0008] A backup partition upgrade method for a data link system, applied to the backup partition upgrade multi-step verification method for a data link system according to claim 1, wherein the terminal device is communicatively connected with the ground device and the air device via a transfer cable;

[0009] The terminal device transmits the upgraded firmware to the aerial device and the ground device by copying, and the firmware of the aerial device and the ground device are upgraded by an incremental upgrade method.

[0010] Preferably, the terminal device comprises: a dual-core processor and a storage device in an integrated configuration, wherein two real-time operating systems FreeRTOS1 and FreeRTOS2 are stored in the storage device.

[0011] Preferably, when the FreeRTOS1 and FreeRTOS2 are executed by the processor, the following method is adopted:

[0012] After each successful upgrade, the upgrade file will be burned to the backup partition. When the upgrade to a higher version fails, the FreeRTOS1 or FreeRTOS2 real-time operating system is used to switch to a lower version in the backup partition, so that the air and ground devices can be online again.

[0013] Preferably, before the firmware is upgraded, the terminal device is powered on and started up by the software system in two stages.

[0014] Preferably, the first stage of powering on the software system includes:

[0015] Step 1: After the power is turned on, the CPU starts running directly from the BootROM on the read-only ROM embedded in the ZYQN chip. At the same time, the FPGA also performs parallel loading operations.

[0016] Step 2: BootROM starts loading Flash through the pin, and the bootloader loader FSBL data is sent to the internal high-speed memory OCM of the ZYQN chip for operation;

[0017] Step 3: The bootloader FSBL completes the initialization of the DDR hardware, and the bootloader FSBL loads UBOOT into the DDR for execution.

[0018] Preferably, the second stage of powering on the software system includes:

[0019] Step 4: FSBL first performs some basic initialization tasks and then passes control to U-Boot. U-Boot then reads the FPGA configuration information and loads the corresponding bitstream into the FPGA.

[0020] Step 5: UBOOT loads the FreeRTOS1 firmware into DDR and runs FreeRTOS1 through the CPU;

[0021] Step 6: UBOOT boots FreeRTOS2.

[0022] Preferably, the dual-core processor is configured as a Zynq7000 SOC chip, and the Zynq7000 SOC chip includes: an AD sampling module, an AGC module, a capture and multipath search module, a despreading module, a frequency estimation compensation module, a channel estimation module, an equalization module, a demodulation module and a decoding module;

[0023] Among them, the RF signal sampled by the AD sampling module inside the chip is received by the control circuit inside the chip. The sampled data first enters the AGC module for gain adjustment. Then, the discrete sampled data enters the capture and multipath search module. This module is responsible for determining whether the signal exists and providing multipath timing information when the signal is detected. Based on the multipath information, the data of each path will be despread. The despread data needs to be frequency offset compensated. The frequency offset information is provided by the frequency estimation compensation module. The multipath data after frequency offset compensation is further channel equalized. The channel estimation coefficient comes from the channel estimation module. The equalization module is responsible for merging the data of multiple paths and outputting it to the demodulation and decoding module. If the data demodulation is successful, it will be further processed by the ARM processor in the chip.

[0024] The present invention includes at least the following beneficial effects: The present invention provides a method for upgrading a backup partition of a data link system, which effectively ensures the reliability and security of the upgrading process through a multi-step verification mechanism.

[0025] Other advantages, objectives and features of the present invention will be embodied in part through the following description, and in part will be understood by those skilled in the art through study and practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The software system structure of the present invention;

[0027] Figure 2 The first stage of the software system of the present invention is powered on and started;

[0028] Figure 3The second stage of the software system of the present invention is powered on and started;

[0029] Figure 4 It is a connection diagram of the aerial equipment upgrade of the present invention;

[0030] Figure 5 It is a connection diagram for upgrading the ground equipment of the present invention;

[0031] Figure 6 It is a configuration diagram of the aerial device serial port of the present invention;

[0032] Figure 7 It is the serial port setting diagram of the ground equipment of the present invention;

[0033] Figure 8 The backup partition interface of the present invention;

[0034] Fig. 9 Password verification for upgrading the backup partition of the present invention;

[0035] Fig.10 Upgrading the backup partition of the present invention;

[0036] Fig.11 A schematic diagram of the modules designed for the software architecture of the present invention. DETAILED DESCRIPTION

[0037] The present invention is further described in detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0038] It should be understood that the terms such as “having”, “including” and “comprising” used herein do not exclude the existence or addition of one or more other elements or combinations thereof.

[0039] It should be noted that in the description of the present invention, the orientation or positional relationship indicated by the term is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0040] In the description of the present invention, unless otherwise clearly stipulated and limited, the terms "installed", "provided with", "mounted / connected", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be a direct connection or an indirect connection through an intermediate medium. It can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In addition, in the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0042] Figure 1 The present invention discloses a backup partition upgrade method for a data link system. In the process of performing backup partition upgrade on the firmware of an aerial device and a ground device through a terminal device, an upgrade file package corresponding to the firmware to be upgraded is verified by a multi-step verification method. The multi-step verification method includes the following steps:

[0043] Step 1: Double check the version number of the upgrade file package obtained by the terminal device through flag bit Ⅰ, and perform a third check on the corresponding device type through flag bit Ⅱ;

[0044] Step 2: Sum all characters of the upgrade file package that has passed the triple check in hexadecimal, take the lower eight bits, and compare them with the checksum calculated by the device board running program. If the two are consistent, perform the file upgrade operation in the backup partition.

[0045] Working principle:

[0046] In actual applications, the terminal device is upgraded online through the upgrade software to obtain the upgrade firmware of the air device and the ground device. Through step one, the first step is to check the version number, check whether the upgrade firmware has the firmware version number, and determine whether there is a version identifier V in the upgrade firmware;

[0047] The second step is version compliance verification to confirm whether the version is in the Va.b.cd format;

[0048] The third step is device category verification. Before upgrading the firmware, add the "air" and "ground" fields to verify and compare the air and ground devices one by one. When the upgraded device and the upgraded firmware are inconsistent, an upgrade error will be prompted. Only when the upgraded device and the upgraded firmware device category check bits are consistent can the upgrade be normal; then go through step 2, the fourth step is inspection and confirmation. Sum all the characters of the upgrade firmware name in hexadecimal and take the lower eight bits. When the checksum calculated by the device board running program is consistent with the checksum of the upgrade firmware itself, the backup partition upgrade can be performed.

[0049] The connection diagram of the aerial device upgrade is as follows: install the backup partition upgrade software on a computer, use a USB to RS422 serial cable, connect the USB port of the cable to the computer, and plug the DB9 male connector at the other end into the DB9 female connector of the aerial device transfer cable; the other end of the aerial device transfer cable is a J30J connector, model J30J-9ZKL; plug the aerial device transfer cable into the X2 connector of the aerial device, where the model of the X2 connector is J30J-9TJNP5-J, to achieve communication with the aerial device serial port 5, which is the serial port for the aerial device upgrade.

[0050] Ground upgrade connection diagram, install the backup partition upgrade software on a computer, use a USB to RS422 serial cable, the USB port of the cable is connected to the computer, and the DB9 male connector at the other end is plugged into the DB9 female connector corresponding to the serial port C of the ground equipment adapter cable; the other end of the ground equipment adapter cable is a 3-in-1 aviation plug; plug the ground equipment adapter cable into the 3-in-1 aviation socket of the ground equipment to achieve communication with the serial port C of the ground equipment, which is the serial port for ground equipment upgrade.

[0051] The aerial device does not have a power switch. When there is an external 24V power supply, the device is powered on directly. Open the "Backup Partition Upgrade PC Host" software, set the serial port, set the baud rate to 230400, data bit 8, check bit EVEN, stop bit 1. Since the X2 connector has two serial ports, confirm that the connection is serial port 5, click the "Open Serial Port" command to operate the aerial device;

[0052] The ground equipment is not limited by space and has a power switch. When there is an external 28V power supply, you need to press the power switch button to power on the equipment. Open the "Backup Partition Upgrade PC Host" software, set the serial port, set the baud rate to 460800, data bit 8, check bit EVEN, stop bit 1. Since the 3-in-1 aviation plug has three serial ports, confirm that the serial port C is connected, click the "Open Serial Port" command to operate the ground equipment.

[0053] A method for upgrading the backup partition of a data link system, after being applied to the multi-step verification method for upgrading the backup partition of a data link system described in claim 1, the terminal device is communicatively connected with the ground device and the aerial device via a switching cable; the terminal device transmits the upgraded firmware to the aerial device and the ground device via a copying method, and the firmware of the aerial device and the ground device are both upgraded using an incremental upgrade method. By adopting this technical solution, the terminal device periodically queries whether the version number of the firmware of the aerial device and the ground device is the latest version and verifies it. When the internal firmware of the aerial device and the ground device needs to be upgraded, the terminal device transmits the upgraded firmware to the aerial device and the ground device. At the same time, both the aerial device and the ground device adopt an incremental upgrade method, and only update the changed parts in the firmware, which greatly reduces the time and resources required for the upgrade. The upgrade files of the CPU and FPGA firmware of the ground device and the aerial device are divided into boot files, bootcfg configuration files, cpu files, and fpga files, among which the boot files and bootcfg configuration files are basically unchanged; the upgrade firmware of CPU1 is named airapp, the upgrade firmware of CPU2 is named airmac, and the upgrade firmware of FPGA is named airfpga. When a firmware is updated, the corresponding firmware is upgraded only when the version changes, in order to distinguish the firmware of the aerial device from the firmware of the ground device.

[0054] The terminal device described in the above technical solution includes: a dual-core processor and a storage device with an integrated setting, and two sets of real-time operating systems FreeRTOS1 and FreeRTOS2 are stored in the storage device. With this technical solution, first, the dual-core processor is the core computing unit of the terminal device, responsible for executing various calculations and instructions in the firmware upgrade process. The integrated design makes the data transmission between the dual-core processor and the storage device more efficient, reducing the possibility of data delay and transmission errors. The two sets of real-time operating systems FreeRTOS1 and FreeRTOS2 stored in the storage device provide a flexible and reliable software environment for firmware upgrades. The two operating systems can run independently without interfering with each other, so that the firmware upgrades of air equipment and ground equipment can be carried out simultaneously, greatly improving the upgrade efficiency. The Zynq7000 SOC chip is selected, and the physical layer algorithm and MAC layer algorithm are run on the Free RTOS1 system, and the application layer software is run on the Free RTOS2 system, thereby effectively reducing the pressure on one ARM. Through dual-core parallel loading, the device startup time and device response speed are effectively improved at the same time; RTOS is used to effectively implement task scheduling, and tasks are scheduled by priority. Once a task with a high priority is ready, it can deprive the CPU usage rights of tasks with a lower priority, thereby improving the real-time response capability of the system.

[0055] In the above technical solution, when the FreeRTOS1 and FreeRTOS2 are executed by the processor, the following method is adopted:

[0056] After each successful upgrade, the upgrade file is burned to the backup partition. When the upgrade to a higher version fails, the FreeRTOS1 or FreeRTOS2 real-time operating system switches to the lower version in the backup partition so that the air device and the ground device can go online again. With this technical solution, after each successful upgrade, the upgrade file of the new version will be burned to the backup partition. If the attempt to upgrade to a higher version fails (possibly due to incompatibility between the new version and the hardware, damage to the upgrade file, insufficient memory, etc.), the system will fall into an unusable state. At this time, the FreeRTOS1 or FreeRTOS2 real-time operating system will intervene and switch to the lower version stored in the backup partition. By rolling back the version to the lower version in the backup partition, the air device and the ground device can go back online and continue to perform their tasks. The backup partition and version rollback mechanism ensure the reliability of the system upgrade process and reduce the risk of system downtime caused by upgrade failure.

[0057] In the above technical solution, before the firmware is upgraded, the terminal device is powered on by the software system in two stages. With this technical solution, the software system power-on stage in the backup partition upgrade method of the data link system is a key step to ensure the smooth progress of the upgrade process. The technical solution of powering on and starting in stages can effectively manage resources, reduce conflicts, and improve the stability of the system.

[0058] In the above technical solution, the first stage of powering on the software system includes:

[0059] Step 1: After the power is turned on, the CPU starts running directly from the BootROM on the read-only ROM embedded in the ZYQN chip. At the same time, the FPGA also performs parallel loading operations.

[0060] Step 2: BootROM starts loading Flash through the pin, and the bootloader loader FSBL data is sent to the internal high-speed memory OCM of the ZYQN chip for operation;

[0061] Step 3: The bootloader FSBL completes the initialization of the DDR hardware, and the bootloader FSBL loads UBOOT into the DDR to run. With this technical solution, when the power is turned on, the CPU will not execute the main program immediately, but will start from a read-only memory (ROM) area inside the chip, usually called BootROM (bootloader read-only memory). This BootROM contains the basic code required to start the CPU and initialize the hardware. At the same time, the FPGA is also loading to prepare for subsequent hardware acceleration or specific functions.

[0062] After BootROM is executed, it will load the bootloader FSBL from the external memory (such as Flash). FSBL is usually loaded into the high-speed memory OCM (on-chip memory) inside the chip for execution. The advantage of this is that the access speed of OCM is very fast, which can ensure the fast execution of FSBL.

[0063] When FSBL is executed in OCM, it performs hardware initialization of DDR. DDR is the main memory used to store operating systems, applications, and data. Once DDR initialization is complete, FSBL then loads UBOOT into DDR and starts it. In this way, UBOOT can control the hardware, load and start the operating system or other applications.

[0064] In the above technical solution, the second stage of powering on the software system includes:

[0065] Step 4: After UBOOT takes over the authority from the bootloader loader FSBL, it loads the bitStream into the FPGA according to the partition information;

[0066] Step 5: UBOOT loads the FreeRTOS1 firmware into DDR and runs FreeRTOS1 through the CPU;

[0067] Step 6: UBOOT boots FreeRTOS2. With this technical solution, after FSBL completes DDR initialization, control is transferred to UBOOT. UBOOT then reads the partition information in the storage and finds the bitStream of the FPGA. UBOOT then loads the bitStream into the FPGA, thereby configuring the FPGA to perform specific hardware acceleration tasks or functions.

[0068] After the FPGA configuration is completed, UBOOT then loads the FreeRTOS1 firmware into DDR. FreeRTOS is a real-time operating system used in embedded systems to provide multi-tasking management, time slicing, memory management and other functions. UBOOT starts and runs FreeRTOS1 through the CPU, enabling it to manage subsequent tasks and applications. After FreeRTOS1 is running, UBOOT may also boot another real-time operating system instance, FreeRTOS2. Through the software power-on startup design, the system can be quickly started to meet the application requirements of the data link system to respond in a timely manner;

[0069] The dual-core processor in the above technical solution is configured as a Zynq7000 SOC chip, and the Zynq7000 SOC chip includes: an AD sampling module, an AGC module, a capture and multipath search module, a despreading module, a frequency estimation compensation module, a channel estimation module, an equalization module, a demodulation module and a decoding module;

[0070] Among them, the RF signal sampled by the AD sampling module inside the chip is received by the control circuit inside the chip, and first enters the AGC module for gain adjustment. Subsequently, the discrete sampling data enters the capture and multipath search module, which is responsible for determining whether the signal exists and providing multipath timing information when the signal is detected. Based on the multipath information, the data of each path will be despread. The despread data needs to be frequency offset compensated, and the frequency offset information is provided by the frequency estimation compensation module. The multipath data after frequency offset compensation is further channel equalized, and the channel estimation coefficient comes from the channel estimation module. The equalization module is responsible for merging the data of multiple paths and outputting it to the demodulation and decoding module. If the data demodulation is successful, it is further processed by the ARM processor in the chip. With this technical solution, the control circuit inside the chip receives the radio frequency signal and enters the AGC module for gain adjustment after AD sampling, and then the discrete sampling data enters the capture and multipath search module, through which the signal is judged whether it exists. If it exists, the timing information of the multipath is given, and then each path is despread according to the multipath information. The despread data needs to be compensated for frequency deviation, and the frequency deviation information comes from the frequency estimation compensation module. The multipath data after frequency deviation compensation needs to be channel equalized, and the channel estimation coefficient comes from the channel estimation module. Then the multipath and channel information are transmitted to the equalization module, which is responsible for merging multiple paths and then outputting them to the demodulation and decoding module to determine whether the received data is successful. If the data demodulation is successful, it is reported to the ARM of the chip for processing. The frequency estimation compensation module uses the local reference pilot and spread spectrum sequence for processing. First, after despreading each path, the despread received pilot symbol is obtained, and the frequency deviation is estimated by using the phase difference between the two symbols after removing the pilot reference information. According to the calculation of system parameters, the maximum Doppler shift of the airborne equipment relative to the ground equipment is 8650Hz, and the frequency deviation range that can be estimated using the pilot symbol phase difference is 312500Hz, which meets the system requirements. After estimating the signal frequency deviation, the received symbol data is frequency compensated using the estimated parameters, and the processing of subsequent modules is based on the compensated symbol data.

[0071] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation modes, and they can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A multi-step verification method for upgrading a backup partition of a data link system, characterized in that: In the process of performing a backup partition upgrade of the firmware of the air device and the ground device through the terminal device, the upgrade file package corresponding to the firmware to be upgraded is verified by a multi-step verification method, and the multi-step verification method includes the following steps: Step 1: Double check the version number of the upgrade file package obtained by the terminal device through flag bit Ⅰ, and perform a third check on the corresponding device type through flag bit Ⅱ; Step 2: Sum all characters of the upgrade file package that has passed the triple check in hexadecimal, take the lower eight bits, and compare them with the checksum calculated by the device board running program. If the two are consistent, perform the file upgrade operation in the backup partition.

2. A backup partition upgrade method for a data link system, applied to the backup partition upgrade multi-step verification method for a data link system according to claim 1, characterized in that: The terminal device is communicatively connected with the ground device and the aerial device via a switching cable; The terminal device transmits the upgraded firmware to the aerial device and the ground device by copying, and the firmware of the aerial device and the ground device are upgraded by an incremental upgrade method.

3. The backup partition upgrade method of the data link system according to claim 2, characterized in that: The terminal device comprises: a dual-core processor and a storage in an integrated arrangement, wherein two sets of real-time operating systems FreeRTOS1 and FreeRTOS2 are stored in the storage.

4. The backup partition upgrade method of the data link system according to claim 3, characterized in that: When the FreeRTOS1 and FreeRTOS2 are executed by the processor, the following method is adopted: After each successful upgrade, the upgrade file will be burned to the backup partition. When the upgrade to a higher version fails, the FreeRTOS1 or FreeRTOS2 real-time operating system is used to switch to a lower version in the backup partition, so that the air and ground devices can be online again.

5. The backup partition upgrade method of the data link system according to claim 4, characterized in that: Before the firmware is upgraded, the terminal device is powered on and started up by the software system in two stages.

6. The backup partition upgrade method of the data link system according to claim 5, characterized in that: The first stage of powering on the software system includes: Step 1: After the power is turned on, when the ZYNQ chip starts, its internal CPU will directly read and execute the startup code from the BootROM solidified on the read-only ROM. At the same time, the FPGA also performs parallel loading operations; Step 2: BootROM starts loading Flash through the pin, and the bootloader loader FSBL data is sent to the internal high-speed memory OCM of the ZYQN chip for operation; Step 3: The bootloader FSBL completes the initialization of the DDR hardware, and the bootloader FSBL loads UBOOT into the DDR for execution.

7. The backup partition upgrade method of the data link system according to claim 5, characterized in that: The second stage of powering on the software system includes: Step 4: FSBL first performs some basic initialization tasks and then passes control to U-Boot. U-Boot then reads the FPGA configuration information and loads the corresponding bitstream into the FPGA. Step 5: UBOOT loads the FreeRTOS1 firmware into DDR and runs FreeRTOS1 through the CPU; Step 6: UBOOT boots FreeRTOS2.

8. The backup partition upgrade method of the data link system according to claim 3, characterized in that: Also includes: The dual-core processor is configured as a Zynq7000 SOC chip, and the Zynq7000 SOC chip includes: an AD sampling module, an AGC module, a capture and multipath search module, a despreading module, a frequency estimation compensation module, a channel estimation module, an equalization module, a demodulation module and a decoding module; Among them, the RF signal sampled by the AD sampling module inside the chip is received by the control circuit inside the chip. The sampled data first enters the AGC module for gain adjustment. Then, the discrete sampled data enters the capture and multipath search module. This module is responsible for determining whether the signal exists and providing multipath timing information when the signal is detected. Based on the multipath information, the data of each path will be despread. The despread data needs to be frequency offset compensated. The frequency offset information is provided by the frequency estimation compensation module. The multipath data after frequency offset compensation is further channel equalized. The channel estimation coefficient comes from the channel estimation module. The equalization module is responsible for merging the data of multiple paths and outputting it to the demodulation and decoding module. If the data demodulation is successful, it will be further processed by the ARM processor in the chip.

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