Data processing device, memory failure determination method, and recording medium

Abstract

The present invention relates to a data processing device, a memory failure determination method, and a recording medium that accurately determine the presence or absence of a memory failure. In a data processing device (11), each of a first buffer memory (RM1), a second buffer memory (MM1), a third buffer memory (RM2), and a fourth buffer memory (MM2) stores data formed by a plurality of bits, a CPU (11A) reads data from the buffer memory (BM), performs bit inversion for the plurality of bits, generates bit-inverted data after value inversion for each of the plurality of bits, and performs bit inversion for each of the plurality of bits. Bit-inverted data is written to the buffer memory (BM) at a first time, the bit-inverted data is read from the buffer memory (BM) at a second time after the first time, and first data, which is the bit-inverted data written to the buffer memory (BM) at the first time, and second data, which is the bit-inverted data read from the buffer memory (BM) at the second time, are compared. Thus, the presence or absence of a failure in the buffer memory (BM) is determined.

Description

Technical Field

[0001] The present invention relates to a data processing device, a memory failure determination method and a recording medium. Background Art

[0002] Data (hereinafter sometimes referred to as "detection data") representing a value detected by a detector (hereinafter sometimes referred to as "detection value") is sometimes temporarily stored in a memory within an FPGA (Field-Programmable Gate Array) of a data processing device connected to the detector.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-191770

[0004] However, a failure easily occurs in the memory within the FPGA, and therefore when a failure occurs in the memory, accurate detection values ​​may not be presented to the operator of the detector. Summary of the invention

[0005] Therefore, the present invention proposes a technique capable of accurately determining the presence or absence of a failure in a memory.

[0006] The data processing device of the present invention has a memory and a processor. The memory stores data formed by multiple bits. The processor reads the data from the memory, performs bit inversion on the multiple bits to generate bit inversion data after the value of each bit of the multiple bits is inverted, writes the bit inversion data to the memory at a first moment, and reads the bit inversion data from the memory at a second moment after the first moment. Moreover, the processor compares the bit inversion data written to the memory at the first moment, that is, the first data, and the bit inversion data read from the memory at the second moment, that is, the second data, thereby determining whether the memory has a fault.

[0007] Effects of the Invention

[0008] According to the present invention, it is possible to accurately determine whether or not there is a failure in the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a diagram showing a configuration example of a substance detection system according to an embodiment of the present invention.

[0010] Figure 2 It is a diagram showing a configuration example of a buffer memory according to an embodiment of the present invention.

[0011] Figure 3 This is a diagram showing an example of bit inversion according to an embodiment of the present invention.

[0012] Figure 4 This is a diagram showing an example of bit inversion according to an embodiment of the present invention.

[0013] Figure 5 This is a diagram showing an example of a processing flow of the substance detection system according to the embodiment of the present invention.

[0014] Figure 6 This is a diagram showing an example of fixed data according to a comparative example of the present invention.

[0015] Figure 7 This is a diagram showing an example of fixed data according to a comparative example of the present invention. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present invention will be described based on the drawings. In the following embodiments, the same parts or processes are sometimes denoted by the same reference numerals and repeated descriptions are omitted.

[0017] [Example]

[0018] <Structure of the material detection system>

[0019] Figure 1 FIG. 1 is a diagram showing a configuration example of a substance detection system according to an embodiment of the present invention. Figure 1 In the embodiment, the material detection system 1 has a detection value display device 10 and a detector 20. The detection value display device 10 has a data processing device 11 and an LCD (Liquid Crystal Display) 12, and the data processing device 11 is connected to the detector 20. The data processing device 11 has a CPU (Central Processing Unit) 11A and an FPGA 11B. The CPU 11A has a CPU memory CM. The FPGA 11B has an A / D conversion unit 11C, a first buffer memory RM1, a second buffer memory MM1, a third buffer memory RM2, and a fourth buffer memory MM2. In the following, the first buffer memory RM1, the second buffer memory MM1, the third buffer memory RM2, and the fourth buffer memory MM2 are sometimes collectively referred to as "buffer memory BM".

[0020] An example of a substance to be detected by the substance detection system 1 is a gas, and an example of the detector 20 is a detection type gas analyzer. CPU11A is an example of a processor. An example of a buffer memory BM is a FIFO (First In First Out) type RAM (Random Access Memory). LCD12 is an example of a display.

[0021] The detector 20 detects the absorption spectrum of the reference gas for the first gas (hereinafter sometimes referred to as "the first reference gas"), and outputs the detection data indicating the value of the absorption spectrum of the first reference gas (hereinafter sometimes referred to as "the first gas reference data") to the A / D converter 11C. The A / D converter 11C converts the analog first gas reference data into digital first gas reference data, and writes the converted digital first gas reference data into the first buffer memory RM1. The digital first gas reference data is formed of a plurality of bits (e.g., 8 bits).

[0022] In addition, the detector 20 detects the absorption spectrum of the first gas, and outputs detection data indicating the value of the absorption spectrum of the first gas (hereinafter sometimes referred to as "first gas detection data") to the A / D converter 11C. The A / D converter 11C converts the analog first gas detection data into digital first gas detection data, and writes the converted digital first gas detection data into the second buffer memory MM1. The digital first gas detection data is formed of a plurality of bits (e.g., 8 bits).

[0023] In addition, the detector 20 detects the absorption spectrum of the reference gas for the second gas (hereinafter sometimes referred to as "second reference gas"), and outputs the detection data indicating the value of the absorption spectrum of the second reference gas (hereinafter sometimes referred to as "second gas reference data") to the A / D converter 11C. The A / D converter 11C converts the analog second gas reference data into digital second gas reference data, and writes the converted digital second gas reference data into the third buffer memory RM2. The digital second gas reference data is formed of a plurality of bits (e.g., 8 bits).

[0024] In addition, the detector 20 detects the absorption spectrum of the second gas, and outputs detection data indicating the value of the absorption spectrum of the second gas (hereinafter sometimes referred to as "second gas detection data") to the A / D converter 11C. The A / D converter 11C converts the analog second gas detection data into digital second gas detection data, and writes the digitally converted second gas detection data into the fourth buffer memory MM2. The digital second gas detection data is formed of a plurality of bits (e.g., 8 bits).

[0025] The CPU 11A reads the first gas reference data from the first buffer memory RM1, and causes the LCD 12 to display the value represented by the read first gas reference data. In addition, the CPU 11A performs bit inversion on the plurality of bits constituting the first gas reference data read from the first buffer memory RM1, thereby generating data after the values ​​of each of the plurality of bits included in the first gas reference data are inverted (hereinafter sometimes referred to as "first reference gas inversion data"). In addition, the CPU 11A writes and stores the first reference gas inversion data in the CPU memory CM at time t11, and writes it to the first buffer memory RM1. Next, the CPU 11A reads the first reference gas inversion data from the first buffer memory RM1 at time t12 after time t11, and reads the first reference gas inversion data from the CPU memory CM. Furthermore, the CPU 11A compares the first reference gas inversion data read from the CPU memory CM at time t12 (i.e., the first reference gas inversion data written to the first buffer memory RM1 at time t11) with the first reference gas inversion data read from the first buffer memory RM1 at time t12, thereby determining whether there is a fault in the first buffer memory RM1. When the value of the first reference gas inversion data written to the first buffer memory RM1 at time t11 and the value of the first reference gas inversion data read from the first buffer memory RM1 at time t12 are different, the CPU 11A determines that there is a fault in the first buffer memory RM1. On the other hand, when the values ​​are the same, the CPU 11A determines that there is no fault in the first buffer memory RM1. In addition, when the CPU 11A determines that there is a fault in the first buffer memory RM1, the LCD 12 displays a warning indicating that there is a fault in the first buffer memory RM1.

[0026] In addition, the CPU 11A reads the first gas detection data from the second buffer memory MM1, and causes the LCD 12 to display the value represented by the read first gas detection data. In addition, the CPU 11A performs bit inversion on the multiple bits forming the first gas detection data read from the second buffer memory MM1, thereby generating data after the values ​​of each of the multiple bits included in the first gas detection data are inverted (hereinafter sometimes referred to as "first gas inversion data"). In addition, the CPU 11A writes and stores the first gas inversion data in the CPU memory CM and writes it to the second buffer memory MM1 at time t21. Next, the CPU 11A reads the first gas inversion data from the second buffer memory MM1 at time t22 after time t21, and reads the first gas inversion data from the CPU memory CM. Moreover, the CPU 11A compares the first gas inversion data read from the CPU memory CM at time t22 (that is, the first gas inversion data written to the second buffer memory MM1 at time t21) and the first gas inversion data read from the second buffer memory MM1 at time t22, thereby determining whether there is a fault in the second buffer memory MM1. When the value of the first gas reversal data written to the second buffer memory MM1 at time t21 and the value of the first gas reversal data read from the second buffer memory MM1 at time t22 are different, the CPU 11A determines that the second buffer memory MM1 has a fault. On the other hand, when the two values ​​are the same, the CPU 11A determines that the second buffer memory MM1 has no fault. In addition, when the CPU 11A determines that the second buffer memory MM1 has a fault, the LCD 12 displays a warning indicating that the second buffer memory MM1 has a fault.

[0027] In addition, the CPU 11A reads the second gas reference data from the third buffer memory RM2, and causes the LCD 12 to display the value represented by the read second gas reference data. In addition, the CPU 11A performs bit inversion on the plurality of bits forming the second gas reference data read from the third buffer memory RM2, thereby generating data after the values ​​of each of the plurality of bits included in the second gas reference data are inverted (hereinafter sometimes referred to as "second reference gas inversion data"). In addition, the CPU 11A writes and stores the second reference gas inversion data in the CPU memory CM at time t31, and writes it to the third buffer memory RM2. Next, the CPU 11A reads the second reference gas inversion data from the third buffer memory RM2 at time t32 after time t31, and reads the second reference gas inversion data from the CPU memory CM. Furthermore, the CPU 11A compares the second reference gas inversion data read from the CPU memory CM at time t32 (i.e., the second reference gas inversion data written to the third buffer memory RM2 at time t31) and the second reference gas inversion data read from the third buffer memory RM2 at time t32, thereby determining whether there is a fault in the third buffer memory RM2. When the value of the second reference gas inversion data written to the third buffer memory RM2 at time t31 and the value of the second reference gas inversion data read from the third buffer memory RM2 at time t32 are different, the CPU 11A determines that the third buffer memory RM2 has a fault. On the other hand, when the values ​​are the same, the CPU 11A determines that the third buffer memory RM2 has no fault. In addition, when the CPU 11A determines that the third buffer memory RM2 has a fault, the LCD 12 displays a warning indicating that the third buffer memory RM2 has a fault.

[0028] In addition, the CPU 11A reads the second gas detection data from the fourth buffer memory MM2, and causes the LCD 12 to display the value represented by the read second gas detection data. In addition, the CPU 11A performs bit inversion for the plurality of bits forming the second gas detection data read from the fourth buffer memory MM2, thereby generating data after the values ​​of each of the plurality of bits included in the second gas detection data are inverted (hereinafter sometimes referred to as "second gas inversion data"). In addition, the CPU 11A writes and stores the second gas inversion data in the CPU memory CM at time t41, and writes it to the fourth buffer memory MM2. Next, the CPU 11A reads the second gas inversion data from the fourth buffer memory MM2 at time t42 after time t41, and reads the second gas inversion data from the CPU memory CM. Moreover, the CPU 11A compares the second gas inversion data read from the CPU memory CM at time t42 (i.e., the second gas inversion data written to the fourth buffer memory MM2 at time t41) and the second gas inversion data read from the fourth buffer memory MM2 at time t42, thereby determining whether there is a fault in the fourth buffer memory MM2. When the value of the second gas reversal data written to the fourth buffer memory MM2 at time t41 and the value of the second gas reversal data read from the fourth buffer memory MM2 at time t42 are different, the CPU 11A determines that the fourth buffer memory MM2 has a fault. On the other hand, when the two values ​​are the same, the CPU 11A determines that the fourth buffer memory MM2 has no fault. In addition, when the CPU 11A determines that the fourth buffer memory MM2 has a fault, the LCD 12 displays a warning indicating that the fourth buffer memory MM2 has a fault.

[0029] <Buffer memory configuration>

[0030] Figure 2 FIG. 1 is a diagram showing a configuration example of a buffer memory according to an embodiment of the present invention. Figure 2 , a FIFO type buffer memory BM formed of five areas, namely, a first area #1, a second area #2, a third area #3, a fourth area #4, and a fifth area #5 is shown as an example.

[0031] about Figure 2 The buffer memory BM shown, when the display object of LCD12, i.e., the detection data (hereinafter sometimes referred to as "display object data"), is the nth detection data written to the first area #1, CPU11A reads out the nth detection data written to the first area #1 as the display object data, and the bit inversion object, i.e., the detection data (hereinafter sometimes referred to as "bit inversion object data") from the buffer memory BM.

[0032] Next, the CPU 11A writes the n-th detection data read from the buffer memory BM into the area #A in the CPU memory CM as display target data.

[0033] In addition, CPU 11A performs bit inversion on a plurality of bits constituting the nth detection data read from buffer memory BM, and writes the bit-inverted data (hereinafter sometimes referred to as "nth inverted data") to area #B in CPU memory CM and to first area #1 of buffer memory BM.

[0034] Next, the CPU 11A reads out the n-th inverted data from the first area # 1 of the buffer memory BM.

[0035] Then, the CPU 11A determines whether the nth inverted data written in the area #B in the CPU memory CM and the nth inverted data read from the first area #1 of the buffer memory BM are different, thereby determining whether there is a memory error in the first area #1 of the buffer memory BM.

[0036] Next, the CPU 11A determines the presence or absence of a memory error for each of the second area #2, the third area #3, the fourth area #4, and the fifth area #5 of the buffer memory BM in the same manner as the first area #1.

[0037] <Bit inversion>

[0038] Figure 3 and Figure 4 FIG. 1 is a diagram showing an example of bit inversion according to an embodiment of the present invention. Figure 3 For example, when the nth detection data is 8-bit data of "00001111", the CPU 11A inverts the values ​​of each of the plurality of bits forming the nth detection data to generate the following: Figure 4 The n-th inverted data of 8 bits "11110000" is shown.

[0039] <Processing Flow>

[0040] Figure 5 This is a diagram showing an example of a processing flow of the substance detection system according to the embodiment of the present invention.

[0041] exist Figure 5 In step ST1 , the detector 20 writes the first gas reference data into the first buffer memory RM1 .

[0042] Next, in step ST2 , the detector 20 detects the absorption spectrum of the first gas and writes the first gas detection data into the second buffer memory MM1 .

[0043] Next, in step ST3 , the detector 20 detects the absorption spectrum of the second gas and writes the second gas detection data into the fourth buffer memory MM2 .

[0044] Next, in step ST4 , the CPU 11A determines the presence or absence of a failure in the first buffer memory RM1 and the second buffer memory MM1 in the above-described manner.

[0045] Next, in step ST5 , the detector 20 writes the second gas reference data into the third buffer memory RM2 .

[0046] Next, in step ST6 , the detector 20 detects the absorption spectrum of the first gas and writes the first gas detection data into the second buffer memory MM1 .

[0047] Next, in step ST7 , the detector 20 detects the absorption spectrum of the second gas and writes the second gas detection data into the fourth buffer memory MM2 .

[0048] Next, in step ST8 , the CPU 11A determines the presence or absence of a failure in the third buffer memory RM2 and the fourth buffer memory MM2 in the above-described manner.

[0049] As described above, the CPU 11A determines whether there is a fault in the first buffer memory RM1 and the second buffer memory MM1 in step ST4 just after the detector 20 writes the first gas detection data to the second buffer memory MM1 in step ST2 and writes the second gas detection data to the fourth buffer memory MM2 in step ST3. In addition, the CPU 11A determines whether there is a fault in the third buffer memory RM2 and the fourth buffer memory MM2 in step ST8 just after the detector 20 writes the first gas detection data to the second buffer memory MM1 in step ST6 and writes the second gas detection data to the fourth buffer memory MM2 in step ST7.

[0050] After the process of step ST8, the processes of steps ST1 to ST8 are set as one cycle, and the processes of steps ST1 to ST8 are repeatedly performed.

[0051] <Comparative Example>

[0052] In the above-described embodiment of the present invention, in order to determine whether or not there is a fault in the buffer memory BM, data in which the values ​​of each bit of data consisting of a plurality of bits are inverted (hereinafter sometimes referred to as "bit inverted data") is used.

[0053] Here, as failure modes of the buffer memory BM, there are a failure in which a bit value is fixed to "0" (hereinafter sometimes referred to as a "0 fixed failure") and a failure in which a bit value is fixed to "1" (hereinafter sometimes referred to as a "1 fixed failure").

[0054] As in the above-described embodiment, by writing and reading one bit inversion data once to one area in the buffer memory BM, both a 0 stuck fault and a 1 stuck fault in the one area can be detected.

[0055] On the other hand, a comparative example is considered in which the presence or absence of a failure in the buffer memory BM is determined using data whose bit values ​​are fixed in advance (hereinafter sometimes referred to as “fixed data”) without using bit inversion data. Figure 6 and Figure 7 1 is a diagram showing an example of fixed data involved in a comparative example of the present invention. Figure 6 In the case of the first fixed data having an 8-bit value of "10101010" as shown in the figure, it is also necessary to use the first fixed data after the values ​​of each bit are inverted. Figure 7 That is, in the comparative example, in order to detect both a 0-stuck fault and a 1-stuck fault in one area that is a fault determination target in the buffer memory BM, it is necessary to write and read the first fixed data once and to write and read the second fixed data once in the one area.

[0056] As described above, by using bit inversion data to determine whether the buffer memory BM has a fault, the number of write and read operations to the buffer memory BM can be halved compared to the case of using fixed data, thereby efficiently determining whether the buffer memory BM has a fault.

[0057] The embodiments and comparative examples of the present invention are described above.

[0058] In the above embodiment, the case where the substance detection system 1 detects a gas is described as an example. However, the technology of the present invention can be applied even when the substance detection system 1 detects a substance other than a gas.

[0059] In the above embodiment, a case where one detector 20 is connected to one data processing device 11 is described as an example. However, even when a plurality of detectors 20 are connected to one data processing device 11, the technology of the present invention can be applied.

[0060] In addition, all or part of each of the processes described above by the data processing device 11 can be implemented by causing the CPU 11A to execute a program corresponding to each of the processes. For example, the program corresponding to each of the processes described above can be stored in a memory or storage device of the data processing device 11, and the CPU 11A reads the program from the memory or storage device and executes it. In addition, the program can be stored in a program server connected to the data processing device 11 via any network, and downloaded from the program server to the data processing device 11 and executed, or stored in a recording medium that can be read by the data processing device 11 and read from the recording medium and executed. The recording medium that can be read by the data processing device 11 can include, for example, a removable storage medium such as a memory card, a USB memory, an SD card, a floppy disk, a magneto-optical disk, a CD-ROM, and a DVD.

[0061] As described above, the data processing device of the present invention (data processing device 11 of the embodiment) has a memory (buffer memory BM of the embodiment) and a processor (CPU 11A of the embodiment). The memory stores data formed by multiple bits. The processor reads data from the memory, performs bit inversion on multiple bits, and generates bit inversion data after the values ​​of each bit of the multiple bits are inverted. In addition, the processor writes the bit inversion data to the memory at a first moment, and reads the bit inversion data from the memory at a second moment after the first moment. Moreover, the processor compares the bit inversion data written to the memory at the first moment, that is, the first data, and the bit inversion data read from the memory at the second moment, that is, the second data, thereby determining whether there is a fault in the memory.

[0062] For example, the processor determines that the memory is not faulty when the value of the first data and the value of the second data are the same, and determines that the memory is faulty when the value of the first data and the value of the second data are different.

[0063] Furthermore, for example, the data processing device of the present invention includes an FPGA (FPGA11B in the embodiment) having a memory.

[0064] In addition, for example, the data stored in the memory is detection data indicating a value detected by a detector connected to the data processing device.

[0065] As described above, the presence or absence of a failure in the memory can be accurately determined.

[0066] In addition, several examples of several combinations of the techniques of the present invention are described below.

[0067] (1) A data processing device, comprising: a memory for storing data formed by a plurality of bits; and a processor for reading the data from the memory, performing bit inversion on the plurality of bits to generate bit inversion data after the values ​​of each of the plurality of bits are inverted, writing the bit inversion data to the memory at a first moment, reading the bit inversion data from the memory at a second moment after the first moment, and comparing the bit inversion data written to the memory at the first moment, i.e., first data, with the bit inversion data read from the memory at the second moment, i.e., second data, to determine whether the memory has a fault.

[0068] (2) According to the data processing device described in (1), the processor determines that the memory has no fault when the value of the first data and the value of the second data are the same, and on the other hand, determines that the memory has a fault when the value of the first data and the value of the second data are different.

[0069] (3) The data processing device according to (2) includes an FPGA having the memory.

[0070] (4) In the data processing device according to any one of (1) to (3), the data is detection data indicating a value detected by a detector connected to the data processing device.

[0071] (5) A memory fault determination method, wherein a processor reads data consisting of a plurality of bits from a memory, performs bit inversion on the plurality of bits to generate bit inversion data after the values ​​of each bit of the plurality of bits are inverted, writes the bit inversion data to the memory at a first moment, reads the bit inversion data from the memory at a second moment after the first moment, and compares the bit inversion data written to the memory at the first moment, i.e., first data, with the bit inversion data read from the memory at the second moment, i.e., second data, to determine whether the memory has a fault.

[0072] (6) A memory fault determination program, which is used to cause a processor to execute the following processing, namely, reading data formed by a plurality of bits from a memory, performing bit inversion on the plurality of bits to generate bit inversion data after the values ​​of each bit of the plurality of bits are inverted, writing the bit inversion data to the memory at a first moment, reading the bit inversion data from the memory at a second moment after the first moment, and comparing the bit inversion data written to the memory at the first moment, i.e., the first data, with the bit inversion data read from the memory at the second moment, i.e., the second data, to determine whether the memory has a fault.

[0073] Description of the label

[0074] 1 Material detection system

[0075] 10 Detection value display device

[0076] 20 Detector

[0077] 11 Data processing device

[0078] 11A CPU

[0079] CM CPU Memory

[0080] 11B FPGA

[0081] RM1 first buffer memory

[0082] MM1 second buffer memory

[0083] RM2 third buffer memory

[0084] MM2 fourth buffer memory

Claims

1. A data processing device, wherein: The data processing device comprises: a memory that stores data formed of a plurality of bits; and A processor reads the data from the memory, generates bit-reversed data after the values ​​of each bit of the plurality of bits are inverted by bit-reversing the plurality of bits, writes the bit-reversed data to the memory at a first moment, reads the bit-reversed data from the memory at a second moment after the first moment, and compares the bit-reversed data written to the memory at the first moment, i.e., the first data, with the bit-reversed data read from the memory at the second moment, i.e., the second data, thereby determining whether the memory is faulty.

2. The data processing device according to claim 1, wherein: The processor determines that the memory is not faulty when the value of the first data and the value of the second data are the same, and determines that the memory is faulty when the value of the first data and the value of the second data are different.

3. The data processing device according to claim 1, wherein: The data processing device has an FPGA having the memory.

4. The data processing device according to claim 1, wherein: The data is detection data indicating a value detected by a detector connected to the data processing device.

5. A memory failure determination method, wherein: The processor reads data consisting of multiple bits from the memory, By performing bit inversion on the plurality of bits, bit inversion data is generated in which the values ​​of each of the plurality of bits are inverted, writing the bit-reversed data into the memory at a first moment, reading the bit-reversed data from the memory at a second time after the first time, The presence or absence of a failure in the memory is determined by comparing the first data, which is the bit-inverted data written to the memory at the first time, with the second data, which is the bit-inverted data read from the memory at the second time.

6. A recording medium storing a memory failure determination program, the memory failure determination program being configured to cause a processor to execute the following processing: Reading data consisting of multiple bits from the memory, performing bit inversion on the plurality of bits to generate bit inversion data in which the values ​​of each of the plurality of bits are inverted, writing the bit-reversed data into the memory at a first moment, reading the bit-reversed data from the memory at a second time after the first time, The presence or absence of a failure in the memory is determined by comparing the first data, which is the bit-inverted data written to the memory at the first time, with the second data, which is the bit-inverted data read from the memory at the second time.

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