Data transmission system and method based on SoC bus

Abstract

The present invention discloses a data transmission system and method based on an SoC bus. The data transmission system based on the SoC bus includes a write control unit, a read control unit, and an arbiter. The write control unit and the read control unit are connected in parallel and serially arranged between the arbiter and the slave device. By providing the write control unit and the read control unit between the arbiter and the slave device, the present invention realizes data operation during data transmission. Specifically, when the write control unit receives the write enable signal sent by the arbiter, it caches and calculates the write address and write data, and writes the cached calculation data into the slave device. When the read control unit receives the read enable signal sent by the arbiter, it selects the bus read-back data according to the cached write address and read address, so as to reduce the storage access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and particularly to a data transmission system and method based on an SoC bus. Background Art

[0002] With the development of chip design level and manufacturing process, in the post-Moore era, the storage read and write efficiency of the von Neumann-based memory-computation separation architecture restricts the computing efficiency of the chip. Traditional data processing methods require first reading out the memory data, and then writing it back to the memory after data processing. However, this will increase the load on the bus and the memory, resulting in an increase in power consumption during data access and transmission of the chip, and reducing the data transmission efficiency. Summary of the Invention

[0003] An object of the present invention is to design a data transmission system based on an SoC bus to solve the above problems.

[0004] The present invention achieves the above object through the following technical solutions:

[0005] A data transmission system based on an SoC bus includes:

[0006] A write control unit, a read control unit, and an arbiter, wherein the write control unit and the read control unit are connected in parallel and serially arranged between the arbiter and the slave device;

[0007] The write control unit is configured to cache write data and a write address when receiving a write enable signal sent by the arbiter, perform data calculation on the cached write data, and write the data calculation result into the slave device;

[0008] The read control unit is configured to select bus read-back data according to the cached write address and read address when receiving a read enable signal sent by the arbiter.

[0009] The present invention also provides a data transmission method based on an SoC bus, which is applied to the above data transmission system based on an SoC bus. The data transmission method based on an SoC bus includes the following steps:

[0010] Cache the write address and write data, perform data calculation on the cached write data, and write the data calculation result into the slave device;

[0011] Select bus read-back data according to the cached write address and read address.

[0012] The beneficial effects of the present invention are as follows:

[0013] The data transmission system based on the SoC bus realizes data operation during data transmission by setting a write control unit and a read control unit between the arbiter and the slave device. Specifically, when the write control unit receives the write enable signal sent by the arbiter, it caches the write address and write data, performs data calculation on the cached write data, and writes the data calculation result into the slave device. When the read control unit receives the read enable signal sent by the arbiter, it selects the bus read-back data according to the cached write address and read address to reduce the memory access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption. Brief Description of the Drawings

[0014] Figure 1 It is the overall block diagram of the data transmission system based on the SoC bus of the present invention;

[0015] Figure 2 It is the flowchart of an embodiment of the data transmission method based on the SoC bus of the present invention;

[0016] Figure 3 It is the flowchart of another embodiment of the data transmission method based on the SoC bus of the present invention. Detailed Embodiments

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0019] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0020] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "inner", "outer", "left", "right", etc. are based on the orientation or positional relationships shown in the drawings, or the orientation or positional relationships in which the inventive product is customarily placed during use, or the orientation or positional relationships commonly understood by those skilled in the art. These are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0021] In addition, the terms "first", "second", etc. are only used for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0022] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, terms such as "arrangement", "connection", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] The following will describe in detail the specific embodiments of the present invention with reference to the drawings.

[0024] As Figures 1-3 shown, a data transmission system based on the SoC bus includes:

[0025] A write control unit, a read control unit, and an arbiter, where the write control unit and the read control unit are connected in parallel and serially arranged between the arbiter and the slave device;

[0026] The write control unit is configured to cache write data and a write address when receiving a write enable signal sent by the arbiter, perform data calculation on the cached write data, and write the data calculation result into the slave device;

[0027] The read control unit is configured to select bus read-back data according to the cached write address and read address when receiving a read enable signal sent by the arbiter.

[0028] In this embodiment, the arbiter is connected to the master device. During the data transmission process, the write control unit stores the write address and write data, divides them into two-level pipelines for optimizing the write data timing, performs data calculation, and writes the data calculation result into the slave device; the read control unit judges the cached write address and read address to select bus read-back data, thereby solving the problem of data delay.

[0029] The data transmission system based on the SoC bus of the present invention realizes data operation during data transmission by setting a write control unit and a read control unit between the arbiter and the slave device. Specifically, when the write control unit receives the write enable signal sent by the arbiter, it caches the write address and the write data, performs data calculation on the write data, and writes the data calculation result into the slave device. When the read control unit receives the read enable signal sent by the arbiter, it selects the bus read-back data according to the cached write address and read address, so as to reduce the storage access of the data processing module, thereby improving the data transmission efficiency and reducing the power consumption.

[0030] In one embodiment, the write control unit includes a write cache unit and a calculation unit. The write cache unit is used to cache the write address and the write data, and the calculation unit is used to perform data calculation on the cached write data and write the data calculation result into the slave device.

[0031] Among them, the write cache unit can be implemented by any write cache unit that can cache the write address and the write data. In this embodiment, the write cache unit can be selected as a register, and the register is used to cache the write address and the write data. It can be understood that since the register is tightly coupled with the arbiter, the access speed is very fast, which can reduce the access power consumption to improve the data transmission efficiency.

[0032] In this embodiment, the write cache unit stores the write address and the write data, and divides them into two-level pipelines for write data timing optimization. The calculation unit performs data calculation on the write data and writes the data calculation result into the slave device, so as to realize data calculation during data transmission to improve the data transmission efficiency.

[0033] In one embodiment, the read control unit includes an address judgment unit and a data selection unit. The address judgment unit is used to judge the cached write address and read address and output the corresponding judgment result, and the data selection unit selects the bus read-back data according to the judgment result.

[0034] In this embodiment, the address judgment unit judges whether the cached write address is consistent with the read address, and selects the bus read-back data according to the judgment result. Specifically, when the cached write address is consistent with the read address, the arbiter reads the data calculation result in the write control unit, and the data selection unit selects the data calculation result as the bus read-back data. When the cached write address and read address are inconsistent, the read data of the slave device is selected as the bus read-back data to solve the read data delay problem.

[0035] The present invention also proposes a data transmission method based on the SoC bus. The data transmission method based on the SoC bus is applied to the above-mentioned data transmission system based on the SoC bus. The data transmission method based on the SoC bus includes the following steps:

[0036] Cache the write address and write data, perform data calculation on the write data of the cache, and write the data calculation result to the slave device;

[0037] Select bus read-back data according to the write address and read address of the cache.

[0038] In this embodiment, the bus write process is divided into two-level pipelines. The first-level pipeline is responsible for caching the write data and address, and the second-level pipeline is responsible for writing the data calculation result to the slave device. Specifically, in the first-level pipeline, when the arbiter sends out a write enable signal, the write data and write address are cached in the corresponding registers, respectively identified as wdata_cache and waddr_cache. At the same time, the write cache flag signal wen_flag is set to indicate whether there is data in the write cache unit that needs to be written to the slave device. In the second-level pipeline, the data output from the write cache unit is calculated in the calculation unit and then the data calculation result wdata_cal is output. At this time, it is necessary to determine whether the arbiter has sent a read / write enable signal. The arbiter will only send one read / write enable signal in the same clock cycle. According to the presence or absence of the read / write enable signal, it is divided into the following three situations: Situation 1, there is no read enable signal and no write enable signal, that is, the data calculation result wdata_cal is written into the slave device, and the cache flag signal wen_flag is set to 0, indicating that the write cache is cleared and the calculation is completed; Situation 2, there is no read enable signal and there is a write enable signal, that is, the data calculation result wdata_cal is written into the slave device. At this time, the cache flag signal wen_flag needs to be kept at 1, indicating that the write cache is valid and the calculation is completed; Situation 3, there is a read enable signal and no write enable signal, that is, a read request is sent to the slave device first, the data calculation result wdata_cal is postponed from being written, and the write cache flag signal wen_flag is still set to 1. At this time, the read data path needs to be controlled by the read data module; The bus write process alternates through the above two-level pipelines to perform data calculation while realizing data transmission, reducing the storage access of the data processing module to improve the data transmission efficiency. The bus read process selects bus read-back data according to the write address and read address of the cache to solve the data latency problem.

[0039] In one embodiment, the step of selecting bus read-back data according to the write address and read address of the cache is specifically:

[0040] When the write address in the cache is the same as the read address, read the data calculation result in the write control unit and select the data calculation result as the bus read-back data;

[0041] When the write address in the cache is different from the read address, select the read data of the slave device as the bus read-back data.

[0042] In this embodiment, after receiving the read enable signal sent by the arbiter, the read control unit first determines whether the read address is consistent with the write address waddr_cache of the cache through the address determination unit. If the current read address is consistent with the write address waddr_cache of the cache, the arbiter reads the data calculation result wdata_cal from the calculation unit, and selects this data as the bus read-back data in the next clock cycle; if the current read address is inconsistent with the write address waddr_cache of the cache, the arbiter sends a read request to the slave device, and selects the data read from the slave device as the bus read-back data in the next clock cycle, thereby reducing the timing cost of the operation during the data transmission process to solve the problem of read data delay.

[0043] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A data transmission system based on SoC bus, characterized in that: The data transmission system based on the SoC bus includes a write control unit, a read control unit and an arbiter, wherein the write control unit and the read control unit are connected in parallel and arranged in series between the arbiter and the slave device; The write control unit is used for caching write data and write addresses when receiving a write enable signal sent by the arbitrator, performing data calculation on the cached write data, and writing the data calculation result into the slave device; The read control unit is used to select a bus to read back data according to the cached write address and read address when receiving a read enable signal sent by the arbitrator.

2. The data transmission system based on SoC bus according to claim 1, characterized in that: The write control unit includes a write cache unit and a calculation unit. The write cache unit is used to cache the write address and the write data. The calculation unit is used to perform data calculation on the cached write data and write the data calculation result into the slave device.

3. The data transmission system based on SoC bus according to claim 2, characterized in that: The write cache unit is a register, and the register is used to cache the write address and the write data.

4. The data transmission system based on SoC bus according to claim 1, characterized in that: The read control unit includes an address judgment unit and a data selection unit. The address judgment unit is used to judge the cached write address and the read address and output a corresponding judgment result. The data selection unit selects bus readback data according to the judgment result.

5. A data transmission method based on SoC bus, characterized in that: Applied to the data transmission system based on SoC bus as claimed in any one of claims 1 to 4, characterized in that the data transmission method based on SoC bus comprises the following steps: Cache write addresses and write data, perform data calculation on the cached write data, and write the data calculation result into the slave device; The bus is selected to read back data according to the cached write address and read address.

6. The data transmission method based on SoC bus according to claim 5, characterized in that: The step of selecting a bus to read back data according to the cached write address and read address is specifically: When the cached write address and read address are consistent, reading the data calculation result in the write control unit, and selecting the data calculation result as bus readback data; When the cached write address and read address are inconsistent, the read data from the device is selected as the bus read-back data.

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