Chip platform hardware abstraction layer construction method

Abstract

The embodiment of the present application provides a method for constructing a hardware abstraction layer of a chip platform, the method comprising: scanning the hardware feature information of the chip platform, constructing a hardware feature analysis model, classifying and annotating the hardware feature information to extract device interfaces, resource attributes and operation features, establishing a feature vector library of hardware components, and using a hierarchical clustering algorithm to group the hardware components to form a function category tree; training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters to generate a hardware abstraction rule library; loading the hardware abstraction rule library in a hardware abstraction layer engine, dynamically monitoring resource usage status and updating allocation strategies, and returning hardware operation results to the application layer through a unified interface; the present application can deeply understand hardware features, construct an intelligent interface encapsulation strategy, and realize efficient resource scheduling through technologies such as reinforcement learning.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method for constructing a hardware abstraction layer of a chip platform. Background Art

[0002] The design and implementation of the chip platform hardware abstraction layer is of great significance to improving the efficiency of software and hardware collaboration. Traditional hardware abstraction methods often adopt static interface encapsulation strategies, which are difficult to adapt to complex and changing hardware architectures and application requirements, and lack the ability to intelligently schedule hardware resources.

[0003] Existing hardware abstraction systems have deficiencies in many aspects. In terms of hardware feature analysis, the system lacks an in-depth understanding of the functional and performance characteristics of hardware components, and simple interface mapping cannot fully tap the performance potential of hardware resources. The feature extraction process is relatively mechanical, making it difficult to accurately capture the functional associations and dependencies between hardware components, resulting in a lack of systematic design of the abstraction layer.

[0004] Optimizing the interface encapsulation strategy is another key issue. Existing solutions mainly rely on preset encapsulation rules, lack adaptive learning capabilities, and are difficult to dynamically adjust interface design according to actual application scenarios. At the same time, the resource scheduling strategy is relatively simple and cannot effectively balance multiple performance indicators such as system latency, resource utilization, and compatibility, which can easily lead to resource waste or performance bottlenecks.

[0005] The scheduling and management of hardware operations also faces challenges. Traditional scheduling mechanisms often use simple queue management methods, lack dynamic analysis of operation request characteristics and resource status, and are difficult to achieve refined resource allocation. The cache strategy is not smart enough and cannot effectively utilize the local characteristics of hardware operations, affecting the response efficiency of the system.

[0006] Therefore, a smarter and more flexible hardware abstraction layer construction solution is needed. Summary of the invention

[0007] In response to the problems in the prior art, the present application provides a method for constructing a hardware abstraction layer of a chip platform, which can deeply understand the hardware characteristics, build an intelligent interface packaging strategy, and achieve efficient resource scheduling through technologies such as reinforcement learning.

[0008] In order to solve at least one of the above problems, the present application provides the following technical solutions:

[0009] In a first aspect, the present application provides a method for constructing a chip platform hardware abstraction layer, comprising:

[0010] Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree;

[0011] Based on the function category tree, the adaptive abstract model is trained, hardware components with similar functions are mapped to a unified interface space, a graph structure is used to represent the dependencies between hardware components, a deep Q network is constructed to optimize the interface encapsulation strategy, hardware resource status and operation requests are used as status inputs, an action space including interface merging, parameter adjustment and resource reallocation is defined, a composite reward function is designed to comprehensively calculate interface call delay, resource utilization and compatibility scores, the three scores are integrated into a strategy evaluation index based on a weighted summation method, an experience pool with a double-ended queue structure is constructed to store training samples, a priority sampling method is used to select experience data with higher value, and a target Q value is calculated based on a temporal difference algorithm to update the strategy network parameters to generate a hardware abstract rule base;

[0012] The hardware abstract rule library is loaded in the hardware abstraction layer engine, the input hardware operation request is parsed, the operation request is mapped to the corresponding abstract module through the hierarchical routing algorithm, the hardware resources are scheduled and allocated according to the abstract rule library, a cache queue for hardware operations is established, the resource usage status is dynamically monitored and the allocation strategy is updated, and the hardware operation results are returned to the application layer through a unified interface.

[0013] Furthermore, the hardware characteristic information of the scanning chip platform is constructed, a hardware characteristic analysis model is constructed, the hardware characteristic information is classified and labeled to extract device interfaces, resource attributes and operation characteristics, a characteristic vector library of hardware components is constructed, and a hierarchical clustering algorithm is used to group the hardware components to form a functional category tree, including:

[0014] Scan the hardware device information of the chip platform through the system bus interface, read the device descriptor to obtain the model and configuration parameters of the hardware components, establish a feature extraction model based on a convolutional neural network, standardize the interface specifications, working modes and performance parameters of the hardware components, and generate hardware feature vectors;

[0015] The cosine similarity between hardware feature vectors is calculated to construct a similarity matrix. A bottom-up hierarchical clustering algorithm is used to recursively merge hardware components. The clustering level is determined based on the inter-class distance threshold. The clustering results are organized into a tree structure to represent the functional classification relationship of hardware components.

[0016] Furthermore, the training of the adaptive abstract model based on the functional category tree to map hardware components with similar functions to a unified interface space includes:

[0017] The network structure of the abstract model is constructed using a recurrent neural network. The node features of the functional category tree are used as the input sequence. The cross entropy loss function is used to train the model to learn the functional feature distribution of hardware components. The network parameters are optimized through the back propagation algorithm to obtain an adaptive abstract model.

[0018] Based on the trained abstract model, the functional feature vectors of the hardware components are extracted, and the coordinate system of the unified interface space is constructed. The t-SNE algorithm is used to reduce the dimension of the functional feature vectors. The interface similarity matrix is ​​calculated according to the Euclidean distance between the vectors, and the components with similarity higher than the preset threshold are mapped to the same interface specification.

[0019] Furthermore, the dependency relationship between hardware components is represented by a graph structure, a deep Q network is constructed to optimize the interface encapsulation strategy, hardware resource status and operation request are used as status input, and an action space including interface merging, parameter adjustment and resource reallocation is defined, including:

[0020] Construct a directed acyclic graph data structure to store the dependencies between hardware components. Use the data flow and control flow between component nodes as the edges of the graph. Sort the components based on the topological sorting algorithm to determine the execution order. Use the adjacency matrix to represent the connection relationship between components. Use the graph embedding algorithm to generate a low-dimensional representation vector of the component nodes.

[0021] A deep neural network structure consisting of convolutional layers and fully connected layers is designed. Hardware resource occupancy, request queue length and response delay are taken as state vector inputs. The action space is defined to include three dimensions: interface merging threshold adjustment, cache strategy selection and resource quota allocation. The ε-greedy strategy is used for action exploration, and a double Q network structure is adopted to reduce the impact of over-estimation.

[0022] Furthermore, the composite reward function is designed to comprehensively calculate the interface call delay, resource utilization and compatibility score, and the three scores are integrated into a strategy evaluation index based on a weighted summation method. An experience pool with a double-ended queue structure is constructed to store training samples, and a priority sampling method is used to select high-value experience data. The target Q value is calculated based on a temporal difference algorithm to update the strategy network parameters and generate a hardware abstract rule base, including:

[0023] The interface call delay is normalized to obtain the latency score, the average CPU and memory utilization is calculated to obtain the resource score, the success rate is calculated based on the interface compatibility test results to obtain the compatibility score, the adaptive weight method is used to weight the sum of the three scores to obtain the comprehensive evaluation index, and the sliding window method is used to smooth the fluctuation of the evaluation index;

[0024] A double-ended queue data structure is used to implement a limited-capacity experience replay pool. Importance sampling is performed based on the sample priority calculated based on the TD error. The sampled transfer sequence is input into the target network to calculate the target Q value. The Bellman equation is used to calculate the temporal difference error. The policy network parameters are updated through the back-propagation algorithm, and the converged network parameters are saved as an abstract rule base.

[0025] Furthermore, the hardware abstraction rule library is loaded in the hardware abstraction layer engine, the input hardware operation request is parsed, and the operation request is mapped to the corresponding abstract module through the hierarchical routing algorithm, including:

[0026] Read the network parameters of the abstract rule library from the persistent storage, build the inference calculation graph and initialize the neural network model, establish a rule index table to save the mapping relationship between abstract rules and hardware components, create a request parser for each type of hardware operation to parse the operation parameters and constraints, and start the load check service of the rule library to verify the integrity of the rules;

[0027] A hierarchical routing table is implemented based on a hash table to store the correspondence between requests and abstract modules. The longest prefix matching algorithm is used to find the target module of the operation request. The routing weight is calculated according to the priority and resource requirements of the request. A weighted round-robin method is used to load balance among multiple candidate modules and distribute the requests to the selected abstract module for processing.

[0028] Furthermore, the scheduling and allocation of hardware resources according to the abstract rule base, establishing a cache queue for hardware operations, dynamically monitoring resource usage status and updating allocation strategies, and returning hardware operation results to the application layer through a unified interface include:

[0029] Initialize the scheduler based on the resource quota policy in the abstract rule base, use the priority queue to manage hardware operation requests, use the token bucket algorithm to control the resource access frequency, reserve resource quotas for high-priority requests through the resource reservation mechanism, and calculate resource utilization in real time to update the dynamic allocation threshold;

[0030] A circular buffer is used to cache the results of hardware operations, an asynchronous notification mechanism is established to monitor operation completion events, a memory pool is used to manage the temporary storage space of result data, the operation results and status information are encapsulated through a unified interface protocol, and the encapsulated data is returned to the application layer program through a callback function.

[0031] In a second aspect, the present application provides a chip platform hardware abstraction layer construction device, comprising:

[0032] Function classification module, used to scan the hardware feature information of the chip platform, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group hardware components to form a function category tree;

[0033] A rule abstraction module is used to train an adaptive abstract model based on the function category tree, map hardware components with similar functions to a unified interface space, use a graph structure to represent the dependencies between hardware components, build a deep Q network to optimize the interface encapsulation strategy, use hardware resource status and operation requests as status inputs, define an action space including interface merging, parameter adjustment, and resource reallocation, design a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrate the three scores into a strategy evaluation index based on a weighted summation method, build an experience pool with a double-ended queue structure to store training samples, use a priority sampling method to select high-value experience data, calculate the target Q value based on a temporal difference algorithm, update the strategy network parameters, and generate a hardware abstract rule base;

[0034] The resource allocation module is used to load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor the resource usage status and update the allocation strategy, and return the hardware operation results to the application layer through a unified interface.

[0035] In a third aspect, the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the chip platform hardware abstraction layer construction method when executing the program.

[0036] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip platform hardware abstraction layer construction method.

[0037] In a fifth aspect, the present application provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the chip platform hardware abstraction layer construction method.

[0038] It can be seen from the above technical scheme that the present application provides a method for constructing a hardware abstraction layer of a chip platform, which constructs a hardware feature analysis model by scanning the hardware feature information of the chip platform, classifies and annotates the hardware feature information to extract device interfaces, resource attributes and operation features, establishes a feature vector library of hardware components, and uses a hierarchical clustering algorithm to group the hardware components to form a functional category tree; trains an adaptive abstract model based on the functional category tree, maps hardware components with similar functions to a unified interface space, calculates the target Q value based on the temporal difference algorithm, updates the strategy network parameters to generate a hardware abstraction rule library; loads the hardware abstraction rule library in the hardware abstraction layer engine, dynamically monitors the resource usage status and updates the allocation strategy, and returns the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics, building an intelligent interface encapsulation strategy, and achieving efficient resource scheduling through technologies such as reinforcement learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 This is one of the flow charts of the chip platform hardware abstraction layer construction method in the embodiment of the present application;

[0041] Figure 2 This is a second flow chart of the method for constructing a chip platform hardware abstraction layer in an embodiment of the present application;

[0042] Figure 3 The third flowchart of the chip platform hardware abstraction layer construction method in the embodiment of the present application;

[0043] Figure 4 This is a fourth flow chart of the chip platform hardware abstraction layer construction method in the embodiment of the present application;

[0044] Figure 5 This is a fifth flow chart of the chip platform hardware abstraction layer construction method in the embodiment of the present application;

[0045] Figure 6 This is a sixth flow chart of the chip platform hardware abstraction layer construction method in the embodiment of the present application;

[0046] Figure 7 FIG7 is a flowchart of a method for constructing a chip platform hardware abstraction layer in an embodiment of the present application;

[0047] Figure 8A structural diagram of a chip platform hardware abstraction layer construction device in an embodiment of the present application;

[0048] Fig. 9 It is a schematic diagram of the structure of an electronic device in an embodiment of the present application.

[0049] Reference numerals:

[0050] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0052] The acquisition, storage, use, and processing of data in the technical solution of this application comply with the relevant provisions of national laws and regulations.

[0053] In view of the problems existing in the prior art, the present application provides a method for constructing a hardware abstraction layer of a chip platform, which constructs a hardware feature analysis model by scanning the hardware feature information of the chip platform, classifies and annotates the hardware feature information to extract device interfaces, resource attributes and operation features, establishes a feature vector library of hardware components, and uses a hierarchical clustering algorithm to group the hardware components to form a functional category tree; trains an adaptive abstract model based on the functional category tree, maps hardware components with similar functions to a unified interface space, calculates the target Q value based on the temporal difference algorithm, updates the strategy network parameters to generate a hardware abstraction rule library; loads the hardware abstraction rule library in the hardware abstraction layer engine, dynamically monitors the resource usage status and updates the allocation strategy, and returns the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware features and building an intelligent interface encapsulation strategy.

[0054] In order to deeply understand the hardware features, build an intelligent interface packaging strategy, and realize efficient resource scheduling through technologies such as reinforcement learning, this application provides an embodiment of a method for building a chip platform hardware abstraction layer, see Figure 1 The chip platform hardware abstraction layer construction method specifically includes the following contents:

[0055] Step S101: Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree;

[0056] Optionally, in this embodiment, during the construction of the hardware abstraction layer of the chip platform, it is first necessary to comprehensively collect and analyze the hardware characteristic information. The system scans various hardware devices connected to the platform through the bus interface and reads the device descriptor to obtain basic configuration information. For common peripherals such as UART, I2C, SPI and other communication interfaces, the system collects parameters such as baud rate, clock frequency, data bit width, etc.; for storage devices such as SRAM and Flash, the system records the capacity, access timing, address range and other characteristics; for computing units such as DSP and NPU, the system obtains its instruction set architecture, calculation accuracy, parallelism and other attributes.

[0057] In order to realize intelligent analysis of hardware characteristics, the system builds a feature extraction model based on convolutional neural network. The model contains multiple convolution layers to extract local features, and extracts significant features through maximum pooling layer dimensionality reduction, and finally generates fixed-dimensional feature vectors through full connection layer. For example, for a certain model of UART controller, its feature vector contains key information such as baud rate range, FIFO depth, interrupt trigger conditions, etc., which are encoded in numerical form for subsequent processing.

[0058] The system uses a hierarchical annotation strategy to classify and organize hardware features. At the interface level, the physical interface type, signal timing, transmission protocol, etc. are annotated; at the resource level, memory usage, power consumption characteristics, interrupt resources, etc. are annotated; at the operation level, the supported command set, operation mode, error handling mechanism, etc. are annotated. This multi-dimensional feature annotation provides a sufficient basis for the subsequent abstract layer design.

[0059] Based on the annotated feature vectors, the system uses a hierarchical clustering algorithm to build a functional category tree. The algorithm first calculates the cosine similarity between the feature vectors of each hardware component to form a similarity matrix. Then, a bottom-up clustering strategy is adopted, starting from a single leaf node, and gradually merging component clusters with high similarity until the preset clustering threshold is reached. For example, UART and USB devices with similar communication functions may be clustered into the same branch, while DSP and NPU with data processing functions are clustered into another branch.

[0060] This technical solution solves the problem of subjectivity and incompleteness of manually defined features in traditional hardware abstraction layer design. Through automated feature extraction and cluster analysis, the system can objectively identify the functional similarities between hardware components, laying the foundation for subsequent interface unification. In practical applications, this solution significantly improves the adaptability of the hardware abstraction layer and can automatically adapt to newly added hardware devices. Test results show that for common embedded platforms, the system can complete the scanning and analysis of all hardware features within 10 seconds, with a clustering accuracy of more than 95%, providing a stable and reliable hardware access interface for upper-level applications.

[0061] In particular, the solution demonstrates excellent scalability when dealing with heterogeneous computing platforms. For example, on a certain AI acceleration chip platform, the system successfully identified the functional characteristics of dedicated computing units including CNN accelerators and vector processors, and rationally integrated them into a unified hardware abstraction framework, greatly simplifying the complexity of application development.

[0062] Step S102: training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, using a graph structure to represent the dependencies between hardware components, building a deep Q network to optimize the interface encapsulation strategy, taking hardware resource status and operation requests as status inputs, defining an action space including interface merging, parameter adjustment, and resource reallocation, designing a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrating the three scores into a strategy evaluation index based on a weighted summation method, building an experience pool with a double-ended queue structure to store training samples, using a priority sampling method to select experience data with higher value, and calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters and generate a hardware abstract rule base;

[0063] Optionally, in this embodiment, after completing the hardware feature analysis and function classification, this embodiment uses a recurrent neural network (RNN) to train an adaptive abstract model based on the function category tree obtained in the above steps. The model uses the node feature sequence in the function category tree as input and captures the long-term dependencies between hardware components through LSTM units. For example, for the data acquisition devices identified in the above steps, the model can learn the common feature patterns of components such as ADC and sensor interfaces, thereby mapping them to similar areas in the unified interface space.

[0064] This embodiment constructs a directed acyclic graph (DAG) to describe the dependencies between hardware components, and the edges represent the data flow and control flow between components. Taking the image processing pipeline as an example, the components such as the camera interface, ISP processing unit, and display controller that have completed feature extraction in the previous steps form a serial dependency chain at this stage. Through the graph embedding algorithm, a low-dimensional vector representation reflecting the topological relationship of the components is generated, and these vectors are used as input features of the deep Q network.

[0065] The state space of the deep Q network contains dynamic information such as hardware resource utilization and request queue length. The network structure uses three layers of convolution to extract features and outputs Q value estimation through the fully connected layer. For the different types of hardware components identified in the previous steps, this embodiment defines three key action dimensions: interface merging threshold, cache strategy selection, and resource quota allocation. Through the ε-greedy strategy, the exploration and utilization of strategy optimization are balanced by exploring in the action space.

[0066] The reward function design of this embodiment takes into account multiple performance indicators: the interface call delay reflects the response speed of the abstraction layer, the resource utilization reflects the system efficiency, and the compatibility score represents the versatility of the interface. The sliding window method is used to calculate the mean of each indicator, and they are integrated into a unified evaluation standard through an adaptive weight mechanism.

[0067] In order to improve the training efficiency, this embodiment implements an experience replay mechanism based on a double-ended queue. New training samples are queued from the end of the queue, and old samples are removed from the head when the queue is full. Sample priority is calculated based on the TD error, and experience data with larger errors are preferentially sampled for training. This mechanism ensures that the network can quickly learn from the most valuable experience.

[0068] Through temporal difference learning, this embodiment gradually optimizes the policy network parameters. For each training batch, the difference between the current Q value and the target Q value is calculated, and the network weights are updated through back propagation. The network parameters after training convergence are saved as a hardware abstraction rule library to guide interface encapsulation and resource scheduling decisions during actual runtime.

[0069] This technical solution solves the problem that traditional hardware abstraction layers are difficult to adapt to complex heterogeneous systems. For the various hardware components identified in the previous steps, the test of this embodiment on a certain type of AI accelerator platform shows that the abstraction layer optimized by reinforcement learning can reduce interface call latency by 30%, increase resource utilization by 25%, and maintain more than 95% interface compatibility. Especially when dealing with burst loads, it can adaptively adjust resource allocation strategies to ensure timely response to critical tasks.

[0070] Step S103: Load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor resource usage status and update allocation strategies, and return the hardware operation results to the application layer through a unified interface.

[0071] Optionally, this embodiment loads the hardware abstraction rule library obtained by the training in the above steps into the hardware abstraction layer engine to build an efficient request processing framework. When the application layer initiates a hardware operation request, the engine first performs syntax parsing on the request message to extract key information such as operation type, target device, parameter configuration, etc. For example, for data acquisition requests, the parser can identify parameters such as sampling frequency, channel selection, and trigger conditions.

[0072] Based on the function category tree structure constructed in the above steps, this embodiment implements a multi-level routing mechanism. The routing algorithm first locates the target branch in the function category tree according to the requested operation type, and then selects a specific abstract module based on the hardware feature matching degree. Taking image processing as an example, when an image scaling request is received, the routing algorithm weighs the current load and processing capacity of processing units such as GPU and dedicated ISP to select the optimal execution path.

[0073] This embodiment implements an adaptive resource allocation mechanism based on the scheduling strategy in the abstract rule base. The rule base contains policy parameters such as priority definition, resource quota limit and access rights for different operation types. The scheduler will dynamically adjust the resource allocation plan according to the current system load status. For example, when it is detected that a storage device is close to the bandwidth limit, the scheduler will automatically enable data compression or load distribution mechanism.

[0074] In order to optimize the request processing efficiency, this embodiment establishes a multi-level cache queue structure. For each type of hardware operation identified in the previous steps, requests are assigned to queues of different priorities according to their time sensitivity and resource demand characteristics. The high-priority queue adopts a real-time scheduling strategy to ensure timely response to key operations; the low-priority queue implements request merging and batch processing mechanisms to improve resource utilization efficiency.

[0075] This embodiment implements a real-time monitoring mechanism for the use status of hardware resources. The monitoring module periodically collects operating indicators such as load, temperature, and power consumption of each hardware component, and feeds this information back to the scheduler. When a performance bottleneck or abnormal state is detected, the scheduler can adjust the resource allocation strategy in time to ensure stable operation of the system. For example, when it is found that the temperature of an AI accelerator is too high, its operating frequency is automatically reduced and the computing tasks are reallocated.

[0076] Finally, this embodiment returns the hardware operation results to the application layer through a unified interface specification. The interface encapsulates the underlying hardware differences and provides a consistent calling method for the application. For the various hardware components defined in the above steps, the interface layer implements a standardized error handling mechanism and status reporting function.

[0077] This technical solution effectively solves the problem of resource management and interface unification on heterogeneous hardware platforms. In actual tests, the hardware abstraction layer implemented in this embodiment can simultaneously process concurrent requests from multiple applications, with an average response time of less than 100 microseconds and resource utilization maintained at more than 85%. Especially when processing complex multimedia applications, through intelligent request routing and resource scheduling, the system throughput is increased by 40% compared with the traditional solution, while maintaining a stable service quality.

[0078] From the above description, it can be seen that the chip platform hardware abstraction layer construction method provided in the embodiment of the present application can build a hardware feature analysis model by scanning the chip platform hardware feature information, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation characteristics, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group hardware components to form a functional category tree; train an adaptive abstract model based on the functional category tree, map hardware components with similar functions to a unified interface space, calculate the target Q value based on the timing difference algorithm to update the strategy network parameters to generate a hardware abstract rule library; load the hardware abstract rule library in the hardware abstraction layer engine, dynamically monitor the resource usage status and update the allocation strategy, and return the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics and building an intelligent interface encapsulation strategy.

[0079] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 2 , and can also include the following:

[0080] Step S201: Scan the hardware device information of the chip platform through the system bus interface, read the device descriptor to obtain the model and configuration parameters of the hardware component, establish a feature extraction model based on a convolutional neural network, standardize the interface specifications, working modes and performance parameters of the hardware components, and generate a hardware feature vector;

[0081] Step S202: Calculate the cosine similarity between hardware feature vectors to construct a similarity matrix, use a bottom-up hierarchical clustering algorithm to recursively merge hardware components, determine the clustering level based on the inter-class distance threshold, and organize the clustering results into a tree structure to represent the functional classification relationship of hardware components.

[0082] Optionally, this embodiment first implements a comprehensive scan of the chip platform through the system bus interface. During the scanning process, each device node is accessed in turn through standard bus protocols such as AMBA, AXI, and APB to read its device descriptor information. For example, for communication peripherals, obtain its communication protocol type, data bit width, clock frequency and other parameters; for storage devices, read its storage capacity, access timing, address range and other information; for computing acceleration units, collect its operation accuracy, instruction set characteristics, parallel capability and other key parameters.

[0083] This embodiment constructs a multi-layer convolutional neural network for feature extraction. The input layer of the network receives the original parameters in the device descriptor and gradually extracts features through a three-layer convolution structure. The first layer uses a 1×3 convolution kernel to extract local features, the second layer uses a 1×5 convolution kernel to capture medium-scale feature patterns, and the third layer uses a 1×7 convolution kernel to integrate large-scale features. Each layer of convolution is followed by a maximum pooling layer to extract significant features and reduce feature dimensions. Finally, the features are mapped to a vector space of fixed dimensionality through a fully connected layer.

[0084] In the standardization processing stage, this embodiment adopts differentiated normalization strategies for different types of parameters. For numerical parameters such as clock frequency, cache size, etc., the Min-Max normalization method is used to map them to the [0,1] interval; for enumerated parameters such as interface type, working mode, etc., one-hot encoding (One-HotEncoding) is used; for text description information, it is converted into a numerical vector through word embedding technology. This multi-modal standardization process ensures the comparability of different types of parameters.

[0085] After obtaining the hardware feature vectors, this embodiment calculates the cosine similarity between the vectors and constructs an N×N similarity matrix (N is the number of hardware components). The similarity calculation takes into account the importance weights of each dimension of the feature vector, which are determined through preliminary training. For example, for communication devices, the weight of the protocol type is higher than the physical interface parameter; for storage devices, the weight of the access performance is higher than the capacity parameter.

[0086] Based on the similarity matrix, this embodiment uses a hierarchical clustering algorithm to build a classification tree from bottom to top. Initially, each hardware component is an independent leaf node. In each iteration, the algorithm selects the two categories with the highest similarity to merge and updates the inter-class distance at the same time. The inter-class distance is calculated using the average link method, that is, the average similarity of all component pairs in the two categories. When the inter-class distance is less than the preset threshold, the merging process is stopped.

[0087] The resulting functional category tree reflects the hierarchical functional relationship between hardware components. For example, on an AI chip platform, the top level of the tree may contain three main branches: communication, storage, and computing; the communication branch may be further subdivided into subcategories such as high-speed serial interfaces and bus controllers; the computing branch may contain subcategories such as general-purpose processors and neural network accelerators.

[0088] This technical solution solves the problem of strong subjectivity and poor scalability of traditional hardware feature extraction methods. Through automated feature extraction and cluster analysis, this embodiment can accurately identify the functional characteristics and classification relationships of hardware components. In actual tests, for a complex chip platform containing more than 50 heterogeneous components, the feature extraction and classification process can be completed within 5 seconds, and the classification accuracy rate reaches 92%, providing a reliable foundation for the subsequent abstract layer design.

[0089] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 3 , and can also include the following:

[0090] Step S301: Use a recurrent neural network to build a network structure of an abstract model, use the node features of the function category tree as an input sequence, use a cross entropy loss function to train the model to learn the functional feature distribution of hardware components, and optimize the network parameters through a back propagation algorithm to obtain an adaptive abstract model;

[0091] Step S302: Extract the functional feature vectors of the hardware components based on the trained abstract model, construct a coordinate system of the unified interface space, use the t-SNE algorithm to perform dimensionality reduction mapping on the functional feature vectors, calculate the interface similarity matrix based on the Euclidean distance between vectors, and map the components with similarity higher than a preset threshold to the same interface specification.

[0092] Optionally, this embodiment first constructs a LSTM-based recurrent neural network model. The network includes a bidirectional LSTM layer for simultaneously capturing the functional associations of the preceding and succeeding components. The input layer of the network receives the node feature sequence of the functional category tree in the aforementioned step, and the feature of each node contains the key attribute information of the hardware component. The hidden state dimension of the LSTM unit is set to 128, and long-term dependencies are learned through a gating mechanism. For example, for continuous components in a data processing pipeline, the model can learn the data flow characteristics and processing dependencies between them.

[0093] During the training process, this embodiment uses the cross entropy loss function to evaluate the difference between the model prediction and the true function category. The loss function takes into account the hierarchical relationship of the categories and gives a smaller penalty for incorrect predictions with closer hierarchical distances in the function category tree. The training adopts the mini-batch method, the batch size is set to 64, the Adam optimizer is used for parameter update, the initial value of the learning rate is set to 0.001, and the learning rate decay strategy is used. To prevent overfitting, a Dropout layer is added after the LSTM layer, and the dropout rate is set to 0.3.

[0094] After the model training is completed, this embodiment uses the trained abstract model to generate functional feature vectors for each hardware component. These feature vectors encode the functional characteristics and runtime behavior of the components. In order to build a unified interface space, this embodiment designs a multi-dimensional coordinate system, whose dimensions cover key characteristics such as data flow, processing timing, and resource requirements. For example, for the image processing component identified in the previous step, its coordinates in the interface space reflect performance characteristics such as data throughput and processing delay.

[0095] Considering that high-dimensional feature vectors are not convenient for visualization and analysis, this embodiment uses the t-SNE algorithm to reduce the feature vector to three-dimensional space. The t-SNE algorithm maintains the local structure of the sample in the original space and maps similar functional features to similar spatial positions through nonlinear transformation. During the dimensionality reduction process, the perplexity parameter is set to 30 and the maximum number of iterations is 1000 to ensure convergence to a stable low-dimensional representation.

[0096] Based on the reduced eigenvectors, this embodiment calculates the Euclidean distance between components and constructs an interface similarity matrix. The similarity calculation takes into account the weights of different dimensions, and these weights are dynamically adjusted according to the importance of the actual application scenario. For example, in real-time control applications, the weight of timing characteristics will be set higher. When the similarity between two components exceeds a preset threshold (the empirical value is set to 0.85), the system maps them to the same interface specification.

[0097] This technical solution effectively solves the problem of abstraction and unification of hardware component interfaces. In the test of a certain type of heterogeneous computing platform, this embodiment can summarize more than 30 different types of hardware interfaces into 5 standard interface specifications, significantly reducing the complexity of application development. The accuracy of interface mapping reaches 95%, and when the hardware configuration changes, the abstract model can adaptively adjust the mapping strategy to maintain the consistency of the interface. In particular, for newly added hardware components, the system can complete interface feature analysis and mapping at the millisecond level, realizing the dynamic expansion of interface abstraction.

[0098] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 4 , and can also include the following:

[0099] Step S401: construct a directed acyclic graph data structure to store the dependency relationship between hardware components, use the data flow and control flow between component nodes as the edges of the graph, sort the components based on the topological sorting algorithm to determine the execution order, use the adjacency matrix to represent the connection relationship between components, and use the graph embedding algorithm to generate a low-dimensional representation vector of the component nodes;

[0100] Step S402: Design a deep neural network structure including convolutional layers and fully connected layers, take hardware resource occupancy, request queue length and response delay as state vector inputs, define the action space including three dimensions: interface merging threshold adjustment, cache strategy selection and resource quota allocation, use the ε-greedy strategy for action exploration, and adopt a double Q network structure to reduce the impact of over-estimation.

[0101] Optionally, this embodiment first constructs a directed acyclic graph (DAG) to describe the dependencies of hardware components. The nodes in the graph represent the various hardware components identified in the previous steps, and the edges represent the data flow and control flow relationships between components. For example, in an image processing system, a typical data processing link is formed from the camera interface to the ISP processing unit and then to the display controller. This embodiment uses an adjacency matrix to store these connection relationships. The matrix elements not only record the existence of the connection, but also include weight information such as data bandwidth and transmission delay.

[0102] Based on the constructed DAG structure, this embodiment uses the improved Kahn algorithm to perform topological sorting to determine the execution order of the components. The component priority information obtained in the previous steps is taken into account during the sorting process to ensure that the components on the critical path can be scheduled first. For components that can be executed in parallel, the system will mark their parallelism to provide a basis for subsequent resource scheduling.

[0103] This embodiment uses the DeepWalk graph embedding algorithm to generate a low-dimensional representation of component nodes. The algorithm generates node sequences through random walks and uses the Skip-gram model to learn the distributed representation of nodes. During the walk, this embodiment adjusts the transition probability according to the weight of the edge, so that the node pairs with higher correlation are closer in the low-dimensional space. The dimension of the final embedded vector is set to 64, which effectively captures the topological relationship and functional correlation between components.

[0104] On this basis, this embodiment designs a deep Q network structure for learning the optimal scheduling strategy for hardware resources. The input layer of the network receives a multi-dimensional state vector, including runtime indicators such as resource occupancy, request queue length, and response latency of each hardware component. The convolution layer consists of three layers of 1D convolutions with kernel sizes of 3, 5, and 7, respectively, which are used to extract state features of different scales. The features are integrated through two fully connected layers (with dimensions of 256 and 128, respectively), and the Q value estimation is finally output.

[0105] The design of the action space fully considers the key adjustment dimensions of the hardware abstraction layer. The interface merge threshold determines the abstract granularity of the component interface. A higher threshold will produce a finer-grained interface division; the cache strategy includes multiple modes such as write-back and write-through, which affect the efficiency of data access; and the resource quota allocation controls the proportion of computing and bandwidth resources that each component can use.

[0106] This embodiment uses the ε-greedy strategy for action exploration. The initial ε value is set to 0.9 and linearly decays to 0.1 during training. To reduce the overestimation problem in Q learning, a dual Q network structure is used, including an online network and a target network. The target network parameters are updated every 1000 steps, and the fluctuation of value estimation is reduced by soft updating.

[0107] This technical solution solves the problem of dynamic scheduling and optimization of hardware resources. Tests on a certain type of heterogeneous computing platform show that this embodiment can accurately capture the complex dependencies between hardware components, and the optimized scheduling strategy reduces the average system response delay by 35% and improves resource utilization by 28%. Especially in scenarios with drastic load fluctuations, the system can quickly adjust the resource allocation strategy to maintain a stable quality of service. For example, in video processing applications, when the input frame rate suddenly increases, the scheduler can reallocate the computing resources of the processing unit at the millisecond level to avoid processing delays exceeding the threshold.

[0108] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 5 , and can also include the following:

[0109] Step S501: normalize the interface call delay to obtain a latency score, calculate the average utilization of the CPU and memory to obtain a resource score, calculate the success rate based on the interface compatibility test results to obtain a compatibility score, use an adaptive weight method to perform weighted summation on the three scores to obtain a comprehensive evaluation index, and use a sliding window method to smooth the fluctuation of the evaluation index;

[0110] Step S502: Use a double-ended queue data structure to implement a limited-capacity experience replay pool, perform importance sampling based on the TD error calculation sample priority, input the sampled transfer sequence into the target network to calculate the target Q value, calculate the temporal difference error in combination with the Bellman equation, update the policy network parameters through the back-propagation algorithm, and save the trained converged network parameters as an abstract rule base.

[0111] Optionally, this embodiment first normalizes the multi-dimensional performance indicators of the system. For the interface call delay, the Min-Max normalization method is used to map the original delay to the [0,1] interval and convert it into a delay score. Specifically, for each interface call, its response time is recorded, and the normalization interval is determined based on the statistical distribution of historical data. For example, in a real-time image processing system, a delay below 1ms is mapped to 1.0 points, a delay above 10ms is mapped to 0 points, and linear interpolation is used in the middle interval.

[0112] The calculation of the resource score comprehensively considers the usage of CPU and memory. This embodiment calculates the sliding average of CPU usage and memory occupancy by sampling the resource utilization of the monitoring system. The sampling period is set to 100ms and the window size is 10 sampling points. In order to balance the importance of different resource indicators, the weights are dynamically adjusted according to the characteristics of the application scenario. For example, in computing-intensive applications, the weight of CPU utilization will be set higher.

[0113] The compatibility score is obtained based on the success rate of interface calls. This embodiment records the call history of each abstract interface and counts the number of successful and failed calls. Taking into account the different severity of different types of errors, the error types are graded. For example, a minor data format mismatch is scored as 0.5 points, while a serious error that causes a system crash is scored as 0 points. At the same time, a time decay factor is used to give the most recent call results a higher weight.

[0114] These three scores are combined into a comprehensive evaluation index through an adaptive weighting method. The adaptive adjustment of the weight is based on the real-time status and performance goals of the system. For example, when the system load is high, the weight of the resource score will be increased accordingly. This embodiment uses the exponential moving average method to smooth the evaluation index, and the smoothing factor is set to 0.9, which effectively reduces the impact of short-term fluctuations.

[0115] In the design of the experience replay mechanism, this embodiment uses a double-ended queue to implement a replay pool with a capacity of 10,000. New experience samples are inserted from the tail of the queue, and the oldest sample is removed from the head when the capacity limit is exceeded. Each experience sample contains a state transition quadruple (current state, action performed, reward obtained, next state) and timestamp information.

[0116] The priority of the sample is calculated based on the absolute value of the TD error, and a small positive number ε=0.01 is added to prevent the priority from being zero. The sampling probability is proportional to the priority, and the Sum Tree data structure is used to achieve efficient priority sampling. In order to prevent high-priority samples from being oversampled, importance weights are used for correction, and the weights increase linearly with the training process β from 0.4 to 1.

[0117] In the network update phase, this embodiment samples a mini-batch of size 256 from the experience pool each time, and inputs the sampled sequence into the target network to calculate the target Q value. The target Q value is calculated using the dual Q learning method, which uses two network structures to alternately evaluate the action value, effectively suppressing over-optimistic estimation. The TD error is calculated using the Bellman equation, and the discount factor γ is set to 0.99, taking into account long-term benefits.

[0118] The Adam optimizer is used to update the network parameters, and the learning rate is set to 0.0001. To improve the stability of training, the gradient clipping technique is used to limit the gradient norm to no more than 10. During the training process, when the average return increase of 10 consecutive episodes is less than 1%, it is considered to be converged. Finally, the converged network parameters are saved as a binary rule base file.

[0119] This technical solution solves the problem of hardware abstraction layer performance evaluation and optimization. In actual deployment tests, when processing more than 1 million interface calls, the calculation overhead of the evaluation index of this embodiment does not exceed 1% of the total system overhead. The optimized strategy can reduce the average system response delay by 40%, increase resource utilization by 32%, and reduce the error rate caused by interface compatibility issues to less than 0.1%. Especially in dynamic load scenarios, the system can adjust policy parameters in real time to maintain stable service quality.

[0120] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 6 , and can also include the following:

[0121] Step S601: read the network parameters of the abstract rule base from the persistent storage, build the inference calculation graph and initialize the neural network model, establish a rule index table to save the mapping relationship between the abstract rules and the hardware components, create a request parser for each type of hardware operation to parse the operation parameters and constraints, and start the load check service of the rule base to verify the integrity of the rules;

[0122] Step S602: Implement a hierarchical routing table based on a hash table to store the correspondence between requests and abstract modules, use the longest prefix matching algorithm to find the target module of the operation request, calculate the routing weight according to the priority and resource requirements of the request, use a weighted polling method to perform load balancing among multiple candidate modules, and distribute the request to the selected abstract module for processing.

[0123] Optionally, this embodiment first loads the abstract rule base from persistent storage. The rule base is stored in binary format and contains weight parameters, bias values ​​and network structure descriptions of the neural network. The loading process uses memory mapping technology to reduce data copy overhead. For example, for a network structure containing three layers of convolution and two layers of full connection, the parameter file size is about 10MB, and the use of memory mapping technology can control the loading time to less than 100ms.

[0124] When constructing the inference calculation graph, this embodiment uses static graph optimization technology to perform operator fusion and memory planning in advance. The initialization process of the network model includes weight loading, computing resource allocation, and runtime cache preheating. To ensure that the model is loaded correctly, an integrity verification mechanism is implemented to verify the integrity of the parameter file through the SHA-256 hash value.

[0125] The rule index table is implemented using a red-black tree data structure, which supports fast search and dynamic update. Each record in the index table contains information such as the identifier of the abstract rule, the applicable hardware type, parameter constraints, etc. For example, for an image processing component, the index record will contain constraints such as supported image formats and resolution ranges. This embodiment implements a dedicated request parser for each type of hardware operation. The parser adopts a state machine design pattern and can efficiently process complex parameter structures.

[0126] The rule base loading check service runs as an independent thread and regularly verifies the validity and integrity of the rules. The check includes rule conflict detection, constraint verification, and performance indicator monitoring. The service uses a lightweight heartbeat mechanism to ensure the continuous availability of the rule base.

[0127] At the request routing level, this embodiment designs a multi-level hash table structure to implement a hierarchical routing table. The first-level hash table is classified based on the operation type, and the second-level hash table performs refined matching based on specific parameter features. The selection of the hash function takes into account the distribution of request features, and the MurmurHash3 algorithm is used to achieve efficient hash calculation.

[0128] The longest prefix match algorithm uses a compressed prefix tree (Trie) data structure when searching for routes, and supports wildcard matching. For example, for address space matching, it can support bitwise pattern matching to implement flexible routing strategies. The time complexity of the search process is O(k), where k is the prefix length.

[0129] The calculation of routing weights takes into account the priority of requests, resource requirements, and current system load. An adaptive factor is introduced into the weight calculation formula, which can be dynamically adjusted according to the system status. For example, when the load of an abstract module is high, its weight will be reduced accordingly to avoid request concentration.

[0130] In the load balancing link, this embodiment implements an improved weighted polling algorithm. The algorithm maintains a balance factor, records the deviation between the actual number of processed requests of each module and the theoretical allocation ratio, and dynamically adjusts the selection probability. To improve concurrency performance, the load balancer adopts a lock-free queue design and supports multi-threaded concurrent access.

[0131] This technical solution solves the problem of dynamic loading and request scheduling of the hardware abstraction layer. In the actual application of a certain type of embedded system, the loading time of the rule base does not exceed 200ms, and supports millisecond-level rule updates. The throughput of the routing system reaches 100,000 requests per second, and the average routing delay is controlled within 5 microseconds. The load balancing algorithm keeps the load difference of each module of the system within 10%, effectively improving the efficiency of resource utilization. Especially in burst traffic scenarios, the system can quickly adjust the routing strategy and maintain a stable service quality. For example, in a video processing application, even if the input frame rate suddenly doubles, the system can keep the frame processing delay within an acceptable range.

[0132] In one embodiment of the chip platform hardware abstraction layer construction method of the present application, see Figure 7 , and can also include the following:

[0133] Step S701: Initialize the scheduler based on the resource quota policy in the abstract rule base, use the priority queue to manage hardware operation requests, use the token bucket algorithm to control the resource access frequency, reserve resource quotas for high priority requests through the resource reservation mechanism, and calculate the resource utilization in real time to update the dynamic allocation threshold;

[0134] Step S702: Use a circular buffer to implement hardware operation result caching, establish an asynchronous notification mechanism to listen to operation completion events, use a memory pool to manage temporary storage space for result data, encapsulate operation results and status information through a unified interface protocol, and return the encapsulated data to the application layer program through a callback function.

[0135] This embodiment first implements the initialization of the resource scheduler based on the quota policy in the rule base. The scheduler adopts a hierarchical design, including three core modules: request management, resource control, and result processing. The initialization process includes creating a priority queue, configuring token bucket parameters, and initializing a resource reservation table. For example, in a real-time image processing system, the scheduler pre-allocates differentiated resource quotas for processing tasks of different priorities to ensure timely response to key tasks.

[0136] The priority queue is implemented using a binary heap, which supports insertion and deletion operations with O(logn) time complexity. Each request item in the queue contains attributes such as priority, resource requirements, and timeout. In order to support dynamic adjustment of priority, the floating and sinking operations of the heap are implemented. This embodiment improves the standard binary heap and adds a request starvation detection mechanism. When the waiting time of a low-priority request exceeds a threshold, its priority will be appropriately increased.

[0137] The token bucket algorithm is used to implement fine-grained resource access control. Each type of resource maintains an independent token bucket, and the token generation rate is dynamically adjusted according to the resource capacity. For example, for GPU computing resources, the token bucket capacity is set to 1.2 times the maximum number of parallel tasks, and the generation rate matches the processing power of the GPU. When tokens are insufficient, requests are temporarily cached in the priority queue waiting to be scheduled.

[0138] The resource reservation mechanism is implemented by maintaining a reservation table, which records the minimum guaranteed resource amount for each priority level. When system resources are tight, the scheduler will give priority to meeting the reservation requirements, and the remaining resources will be allocated according to priority. The reservation mechanism is particularly suitable for scenarios with real-time requirements, such as key frame processing in video encoding and decoding.

[0139] This embodiment uses a sliding window method to monitor resource utilization in real time, with a window size of 1 second and a sampling interval of 10ms. Based on the monitoring data, an exponentially weighted moving average algorithm is used to smooth utilization fluctuations, and the resource allocation threshold is dynamically adjusted accordingly. For example, when it is detected that the memory utilization rate continues to rise, the memory allocation limit of non-critical requests will be reduced accordingly.

[0140] In the result processing phase, this embodiment uses a ring buffer to store the operation results. The buffer adopts a multi-producer single-consumer model and uses atomic operations to ensure thread safety. The buffer size is dynamically adjusted according to the typical workload, initially set to 1024 result items, and supports automatic expansion.

[0141] The asynchronous notification mechanism is implemented based on an event-driven model. Each hardware operation registers a completion callback function when it is submitted, and the callback is triggered through the event loop after the operation is completed. In order to improve concurrency performance, an event merging mechanism is implemented, and callbacks can be processed in batches when multiple related operations are completed at the same time.

[0142] The memory pool adopts a block design, pre-allocating memory blocks of different sizes for result data storage. The memory block size ranges from 64 bytes to 16KB, and a buddy system algorithm is used to manage memory allocation. In order to reduce memory fragmentation, a memory block merging and splitting mechanism is implemented.

[0143] The unified interface protocol defines a standard result encapsulation format, including fields such as operation status code, timestamp, result data, and extended information. The protocol supports an extensible serialization scheme to facilitate subsequent functional expansion. The result data is directly passed to the application layer through a zero-copy mechanism to maximize transmission efficiency.

[0144] This technical solution solves the efficiency issues of hardware resource scheduling and result processing. In actual application tests, the scheduler can handle more than 10,000 concurrent requests at the same time, and the average scheduling delay is controlled within 50 microseconds. The resource utilization rate reaches more than 85%, while ensuring that the average response time of high-priority requests does not exceed 1ms. The memory overhead of the result processing mechanism is controlled within 10% of the peak load, supporting the processing of more than 100,000 operation completion events per second. For example, in a certain image processing pipeline, the system can stably support real-time processing of 4K resolution video, and the end-to-end delay is controlled within 16.7ms, meeting the display requirements of 60fps.

[0145] In order to deeply understand the hardware features, build an intelligent interface encapsulation strategy, and realize efficient resource scheduling through technologies such as reinforcement learning, the present application provides an embodiment of a chip platform hardware abstraction layer construction device for realizing all or part of the contents of the chip platform hardware abstraction layer construction method, see Figure 8 The chip platform hardware abstraction layer construction device specifically includes the following contents:

[0146] Function classification module 10, used to scan chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group hardware components to form a function category tree;

[0147] A rule abstraction module 20 is used to train an adaptive abstract model based on the function category tree, map hardware components with similar functions to a unified interface space, use a graph structure to represent the dependencies between hardware components, build a deep Q network to optimize the interface encapsulation strategy, use hardware resource status and operation requests as status inputs, define an action space including interface merging, parameter adjustment, and resource reallocation, design a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrate the three scores into a strategy evaluation index based on a weighted summation method, build an experience pool with a double-ended queue structure to store training samples, use a priority sampling method to select high-value experience data, calculate the target Q value based on a temporal difference algorithm, update the strategy network parameters, and generate a hardware abstraction rule base;

[0148] The resource allocation module 30 is used to load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor the resource usage status and update the allocation strategy, and return the hardware operation results to the application layer through a unified interface.

[0149] From the above description, it can be seen that the chip platform hardware abstraction layer construction device provided in the embodiment of the present application can build a hardware feature analysis model by scanning the chip platform hardware feature information, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group hardware components to form a functional category tree; train an adaptive abstract model based on the functional category tree, map hardware components with similar functions to a unified interface space, calculate the target Q value based on the timing difference algorithm to update the strategy network parameters to generate a hardware abstract rule library; load the hardware abstract rule library in the hardware abstraction layer engine, dynamically monitor the resource usage status and update the allocation strategy, and return the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics and building an intelligent interface encapsulation strategy.

[0150] From the hardware level, in order to deeply understand the hardware features, build an intelligent interface encapsulation strategy, and realize efficient resource scheduling through technologies such as reinforcement learning, the present application provides an embodiment of an electronic device for implementing all or part of the contents of the chip platform hardware abstraction layer construction method, and the electronic device specifically includes the following contents:

[0151] Processor, memory, communication interface and bus; wherein the processor, memory and communication interface communicate with each other through the bus; the communication interface is used to realize information transmission between the chip platform hardware abstraction layer construction device and the core business system, user terminal and related database and other related devices; the logic controller can be a desktop computer, a tablet computer and a mobile terminal, etc., but the present embodiment is not limited thereto. In the present embodiment, the logic controller can be implemented with reference to the embodiment of the chip platform hardware abstraction layer construction method and the embodiment of the chip platform hardware abstraction layer construction device in the embodiment, and the contents thereof are incorporated herein, and the repeated parts are not repeated.

[0152] It is understandable that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0153] In practical applications, part of the chip platform hardware abstraction layer construction method can be executed on the electronic device side as described above, or all operations can be completed in the client device. The specific selection can be based on the processing capability of the client device and the limitations of the user's usage scenario. This application does not limit this. If all operations are completed in the client device, the client device may also include a processor.

[0154] The client device may have a communication module (i.e., a communication unit) that can communicate with a remote server to achieve data transmission with the server. The server may include a server on the task scheduling center side, and other implementation scenarios may also include a server on an intermediate platform, such as a server on a third-party server platform that has a communication link with the task scheduling center server. The server may include a single computer device, or a server cluster consisting of multiple servers, or a server structure of a distributed device.

[0155] Fig. 9 FIG. 9 is a schematic block diagram of the system structure of the electronic device 9600 according to an embodiment of the present application. Fig. 9 As shown, the electronic device 9600 may include a central processor 9100 and a memory 9140; the memory 9140 is coupled to the central processor 9100. It is worth noting that Fig. 9 is exemplary; other types of structures may also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0156] In one embodiment, the chip platform hardware abstraction layer construction method function may be integrated into the central processing unit 9100. The central processing unit 9100 may be configured to perform the following control:

[0157] Step S101: Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree;

[0158] Step S102: training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, using a graph structure to represent the dependencies between hardware components, building a deep Q network to optimize the interface encapsulation strategy, taking hardware resource status and operation requests as status inputs, defining an action space including interface merging, parameter adjustment, and resource reallocation, designing a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrating the three scores into a strategy evaluation index based on a weighted summation method, building an experience pool with a double-ended queue structure to store training samples, using a priority sampling method to select experience data with higher value, and calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters and generate a hardware abstract rule base;

[0159] Step S103: Load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor resource usage status and update allocation strategies, and return the hardware operation results to the application layer through a unified interface.

[0160] From the above description, it can be seen that the electronic device provided in the embodiment of the present application constructs a hardware feature analysis model by scanning the hardware feature information of the chip platform, classifies and annotates the hardware feature information to extract the device interface, resource attributes and operation characteristics, establishes a feature vector library of hardware components, and uses a hierarchical clustering algorithm to group the hardware components to form a functional category tree; trains an adaptive abstract model based on the functional category tree, maps hardware components with similar functions to a unified interface space, calculates the target Q value based on the timing difference algorithm, updates the strategy network parameters to generate a hardware abstract rule library; loads the hardware abstract rule library in the hardware abstraction layer engine, dynamically monitors the resource usage status and updates the allocation strategy, and returns the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics and building an intelligent interface encapsulation strategy.

[0161] In another embodiment, the chip platform hardware abstraction layer construction device can be configured separately from the central processing unit 9100. For example, the chip platform hardware abstraction layer construction device can be configured as a chip connected to the central processing unit 9100, and the chip platform hardware abstraction layer construction method function is implemented through the control of the central processing unit.

[0162] like Fig. 9 As shown, the electronic device 9600 may also include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It is worth noting that the electronic device 9600 does not necessarily have to include Fig. 9In addition, the electronic device 9600 may also include Fig. 9 For components not shown, reference may be made to the prior art.

[0163] like Fig. 9 As shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor device and / or logic device. The central processing unit 9100 receives input and controls the operation of various components of the electronic device 9600.

[0164] The memory 9140 may be, for example, one or more of a cache, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory or other suitable devices. The above-mentioned information related to the failure may be stored, and a program for executing the relevant information may also be stored. The CPU 9100 may execute the program stored in the memory 9140 to implement information storage or processing, etc.

[0165] The input unit 9120 provides input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to provide power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display may be, for example, an LCD display, but is not limited thereto.

[0166] The memory 9140 may be a solid-state memory, such as a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It may also be a memory that saves information even when the power is off, can be selectively erased, and is provided with more data, examples of which are sometimes referred to as EPROMs, etc. The memory 9140 may also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 may include an application / function storage unit 9142, which is used to store application programs and function programs or processes for executing the operation of the electronic device 9600 through the central processor 9100.

[0167] The memory 9140 may also include a data storage unit 9143 for storing data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 may include various drivers for communication functions of the electronic device and / or for executing other functions of the electronic device (such as messaging applications, address book applications, etc.).

[0168] The communication module 9110 is a transmitter / receiver that sends and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processor 9100 to provide input signals and receive output signals, which may be the same as the case of a conventional mobile communication terminal.

[0169] Based on different communication technologies, multiple communication modules 9110 may be provided in the same electronic device, such as a cellular network module, a Bluetooth module and / or a wireless LAN module. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby realizing a common telecommunication function. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. In addition, the audio processor 9130 is also coupled to the central processor 9100, so that recording can be performed on the local machine through the microphone 9132, and the sound stored on the local machine can be played through the speaker 9131.

[0170] The embodiments of the present application also provide a computer-readable storage medium capable of implementing all the steps in the method for constructing a chip platform hardware abstraction layer in the above embodiment, where the execution subject is a server or a client. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, all the steps in the method for constructing a chip platform hardware abstraction layer in the above embodiment are implemented. For example, when the processor executes the computer program, the following steps are implemented:

[0171] Step S101: Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree;

[0172] Step S102: training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, using a graph structure to represent the dependencies between hardware components, building a deep Q network to optimize the interface encapsulation strategy, taking hardware resource status and operation requests as status inputs, defining an action space including interface merging, parameter adjustment, and resource reallocation, designing a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrating the three scores into a strategy evaluation index based on a weighted summation method, building an experience pool with a double-ended queue structure to store training samples, using a priority sampling method to select experience data with higher value, and calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters and generate a hardware abstract rule base;

[0173] Step S103: Load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor resource usage status and update allocation strategies, and return the hardware operation results to the application layer through a unified interface.

[0174] From the above description, it can be seen that the computer-readable storage medium provided in the embodiment of the present application constructs a hardware feature analysis model by scanning the hardware feature information of the chip platform, classifies and annotates the hardware feature information to extract device interfaces, resource attributes and operation characteristics, establishes a feature vector library of hardware components, and uses a hierarchical clustering algorithm to group the hardware components to form a functional category tree; trains an adaptive abstract model based on the functional category tree, maps hardware components with similar functions to a unified interface space, calculates the target Q value based on the timing difference algorithm, updates the strategy network parameters to generate a hardware abstract rule library; loads the hardware abstract rule library in the hardware abstraction layer engine, dynamically monitors the resource usage status and updates the allocation strategy, and returns the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics and building an intelligent interface encapsulation strategy.

[0175] The embodiments of the present application also provide a computer program product capable of implementing all the steps in the chip platform hardware abstraction layer construction method in the above embodiments, where the execution subject is a server or a client. When the computer program / instruction is executed by a processor, the steps of the chip platform hardware abstraction layer construction method are implemented. For example, the computer program / instruction implements the following steps:

[0176] Step S101: Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree;

[0177] Step S102: training an adaptive abstract model based on the function category tree, mapping hardware components with similar functions to a unified interface space, using a graph structure to represent the dependencies between hardware components, building a deep Q network to optimize the interface encapsulation strategy, taking hardware resource status and operation requests as status inputs, defining an action space including interface merging, parameter adjustment, and resource reallocation, designing a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrating the three scores into a strategy evaluation index based on a weighted summation method, building an experience pool with a double-ended queue structure to store training samples, using a priority sampling method to select experience data with higher value, and calculating the target Q value based on a temporal difference algorithm to update the strategy network parameters and generate a hardware abstract rule base;

[0178] Step S103: Load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor resource usage status and update allocation strategies, and return the hardware operation results to the application layer through a unified interface.

[0179] From the above description, it can be seen that the computer program product provided in the embodiment of the present application constructs a hardware feature analysis model by scanning the hardware feature information of the chip platform, classifies and annotates the hardware feature information to extract device interfaces, resource attributes and operation characteristics, establishes a feature vector library of hardware components, and uses a hierarchical clustering algorithm to group the hardware components to form a functional category tree; trains an adaptive abstract model based on the functional category tree, maps hardware components with similar functions to a unified interface space, calculates the target Q value based on the timing difference algorithm, updates the strategy network parameters to generate a hardware abstract rule library; loads the hardware abstract rule library in the hardware abstraction layer engine, dynamically monitors the resource usage status and updates the allocation strategy, and returns the hardware operation results to the application layer through a unified interface, thereby enabling an in-depth understanding of the hardware characteristics and building an intelligent interface encapsulation strategy.

[0180] It should be understood by those skilled in the art that embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0181] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0182] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0183] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0184] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for constructing a chip platform hardware abstraction layer, characterized in that: The method comprises: Scan the chip platform hardware feature information, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group the hardware components to form a functional category tree; Based on the function category tree, the adaptive abstract model is trained, hardware components with similar functions are mapped to a unified interface space, a graph structure is used to represent the dependencies between hardware components, a deep Q network is constructed to optimize the interface encapsulation strategy, hardware resource status and operation requests are used as status inputs, an action space including interface merging, parameter adjustment and resource reallocation is defined, a composite reward function is designed to comprehensively calculate interface call delay, resource utilization and compatibility scores, the three scores are integrated into a strategy evaluation index based on a weighted summation method, an experience pool with a double-ended queue structure is constructed to store training samples, a priority sampling method is used to select experience data with higher value, and a target Q value is calculated based on a temporal difference algorithm to update the strategy network parameters to generate a hardware abstract rule base; The hardware abstract rule library is loaded in the hardware abstraction layer engine, the input hardware operation request is parsed, the operation request is mapped to the corresponding abstract module through the hierarchical routing algorithm, the hardware resources are scheduled and allocated according to the abstract rule library, a cache queue for hardware operations is established, the resource usage status is dynamically monitored and the allocation strategy is updated, and the hardware operation results are returned to the application layer through a unified interface.

2. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The scanning chip platform hardware feature information, building a hardware feature analysis model, classifying and labeling the hardware feature information to extract device interfaces, resource attributes and operation features, building a feature vector library of hardware components, and using a hierarchical clustering algorithm to group the hardware components to form a functional category tree, including: Scan the hardware device information of the chip platform through the system bus interface, read the device descriptor to obtain the model and configuration parameters of the hardware components, establish a feature extraction model based on a convolutional neural network, standardize the interface specifications, working modes and performance parameters of the hardware components, and generate hardware feature vectors; The cosine similarity between hardware feature vectors is calculated to construct a similarity matrix. A bottom-up hierarchical clustering algorithm is used to recursively merge hardware components. The clustering level is determined based on the inter-class distance threshold. The clustering results are organized into a tree structure to represent the functional classification relationship of hardware components.

3. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The training of the adaptive abstract model based on the function category tree to map hardware components with similar functions to a unified interface space includes: The network structure of the abstract model is constructed using a recurrent neural network. The node features of the functional category tree are used as the input sequence. The cross entropy loss function is used to train the model to learn the functional feature distribution of hardware components. The network parameters are optimized through the back propagation algorithm to obtain an adaptive abstract model. Based on the trained abstract model, the functional feature vectors of the hardware components are extracted, and the coordinate system of the unified interface space is constructed. The t-SNE algorithm is used to reduce the dimension of the functional feature vectors. The interface similarity matrix is ​​calculated according to the Euclidean distance between the vectors, and the components with similarity higher than the preset threshold are mapped to the same interface specification.

4. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The method uses a graph structure to represent the dependencies between hardware components, builds a deep Q network to optimize the interface encapsulation strategy, takes the hardware resource status and operation request as the status input, and defines an action space including interface merging, parameter adjustment, and resource reallocation, including: Construct a directed acyclic graph data structure to store the dependencies between hardware components. Use the data flow and control flow between component nodes as the edges of the graph. Sort the components based on the topological sorting algorithm to determine the execution order. Use the adjacency matrix to represent the connection relationship between components. Use the graph embedding algorithm to generate a low-dimensional representation vector of the component nodes. A deep neural network structure consisting of convolutional layers and fully connected layers is designed. Hardware resource occupancy, request queue length and response delay are taken as state vector inputs. The action space is defined to include three dimensions: interface merging threshold adjustment, cache strategy selection and resource quota allocation. The ε-greedy strategy is used for action exploration, and a double Q network structure is adopted to reduce the impact of over-estimation.

5. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The designed composite reward function comprehensively calculates the interface call delay, resource utilization and compatibility score, integrates the three scores into a strategy evaluation index based on a weighted summation method, constructs an experience pool with a double-ended queue structure to store training samples, uses a priority sampling method to select high-value experience data, calculates the target Q value based on a temporal difference algorithm, updates the strategy network parameters, and generates a hardware abstract rule base, including: The interface call delay is normalized to obtain the latency score, the average CPU and memory utilization is calculated to obtain the resource score, the success rate is calculated based on the interface compatibility test results to obtain the compatibility score, the adaptive weight method is used to weight the sum of the three scores to obtain the comprehensive evaluation index, and the sliding window method is used to smooth the fluctuation of the evaluation index; A double-ended queue data structure is used to implement a limited-capacity experience replay pool. Importance sampling is performed based on the sample priority calculated based on the TD error. The sampled transfer sequence is input into the target network to calculate the target Q value. The Bellman equation is used to calculate the temporal difference error. The policy network parameters are updated through the back-propagation algorithm, and the converged network parameters are saved as an abstract rule base.

6. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The hardware abstraction rule library is loaded in the hardware abstraction layer engine, the input hardware operation request is parsed, and the operation request is mapped to the corresponding abstract module through the hierarchical routing algorithm, including: Read the network parameters of the abstract rule library from the persistent storage, build the inference calculation graph and initialize the neural network model, establish a rule index table to save the mapping relationship between abstract rules and hardware components, create a request parser for each type of hardware operation to parse the operation parameters and constraints, and start the load check service of the rule library to verify the integrity of the rules; A hierarchical routing table is implemented based on a hash table to store the correspondence between requests and abstract modules. The longest prefix matching algorithm is used to find the target module of the operation request. The routing weight is calculated according to the priority and resource requirements of the request. A weighted round-robin method is used to load balance among multiple candidate modules and distribute the requests to the selected abstract module for processing.

7. The chip platform hardware abstraction layer construction method according to claim 1, characterized in that: The scheduling and allocation of hardware resources according to the abstract rule base, establishing a cache queue for hardware operations, dynamically monitoring resource usage status and updating allocation strategies, and returning hardware operation results to the application layer through a unified interface include: Initialize the scheduler based on the resource quota policy in the abstract rule base, use the priority queue to manage hardware operation requests, use the token bucket algorithm to control the resource access frequency, reserve resource quotas for high-priority requests through the resource reservation mechanism, and calculate resource utilization in real time to update the dynamic allocation threshold; A circular buffer is used to cache the results of hardware operations, an asynchronous notification mechanism is established to monitor operation completion events, a memory pool is used to manage the temporary storage space of result data, the operation results and status information are encapsulated through a unified interface protocol, and the encapsulated data is returned to the application layer program through a callback function.

8. A chip platform hardware abstraction layer construction device, characterized in that: The device comprises: Function classification module, used to scan the hardware feature information of the chip platform, build a hardware feature analysis model, classify and annotate the hardware feature information to extract device interfaces, resource attributes and operation features, establish a feature vector library of hardware components, and use a hierarchical clustering algorithm to group hardware components to form a function category tree; A rule abstraction module is used to train an adaptive abstract model based on the function category tree, map hardware components with similar functions to a unified interface space, use a graph structure to represent the dependencies between hardware components, build a deep Q network to optimize the interface encapsulation strategy, use hardware resource status and operation requests as status inputs, define an action space including interface merging, parameter adjustment, and resource reallocation, design a composite reward function to comprehensively calculate interface call delay, resource utilization, and compatibility scores, integrate the three scores into a strategy evaluation index based on a weighted summation method, build an experience pool with a double-ended queue structure to store training samples, use a priority sampling method to select high-value experience data, calculate the target Q value based on a temporal difference algorithm, update the strategy network parameters, and generate a hardware abstract rule base; The resource allocation module is used to load the hardware abstract rule library in the hardware abstraction layer engine, parse the input hardware operation request, map the operation request to the corresponding abstract module through the hierarchical routing algorithm, schedule and allocate hardware resources according to the abstract rule library, establish a cache queue for hardware operations, dynamically monitor the resource usage status and update the allocation strategy, and return the hardware operation results to the application layer through a unified interface.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the chip platform hardware abstraction layer construction method described in any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip platform hardware abstraction layer construction method described in any one of claims 1 to 7 are implemented.

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