A hardware Trojan detection and positioning method based on a graph convolutional neural network

Abstract

A kind of hardware Trojan detection and positioning method based on graph convolutional neural network, based on graph learning method, circuit structure is converted into graph structure, and the basic structure features of node are extracted in this process;Based on the construction of two new features Cov and Lfp with depth search strategy and topological logic analysis method to improve the feature information of circuit node;Based on the neighbor feature of GCN aggregation node and update its own node feature information to improve the local perception and generalization ability of node;Using the global feature fusion method based on attention mechanism to extract and update the global feature of graph, and fuse with the node feature vector after aggregating neighbor feature;Based on the idea of stochastic gradient descent and combined with small batch over-sampling and under-sampling method to balance training data;Using multilayer perception machine model to train balanced data based on leave-one-out cross-validation method, and predicting unknown circuit, identifying potential HTs node in circuit.The present application realizes the detection and positioning of HTs.

Description

TECHNICAL FIELD

[0001] The present application belongs to a kind of detection and positioning method of multiple types of hardware Trojan (HT) in integrated circuit (IC), and more particularly to a kind of hardware Trojan detection and positioning method based on graph convolutional neural network. BACKGROUND

[0002] With the increasing demand for high-performance, low-cost and multi-functional ICs, enterprises and designers increasingly rely on introducing third-party intellectual property (3PIP) cores or outsourcing standard and universal logic design to professional design companies in order to lead in the competition. This strategy enables them to focus on the development of new functions, but at the same time, it also increases the risk of malicious hardware attacks on chips. For example, untrusted 3PIP suppliers or third-party design contractors may implant malicious Trojans in the design, and even if the supplier or contractor is trustworthy, a contaminated design tool may inadvertently add HTs or other threat attacks. HTs are lightweight components in large-scale complex ICs, containing a Trojan trigger and a payload. Most HTs are only triggered in special cases, making it difficult for traditional verification and testing methods to detect their existence. Attackers can construct and implant HTs that are difficult to detect, such as designing their triggers to be activated only when checked, making them appear to be non-malicious ICs in the eyes of the outside world. However, when the HT trigger is eventually activated, it may cause the leakage or tampering of confidential information stored in the IC, or even cause the IC chip to fail or be damaged. Therefore, it is necessary to build an efficient method to achieve rapid detection of HTs.

[0003] To achieve the above goal, researchers have proposed various methods, such as logic testing-based methods, side-channel analysis-based methods, and code review methods to detect HTs in ICs. The logic testing-based method generates a large number of test patterns to activate potential HTs, causing them to produce observable errors or abnormal behavior for detection purposes; the side-channel analysis-based method often uses power, delay, and temperature analysis-based signal features to detect changes in ICs to find HTs; and the code review method carefully examines the design code to find parts that do not match normal functions to identify HTs. Although these methods can be used to detect HTs in ICs, they often require large test vectors, complex and precise hardware equipment, and a large amount of time and human resources, and it is also difficult to achieve accurate positioning of HTs based on detection. SUMMARY

[0004] To overcome the shortcomings of low accuracy and high computational complexity in existing technologies for detecting HTs, this invention provides a hardware Trojan detection and localization method based on graph convolutional neural networks. First, two new features of gate nodes are constructed. Then, local feature aggregation and global feature fusion are performed on circuit nodes, and the problem of scarce HT nodes in the circuit is solved, thereby realizing the detection and localization of HTs. This method shows superior performance on multiple datasets and has good generalization and robustness.

[0005] The technical solution adopted by this invention to solve its technical problem is:

[0006] A method for detecting and locating hardware Trojans based on graph convolutional neural networks, the method comprising the following steps:

[0007] Step 1: Based on graph learning methods, the circuit structure is transformed into a graph structure, and in the process, the basic structural features of the nodes are extracted, namely, node type, in-degree, out-degree, shortest distance from the node to any original input, and shortest distance from the node to any original output.

[0008] Step 2: Construct two new features, Cov and Lfp, based on a deep search strategy and topology logic analysis method to improve the feature information of the circuit nodes;

[0009] Step 3: Aggregate the neighbor features of nodes based on GCN and update the node's own feature information to improve the node's local perception and generalization ability;

[0010] Step 4: Use an attention-based global feature fusion method to extract and update the global features of the graph, and fuse them with the node feature vector obtained in Step 3 after aggregating neighbor features;

[0011] Step 5: Based on the idea of ​​stochastic gradient descent and combined with mini-batch oversampling and undersampling methods to balance the training data, the impact of the scarcity of HTs nodes in the circuit on the model is resolved.

[0012] Step 6. Use a multilayer perceptron model to train the balanced data based on leave-one-out cross-validation, and make predictions on unknown circuits to identify potential HTs nodes in the circuit.

[0013] Furthermore, the process of step 2 is as follows:

[0014] 2.1. Calculate the relationship between nodes using formula (1) The number of nodes connected by paths is quantified. connectivity A normalization strategy was employed to eliminate the potential adverse effects of scale differences on the results. i =1, 2, …,N, where N is the number of nodes in the graph. the number of nodes that can be reached from node in the directed graph, the number of nodes that can be reached from node in the directed graph, the sum of the above two is the number of nodes that have connectivity to the target node in the graph.

[0015] (1).

[0016] 2.2. Calculate the influence ability of node on the logical value distribution of all target nodes by formula (2), and then approximate the logical value probability distribution of node by formula (3), and then calculate the logical flip probability of node by formula (4), wherein the target node is the AND gate and OR NOT gate with output logic 1, and the NAND gate and OR gate with output logic 0; in formula (2), represents the influence degree of the target node on the probability of node outputting 1 or 0, n is the number of input ends of node , and quantifies the influence degree of multiple input paths with the most target nodes on node Lfp; in formula (3), is the probability of node outputting logic 1 (or 0), represents the type of target node, represents the in-degree of node , and in formula (4), , that is, the logical flip probability of node .

[0017] (2).

[0018] (3).

[0019] (4).

[0020] 2.3. Fuse the above two new features with the basic structural features of step 1 to obtain the initial feature vector of the node.

[0021] Further, the process of step 3 is as follows:

[0022] 3.1. Aggregate the feature vectors of the nodes adjacent to node v by formula (5), and generate a message vector ​Then, the nodes are combined using the update function of formula (6). v eigenvectors and message vector Get the updated node v eigenvectors ,in, Represents nodes v An adjacent pair of nodes, Indicates the first l Layer message functions, Indicates the first l The layer update function, Represents a node v The initial feature vector, Nodes representing aggregation v Neighbor information;

[0023] (5);

[0024] (6);

[0025] 3.2. Aggregate and update data from nodes using the message function shown in equation (5) and the update function shown in equation (6). v The features of neighboring nodes within two hops enrich the node feature information while avoiding overfitting and high computational cost. The above aggregation process yields the feature vector matrix. eb .

[0026] Furthermore, the process of step 4 is as follows:

[0027] 4.1. Feature vector matrix after aggregating neighbor node feature information using average pooling GCN eb To obtain the initial global feature vector, denoted as... Then, according to formula (7), the feature vector of each node is compared with the current global feature vector. Perform an inner product operation and normalize all inner product results to obtain the weight vector. , This reflects each node's response to the initial global feature vector. The degree of contribution, among which, Representative node The value obtained by the inner product, Representative node eigenvectors; i =1, 2, …, N, where N is the number of nodes in the graph;

[0028] (7);

[0029] 4.2. The feature vector of each node is obtained by formula (8). corresponding weight value carrying out weighted summation to update the global feature vector, denoted as ;

[0030] (8)

[0031] 4.3. Repeat the above two-step operation once to extract the global feature vector that effectively fuses the feature vector information of each node, denoted as , and finally obtain the final node feature vector matrix by weighted fusion of and the feature vector of each node neb , where k 1 is the proportion of global feature fusion;

[0032] neb = (1- k 1 ) × eb + k 1 × (9).

[0033] The process of step 5 is as follows:

[0034] 5.1. Randomly divide the normal node set into m equal parts, m where is the number of small batches;

[0035] 5.2. For each of the , carry out random sampling from the HTs node set to obtain and place it in , where the number of nodes in tends to j , so as to achieve data balancing processing, where m = 1, 2, …, .

[0036] In the present application, according to the abnormal performance of HTs nodes in the graph, two new features of gate nodes are extracted based on a deep search strategy and a topological logic analysis method to enrich the feature information of circuit nodes; and according to the influence of neighbor nodes and global information of the graph on the current node features, a local feature aggregation method based on GCN and a global feature fusion method based on an attention mechanism are constructed to improve the expressiveness of circuit node features; in order to solve the influence of unbalanced data on the HTs performance of the model, a data imbalance processing method is constructed based on the idea of stochastic gradient descent and combined with the small batch over-sampling and under-sampling method to solve the problem of the scarcity of HTs nodes in the circuit. Based on the above methods, the rapid and effective detection and positioning of HTs in unknown circuits can be effectively realized based on limited known circuits and in a relatively short training time.

[0037] In the present application, first, the GL method is used to convert the circuit structure into a graph structure; then, the neighbor information of the nodes is aggregated by GCN, and the global features of the circuit are fused through the attention mechanism; then, the set of node feature vectors after feature fusion is subjected to data balancing processing to solve the adverse effects of the small number of HTs nodes on the performance of the model; finally, the detection and positioning of HTs in unknown circuits are realized based on the balanced training data.

[0038] The beneficial effects of the present application mainly include that the two new features of gate nodes extracted based on the deep search strategy and the topological logic analysis method can greatly enrich the feature information of circuit nodes, which is beneficial to the model to distinguish HTs nodes from normal nodes; the local feature aggregation method based on GCN and the global feature fusion method based on the attention mechanism can improve the expressiveness of circuit node features, which is helpful to further increase the distinction of HTs nodes; and the data balancing processing method can effectively solve the problem of the scarcity of HTs nodes. These not only help to accurately detect and locate the potential HTs in the circuit, but also ensure good model generalization and robustness, which helps to greatly improve the reliability of hardware security. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a flowchart of a hardware Trojan detection and positioning method based on a graph convolutional neural network.

[0040] Figure 2 is the experimental result of the method of the present application on a large-scale data set. DETAILED DESCRIPTION

[0041] The present application will be further described below with reference to the accompanying drawings.

[0042] REFERENCE Figure 1 and Figure 2A hardware Trojan detection and positioning method based on a graph convolutional neural network, the method comprising the following steps:

[0043] Step 1, a graph learning (GL) method is used to convert the circuit structure into a graph structure, and in the process, basic structural features of the nodes are extracted, such as node type, in-degree, out-degree, shortest distance of the node to any original input, and shortest distance of the node to any original output, etc.

[0044] Step 2, two new features Cov and Lfp are constructed based on a deep search strategy and a topological logic analysis method to improve the feature information of the circuit nodes, and the process is as follows:

[0045] 2.1. Calculate Cov and Lfp of the node by formula (1). The number of nodes connected by paths is used to quantify the connectivity of i . A normalization strategy is used to eliminate the adverse effects of scale differences on the results, where =1, 2, …,N, N is the number of nodes in the graph, represents the number of nodes in the directed graph that can reach node , represents the number of nodes that can be reached from node , and the sum of the two is the number of all nodes in the graph that have connectivity with the target node

[0046] = , (1).

[0047] 2.2. Calculate the influence ability of all target nodes on the logic value distribution of node by formula (2), and then approximate the logic value probability distribution of node by formula (3), and then calculate the logic flip probability of node by formula (4), where the target node is an AND gate and an OR NOT gate with output logic 1, and a NAND gate and an OR gate with output logic 0. In formula (2), represents the influence degree of the target node on the output 1 (or 0) probability of node , n is the number of input ends of node , quantifies the influence degree of multiple input paths with the most target nodes on node Lfp. In formula (3), is the probability of node outputting logic 1 (or 0), represents the target node type, in-degree of node in formula (4), i.e. the logical flip probability of node ;

[0048] (2);

[0049] (3);

[0050] (4);

[0051] 2.3. Fuse the above two new features with the basic structure features of step 1 to obtain the initial feature vector of the node;

[0052] Step 3, based on GCN, aggregate the neighbor features of the node and update the node feature information itself to improve the local perception and generalization ability of the node, the process is as follows:

[0053] 3.1. Aggregate the feature vectors of the nodes adjacent to node v by formula (5), and generate message vector , and then combine the feature vector v of node and the message vector to obtain the updated feature vector v of node , wherein, denotes a set of nodes adjacent to node v , denotes the message function of the layer, l denotes the update function of the layer, l denotes the initial feature vector of node , v denotes the aggregated neighbor information of node ; v

[0054] (5);

[0055] (6);

[0056] 3.2. Aggregate and update the neighbor node features within two hops from node v using the message function shown in formula (5) and the update function shown in formula (6), enrich the node feature information while avoiding overfitting and high computational cost, and complete the above aggregation process to obtain the feature vector matrix eb ;

[0057] ​​Step 4, use the global feature fusion method based on attention mechanism to extract and update the global feature of the graph, and fuse it with the node feature vector after the aggregated neighbor feature obtained in step 3, the process is as follows:

[0058] 4.1. Feature vector matrix after GCN aggregates neighbor node feature information eb To obtain the initial global feature vector, denoted as , then according to formula (7), each node feature vector is respectively multiplied with the current global feature vector Carry out inner product operation, and normalize all inner product results to get weight vector , Reflects the contribution of each node to the initial global feature vector , where Represents the value obtained by the inner product of node , Represents the feature vector of node ; i =1, 2, …, N, N is the number of nodes in the graph;

[0059] (7);

[0060] 4.2. Update the global feature vector by weighted sum of each node feature vector And the corresponding weight value According to formula (8), denoted as ;

[0061] (8);

[0062] 4.3. Repeat the above two steps once to extract the global feature vector that effectively fuses each node feature vector information, denoted as , finally weighted fusion And the feature vector of each node To obtain the final node feature vector matrix neb , where k 1 The proportion of global feature fusion, usually takes the value of 0.5.

[0063] neb =(1- k 1 )× eb + k 1 × (9);

[0064] Step 5. Based on the idea of stochastic gradient descent and combined with the small batch oversampling and undersampling method to balance the training data, the influence of the HTs node scarcity in the circuit on the model is solved, and the process is as follows:

[0065] 5.1. The normal node set is randomly divided into m equal parts, m and the number of small batches is

[0066] 5.2. For each part , random sampling is carried out from the HTs node set to obtain and place it in , where the number of nodes in tends to , so as to realize data balancing processing, where j = 1, 2, …, m ;

[0067] Step 6. The balanced data is trained based on the leave-one-out cross-validation method using the multilayer perception model, and the unknown circuit is predicted to identify the potential HTs node in the circuit.

[0068] The scheme of the embodiment extracts two new features of gate nodes based on deep search strategy and topological logic analysis method according to the abnormal performance of HTs nodes in the graph to enrich the feature information of circuit nodes; and according to the influence of neighbor nodes and global information of the graph on the current node features, a local feature aggregation method based on GCN and a global feature fusion method based on attention mechanism are constructed to improve the expressiveness of circuit node features; in order to solve the influence of unbalanced data on the performance of model identifying HTs, a data imbalance processing method is constructed based on the idea of stochastic gradient descent and combined with the small batch oversampling and undersampling method to solve the problem of HTs node scarcity in the circuit. Based on the above methods, the HTs in the unknown circuit can be effectively detected and positioned in a short training time based on limited known circuits.

[0069] In the embodiment, Figure 2 is the experimental result of the proposed method on a large-scale data set, from which it can be seen that the performance of the proposed method on 4 EthernetMAC10GE circuits is similar, and on 2 B19 circuits also has similar performance. The method not only performs well in Acc and Recall indicators, with average values of about 100.0% and 95.15%, respectively, but also has very good performance in Pre and F1-score indicators, with average values of about 91.27% and 93.13%, respectively. Compared with the latest similar method, the performance of the method is better, which verifies its advancement and effectiveness.

[0070] The embodiments of the present specification are merely illustrative of the implementation forms of the inventive concept, and are only used for the purpose of description. The protection scope of the present application should not be regarded as being limited to the specific forms described in the present embodiments, and the protection scope of the present application also encompasses equivalent technical means that can be thought of by those skilled in the art according to the inventive concept.

Claims

1. A method for detecting and locating hardware Trojans based on graph convolutional neural networks, characterized in that, The method includes the following steps: Step 1: Based on graph learning methods, the circuit structure is transformed into a graph structure, and in the process, the basic structural features of the nodes are extracted, namely, node type, in-degree, out-degree, shortest distance from the node to any original input, and shortest distance from the node to any original output. Step 2: Construct two new features, Cov and Lfp, based on a deep search strategy and topology logic analysis method to improve the feature information of the circuit nodes; Step 3: Aggregate the neighbor features of nodes based on GCN and update the node's own feature information to improve the node's local perception and generalization ability; Step 4: Use an attention-based global feature fusion method to extract and update the global features of the graph, and fuse them with the node feature vector obtained in Step 3 after aggregating neighbor features; Step 5: Based on the idea of ​​stochastic gradient descent and combined with mini-batch oversampling and undersampling methods to balance the training data, the impact of the scarcity of HTs nodes in the circuit on the model is resolved. Step 6. Use a multilayer perceptron model to train the balanced data based on leave-one-out cross-validation, and make predictions on unknown circuits to identify potential HTs nodes in the circuit.

2. The hardware Trojan detection and localization method based on graph convolutional neural networks as described in claim 1, characterized in that, The process of step 2 is as follows: 2.

1. Calculate the relationship between nodes using formula (1) The number of nodes connected by paths is quantified. connectivity A normalization strategy was employed to eliminate the potential adverse effects of scale differences on the results. i =1, 2, …, N, where N is the number of nodes in the graph. Represents all reachable nodes in a directed graph. The number of nodes, Represents a node in a directed graph The sum of the number of nodes reachable from the starting point and the number of nodes reached from the starting point is the distance to the target node in the graph. The number of all nodes that are connected; = , (1)； 2.

2. Calculate the nodes using formula (2) The influence of all target nodes on their logical value distribution is then approximated using formula (3). The logical value probability distribution is then calculated using formula (4) to determine the node. The logic flip probability, where the target node is the AND gate and NOR gate under output logic 1, and the NOR gate and OR gate under output logic 0; in formula (2), This indicates the target node-to-node pair in the graph. The degree of influence of the probability of outputting 1 or 0. n For nodes The number of input terminals, The influence of multiple input paths with the most target nodes on node Lfp was quantified; in formula (3), For nodes The probability of outputting a logic 1 (or 0). Indicates the type of the target node. Represents a node The in-degree, in formula (4), That is, to represent a node The logical flip probability; (2)； (3)； (4)； 2.

3. Combine the two new features mentioned above with the basic structural features from step 1 to obtain the initial feature vector of the node.

3. A hardware Trojan detection and localization method based on graph convolutional neural networks as described in claim 1 or 2, characterized in that, The process of step 3 is as follows: 3.

1. Aggregate nodes using formula (5) v The feature vectors of adjacent nodes are used to generate message vectors. Then, the nodes are combined using the update function of formula (6). v eigenvectors and message vector Get the updated node v eigenvectors ,in, Represents nodes v An adjacent pair of nodes, Represents a node eigenvectors, , Indicates the first l Layer message functions, Indicates the first l The layer's update function; (5)； (6)； 3.

2. Aggregate and update data from nodes using the message function shown in equation (5) and the update function shown in equation (6). v The features of neighboring nodes within two hops enrich the node feature information while avoiding overfitting and high computational cost. The above aggregation process yields the feature vector matrix. eb .

4. A hardware Trojan detection and localization method based on graph convolutional neural networks as described in claim 1 or 2, characterized in that, The process of step 4 is as follows: 4.

1. Feature vector matrix after aggregating neighbor node feature information using average pooling GCN eb To obtain the initial global feature vector, denoted as... Then, according to formula (7), the feature vector of each node is compared with the current global feature vector. Perform inner product operations and normalize all inner product results to obtain the weight vector. , This reflects each node's response to the initial global feature vector. The degree of contribution, among which, Representative node The value obtained by the inner product, Representative node eigenvectors; i =1, 2,…, N, where N is the number of nodes in the graph; (7)； 4.

2. The feature vector of each node is obtained by formula (8). With the corresponding weight value We perform a weighted summation to update the global feature vector, denoted as ; (8)； 4.

3. Repeat the above two steps once to extract a global feature vector that effectively fuses the feature vector information of each node, denoted as . Finally, the weighted fusion is performed using formula (9). With the feature vector of each node To obtain the final node feature vector matrix neb ,in, k 1 The proportion of global feature fusion; neb =(1- k 1 )× eb + k 1 × (9)。 5. A hardware Trojan detection and localization method based on graph convolutional neural networks as described in claim 1 or 2, characterized in that, The process of step 5 is as follows: 5.

1. Convert the normal node set Randomly divided into m Equal portions, m For small batches; 5.

2. For each of them From HTs node set Random sampling was conducted in the middle to obtain and insert Among the requirements The number of nodes in the array approaches This achieves data balancing, whereby... j =1, 2, …, m 。

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