A semiconductor device general modeling method based on weight prediction network optimization

Abstract

The application discloses a kind of based on weight prediction network optimization semiconductor device general modeling method, characterized in that by actual measurement or TCAD simulation obtains semiconductor device original I-V characteristic data, using weight prediction network model to the I-V characteristic of semiconductor device is modeled, then by Verilog-A language will weight prediction network model be converted into SPICE model, finally SPICE model is placed into test circuit and is simulated, and compared with TCAD simulation result, specifically include: the construction and training of weight prediction network model, and the step of converting weight prediction network model into SPICE model.The application does not need to carry out complex data preprocessing process, also does not need to design complex loss function, and weight prediction network model is converted into the model that can be used for SPICE simulation, compared with traditional neural network model, higher accuracy can be obtained, for the academic research and industrial application of new device circuit design and process collaborative optimization (DTCO) Provide an efficient and reliable method.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device modeling technology, and in particular to a general semiconductor device modeling method based on weight prediction network optimization for SPICE circuit simulation. Background Technology

[0002] Semiconductor device modeling serves as a bridge between integrated circuit design and manufacturing. Commercial BSIM models are suitable for modeling conventional single-gate devices. However, with the advent of multi-gate devices using various advanced processes, BSIM models are no longer applicable.

[0003] Currently, most researchers, when modeling semiconductor devices using neural network models, simply fit the device's transfer and output characteristics without considering the device's transconductance G. m and output conductance G DS In terms of characteristic fitting, a small number of researchers have achieved ultra-high precision IV characteristic fitting through complex training to achieve fitting of transconductance and output conductance.

[0004] In existing technologies, most semiconductor device modeling using neural network models involves building fully connected neural network models for regression prediction. This typically requires complex data preprocessing to ensure the convergence of the neural network model in circuit simulation, and necessitates the design of complex loss functions to achieve IV characteristics and G. m Features and G DS High-precision fitting of characteristics. Summary of the Invention

[0005] The purpose of this invention is to provide a general modeling method for semiconductor devices based on weighted prediction network optimization, addressing the shortcomings of existing technologies. This method uses a weighted prediction network to model the IV characteristics of semiconductor devices. The weighted prediction network model is converted into a SPICE model using Verilog-A language. Finally, the SPICE model is placed into a test circuit for simulation, and the circuit simulation results are compared with TCAD simulation results. This method, through weighted prediction network modeling, can directly use raw IV data for training, eliminating the need for complex data preprocessing, reducing the difficulty of model training, improving the accuracy of model prediction, and significantly enhancing the efficiency of integrated circuit design and manufacturing.

[0006] The specific technical solution for achieving the objective of this invention is as follows:

[0007] A general modeling method for semiconductor devices based on weighted prediction network optimization is proposed. The method is characterized by modeling the IV characteristics of the device by establishing a weighted prediction network model. In the modeling process, curve fitting is first performed using raw IV characteristic data under a given process parameter condition to obtain the initial weight values ​​for each layer of the weighted prediction network. Then, all raw IV characteristic data are used as the training set, and the mean squared error is used as the loss function of the weighted prediction network model with a learning rate of 10. -5 The Adam algorithm was used as the parameter optimizer for training the weight prediction network model. Finally, the trained weight prediction network model was converted into a function expression of the drain current. This function expression was then equated to a current source controlled by the gate and drain voltages. Finally, it was converted into a model usable for SPICE simulation using Verilog-A, and this model was used to build basic logic gate circuits for testing and verification.

[0008] This invention provides a general modeling method for semiconductor devices based on weighted prediction network optimization. The method uses a weighted prediction network model to model the IV characteristics of semiconductor devices, converts the weighted prediction network model into a SPICE model using Verilog-A language, and finally places the SPICE model into a test circuit for simulation. The modeling method specifically includes the following steps:

[0009] Step 1: Data Preparation

[0010] The Synopsys Sentaurus TCAD software was used to construct a semiconductor device structure model and perform IV characteristic simulations under different process conditions to obtain raw IV characteristic data. First, the device structure was built using the Sentaurus Structure Editor, defining the dimensions, structural regions, doping type, material type, electrode positions, and mesh size. Then, the Sentaurus Device was used to perform IV characteristic simulations of the device, including transfer curves and output curves.

[0011] Step 2: Construct a weight prediction network model

[0012] Two neural network models were established for the IV characteristics of semiconductor devices using the Tanh activation function: a first neural network and a second neural network. The first neural network is a single-hidden-layer neural network model that takes process parameters and gate voltage as input and the weight values ​​and bias terms in the second neural network as output. The second neural network is a single-hidden-layer neural network model that takes drain voltage as input and drain current as output. The output layer bias term of the second neural network must meet certain constraints, that is, when the input drain voltage is 0V, the output drain current of the model is 0A.

[0013] Step 3: Training the weight prediction network model

[0014] The constructed weight prediction network model is used to train IV characteristic data. The training is divided into two steps: the first step is to initialize the weights of the weight prediction network model, and the second step is to train the weight prediction network model.

[0015] Step 4: Convert the weight prediction network model into a SPICE model

[0016] The bias values ​​of each node in the weight prediction network model and the weight values ​​between nodes are extracted using Python scripts. Then, the weight prediction network model is converted into a mathematical expression, and the mathematical expression is converted into a SPICE model using Verilog-A language.

[0017] Step 5: Put the SPICE model into the SPICE simulator for circuit simulation verification.

[0018] Furthermore, the TCAD software described in step 1 requires the following data for simulation: device width W, gate length L. G Doping type (Dope), gate voltage (V) GS Drain voltage V DS and drain current I DS .

[0019] Furthermore, the constraints of the second neural network in step 2 are defined by the following equation (a):

[0020]

[0021] Where b2 is the bias term of the output layer node, c i Let b be the weight value between the i-th node in the hidden layer and the node in the output layer. 1i It is the weight value between the input layer node and the i-th node in the hidden layer.

[0022] Furthermore, step 3 involves initializing the weights of the weight prediction network model. This is achieved by curve fitting of the IV characteristic data under a given process parameter condition to obtain the initial weight values ​​for each layer of the weight prediction network. Then, the original data of all IV characteristics are used as the training set to train the weight prediction network model. The training strategy is as follows: the mean squared error is used as the loss function for the weight prediction network model, and the learning rate is 10. -5 The Adam algorithm was used as the parameter optimizer for training the weight prediction network model.

[0023] Further, in step 4, the weight prediction network model is converted into a mathematical expression, which is a function expression of the drain current. The independent variables of this function expression are process parameters, gate voltage, and drain voltage. Then, this function expression is equivalent to a current source controlled by the gate voltage and drain voltage, and then converted into an equivalent model of the SPICE sub-circuit using Verilog-A language.

[0024] Furthermore, step 5 specifically involves: placing the converted SPICE model into different test circuits to test the IV characteristics under different process parameters, and using the model to build basic logic gate circuit characteristics and compare them with the TCAD simulation results to verify the accuracy.

[0025] Compared with existing technologies, this invention has higher IV characteristic fitting accuracy and effectively optimizes the transconductance G of semiconductor devices by utilizing a weighted prediction network model. m and output conductance G DS Furthermore, the modeling steps of this invention are simpler, allowing direct training using raw IV data, eliminating complex data preprocessing and reducing the difficulty of model training. It converts the weight prediction network model into a model usable for SPICE simulation, reducing the cost and time of manual modeling. This provides an efficient and reliable method for academic research and industrial applications of circuit design and process co-optimization (DTCO) for future novel devices. Attached Figure Description

[0026] Figure 1 This is a 3D schematic diagram of the RFET nanowire structure device of Embodiment 1 of the present invention;

[0027] Figure 2 This is a 2D cross-sectional schematic diagram of the RFET nanowire structure device of Embodiment 1 of the present invention;

[0028] Figure 3 This is a schematic diagram of the weight prediction network model in Embodiment 1 of the present invention;

[0029] Figure 4 The weight prediction network model of Embodiment 1 of the present invention and the traditional neural network model predict D NW For 6nm, L CG A comparison of the transfer characteristic curves of a 10nm RFET device with TCAD simulation data;

[0030] Figure 5 The weight prediction network model of Embodiment 1 of the present invention and the traditional neural network model predict D NW For 6nm, L CG A comparison of the output characteristic curves of a 10nm RFET device with TCAD simulation data;

[0031] Figure 6 The weight prediction network model of Embodiment 1 of the present invention and the traditional neural network model predict D NW For 6nm, L CG For 10nm RFET devices G m Comparison chart of curves and TCAD simulation data;

[0032] Figure 7 The weight prediction network model of Embodiment 1 of the present invention and the traditional neural network model predict D NW For 6nm, L CG For 10nm RFET devices G DS Comparison chart of curves and TCAD simulation data. Detailed Implementation

[0033] This invention trains the IV characteristics of semiconductor devices step-by-step using a weighted prediction network model. First, the weights of the weighted prediction network model are initialized, then the model is trained, and finally, a Python script converts the trained model into a SPICE model for circuit simulation verification. The technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0034] The method of the present invention includes the following steps:

[0035] Step 1: Data Preparation

[0036] Synopsys Sentaurus TCAD software was used to simulate advanced devices. The SentaurusStructure Editor was used to build the device structure, including defining the device's size, structural regions, doping type, material type, electrode position, and mesh size. The Sentaurus Device was used to simulate the device's IV characteristics.

[0037] Step 2: Construct a weight prediction network model

[0038] Semiconductor device modeling based on a weighted prediction network model requires two neural network models: Neural Network 1 and Neural Network 2. Neural Network 1 is used to predict the weights of Neural Network 2. Since the semiconductor device model needs to ensure that the drain current is 0A when the drain voltage is 0V, and the Tanh activation function itself outputs 0 when the input is 0, constraints are typically added to the output layer bias of Neural Network 2, and Tanh is used as the activation function of the weighted prediction network model. Because semiconductor device modeling also requires the drain current to increase with the drain voltage, the weight values ​​in Neural Network 2 are usually required to be greater than 0 during model building. The inputs to Neural Network 1 are process parameters and gate voltage; the selection of process parameters can be adjusted according to actual modeling needs. The input to Neural Network 2 is the drain voltage. To enable rapid simulation in the test circuit after the weighted prediction network model is converted to a SPICE model, only one hidden layer is usually selected. The number of nodes in this hidden layer is determined by the complexity of the training samples. The output layer of the IV model based on the weighted prediction network typically has only one node, representing the drain current value.

[0039] Step 3: Train the weight prediction network model

[0040] Training a weight prediction network model typically involves two steps. The first step is weight initialization, a crucial step before training. Proper weight initialization can effectively prevent gradient vanishing or gradient exploding during training. The second step is to train the weight prediction network model using mean squared error as the loss function.

[0041] Step 4: Convert the weight prediction network model into a SPICE model

[0042] After the weight prediction network model is trained, the bias value of each node and the weight values ​​between nodes are extracted using a Python script. Then, the weight prediction network model is converted into a mathematical expression, and the mathematical expression is converted into a SPICE model using Verilog-A language.

[0043] Step 5: Put the SPICE model into the SPICE simulator for circuit simulation verification.

[0044] The data preparation in step 1 generally includes the device's size parameters or process parameters, the drain current value obtained from simulation, and the corresponding voltage values ​​of each electrode.

[0045] The constraints of neural network 2 in step 2 are defined by the following equation (a):

[0046]

[0047] Where b2 is the bias term of the output layer node, c i Let b be the weight value between the i-th node in the hidden layer and the node in the output layer. 1i It is the weight value between the input layer node and the i-th node in the hidden layer.

[0048] Step 3, weight initialization, is a crucial step before training the weight prediction network model. By curve fitting the IV characteristic data under a specific process parameter condition, the weight values ​​of each layer of the weight prediction network are obtained. These weight values ​​are then used as the initial weight values ​​for the weight prediction network model, effectively avoiding gradient vanishing or gradient exploding phenomena during training. During the training of the weight prediction network model, all raw data of IV characteristics obtained from actual measurements or TCAD simulations are used as the training set. The training strategy is as follows: mean squared error is used as the loss function for the weight prediction network model, and a learning rate of 10 is adopted. -5 The Adam algorithm was used as the parameter optimizer for training the weight prediction network model.

[0049] In step 4, the weighted prediction network model is converted into a function expression of the drain current. The independent variables of this function expression are process parameters, gate voltage, and drain voltage. Then, this function expression is equivalent to a current source controlled by the gate voltage and drain voltage. The secondary current source is then converted into an equivalent SPICE sub-circuit model using Verilog-A language and placed between the drain and source.

[0050] Step 5 involves placing the converted SPICE model into different test circuits to test the IV characteristics under different process parameters. The model is then used to build a basic logic gate circuit, and the accuracy is verified by comparing the characteristics with the TCAD simulation results.

[0051] Example 1

[0052] Step 1: Use TCAD to build the device structure model and perform simulation to obtain data.

[0053] See Figures 1-2 This embodiment uses a novel device reconfigurable field-effect transistor (RFET) nanowire device for modeling. The 3D structure diagram of the RFET nanowire device built using TCAD is shown below. Figure 1 As shown, its 2D cross-sectional structure diagram is as follows: Figure 2 As shown. For RFET nanowire structure devices, different nanowire diameters D are taken. NW Control gate length L CG and polarity gate voltage V PGIn this configuration, the control gate length and the polar gate length are equal. When the polar gate voltage is 1V, the device is N-type; when the polar gate voltage is -1V, the device is P-type. The gate isolation layer length L is used. GI The thickness is 14nm, and the gate oxide layer thickness T OX The wavelength is 2.75nm. The gate isolation layer length L... GI and gate oxide thickness T OX Other process parameters can also be used as inputs to the model, and can be adjusted according to the modeling requirements. After determining the required parameters, the TCAD tool is used to perform IV characteristic simulation of the device under different parameters and obtain the raw data.

[0054] Step 2: Construct a weight prediction network model with a single hidden layer using the Tanh activation function.

[0055] See Figure 3 The weighted prediction network model uses the Tanh function as the activation function. Its neural network 1 has four input layer nodes, corresponding to four features: the nanowire diameter D. NW Control gate length L CG Polar gate voltage V PG Control gate voltage V CG Neural Network 1 has one hidden layer with 64 nodes. The number of nodes in the output layer of Neural Network 1 is three times the number of nodes in the hidden layer of Neural Network 2. Neural Network 2 has one input layer, which is the drain voltage V. DS The number of hidden layer nodes in neural network 2 is 5. Experiments show that when the number of hidden layer nodes n is greater than or equal to 5, the accuracy of neural network 2 is the highest. The number of output layer nodes in neural network 2 is 1, i.e., the drain current I. DS Furthermore, the constraints of neural network 2 are defined by the following equation (a):

[0056]

[0057] Where b2 is the bias term of the output layer node, c i Let b be the weight value between the i-th node in the hidden layer and the node in the output layer. 1i It is the weight value between the input layer node and the i-th node in the hidden layer.

[0058] Step 3: Train the constructed weight prediction network.

[0059] The training strategy for the weight prediction network model is as follows: First, curve fitting is performed on the IV characteristic data under a given process parameter condition to obtain the weight values ​​for each layer of the weight prediction network. These weight values ​​are then used as the initial weight values ​​for the weight prediction network model, effectively avoiding gradient vanishing or gradient exploding during training. Second, all raw IV characteristic data obtained from actual measurements or TCAD simulations are used as the training set to train the weight prediction network model. The training strategy is as follows: mean squared error is used as the loss function for the weight prediction network model, and a learning rate of 10 is adopted. -5 The Adam algorithm was used as the parameter optimizer for training the weight prediction network model.

[0060] Step 4: Convert the weight prediction network model into a SPICE model.

[0061] The weighted prediction network model was extracted using a Python script and mathematically converted into a functional expression for the drain current. The independent variables of this expression were process parameters, gate voltage, and drain voltage. This expression was then equated to a current source controlled by the gate and drain voltages, and finally converted into an equivalent SPICE sub-circuit model using Verilog-A. For ease of SPICE simulation verification, dimensional parameters such as nanowire diameter and gate length, or process parameters, could be set in nanometers in the SPICE model file during the conversion. In the test circuit, D... NW Setting L to 6 means that the diameter of the nanowire structure is 6 nm. CG Setting it to 10 means that the control gate length of the device is 10nm.

[0062] Step 5: Put the SPICE model into the SPICE simulator for circuit simulation verification.

[0063] The converted SPICE model was placed into different test circuits to test the IV characteristics under different process parameters. The accuracy of the model was verified by comparing the characteristics of basic logic gate circuits with the TCAD simulation results.

[0064] See Figure 4 Predicting D from the perspectives of weighted prediction network models and traditional neural network models NW For 6nm, L CG By comparing the transfer characteristic curves of a 10nm RFET device, it was found that the error of the weighted prediction network model was reduced from 1.67% to 0.11% compared with the prediction value of the traditional neural network model, which shows that the weighted prediction network model fits the transfer characteristics of the device more effectively.

[0065] See Figure 5 Predicting D from the perspectives of weighted prediction network models and traditional neural network modelsNW For 6nm, L CG By comparing the output characteristic curves of a 10nm RFET device, it was found that the error of the weighted prediction network model was reduced from 1.94% to 0.08% compared with the prediction value of the traditional neural network model, which shows that the weighted prediction network model fits the output characteristics of the device more effectively.

[0066] See Figure 6 Predicting D from the perspectives of weighted prediction network models and traditional neural network models NW For 6nm, L CG By comparing the transconductance characteristic curves of a 10nm RFET device, it was found that the error of the weighted prediction network model was reduced from 1.06% to 0.18% compared with the prediction value of the traditional neural network model, which shows that the weighted prediction network model fits the transconductance characteristics of the device more effectively.

[0067] See Figure 7 Predicting D from the perspectives of weighted prediction network models and traditional neural network models NW For 6nm, L CG By comparing the output conductance curves of a 10nm RFET device, it was found that the output conductance predicted by the weighted prediction network model is discontinuous compared to that predicted by the traditional neural network model, while the output conductance predicted by the weighted prediction network model is continuous with an error of 6.93%. This indicates that the weighted prediction network model fits the output conductance characteristics of the device more effectively.

[0068] The above embodiments are merely preferred implementations of the present invention and are not intended to limit the scope of protection of the present invention. Any equivalent implementations of the present invention, as well as any changes made without creative effort on this basis, should be included within the scope of the claims of the present invention.

Claims

1. A method for general modeling of semiconductor devices based on weight prediction network optimization, the method comprising: receiving a plurality of training data; training a weight prediction network using the plurality of training data; receiving a plurality of input data; and predicting a plurality of output data using the trained weight prediction network. The modeling method specifically comprises the following steps: Step 1, data preparation The semiconductor device structure model is constructed using Synopsys Sentaurus TCAD software, and I-V characteristic simulation under different process conditions is performed to obtain original I-V characteristic data; first, the device structure is built using Sentaurus Structure Editor, and the size, structure region, doping type, material type, electrode position and grid size are defined; then, I-V characteristic simulation of the device is performed using Sentaurus Device, including transfer curve and output curve; Step 2, constructing a weight prediction network model Two neural network models for the I-V characteristics of a semiconductor device are established using a Tanh activation function, namely a first neural network and a second neural network; the first neural network is a single-hidden-layer neural network model taking process parameters and gate voltage as input and taking weight values and bias terms in the second neural network as output; the second neural network is a single-hidden-layer neural network model taking drain voltage as input and taking drain current as output, wherein the output layer bias term of the second neural network satisfies a certain constraint condition, i.e., when the input drain voltage is 0V, the output drain current of the model is 0A; Step 3, training of the weight prediction network model The constructed weight prediction network model is used to train the I-V characteristic data, which is divided into two steps: the first step is to initialize the weights of the weight prediction network model, and the second step is to train the weight prediction network model; Step 4: converting the weight prediction network model into a SPICE model The bias values of each node and the weight values between nodes of the weight prediction network model are extracted using a Python script, and then the weight prediction network model is converted into a mathematical expression, and the mathematical expression is converted into a SPICE model through Verilog-A language; Step 5: placing the SPICE model into a SPICE simulator for circuit simulation verification.

2. The method of claim 1, wherein, TCAD software described in step 1, the simulation of the required data include: device width W, gate length L G , doping type Dope, gate voltage V GS , drain voltage V DS and drain current I DS .

3. The method of claim 1, wherein, The constraint condition of the second neural network in step 2 is defined by the following formula (a): where b2is the bias term of the output layer node, c i is the weight value between the i-th node in the hidden layer and the output layer node, b 1i is the weight value between the input layer node and the i-th node in the hidden layer.

4. The method of claim 1, wherein, The weight initialization of the weight prediction network model is performed as described in step 3, that is, by performing curve fitting on the I-V characteristic data under one process parameter condition to obtain the initial weight values of each layer of the weight prediction network, and then taking all the original I-V characteristic data as a training set to train the weight prediction network model, and the training strategy is: taking mean square error as the loss function of the weight prediction network model, and taking the Adam algorithm with a learning rate of 10 -5 as the parameter optimizer of the weight prediction network model for training.

5. The method of claim 1, wherein, In step 4, the weight prediction network model is converted into a mathematical expression, which is a function expression of the drain current, and the independent variables of the function expression are process parameters, gate voltage and drain voltage; then the function expression is equivalent to a current source controlled by gate voltage and drain voltage, and is converted into a SPICE subcircuit equivalent model using Verilog-A language.

6. The method of claim 1, wherein, In step 5, the converted SPICE model is placed into different test circuits to test the I-V characteristics under different process parameters, and the model is used to build a basic logic gate circuit to verify the accuracy by comparing with the TCAD simulation results.

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