Methods, apparatus, equipment, and computer storage media for layout optimization

Abstract

This application discloses a method, apparatus, device, and computer storage medium for layout optimization. The method includes: acquiring an original layout and a virtual network, the virtual network comprising grid cells arranged in a matrix; stacking the virtual network on the original layout according to a first stacking position to divide the original layout into multiple grid regions arranged in an array according to the grid cells; iteratively optimizing the graphics in each grid region of the original layout until a preset optimization condition is met to obtain a target layout; updating the original layout to the target layout; translating the virtual network to obtain an updated first stacking position, and then returning to stack the virtual network on the original layout according to the first stacking position to divide the original layout into multiple grid regions arranged in an array, until the number of virtual network movements reaches a first preset number. According to the embodiments of this application, the layout optimization effect can be improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method, apparatus, device and computer storage medium for layout optimization. Background Technology

[0002] With the rapid development of semiconductor manufacturing processes, people's requirements for chip performance and integration have gradually increased, leading to a continuous reduction in the critical dimensions of chip layouts.

[0003] The manufacturing process for critical dimensions in chip layouts has reached the nanometer level. Therefore, even the slightest deviation can affect the overall performance and reliability of the chip. In particular, due to the optical proximity effect, mask layouts may experience pattern distortion during exposure, thus affecting chip performance and even causing chip failure.

[0004] In related technologies, photolithography can be used to correct mask patterns, making the exposed patterns of the corrected mask pattern closer to the requirements of the design layout. However, when optimizing the mask pattern through photolithography, some discontinuities may exist. These discontinuities affect the quality and accuracy of the pattern formed on the wafer, leading to a decrease in chip yield. Summary of the Invention

[0005] This application provides a layout optimization method, apparatus, device, and computer storage medium, which can reduce discontinuities in the layout optimization process and improve product yield.

[0006] In a first aspect, embodiments of this application provide a method for layout optimization, comprising: acquiring an original layout and a virtual network, the virtual network including grid cells arranged in a matrix; stacking the virtual network on the original layout according to a first stacking position to divide the original layout into multiple grid regions arranged in an array according to the grid cells; iteratively optimizing the graphics in each grid region of the original layout until a preset optimization condition is met to obtain a target layout; updating the original layout to the target layout; translating the virtual network to obtain an updated first stacking position, and returning to stack the virtual network on the original layout according to the first stacking position to divide the original layout into multiple grid regions arranged in an array, until the number of times the virtual network is moved reaches a preset number.

[0007] In one possible implementation of the first aspect, the outline of the grid region is rectangular, and translating the virtual network to obtain an updated first stacking position includes: translating the virtual network along the diagonal direction of the grid region to obtain the updated first stacking position.

[0008] In one possible implementation of the first aspect, translating the virtual network to obtain an updated first stacking position includes: determining a translation distance based on the side length of the grid region; and translating the virtual network according to the translation distance to obtain the updated first stacking position.

[0009] In one possible implementation of the first aspect, the translation distance is less than the side length.

[0010] In one possible implementation of the first aspect, the graphics in each grid region of the original layout are iteratively optimized until a preset optimization condition is met to obtain the target layout, including: iteratively performing the following operations until the preset optimization condition is met to obtain the target layout: determining a graphics correction strategy for graphics in each grid region based on the optical proximity effect; determining correction parameters for different graphics in different grid regions based on the graphics correction strategy and the photolithography process model; correcting different graphics in different grid regions based on the correction parameters to obtain corrected graphics; predicting key dimension information of the corrected graphics based on the photolithography process model to obtain predicted key dimension information; calculating the deviation between the predicted key dimension information and the preset key dimension threshold information to obtain deviation information; and updating the corrected graphics to the graphics in the grid region when it is determined that the preset optimization condition is not met.

[0011] In one possible implementation of the first aspect, predicting key dimension information of the modified pattern based on the photolithography process model to obtain the predicted key dimension information includes: determining a mask image based on the modified pattern; and inputting the mask image into the photolithography reaction model to obtain the predicted key dimension information of the pattern.

[0012] In one possible implementation of the first aspect, the graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape; correspondingly, the correction parameters include at least one of the following: graphic edge adjustment amount, size, position, and shape of the auxiliary graphics.

[0013] In one possible implementation of the first aspect, the preset optimization conditions are different in different iterations of the optimization process.

[0014] In one possible implementation of the first aspect, the preset optimization conditions include: the number of iterations being less than a preset number; the preset number of iterations in the preset optimization conditions of two adjacent iterations being different; or, the deviation information being less than a preset deviation; the preset deviation in the preset optimization conditions of two adjacent iterations being different.

[0015] Secondly, embodiments of this application provide a layout optimization apparatus, comprising: an acquisition module for acquiring an original layout and a virtual network, the virtual network including grid cells arranged in a matrix; a division module for overlaying the virtual network onto the original layout according to a first stacking position, thereby dividing the original layout into multiple grid regions arranged in an array according to the grid cells; an optimization module for iteratively optimizing the graphics in each grid region of the original layout until a preset optimization condition is met to obtain a target layout; an update module for updating the original layout to the target layout; and a translation module for translating the virtual network to obtain the updated first stacking position, and returning to overlay the virtual network onto the original layout according to the first stacking position, thereby dividing the original layout into multiple grid regions arranged in an array, until the number of times the virtual network is moved reaches a preset number.

[0016] Thirdly, embodiments of this application provide a layout optimization apparatus, the apparatus including: a processor and a memory storing computer program instructions; the processor executes the computer program instructions to implement the layout optimization method in the first aspect or any embodiment of the first aspect.

[0017] Fourthly, a computer-readable storage medium storing computer program instructions, which, when executed by a processor, implement a layout optimization method according to the first aspect or any embodiment of the first aspect.

[0018] Fifthly, embodiments of this application provide a computer program product in which instructions, when executed by a processor of an electronic device, cause the electronic device to perform a layout optimization method as described in the first aspect or any embodiment of the first aspect.

[0019] This application discloses a method, apparatus, device, and computer storage medium for layout optimization. The method involves acquiring an original layout and a virtual network, and then overlaying the virtual network onto the original layout according to a first overlay position. This divides the original layout into multiple grid regions based on the grid units within the virtual network. The grid regions are then optimized to meet optimization conditions, resulting in a target layout. Further, the virtual network can be shifted to an updated first overlay position, and the number of shifts is determined to be a first preset number. If the number is reached, the layout optimization is considered complete, and an optimized layout is obtained. If the first preset number is not reached, the optimized layout is divided according to the virtual network located at the updated first overlay position, and each grid region is re-optimized until the preset number is reached. It is understood that during iterative optimization of graphics in each grid region, graphics located in the center perform better. Therefore, in this application embodiment, by continuously adjusting the position of graphics within the grid regions, all graphics in the layout have a chance to be located in the center of the grid region, thereby improving the layout optimization effect. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This illustration shows a schematic diagram of a design layout provided in an embodiment of this application;

[0022] Figure 2 A schematic flowchart of a layout optimization method according to an embodiment of this application is shown;

[0023] Figure 3 This illustration shows a schematic diagram of a virtual network stacking method according to a first stacking position, provided in one embodiment of this application;

[0024] Figure 4 This illustration shows a schematic diagram of a virtual network stacking method according to an updated first stacking position provided in one embodiment of this application;

[0025] Figure 5 A flowchart of S230 provided in one embodiment of this application is shown;

[0026] Figure 6 This illustration shows a schematic diagram of the division of an extended region according to an embodiment of this application;

[0027] Figure 7This is a schematic diagram of the layout optimization apparatus provided in another embodiment of this application;

[0028] Figure 8 This is a schematic diagram of the layout optimization device provided in another embodiment of this application. Detailed Implementation

[0029] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0030] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0031] With the rapid development of semiconductor integrated circuit manufacturing technology, the critical dimensions of chip design layouts are constantly decreasing, and the optical proximity effect can cause distortion in the exposure patterns of chip design layouts.

[0032] Therefore, computational lithography is needed to correct the patterns in the mask layout. Computational lithography consumes significant computing resources. To improve computational speed and reduce the bottleneck of resource consumption for individual tasks, distributed computational lithography can solve this problem. Distributed computational lithography divides the entire design layout into multiple small regions of equal size, optimizes each region individually, and then stitches the optimization results of each region together to obtain the overall optimization result. This achieves a parallel processing solution of "partitioning, parallel computing, and stitching," thereby improving the optimization speed of the layout. In one example, Figure 1 This illustration shows a schematic diagram of a design layout provided in an embodiment of this application, such as... Figure 1As shown, layout 10 can be divided according to a preset size to obtain multiple small regions 11. Each small region 11 can completely cover layout 10. Figure 1 (Not all small areas are drawn), and each small area 11 can be called a box.

[0033] However, during the layout partitioning process, a complete graphic may be divided into different small regions. In this case, the complete graphic will be cut off at the boundaries of the small regions, and the geometric properties of the graphic will be destroyed. Computational lithography simulation results are heavily dependent on the surrounding environment; changes in the surrounding environment will affect the simulation results. Understandably, because a complete graphic is divided into different small regions, the geometric properties of the graphic are destroyed, and the optimization results of each small region will be affected by the geometric properties of the graphic. Therefore, optimizing different parts of the same graphic in different small regions may lead to subtle differences in the optimization. These differences may cause discontinuities at the stitching points when the small regions are stitched together. Therefore, ensuring the continuity of the stitching boundaries when the partitioned small regions are stitched into a complete layout during distributed computational lithography is a technical problem that urgently needs to be solved by relevant engineers.

[0034] To address the problems of the prior art, embodiments of this application provide a method, apparatus, device, and computer storage medium for layout optimization. The layout optimization method provided in this application embodiment will be described first below.

[0035] Figure 2 A schematic flowchart illustrating a layout optimization method according to an embodiment of this application is shown. Figure 2 As shown, the layout optimization method provided in this application embodiment includes the following steps:

[0036] S210. Obtain the original map and virtual network, the virtual network consisting of grid cells arranged in a matrix.

[0037] S220. The virtual network is overlaid on the original layout according to the first overlay position, so that the original layout is divided into multiple grid regions arranged in an array according to grid cells.

[0038] S230. Iteratively optimize the graphics in each grid region of the original map until the preset optimization conditions are met to obtain the target map.

[0039] S240. Update the original map to the target map.

[0040] S250: Determine whether the number of times the map has been divided has reached the first preset number. If not, proceed to S260; if yes, end the training.

[0041] S260, shift the virtual network to obtain the updated first stacking position.

[0042] For example, in step S210, the original layout can be a design drawing of an integrated circuit. The original layout can be a pattern drawn by a technician using electronic design automation tools according to functional requirements. Furthermore, the original layout details the shape, location, size, and connection relationships of each component in the circuit. In one example, the components in the circuit may include transistors, resistors, capacitors, etc.

[0043] For example, a virtual network can consist of multiple grid cells arranged in an array. In one example, all grid cells in the virtual network are the same size.

[0044] For example, in step S220, the virtual network can be stacked on the original layout according to the first stacking position, thereby dividing the original layout into multiple grid regions arranged in an array according to each grid cell in the virtual network. Each grid region can be a region of equal size arranged in a row, and the virtual network can completely cover the original layout.

[0045] For example, the first stacking position can be any position in the original layout. In one example, stacking the virtual network on the original layout according to the first stacking position can be done by aligning the bottom left corner of the original layout with the bottom left corner of the virtual network, thereby stacking the virtual network on the original layout. Figure 3 This illustration shows a schematic diagram of a virtual network stacking method according to a first stacking position, as provided in one embodiment of this application. Figure 3 As shown, the lower left corner of the original map is aligned with the lower left corner of the virtual network, ensuring that the virtual network completely covers the original map. Each grid cell in the virtual network can be rectangular, and the side length of each rectangle can be set to m micrometers. The original map 10 is divided into multiple grid regions, including box1, box2, ..., boxn, using m*m grid cells. Here, m is a positive number.

[0046] For ease of understanding, if the coordinates of the lower left corner of the target layout are (0,0), then the coordinates of the first stacking position and the lower left corner of the target layout can also be (0,0). Points 1 and 2 can represent points contained in different graphics. When the virtual mesh is positioned at the first stacking position to divide the original layout, both points 1 and 2 are located in box1. Point 2 is located at the center of box1, and point 1 is located at the edge of box1. In this case, graphics containing point 1 can all be located in box1, while graphics containing point 2 may have some areas located in other boxes.

[0047] For example, in step S230, the graphics in multiple grid regions can be optimized in parallel until the preset optimization conditions are met. Then, the multiple optimized grid regions are stitched together to obtain the target layout.

[0048] In one example, when optimizing box1, it can optimize the graphic containing point 2. Since the graphic containing point 2 is entirely within box1, the geometric properties of the graphic at point 2 are not destroyed. Therefore, when optimizing the graphic containing point 2, the optimized graphic does not have a discontinuity issue. However, when optimizing the graphic containing point 1, since part of the graphic containing point 1 is located in other boxes, the geometric properties of the graphic at point 1 are destroyed. Therefore, when optimizing the graphic containing point 1, discontinuities appear when it is joined with other boxes, meaning the optimized graphic containing point 1 will have a discontinuity issue.

[0049] For example, in step S240, the original layout can be updated to a target layout. The target layout can be an optimized layout.

[0050] For example, in step S250, it can be determined whether the number of times the layout has been divided has reached a first preset number. If yes, that is, the number of times the layout has been divided has reached the first preset number, then the layout optimization is determined to be completed, the training ends, and the optimized layout is obtained; if no, that is, the number of times the layout has been divided has not reached the first preset number, then S260 is executed, that is, the virtual network is translated to obtain the updated first stacking position, and the virtual network is stacked on the target layout according to the updated first stacking position to divide the target layout into multiple grid regions arranged in an array, until the number of times the virtual network has been moved reaches the first preset number.

[0051] Furthermore, after overlaying the virtual networks onto the optimized layout according to the updated first stacking position, the original layout can be divided according to the virtual networks located at the updated first stacking position. In one example, Figure 4 This illustration shows a schematic diagram of a virtual network stacking method according to an updated first stacking position, as provided in one embodiment of this application. Figure 4As shown, the updated first stacking position can be the distance (2m√2) / 3 of moving the lower left corner of the virtual network along the diagonal of the grid area. For ease of understanding, if the coordinates of the left side of the lower left corner of the target layout are (0,0), then the coordinates of the updated first stacking position can be (-2m / 3, -2m / 3). Further, the virtual network is stacked on the target layout according to the updated first stacking position; that is, the lower left corner of the virtual network can be aligned with the updated first stacking position, and the target layout is divided according to the grid area. Specifically, the target layout 20 can be divided according to an m*m grid area, resulting in multiple second division areas, including box1', box2', ..., boxn'. Here, m is a positive number. During this division process, points 1 and 2 can be located in different grid areas; that is, point 2 is located in box1, and point 1 is located in box4. Furthermore, point 2 is located at the edge of box1, while point 1 is located at the center of box4. At this point, the discontinuity in the graphic containing point 2 during the first stitching can be located in box 4.

[0052] Furthermore, the graphics within the re-divided grid regions can be optimized in parallel. In one example, when optimizing box4, it could optimize the positions of discontinuities in the graphics containing point 2, thereby ensuring that the graphics containing point 2 meet the requirements.

[0053] This application provides a method for optimizing a layout. It involves acquiring an original layout and a virtual network, and then overlaying the virtual network onto the original layout according to a first overlay position. This divides the original layout into multiple grid regions based on the grid cells within the virtual network. The grid regions are then optimized to meet optimization conditions, resulting in a target layout. Further, the virtual network can be moved to the updated first overlay position, and the number of moves is determined to be a first preset number. If the number is reached, the layout optimization is considered complete, and an optimized layout is obtained. If the first preset number is not reached, the optimized layout is divided according to the virtual network located at the updated first overlay position, and each grid region is re-optimized until the preset number is reached. It is understood that during iterative optimization of graphics in each grid region, graphics located in the center perform better. Therefore, in this application embodiment, by continuously adjusting the position of graphics within the grid regions, all graphics in the layout have a chance to be located in the center of the grid region, thereby improving the layout optimization effect.

[0054] In some alternative embodiments, if the outline of the grid region is rectangular, the virtual network can be translated along the diagonal direction of the grid region to obtain the updated first stacking position.

[0055] For example, the virtual network can be translated to the updated first stacking position along the diagonal of the grid area, based on the first stacking position.

[0056] In one example, the outline of the grid region can be a square, and the outline of the grid region can be determined by a technician based on the original map.

[0057] In this embodiment, when the outline of the grid area is rectangular, the virtual network can be translated along the diagonal of the grid area to obtain the updated first stacking position. This ensures that the multiple grid areas divided according to the updated first stacking position are different from the previously divided grid areas, further ensuring that the graphics in the original layout can be located in different positions in the grid area. This ensures that during layout optimization, each graphic in the layout has the opportunity to be located in the center of the grid area, thus improving the effect of layout optimization.

[0058] In some alternative embodiments, the updated first stacking position can be determined by a translation distance based on the side length of the grid region. Then, the virtual network is translated according to the translation distance to obtain the updated first stacking position.

[0059] In this embodiment, the translation distance can be determined based on the side length of the grid region, and the virtual network can be translated according to the translation distance so that the virtual grid is located at the updated first stacking position. It is understood that determining the translation distance based on the side length of the grid region can avoid the problem of each grid region overlapping with the previous one after the virtual network is translated. In this way, the graphics in the layout can be located at different positions in the grid region in different partitions.

[0060] In some alternative embodiments, the translation distance is less than the side length. It is understood that a smaller translation distance can be used to allow graphics in the layout to be located at different positions within the grid region in different partitions, improving layout optimization efficiency.

[0061] For example, each partitioned region can be optimized individually, thereby reducing the time required for the overall optimization task and improving optimization efficiency. In one example, each partitioned region can be distributed in parallel across multiple computers or computing nodes, enabling multiple computers or computing nodes to process multiple regions in parallel, thereby improving computational efficiency and reducing memory consumption.

[0062] For example, the following is combined with Figure 5 as well as Figure 7 The process of iteratively optimizing the graphics in the grid region of the original map and the graphics in the second region of the target map is explained.

[0063] Figure 5A flowchart illustrating S230 according to an embodiment of this application is shown. Figure 5 As shown, S230 provided in this embodiment includes the following steps:

[0064] S231. Based on the optical proximity effect, determine the graphic correction strategy for the graphics in each grid region.

[0065] For example, the optical proximity effect (OPE) causes the exposed pattern to deviate from the desired size and shape during photolithography. Therefore, the results of the OPE evaluation can be used to determine specific correction strategies.

[0066] In some optional embodiments, the first graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape.

[0067] In one example, edge adjustment can refer to fine-tuning the edges of a graphic, such as increasing or decreasing the width of the edges, to compensate for the problem of lines becoming wider or narrower due to optical proximity effects during photolithography.

[0068] In another example, adding auxiliary graphics can refer to adding auxiliary graphics to the layout. This alters the light intensity distribution and improves the lithographic effect of adjacent graphics. For instance, adding a small rectangular auxiliary graphic between two closely adjacent lines can reduce interference between the lines.

[0069] In another example, adjusting the shape of a graphic can refer to fine-tuning the shape of the graphic, such as changing right angles to rounded corners, in order to reduce scattering and diffraction effects during the photolithography process.

[0070] In this embodiment of the application, since the optical proximity effect may cause different defects in the pattern during the photolithography process, different correction strategies can be formulated to correct the pattern for different defects that occur during the photolithography process, thereby reducing photolithography defects and improving product yield.

[0071] S232. Based on the pattern correction strategy and the photolithography process model, determine the correction parameters for different patterns in different grid regions.

[0072] For example, correction parameters corresponding to the pattern correction strategy can be determined based on relevant parameters in the photolithography process model. In one example, the relevant parameters in the photolithography process model may include parameters of the photolithography process, characteristics of the photoresist, and material properties of the wafer. Among them, the parameters of the photolithography process include light source wavelength, exposure dose, focal length, etc.

[0073] In some optional embodiments, the correction parameters include at least one of the following: graphic edge adjustment amount, auxiliary graphic size, position, and shape.

[0074] In this embodiment of the application, for different pattern correction strategies, the corresponding correction parameters can be determined by the relevant parameters in the photolithography process model, so as to achieve pattern correction.

[0075] S233. Based on the correction parameters, correct different graphics in different grid areas to obtain the corrected graphics.

[0076] For example, different patterns in different grid regions can be corrected according to different correction parameters to obtain corrected patterns. It is understood that since different patterns are affected differently by the optical proximity effect, the correction strategies for different patterns can be different, and the correction parameters corresponding to the correction strategies can also be different.

[0077] S234. Based on the photolithography process model, predict the key dimension information of the correction pattern to obtain the predicted key dimension information.

[0078] For example, a photolithography process model may include simulating the light intensity distribution during the photolithography process using an optical model, as well as simulating the photoresist reaction process.

[0079] For example, by inputting patterns of multiple grid regions into a photoresist process model, the photoresist process model can predict the critical dimension information corresponding to the pattern on the crystal source under the input pattern. The predicted critical dimension information may include the shape and / or surface morphology of the pattern on the crystal source.

[0080] In some alternative embodiments, a mask image can be determined based on the modified pattern, and the mask image can be input into the photolithography reaction model to obtain the predicted pattern key dimension information.

[0081] For example, since the input to the photolithography process model requires a mask pattern, the mask pattern can be determined by modifying the pattern. This mask pattern is then input into the photolithography reaction model to obtain the predicted key dimension information of the pattern.

[0082] S235. Calculate the deviation between the predicted critical dimension information and the preset critical dimension threshold information to obtain the deviation information.

[0083] For example, the root mean square (RMS) of the deviation can be calculated and the calculated RMS can be used as the deviation information.

[0084] S236. Determine whether the preset optimization conditions are met. If yes, then determine the corrected graphic as the target layout. If not, then proceed to step S237.

[0085] S237. Update the corrected graphic to the graphic in the grid area.

[0086] In some optional embodiments, the preset optimization conditions include at least one of the following: the number of iterations is less than a second preset threshold; or the deviation information is less than a preset deviation threshold. The second preset threshold and the preset deviation threshold can be set by a technician.

[0087] For example, the preset optimization conditions in two adjacent optimization iterations can be different. This could be due to a different second preset number of iterations in two adjacent iterations, or a different preset deviation threshold. In one example, if in two adjacent optimization processes, the preset optimization conditions for the previous optimization process include at least one of the following: the second iteration number is less than the first preset threshold; or the deviation information is less than the second deviation threshold. The preset optimization conditions for the subsequent optimization process include at least one of the following: the second iteration number is less than the third preset threshold; or the deviation information is less than the fourth deviation threshold. In this case, the first preset threshold can be set to be greater than the third preset threshold; and the second deviation threshold can be set to be less than the fourth deviation threshold.

[0088] For example, after determining that the preset optimization conditions are met, the revised layout can be identified as the target layout. Further, the target layout can be divided according to the virtual network located at the first stacked position after the update.

[0089] For example, after determining that the preset optimization conditions are not met, the corrected graphic can be updated to the graphic in the grid area, and the correction strategy corresponding to the updated graphic can be re-determined. Then, the correction parameters can be determined, and the updated graphic can be corrected using the correction parameters until the preset optimization conditions are met.

[0090] Furthermore, since the optimization result of the graphics in each grid region depends on the surrounding environment of the grid region during the optimization process, an extension region can be set for each divided grid region. Then, the graphics in the grid regions, including the extension region, are optimized iteratively.

[0091] In one example, Figure 6 A schematic diagram illustrating the division of an extended region according to an embodiment of this application is shown. Figure 6As shown, the extended region 12 can be an extension distance added to the perimeter of the divided region. It's understandable that the larger the extension distance of each region, the closer its optimization environment is to the overall layout environment, resulting in higher boundary consistency. However, optimizing each region will also consume more computational resources. Therefore, it is necessary to set the range of the extended region reasonably.

[0092] In this embodiment of the application, the optimization speed of the layout is improved by simultaneously optimizing multiple grid regions.

[0093] Based on the layout optimization method provided in the above embodiments, this application also provides specific implementations of the layout optimization apparatus. Please refer to the following embodiments.

[0094] First see Figure 7 The layout optimization apparatus provided in this application embodiment includes the following units:

[0095] The acquisition module 701 is used to acquire the original map and the virtual network, the virtual network comprising grid cells arranged in a matrix;

[0096] The partitioning module 72 is used to overlay the virtual network onto the original layout according to the first overlay position, so as to divide the original layout into multiple grid regions arranged in an array according to the grid cells;

[0097] The optimization module 703 is used to iteratively optimize the graphics in each grid region of the original map until the preset optimization conditions are met, and the target map is obtained.

[0098] Update module 704 is used to update the original map to the target map;

[0099] The translation module 705 is used to translate the virtual network to obtain the updated first stacking position, and then return to stack the virtual network on the original map according to the first stacking position to divide the original map into multiple grid areas arranged in an array, until the number of times the virtual network is moved reaches a first preset number.

[0100] As one implementation of this application, the outline of the grid region is rectangular, and the translation module 705 translates the virtual network in the following manner to obtain the updated first stacking position: translate the virtual network along the diagonal direction of the grid region to obtain the updated first stacking position.

[0101] As one implementation of this application, the translation module 705 translates the virtual network in the following manner to obtain the updated first stacking position: determine the translation distance according to the side length of the grid area; translate the virtual network according to the translation distance to obtain the updated first stacking position.

[0102] As one implementation of this application, the translation distance is less than the side length.

[0103] The optimization module 703 iteratively optimizes the graphics in the grid regions of the original layout in the following manner until the preset optimization conditions are met, and obtains the target layout: Iteratively perform the following operations until the preset optimization conditions are met, and obtain the target layout: Based on the optical proximity effect, determine the first graphic correction strategy for the graphics in each grid region; Based on the first graphic correction strategy and the photolithography process model, determine the first correction parameters for different graphics in different grid regions; Based on the first correction parameters, correct different graphics in different grid regions to obtain the corrected first corrected graphics; Based on the photolithography process model, predict the key dimension information of the first corrected graphics to obtain the first predicted key dimension information; Calculate the deviation between the first predicted key dimension information and the preset key dimension threshold information to obtain the first deviation information; If it is determined that the preset optimization conditions are not met, update the first corrected graphics to the graphics in the grid region.

[0104] As one implementation of this application, the optimization module 703 predicts the key dimension information of the first modified pattern according to the photolithography process model in the following manner to obtain the first predicted key dimension information: determine the first mask image according to the first modified pattern; input the first mask image into the photolithography reaction model to obtain the key dimension information of the first predicted pattern.

[0105] As one implementation of this application, the graphic correction strategy includes at least one of the following: graphic edge adjustment, adding auxiliary graphics, and adjusting graphic shape; correspondingly, the correction parameters include at least one of the following: graphic edge adjustment amount, size, position, and shape of the auxiliary graphics.

[0106] As one implementation of this application, the preset optimization conditions include any one of the following: the preset optimization conditions include the number of iterations being less than a second preset number, or the second preset number in the preset optimization conditions in two adjacent iterations being different; or the deviation information being less than a preset deviation threshold, or the preset deviation threshold in the preset optimization conditions in two adjacent iterations being different.

[0107] Figure 8 A schematic diagram of the layout-optimized hardware structure provided in an embodiment of this application is shown.

[0108] The layout optimization device may include a processor 801 and a memory 802 storing computer program instructions.

[0109] Specifically, the processor 801 may include a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits that can be configured to implement the embodiments of this application.

[0110] Memory 802 may include mass storage for data or instructions. For example, and not limitingly, memory 802 may include a hard disk drive (HDD), floppy disk drive, flash memory, optical disk, magneto-optical disk, magnetic tape, or Universal Serial Bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 802 may include removable or non-removable (or fixed) media. Where appropriate, memory 802 may be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, memory 802 is non-volatile solid-state memory.

[0111] Memory may include read-only memory (ROM), random access memory (RAM), disk storage media devices, optical storage media devices, flash memory devices, and electrical, optical, or other physical / tangible memory storage devices. Therefore, typically, memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the methods according to one aspect of this disclosure.

[0112] The processor 801 implements any of the layout optimization methods described in the above embodiments by reading and executing computer program instructions stored in the memory 802.

[0113] In one example, the layout optimization device may further include a communication interface 803 and a bus 810. Wherein, as Figure 8 As shown, the processor 801, memory 802, and communication interface 803 are connected through bus 810 and complete communication with each other.

[0114] The communication interface 803 is mainly used to realize communication between various modules, devices, units and / or equipment in the embodiments of this application.

[0115] Bus 810 includes hardware, software, or both, that couples components of an online data traffic metering device together. For example, and not limitingly, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infinite Bandwidth Interconnect, a Low Pin Count (LPC) bus, a memory bus, a Microchannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses, or combinations of two or more of these. Where appropriate, bus 810 may include one or more buses. Although specific buses are described and illustrated in embodiments of this application, any suitable bus or interconnect is contemplated herein.

[0116] This layout optimization device can execute the layout optimization method in this application embodiment according to the regions obtained by different division methods, thereby achieving a combination of Figure 2 and Figure 7 The described layout optimization method and apparatus.

[0117] Furthermore, in conjunction with the layout optimization methods in the above embodiments, this application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when these computer program instructions are executed by a processor, they implement any of the layout optimization methods in the above embodiments.

[0118] This embodiment also provides a computer program product, including a computer program, which, when executed, implements any of the layout optimization methods described in the above embodiments.

[0119] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.

[0120] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.

[0121] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0122] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0123] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A method of layout optimization, characterized by, The method comprises the following steps: obtaining an original layout and a virtual network, wherein the virtual network comprises grid cells arranged in a matrix; stacking the virtual network on the original layout according to a first stacking position to divide the original layout into a plurality of grid regions arranged in an array according to the grid cells; iteratively optimizing the patterns in each grid region of the original layout until a preset optimization condition is met to obtain a target layout; updating the original layout to the target layout; translating the virtual network to obtain an updated first stacking position, and returning to the step of stacking the virtual network on the original layout according to the first stacking position to divide the original layout into a plurality of grid regions arranged in an array until the number of movements of the virtual network reaches a first preset number.

2. The method of claim 1, wherein, The contour of the grid region is a rectangle, and the step of translating the virtual network to obtain an updated first stacking position comprises: translating the virtual network along the diagonal direction of the grid region to obtain an updated first stacking position.

3. The method according to any one of claims 1 or 2, characterized in that, The step of translating the virtual network to obtain an updated first stacking position comprises: determining a translation distance according to the side length of the grid region; translating the virtual network according to the translation distance to obtain an updated first stacking position.

4. The method of claim 3, wherein, The translation distance is less than the side length.

5. The method of claim 1, wherein, The step of iteratively optimizing the patterns in each grid region of the original layout until a preset optimization condition is met to obtain a target layout comprises: iteratively performing the following operations until a preset optimization condition is met to obtain a target layout: determining a pattern correction strategy for the patterns in each grid region according to the optical proximity effect; determining correction parameters for different patterns in different grid regions according to the pattern correction strategy and a lithography process model; correcting different patterns in different grid regions according to the correction parameters to obtain corrected correction patterns; predicting critical dimension information of the corrected correction patterns according to the lithography process model to obtain predicted critical dimension information; calculating the deviation between the predicted critical dimension information and preset critical dimension threshold information to obtain deviation information; updating the corrected correction patterns to the patterns in the grid region if it is determined that the preset optimization condition is not met.

6. The method of claim 5, wherein, The step of predicting critical dimension information of the corrected correction patterns according to the lithography process model to obtain predicted critical dimension information comprises: determining a mask pattern according to the corrected correction patterns; inputting the mask pattern into a lithography reaction model to obtain predicted pattern critical dimension information.

7. The method of claim 5, wherein, The pattern correction strategy comprises at least one of the following: pattern edge adjustment, addition of auxiliary patterns, and adjustment of pattern shape. Correspondingly, the correction parameters comprise at least one of the following: pattern edge adjustment amount, size, position, and shape of auxiliary patterns.

8. The method according to any one of claims 1 to 7, characterized in that, The preset optimization conditions in different iteration optimization processes are different.

9. The method of claim 8, wherein, The preset optimization condition comprises that the number of iterations is less than a second preset number, and the second preset number in the preset optimization condition in adjacent two iteration optimization processes is different. Or, The deviation information is less than a preset deviation threshold, and the preset deviation threshold in the preset optimization condition in adjacent two iteration optimization processes is different.

10. A layout optimization apparatus, characterized by comprising: The method comprises the following steps: An acquisition module is configured to acquire an original layout and a virtual network, the virtual network including grid cells arranged in a matrix; A division module is configured to stack the virtual network on the original layout according to a first stacking position, so as to divide the original layout into a plurality of grid regions arranged in an array according to the grid cells; An optimization module is configured to iteratively optimize patterns in each grid region of the original layout until a preset optimization condition is met, so as to obtain a target layout; An update module is configured to update the original layout into the target layout; A translation module is configured to translate the virtual network to obtain an updated first stacking position, and return to stacking the virtual network on the original layout according to the first stacking position to divide the original layout into a plurality of grid regions arranged in an array, until a number of movements of the virtual network reaches a first preset number.

11. A layout optimization apparatus, characterized by comprising: The device comprises a processor and a memory storing computer program instructions; The processor executes the computer program instructions to implement the layout optimization method of any one of claims 1-9.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer program instructions, and the computer program instructions are executed by the processor to implement the layout optimization method of any one of claims 1-9.

13. A computer program product, characterised in that, The instructions in the computer program product are executed by the processor of the electronic device, so that the electronic device executes the layout optimization method of any one of claims 1-9.

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