Anti-fuse memory with finfet

Abstract

The invention discloses an anti-fuse memory with a fin field effect transistor. The anti-fuse memory comprises a first memory cell. The first memory cell comprises a first selection transistor, a first follower transistor and a first anti-fuse transistor. The first drain / source end of the first selection transistor is connected with a first bit line, and the gate end of the first selection transistor is connected with a first word line. A first drain / source terminal of the first following transistor is connected to a second drain / source terminal of the first selection transistor, and a gate terminal of the first following transistor is connected to a first following control line. The first anti-fuse transistor includes a first fin, a first gate structure, a first drain / source contact layer, and a second drain / source contact layer. The first gate structure includes a first gate dielectric layer and a first gate layer connected to the first anti-fuse control line. A first drain / source contact layer is electrically connected to a first end of the first fin and a second drain / source end of the first follower transistor. A second drain / source contact layer is electrically connected to the second end of the first fin.

Description

Technical Field

[0001] The present invention relates to an anti-fuse type memory, and in particular to an anti-fuse type memory with a fin field effect transistor (FinFET transistor for short). Background Art

[0002] As is known to all, one time programming memory (OTP memory) is a non-volatile memory. OTP memory includes multiple one-time programming memory cells (OTP memory cells). OTP memory cells can only be programmed once. Once the OTP memory cells are programmed, the stored data in the OTP memory cells cannot be modified.

[0003] For example, an antifuse-type memory is a type of OTP memory. Before a program action is performed on a memory cell of an antifuse-type memory, the memory cell is in a high resistance storage state. After a program action is performed on a memory cell of an antifuse-type memory, the memory cell is in a low resistance storage state. Once a program action is performed on a memory cell of an antifuse-type memory, the stored data cannot be modified. Summary of the invention

[0004] The present invention relates to an anti-fuse type memory, which has a first memory cell, which is designed on a semiconductor substrate, and the first memory cell includes: a first selection transistor, a first drain / source terminal of the first selection transistor is connected to a first bit line, and a gate terminal of the first selection transistor is connected to a first word line; a first follower transistor, a first drain / source terminal of the first follower transistor is connected to a second drain / source terminal of the first selection transistor, and a gate terminal of the first follower transistor is connected to a first follower control line; and a first anti-fuse transistor, including: a first fin; a first gate structure, including a first gate dielectric layer and a first gate layer; wherein, above a middle area of ​​the first fin The two side surfaces are covered by the first gate dielectric layer, the first gate dielectric layer is covered by the first gate layer, the first gate layer is connected to a first anti-fuse control line; a first drain / source contact layer is electrically connected to a first end of the first fin, and the first drain / source contact layer is connected to a second drain / source end of the first follower transistor; and a second drain / source contact layer is electrically connected to a second end of the first fin; wherein, during a programming action, the first bit line receives a ground voltage, the first word line receives a turn-on voltage, the first follower control line receives a conduction voltage, the first anti-fuse control line receives a programming voltage, and the first gate dielectric layer in the first anti-fuse transistor is broken so that the first storage unit is programmed to a storage state with a low resistance value.

[0005] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below in detail with reference to the accompanying drawings: BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1L is a three-dimensional diagram of the manufacturing process of a fin field effect transistor and a cross-sectional diagram corresponding to the AB dotted line;

[0007] Figure 2 is a schematic diagram of an anti-fuse memory according to a first embodiment of the present invention;

[0008] Figure 3A A schematic diagram of bias voltage for programming an anti-fuse memory according to a first embodiment of the present invention;

[0009] Figure 3B A schematic diagram of bias voltage for reading an anti-fuse memory according to the first embodiment of the present invention;

[0010] Figure 4 is a schematic diagram of an anti-fuse memory according to a second embodiment of the present invention;

[0011] Figure 5A A schematic diagram of bias voltage for programming an anti-fuse memory according to a second embodiment of the present invention;

[0012] Figure 5B A schematic diagram of bias voltage for reading an anti-fuse memory according to a second embodiment of the present invention; and

[0013] Figure 6 FIG. 4 is a schematic diagram of another well region structure of the present invention.

[0014] Explanation of symbols

[0015] 101,201,511,601:Semiconductor substrate

[0016] 102,202,512: Deep N-type well region

[0017] 103,203,513,604: P-type well region

[0018] 104,204,514,605: N-type pickup well region

[0019] 110,200,400:Insulation layer

[0020] 112,114,116,118,212,214,216,218,232,234,236,238,252,254,256,258,312,314,316,318,332,334,336,338,352,354,356,358,412,414,416,418,432,434,436,438,452,454,456,458,472,474,476,478,492,494,496,498: Fin

[0021] 120,220,240,260,320,340,360,420,440,460,480,500: Gate layer

[0022] 122,124,126,128,222,224,226,228,242,244,246,248,262,264,266,268,322,324,326,328,342,344,346,348,362,364,366,368,422,424,426,428,442,444,446,448,462,464,466,468,482,484,486,488,502,504,506,508: Gate dielectric layer

[0023] 130,140,272,274,276,278,374,376,378,401,402,403,404,405,406: drain / source contact layer

[0024] 602: N-type buried layer

[0025] 603: Deep P-type well region DETAILED DESCRIPTION

[0026] The present invention provides an anti-fuse memory including a fin field-effect transistor (FinFET transistor). Furthermore, since the anti-fuse transistor receives a higher operating voltage, the present invention designs an anti-fuse transistor that can operate in a high voltage environment.

[0027] Figures 1A to 1L It is a three-dimensional diagram of the manufacturing process of a fin field effect transistor (hereinafter referred to as FinFET transistor) and a cross-sectional diagram corresponding to the AB dotted line.

[0028] like Figure 1A and Figure 1B As shown, a P-type well region 103 (PW) and a deep N-type well region 102 (deep N-well, DNW) are formed on a semiconductor substrate 101 (sub). The P-type well region 103 (PW) is located on the surface of the semiconductor substrate 101 (sub), and the deep N-type well region 102 (DNW) is located below the P-type well region 103 (PW) and contacts the P-type well region 103 (PW). Furthermore, the semiconductor substrate 101 (sub) can be a P-type substrate (P-substrate).

[0029] like Figure 1C and Figure 1D As shown, an N-type pick up well region 104 (pick up N-well, NW PU ) surrounds the P-type well region 103 (PW). The N-type pickup well region 104 (NW PU ) bottom contacts the deep N-type well region 102 (DNW), the N-type pickup well region 104 (NW PU ) is exposed to the surface of the semiconductor substrate 101 (sub). That is, in the well structure of the present invention, the side surface of the P-type well region 103 (PW) contacts the N-type pickup well region 104 (NW PU ), the bottom of the P-type well region 103 (PW) contacts the deep N-type well region 102 (DNW). The sides and bottom of the P-type well region 103 (PW) are completely covered by the N-type pickup well region 104 (NW PU ) and an N-type region composed of a deep N-type well region 102 (DNW).

[0030] like Figure 1E and Figure 1F As shown, the N-type pickup well region 104 (NW PU) and the P-type well region 103 (PW), and a plurality of protruding structures are formed on the P-type well region 103 (PW), and the protruding structures protrude from the surface of the P-type well region 103 (PW).

[0031] Then, if Figure 1G and Figure 1H As shown, above the P-type well region 103 (PW), the N-type pickup well region 104 (NW PU ). Therefore, the insulating layer 110 covers the surface of the P-type well region 103 (PW) and the bottom of the protruding structure. The area of ​​the protruding structure not covered by the insulating layer 110 becomes the fins 112, 114, 116, 118. In other words, these fins 112, 114, 116, 118 extend from the semiconductor substrate 101 (sub), and the plurality of fins 112, 114, 116, 118 protrude from the surface of the insulating layer 110.

[0032] exist Figure 1G In the case of the above, the fins 112, 114, 116, 118 may be selectively doped so that the fins 112, 114, 116, 118 have various doping types. For example, the fins 112, 114, 116, 118 are all N-type doped regions. The fins 112, 114, 116, 118 are all P-type doped regions. Alternatively, the fins 112, 114, 116, 118 are all undoped regions.

[0033] like Fig. 1I and Figure 1J As shown, a gate structure is formed on the insulating layer 110, covering the middle region of the fins 112, 114, 116, 118, and exposing the two side regions of the fins 112, 114, 116, 118. The gate structure includes: a gate layer 120 and gate dielectric layers 122, 124, 126, 128. The gate dielectric layers 122, 124, 126, 128 cover the middle region above and the two side surfaces (lateral surfaces) of the fins 112, 114, 116, 118, respectively. In fact, the gate dielectric layers 122, 124, 126, 128 can contact each other. In addition, the gate layer 120 of the gate structure covers the gate dielectric layers 122, 124, 126, 128.

[0034] Of course, in Fig. 1IIn the case of the above, the fins 112, 114, 116, 118 may also be doped. The fins 112, 114, 116, 118 may have various doping types. For example, the first side region and the second side region of the fins 112, 114, 116, 118 are N-type doped regions. Alternatively, the first side region and the second side region of the fins 112, 114, 116, 118 are P-type doped regions.

[0035] like Figure 1K and Figure 1L As shown, a drain / source contact layer 130 is formed to electrically contact the first side region and two side surfaces of the fins 112, 114, 116, 118. A drain / source contact layer 140 is formed to electrically contact the second side region and two side surfaces of the fins 112, 114, 116, 118. The drain / source contact layer 130 can be made of a metal material and contact the first side region of the fins 112, 114, 116, 118. The drain / source contact layer 140 can be made of a metal material and contact the second side region of the fins 112, 114, 116, 118. Therefore, the two drain / source contact layers 130, 140, the gate structure and the fins 112, 114, 116, 118 constitute a FinFET transistor. Furthermore, the middle region of the fins 112, 114, 116, 118 can be regarded as the channel region of the FinFET transistor.

[0036] exist Figure 1L In the embodiment, the well region structure includes a P-type region and an N-type region. PU ) and the deep N-type well region 102 (DNW) form the N-type region in the well structure, and the P-type well region 103 (PW) forms the P-type region in the well structure. In other words, the side and bottom of the P-type region in the well structure are in contact with the N-type region of the well structure, and the side and bottom of the P-type region are covered by the N-type region. The FinFET transistor is designed above the P-type region. Furthermore, in the N-type pickup well region 104 (NW PU ) and the FinFET transistor, the top of the P-type region 103 (PW) is covered by the insulating layer 110.

[0037] Furthermore, since the FinFET transistor is fabricated on the P-type well region 103 (PW), the first side regions and the second side regions of the four fins 112 , 114 , 116 , 118 can be doped into N-doped regions, making the FinFET transistor an N-type transistor.

[0038] Of course, the present invention does not limit the FinFET transistor to be an N-type transistor or a P-type transistor. For example, the well structure includes a P-type region and an N-type region. The side and bottom of the N-type region in the well structure are in contact with the P-type region of the well structure, and the side and bottom of the N-type region are covered by the P-type region. The FinFET transistor is designed above the N-type region, and the first side region and the second side region of the fin can be doped as a P-doped region, making the FinFET transistor a P-type transistor.

[0039] In addition, Figure 1L The FinFET transistor in the embodiment is described by taking four fins 112, 114, 116, and 118 as an example. Of course, the present invention is not limited thereto, and N fins may also be designed in the FinFET transistor, where N is a positive integer.

[0040] The present invention designs a plurality of FinFET transistors on a semiconductor substrate 101 (sub) and combines them into a storage unit and an array structure of an antifuse-type memory.

[0041] Please refer to Figure 2 , which illustrates an anti-fuse memory according to a first embodiment of the present invention. Figure 2 As shown, the anti-fuse memory includes storage cells Cell1 and Cell2. Figure 1K The FinFET transistors of the memory cells Cell1 and Cell2 are designed above the P-type well region 203 (PW) in the semiconductor substrate 201 (sub) and are connected to the N-type pickup well region 204 (NW PU ) is surrounded by the P-type well region 203 (PW). Furthermore, the side surface of the P-type well region 203 (PW) contacts the N-type pickup well region 204 (NW PU ), the bottom of the P-type well region 203 (PW) contacts the deep N-type well region 202 (DNW). In other words, the N-type pickup well region 204 (NW PU ) and the deep N-type well region 202 (DNW) form an N-type region in the well region structure, and the P-type well region 203 (PW) is a P-type region in the well region structure, and the side and bottom of the P-type region are covered by the N-type region. PU ) and all FinFET transistors, the top of the P-type region 203 (PW) is covered by the insulating layer 200.

[0042] The anti-fuse memory includes two memory cells Cell1 and Cell2, forming a 2×1 array structure. The array structure is fabricated on a P-type well region 203 (PW) of a semiconductor substrate 201 (sub) and is surrounded by an N-type pickup well region 204 (NW PU) within the area surrounded by .

[0043] According to the first embodiment of the present invention, each storage cell Cell1, Cell2 is composed of three FinFET transistors, and the structure of each FinFET transistor is similar to Figure 1K The memory cell Cell1 includes a selection transistor M S1 , follower transistor M FL1 and the anti-fuse transistor M AF1 .

[0044] In the memory cell Cell1, the transistor M is selected. S1 The present invention comprises a drain / source contact layer 272, a drain / source contact layer 274, a gate structure and a plurality of fins 212, 214, 216, 218. The gate structure covers the middle region and two side surfaces of the fins 212, 214, 216, 218. The gate structure comprises a gate dielectric layer 222, 224, 226, 228 and a gate layer 220. The gate dielectric layers 222, 224, 226, 228 cover the middle region and two side surfaces of the fins 212, 214, 216, 218, respectively. The gate layer 220 covers the gate dielectric layers 222, 224, 226, 228. Furthermore, the drain / source contact layer 272 is electrically in contact with the first side region and two side surfaces of the fins 212, 214, 216, 218, and the drain / source contact layer 274 is electrically in contact with the second side region and two side surfaces of the fins 212, 214, 216, 218. In other words, the first ends of the fins 212, 214, 216, 218 are electrically connected to the drain / source contact layer 272, and the second ends of the fins 212, 214, 216, 218 are electrically connected to the drain / source contact layer 274. Furthermore, the drain / source contact layer 272 is connected to the bit line BL1. The gate layer 220 is connected to the word line WL1.

[0045] Follower transistor M FL1The present invention comprises a drain / source contact layer 274, a drain / source contact layer 276, a gate structure and a plurality of fins 232, 234, 236, 238. The gate structure covers the middle region and two side surfaces of the fins 232, 234, 236, 238. The gate structure comprises a gate dielectric layer 242, 244, 246, 248 and a gate layer 240. The gate dielectric layers 242, 244, 246, 248 cover the middle region and two side surfaces of the fins 232, 234, 236, 238, respectively. The gate layer 240 covers the gate dielectric layers 232, 234, 236, 238. Furthermore, the drain / source contact layer 274 is electrically in contact with the first side region and two side surfaces of the fins 232, 234, 236, 238, and the drain / source contact layer 276 is electrically in contact with the second side region and two side surfaces of the fins 232, 234, 236, 238. In other words, the first ends of the fins 232, 234, 236, 238 are electrically connected to the drain / source contact layer 274, and the second ends of the fins 232, 234, 236, 238 are electrically connected to the drain / source contact layer 276. Furthermore, the gate layer 240 is connected to the follower control line FL1, and the transistor M is selected. S1 With the follower transistor M FL1 The drain / source contact layer 274 is shared.

[0046] Anti-fuse transistor M AF1 The present invention comprises a drain / source contact layer 276, a drain / source contact layer 278, a gate structure and a plurality of fins 252, 254, 256, 258. The gate structure covers the middle region and two side surfaces of the fins 252, 254, 256, 258. The gate structure comprises a gate dielectric layer 262, 264, 266, 268 and a gate layer 260. The gate dielectric layers 262, 264, 266, 268 cover the middle region and two side surfaces of the fins 252, 254, 256, 258, respectively. The gate layer 260 covers the gate dielectric layers 262, 264, 266, 268. Furthermore, the drain / source contact layer 276 is electrically in contact with the first side region and two side surfaces of the fins 252, 254, 256, 258, and the drain / source contact layer 278 is electrically in contact with the second side region and two side surfaces of the fins 252, 254, 256, 258. That is, the first ends of the fins 252, 254, 256, 258 are electrically connected to the drain / source contact layer 276, and the second ends of the fins 252, 254, 256, 258 are electrically connected to the drain / source contact layer 278. Furthermore, the gate layer 260 is connected to the anti-fuse control line AF1. Follower transistor M FL1 With the anti-fuse transistor M AF1 The drain / source contact layer 276 is shared.

[0047] Furthermore, the memory cell Cell2 has the same structure as the memory cell Cell1, and the memory cell Cell2 is briefly described as follows. The memory cell Cell2 includes: a selection transistor M S2 , follower transistor M FL2 and the anti-fuse transistor M AF2 .

[0048] Select transistor M S2 The transistor M includes a drain / source contact layer 372, a drain / source contact layer 374, a gate structure and a plurality of fins 312, 314, 316, and 318. S2 The gate structure includes gate dielectric layers 322 , 324 , 326 , 328 and a gate layer 320 , and the gate layer 320 is connected to the word line WL2 .

[0049] Follower transistor M FL2 The transistor M includes a drain / source contact layer 374, a drain / source contact layer 376, a gate structure and a plurality of fins 332, 334, 336, and 338. FL2 The gate structure includes gate dielectric layers 342 , 344 , 346 , 348 and a gate layer 340 , and the gate layer 340 is connected to the following control line FL2 .

[0050] Anti-fuse transistor M AF2 The anti-fuse transistor M comprises a drain / source contact layer 376, a drain / source contact layer 378, a gate structure and a plurality of fins 352, 354, 356, and 358. AF2 The gate structure includes gate dielectric layers 362 , 364 , 366 , 368 and a gate layer 360 , and the gate layer 360 is connected to the anti-fuse control line AF2 .

[0051] In addition, in order to allow the array structure of the anti-fuse memory of the first embodiment to perform programming and reading operations normally, Figure 2 In the example, a dummy FinFET transistor can be added to the left side of the memory cell Cell1 and connected to the anti-fuse transistor M AF1 Similarly, another dummy FinFET transistor may be added to the right side of the memory cell Cell2, connected to the anti-fuse transistor M. AF2 and share the drain / source contact layer 378. Furthermore, the anti-fuse transistor M AF1 The connection relationship between the dummy FinFET transistor and the follower transistor M is similar. FL1 With the anti-fuse transistor M AF1 The connection relationship between them will not be repeated here.

[0052] Basically, during programming and reading operations, the three terminals of the two dummy FinFET transistors do not receive any bias, so the two dummy FinFET transistors are turned off and do not operate. Using the above connection method, in the anti-fuse type memory array structure, the left side of the memory cell Cell1 can be connected to another memory cell via a dummy FinFET transistor. Similarly, the right side of the memory cell Cell2 can be connected to other memory cells via a dummy FinFET transistor. In this way, the size of the array structure in the anti-fuse type memory of the first embodiment can be expanded.

[0053] In addition, Figure 2 In the case of an anti-fuse transistor M AF1 The first end of the middle fin 258 is electrically connected to the follower transistor M FL1 The second end of the fin 238 and the transistor M FL1 The first end of the fin 238 is electrically connected to the select transistor M S1 The second end of the middle fin 218. Similarly, the anti-fuse transistor M AF1 , follower transistor M FL1 With the selection transistor M S1 In the figure, other fins also have similar connection relationships, which will not be described here.

[0054] Of course, a longer fin can also be made on the semiconductor substrate and divided into three parts. The first part belongs to the selection transistor M S1 The second part of the fin 218 belongs to the follower transistor M FL1 The third portion of the fin 238 belongs to the anti-fuse transistor M AF1 Fin 258. That is, the transistor M is selected S1 Fin 218, following transistor M FL1 The fin 238 and the anti-fuse transistor M AF1 The fin 258 in the embodiment is integrally formed. AF1 , follower transistor M FL1 With the selection transistor M S1 In the embodiment, other fins may also be integrally formed.

[0055] Please refer to Figure 3A , which is a schematic diagram of bias voltage for programming an anti-fuse memory according to the first embodiment of the present invention. Figure 3B , which is a schematic diagram of bias voltage for reading the anti-fuse memory of the first embodiment of the present invention. In order to allow the anti-fuse memory of the present invention to receive a high voltage (e.g., programming voltage V PP ) and operates normally, the semiconductor substrate 201 (sub) receives a relatively large negative substrate voltage V SUB, for example, the substrate voltage V SUB The deep N-type well region 202 (DNW) and the N-type pickup well region 204 (NW PU ) receives the N-type well voltage V NW , for example, the N-type well voltage V NW The P-type well region 203 (PW) receives the P-type well region voltage V PW , for example, the P-type well voltage V PW is 0V.

[0056] like Figure 3A As shown, during the programming action, the anti-fuse control lines AF1 and AF2 receive the programming voltage V PP , following the control lines FL1 and FL2 to receive the conducting voltage (V FL ), the bit line BL1 receives the ground voltage (0V), and the word line WL1 receives the turn-on voltage V ON , word line WL2 receives the shutdown voltage V OFF For example, the programming voltage V PP Between 3V and 6V, the turn-on voltage V ON Between 0.4V and 3V, the on-state voltage V FL In addition, the bias voltage of the deep N-type well region 202 can be equal to the turn-on voltage V ON .

[0057] During programming, the selection transistor M of the memory cell Cell1 is S1 Turn on, follow transistor M FL1 In the conducting state, the ground voltage (0V) of the bit line BL1 is connected to the ground voltage (0V) of the bit line BL1 through the follower transistor M FL1 With the selection transistor M S1 Passed to the anti-fuse transistor M AF1 The drain / source contact layer 276. When the anti-fuse control line AF1 receives the programming voltage V PP When the anti-fuse transistor M AF1 The voltage stress between the fins 252, 254, 256, 258 and the gate layer 260 is the programming voltage V PP , causing one of the gate dielectric layers 262, 264, 266, 268 to rupture, such as the gate dielectric layer 268 to rupture, so that the anti-fuse transistor M AF1 The gate layer 260 and the fin 258 present a low resistance value. Therefore, the memory cell Cell1 generates a programming current I PGMThe anti-fuse control line AF1 flows through the gate layer 260, the rupture point 290 of the gate dielectric layer 268 to the fin 258, and then flows through the follower transistor M FL1 With the selection transistor M S1 That is, the memory cell Cell1 is programmed to a storage state with a low resistance value.

[0058] In addition, the selection transistor M of the memory cell Cell2 S2 Turn off, the anti-fuse transistor M AF2 The fins 352, 354, 356, 358 and the gate layer 360 are not subjected to voltage stress. Therefore, the gate dielectric layers 362, 364, 366, 368 are not ruptured, and the anti-fuse transistor M AF2 A high resistance value is presented between the gate layer 360 and the fins 352, 354, 356, 358. That is, the memory cell Cell2 does not generate a programming current, and the memory cell Cell2 maintains a storage state with a high resistance value.

[0059] like Figure 3B As shown, during the reading operation, the memory cell Cell1 can be judged. At this time, the anti-fuse control lines AF1 and AF2 receive the read voltage V RD , following the control lines FL1 and FL2 to receive the conducting voltage (V FL ), the bit line BL1 receives the ground voltage (0V), and the word line WL1 receives the turn-on voltage V ON , word line WL2 receives the shutdown voltage V OFF For example, reading the voltage V RD Between 0.5V and 2V.

[0060] During the reading operation, the selection transistor M of the memory cell Cell1 is S1 Turn on, follow transistor M FL1 Since the memory cell Cell1 is in a low resistance storage state, the memory cell Cell1 generates a large read current I RD The anti-fuse control line AF1 flows through the gate layer 260, the rupture point 290 of the gate dielectric layer 268 to the fin 258, and then flows through the follower transistor M FL1 With the selection transistor M S1 Flows to bit line BL1.

[0061] Similarly, during the reading operation, the memory cell Cell2 can also be determined. At this time, the word line WL1 receives the shutdown voltage V OFF, word line WL2 receives the turn-on voltage V ON , the bit line BL1 can output the read current of the memory cell Cell2. Since the memory cell Cell2 is in a storage state of a high resistance value, the read current generated by the memory cell Cell2 is very small, almost equal to 0.

[0062] That is, during the reading operation, the reading current I generated by the memory cell RD The memory cell can be determined to be in a high resistance storage state or a low resistance storage state. For example, a current comparator is provided and receives a reference current and a read current I RD When reading the current I RD When the reading current I RD When the current is smaller than the reference current, it can be determined that the memory cell (eg, memory cell Cell2 ) is in a storage state of a high resistance value.

[0063] Please refer to Figure 4 , which illustrates an anti-fuse memory according to a second embodiment of the present invention. Figure 4 As shown, the anti-fuse memory includes storage cells Cell0, Cell1, and Cell2. Figure 1K The FinFET transistors of the storage cells Cell0, Cell1, and Cell2 are all designed on the semiconductor substrate 511 (sub), located above the P-type well region 513 (PW), and are connected to the N-type pickup well region 514 (NW PU ), and the side surface of the P-type well region 513 (PW) contacts the N-type pickup well region 514 (NW PU ), the bottom of the P-type well region 513 (PW) contacts the deep N-type well region 512 (DNW). That is, the N-type pickup well region 514 (NW PU ) and the deep N-type well region 512 (DNW) form an N-type region in the well structure, and the P-type well region 513 (PW) is the P-type region in the well structure, and the side and bottom of the P-type region are covered by the N-type region. PU ) and all FinFET transistors, the top of the P-type region 513 (PW) is covered by the insulating layer 400.

[0064] like Figure 4 As shown, the anti-fuse memory includes three storage cells Cell0, Cell1, and Cell2, forming a 3×1 array structure. The array structure is manufactured above the P-type well region 513 (PW) of the semiconductor substrate 511 (sub) and is surrounded by the N-type pickup well region 514 (NW PU). The structures of Cell0, Cell1, and Cell2 are exactly the same. For the sake of simplicity, Figure 4 Only the complete memory cell Cell1 and partial memory cells Cell0 and Cell2 are shown.

[0065] like Figure 4 As shown, the memory cell Cell1 is composed of five FinFET transistors, and the structure of each FinFET transistor is similar to Figure 1K The memory cell Cell1 includes a selection transistor M S1 , select transistor M S2 , follower transistor M FL1 , follower transistor M FL2 and the anti-fuse transistor M AF1 .

[0066] In the memory cell Cell1, the transistor M is selected. S1 The present invention comprises: a drain / source contact layer 406, a drain / source contact layer 405, a gate structure and a plurality of fins 492, 494, 496, 498. The gate structure covers the middle region and two side surfaces of the fins 492, 494, 496, 498. The gate structure comprises: gate dielectric layers 502, 504, 506, 508 and a gate layer 500. The gate dielectric layers 502, 504, 506, 508 cover the middle region and two side surfaces of the fins 492, 494, 496, 498, respectively. The gate layer 500 covers the gate dielectric layers 502, 504, 506, 508. Furthermore, the drain / source contact layer 406 is electrically in contact with the first side region and two side surfaces of the fins 492, 494, 496, 498, and the drain / source contact layer 405 is electrically in contact with the second side region and two side surfaces of the fins 492, 494, 496, 498. In other words, the first ends of the fins 492, 494, 496, 498 are electrically connected to the drain / source contact layer 406, and the second ends of the fins 492, 494, 496, 498 are electrically connected to the drain / source contact layer 405. Furthermore, the drain / source contact layer 406 is connected to the bit line BL1. The gate layer 500 is connected to the word line WL1.

[0067] Select transistor M S2The present invention comprises: a drain / source contact layer 403, a drain / source contact layer 404, a gate structure and a plurality of fins 452, 454, 456, 458. The gate structure covers the middle region and two side surfaces of the fins 452, 454, 456, 458. The gate structure comprises: gate dielectric layers 462, 464, 466, 468 and a gate layer 460. The gate dielectric layers 462, 464, 466, 468 cover the middle region and two side surfaces of the fins 452, 454, 456, 458, respectively. The gate layer 460 covers the gate dielectric layers 462, 464, 466, 468. Furthermore, the drain / source contact layer 403 is electrically in contact with the first side region and two side surfaces of the fins 452, 454, 456, 458, and the drain / source contact layer 404 is electrically in contact with the second side region and two side surfaces of the fins 452, 454, 456, 458. In other words, the first ends of the fins 452, 454, 456, 458 are electrically connected to the drain / source contact layer 403, and the second ends of the fins 452, 454, 456, 458 are electrically connected to the drain / source contact layer 404. Furthermore, the drain / source contact layer 404 is connected to the bit line BL1. The gate layer 460 is connected to the word line WL1.

[0068] Follower transistor M FL1 The present invention comprises: a drain / source contact layer 405, a drain / source contact layer 401, a gate structure and a plurality of fins 472, 474, 476, 478. The gate structure covers the middle region and two side surfaces of the fins 472, 474, 476, 478. The gate structure comprises: gate dielectric layers 482, 484, 486, 488 and a gate layer 480. The gate dielectric layers 482, 484, 486, 488 cover the middle region and two side surfaces of the fins 472, 474, 476, 478, respectively. The gate layer 480 covers the gate dielectric layers 482, 484, 486, 488. Furthermore, the drain / source contact layer 405 is electrically in contact with the first side region and two side surfaces of the fins 472, 474, 476, 478, and the drain / source contact layer 401 is electrically in contact with the second side region and two side surfaces of the fins 472, 474, 476, 478. In other words, the first ends of the fins 472, 474, 476, 478 are electrically connected to the drain / source contact layer 405, and the second ends of the fins 472, 474, 476, 478 are electrically connected to the drain / source contact layer 401. Furthermore, the gate layer 480 is connected to the follower control line FL1.

[0069] Follower transistor M FL2The present invention comprises: a drain / source contact layer 402, a drain / source contact layer 403, a gate structure and a plurality of fins 432, 434, 436, 438. The gate structure covers the middle region and two side surfaces of the fins 432, 434, 436, 438. The gate structure comprises: gate dielectric layers 442, 444, 446, 448 and a gate layer 440. The gate dielectric layers 442, 444, 446, 448 cover the middle region and two side surfaces of the fins 432, 434, 436, 438, respectively. The gate layer 440 covers the gate dielectric layers 442, 444, 446, 448. Furthermore, the drain / source contact layer 402 is electrically in contact with the first side region and two side surfaces of the fins 432, 434, 436, 438, and the drain / source contact layer 403 is electrically in contact with the second side region and two side surfaces of the fins 432, 434, 436, 438. In other words, the first ends of the fins 432, 434, 436, 438 are electrically connected to the drain / source contact layer 402, and the second ends of the fins 432, 434, 436, 438 are electrically connected to the drain / source contact layer 403. Furthermore, the gate layer 440 is connected to the follower control line FL1.

[0070] Anti-fuse transistor M AF1 The present invention comprises: a drain / source contact layer 401, a drain / source contact layer 402, a gate structure and a plurality of fins 412, 414, 416, 418. The gate structure covers the middle region and two side surfaces of the fins 412, 414, 416, 418. The gate structure comprises: gate dielectric layers 422, 424, 426, 428 and a gate layer 420. The gate dielectric layers 422, 424, 426, 428 cover the middle region and two side surfaces of the fins 412, 414, 416, 418, respectively. The gate layer 420 covers the gate dielectric layers 422, 424, 426, 428. Furthermore, the drain / source contact layer 401 is electrically in contact with the first side region and two side surfaces of the fins 412, 414, 416, 418, and the drain / source contact layer 402 is electrically in contact with the second side region and two side surfaces of the fins 412, 414, 416, 418. In other words, the first ends of the fins 412, 414, 416, 418 are electrically connected to the drain / source contact layer 401, and the second ends of the fins 412, 414, 416, 418 are electrically connected to the drain / source contact layer 402. Furthermore, the gate layer 420 is connected to the anti-fuse control line AF1.

[0071] In addition, the structures of the memory cells Cell0 and Cell2 are identical to those of the memory cell Cell1, and are both composed of five FinFET transistors. S1 Connected to word line WL0, select transistor M in memory cell Cell2 S2Connected to word line WL2. Its detailed connection relationship is similar to that of memory cell Cell1, and will not be repeated here.

[0072] Please refer to Figure 5A , which is a schematic diagram of bias voltage for programming an anti-fuse memory according to a second embodiment of the present invention. Figure 5B , which is a schematic diagram of bias voltage for reading the anti-fuse memory of the second embodiment of the present invention. In order to allow the anti-fuse memory of the present invention to receive a high voltage (such as a programming voltage V PP ) and operates normally, the semiconductor substrate 511 (sub) receives a relatively large negative substrate voltage V SUB , for example, the substrate voltage V SUB The voltage range is between -12V and -16V. The deep N-type well region 512 (DNW) and the N-type pickup well region 514 (NW PU ) receives the N-type well voltage V NW , for example, the N-type well voltage V NW The P-type well region 513 (PW) receives the P-type well region voltage V PW , for example, the P-type well voltage V PW is 0V.

[0073] like Figure 5A As shown, during the programming action, the anti-fuse control line AF1 receives the programming voltage V PP , following the control line FL1 to receive the conducting voltage (V FL ), the bit line BL1 receives the ground voltage (0V), and the word line WL1 receives the turn-on voltage V ON For example, the programming voltage V PP Between 3V and 6V, the turn-on voltage V ON Between 0.4V and 3V, the on-state voltage V FL In addition, the bias voltage of the deep N-type well region 512 can be equal to the turn-on voltage V ON .

[0074] During programming, the selection transistor M of the memory cell Cell1 is S1 、M S2 Turn on, follow transistor M FL1 、M FL2 In the conducting state, the ground voltage (0V) of the bit line BL1 is connected to the ground voltage (0V) of the bit line BL1 through the follower transistor M FL1 、M FL2 With the selection transistor M S1 、M S2 Passed to the anti-fuse transistor M AF1When the anti-fuse control line AF1 receives the programming voltage V PP When the anti-fuse transistor M AF1 The voltage stress between the fins 412, 414, 416, 418 and the gate layer 420 is the programming voltage V PP , causing one of the gate dielectric layers 422, 424, 426, 428 to rupture, such as the gate dielectric layer 428 to rupture, so that the anti-fuse transistor M AF1 The gate layer 420 and the fin 418 present a low resistance value. Therefore, the memory cell Cell1 generates a programming current I PGM The anti-fuse control line AF1 flows through the gate layer 420, the rupture point 520 of the gate dielectric layer 418 to the fin 418, and then flows through the follower transistor M FL1 、M FL2 With the selection transistor M S1 、M S2 That is, the memory cell Cell1 is programmed to a storage state with a low resistance value.

[0075] On the contrary, during programming, if the word line WL1 receives the shutdown voltage V OFF (eg 0V), then the selection transistor M of the storage cell Cell1 S1 、M S2 When turned off, the memory cell Cell1 will not generate programming current, and the memory cell Cell1 will maintain a storage state with a high resistance value.

[0076] like Figure 5B As shown, during the reading operation, the memory cell Cell1 can be judged. At this time, the anti-fuse control line AF1 receives the reading voltage V RD , following the control line FL1 to receive the conducting voltage (V FL ), the bit line BL1 receives the ground voltage (0V), and the word line WL1 receives the turn-on voltage V ON For example, reading the voltage V RD Between 0.5V and 2V.

[0077] During the reading operation, the selection transistor M of the memory cell Cell1 is S1 、M S2 Turn on, follow transistor M FL1 、M FL2 Since the memory cell Cell1 is in a low resistance storage state, the memory cell Cell1 generates a large read current IRD The anti-fuse control line AF1 flows through the gate layer 420, the rupture point 520 of the gate dielectric layer 428 to the fin 418, and then flows through the follower transistor M FL1 、M FL2 With the selection transistor M S1 、M S2 Flows to the bit line BL1. Since the read current I RD is larger, it can be determined that the memory cell Cell1 is in a storage state with a high resistance value.

[0078] On the contrary, if the gate dielectric layers 422, 424, 426, 428 of the memory cell Cell1 are not broken, during the reading operation, the reading current of the memory cell Cell1 is very small, almost equal to 0, and the memory cell Cell1 can be determined to be in a storage state of a high resistance value.

[0079] As can be seen from the above description, the present invention proposes an anti-fuse memory, wherein the memory cell includes a fin field effect transistor (FinFET transistor). Furthermore, the FinFET transistor is used as an anti-fuse transistor in the memory cell. During programming, the gate oxide layer between the gate layer of the anti-fuse transistor and the fin is subjected to a programming voltage V PP The high voltage stress will cause the gate oxide layer of the anti-fuse transistor to break and complete the programming action. Furthermore, the present invention further designs the well region structure so that the anti-fuse memory can receive a high voltage (such as the programming voltage V PP ) and operate normally. In the above embodiment of the present invention, the memory cell is designed above the P-type well region (PW) of the semiconductor substrate (sub) and is connected to the N-type pickup well region (NW PU ). The side of the P-type well region (PW) contacts the N-type pickup well region (NW PU ), the bottom of the P-type well region (PW) contacts the deep N-type well region (DNW). The sides and bottom of the P-type well region (PW) are completely surrounded by the N-type pickup well region (NW PU ) and an N-type region consisting of a deep N-type well region (DNW).

[0080] Of course, the present invention is not limited to the above-mentioned well region structure. Those skilled in the art can also modify the well region structure appropriately. Figure 6 , which is another schematic diagram of the well region structure of the present invention. Figure 6 FinFET transistors are the same as Figure 1L The difference between the two FinFET transistors lies in the well structure. The following only introduces the well structure.

[0081] like Figure 6As shown, the well region structure is formed in a semiconductor substrate 601 (sub), and the semiconductor substrate 601 (sub) can be a P-substrate. The well region structure includes an N-type region and a P-type region. The side and bottom of the P-type region are in contact with the N-type region, and the side and bottom of the P-type region are covered by the N-type region. The FinFET transistor of the memory cell is designed above the surface of the P-type region surrounded by the N-type region. Furthermore, the N-type region includes an N-type buried layer 602 (N buried layer, NBL) and an N-type pickup well region 605 (NW PU The P-type region includes a P-type well region 604 (PW) and a deep P-type well region 603 (deep P-well, DPW).

[0082] like Figure 6 As shown, the bottom of the P-type well region 604 (PW) contacts the deep P-type well region 603 (DPW), and the P-type well region 604 (PW) and the deep P-type well region 603 (DPW) form a P-type region of the well region structure. PU ) surrounds the P-type well region 604 (PW) and the deep P-type well region 603 (DPW), and the N-type pickup well region 605 (NW PU ) contacts the side surfaces of the P-type well region 604 (PW) and the deep P-type well region 603 (DPW). In addition, the bottom of the deep P-type well region 603 (DPW) contacts the N-type buried layer 602 (NBL), and the N-type pickup well region 605 (NW PU ) bottom contacts the N-type buried layer 602 (NBL), the N-type pickup well region 605 (NW PU ) is exposed to the surface of the semiconductor substrate 601 (sub).

[0083] Furthermore, the memory cell Cell1 in the first embodiment of the present invention includes three FinFET transistors, and the memory cell Cell1 in the second embodiment includes five FinFET transistors. In fact, the present invention is not limited thereto, and a person skilled in the art may design the anti-fuse transistor in the memory cell Cell1 as a FinFET transistor, and design other transistors as other types of transistors. Taking the memory cell Cell1 in the first embodiment as an example, the transistor M is selected. S1 and the follower transistor M FL1 It is a general planar field effect transistor (planar FET), the anti-fuse transistor M AF1 is a FinFET transistor. That is, the transistor M is selected S1 The first drain / source terminal of the selection transistor M is connected to the bit line BL1. S1 The gate terminal of the follower transistor M is connected to the word line WL1. FL1The first drain / source terminal is connected to the selection transistor M S1 The second drain / source terminal of the following transistor M FL1 The gate terminal of the anti-fuse transistor M is connected to the follower control line FL1. AF1 The drain / source contact layer 276 is connected to the follower transistor M FL1 The second drain / source terminal of the anti-fuse transistor M AF1 The gate layer 260 is connected to the anti-fuse control line AF1.

[0084] From the above description, it can be seen that the present invention proposes an anti-fuse memory including a FinFET transistor. Furthermore, since the anti-fuse transistor receives a higher operating voltage, the well region structure of the semiconductor substrate of the present invention needs to be specially designed so that the substrate voltage received by the semiconductor substrate is a larger negative voltage value. In this way, the anti-fuse transistor can be operated in a high voltage environment.

[0085] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person skilled in the art of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the definition of the attached claims.

Claims

1. An anti-fuse memory, the anti-fuse memory having a first memory unit, the first memory unit being designed on a semiconductor substrate, and the first memory unit comprising: a first selection transistor, a first drain / source terminal of the first selection transistor being connected to the first bit line, and a gate terminal of the first selection transistor being connected to the first word line; A first follower transistor, a first drain / source terminal of the first follower transistor being connected to a second drain / source terminal of the first selection transistor, and a gate terminal of the first follower transistor being connected to a first follower control line; as well as A first anti-fuse transistor comprises: first fin; A first gate structure, comprising a first gate dielectric layer and a first gate layer; wherein the upper portion of the middle region and two side surfaces of the first fin are covered by the first gate dielectric layer, the first gate dielectric layer is covered by the first gate layer, and the first gate layer is connected to a first anti-fuse control line; A first drain / source contact layer electrically connected to the first end of the first fin, and the first drain / source contact layer is connected to the second drain / source end of the first follower transistor; and A second drain / source contact layer electrically connected to the second end of the first fin; During the programming action, the first bit line receives a ground voltage, the first word line receives a turn-on voltage, the first follower control line receives a conduction voltage, the first anti-fuse control line receives a programming voltage, and the first gate dielectric layer in the first anti-fuse transistor is broken so that the first storage unit is programmed to a storage state with a low resistance value.

2. The anti-fuse memory as claimed in claim 1, wherein the first selection transistor comprises: a third drain / source contact layer connected to the first bit line; a fourth drain / source contact layer; a second fin, a first end of the second fin being electrically connected to the third drain / source contact layer, and a second end of the second fin being electrically connected to the fourth drain / source contact layer; and The second gate structure includes a second gate dielectric layer and a second gate layer; wherein the middle area and two side surfaces of the second fin are covered by the second gate dielectric layer, the second gate dielectric layer is covered by the second gate layer, and the second gate layer is connected to the first word line.

3. The anti-fuse memory as claimed in claim 2, wherein the first follower transistor comprises: the fourth drain / source contact layer; the first drain / source contact layer; A third fin, a first end of the third fin being electrically connected to the fourth drain / source contact layer, and a second end of the third fin being electrically connected to the first drain / source contact layer; as well as The third gate structure includes a third gate dielectric layer and a third gate layer; wherein the upper middle region and two side surfaces of the third fin are covered by the third gate dielectric layer, the third gate dielectric layer is covered by the third gate layer, and the third gate layer is connected to the first follower control line.

4. The anti-fuse memory according to claim 3, further comprising a dummy Fin field effect transistor, wherein the dummy Fin field effect transistor comprises: the second drain / source contact layer; a fifth drain / source contact layer; a fourth fin, wherein a first end of the fourth fin is electrically connected to the second drain / source contact layer, and a second end of the fourth fin is electrically connected to the fifth drain / source contact layer; as well as The fourth gate structure includes a fourth gate dielectric layer and a fourth gate layer; wherein the upper portion of the middle region and two side surfaces of the fourth fin are covered by the fourth gate dielectric layer, and the fourth gate dielectric layer is covered by the fourth gate layer.

5. The anti-fuse memory as claimed in claim 3, wherein the first memory cell further comprises a second selection transistor and a second follower transistor; wherein, The second follower transistor comprises: the second drain / source contact layer; a fifth drain / source contact layer; a fourth fin, a first end of the fourth fin being electrically connected to the second drain / source contact layer, and a second end of the fourth fin being electrically connected to the fifth drain / source contact layer; and A fourth gate structure, comprising a fourth gate dielectric layer and a fourth gate layer; wherein the upper portion of the middle region and two side surfaces of the fourth fin are covered by the fourth gate dielectric layer, the fourth gate dielectric layer is covered by the fourth gate layer, and the fourth gate layer is connected to the first follower control line; Wherein, the second selection transistor comprises: the fifth drain / source contact layer; a sixth drain / source contact layer connected to the first bit line; a fifth fin, a first end of the fifth fin being electrically connected to the fifth drain / source contact layer, and a second end of the fifth fin being electrically connected to the sixth drain / source contact layer; and The fifth gate structure includes a fifth gate dielectric layer and a fifth gate layer; wherein the upper middle region and two side surfaces of the fifth fin are covered by the fifth gate dielectric layer, the fifth gate dielectric layer is covered by the fifth gate layer, and the fifth gate layer is connected to the first bit line.

6. The anti-fuse type memory as described in claim 1, wherein during the programming action, the first bit line receives the ground voltage, the first word line receives the off voltage, the first follower control line receives the on voltage, the first anti-fuse control line receives the programming voltage, and the first gate dielectric layer in the first anti-fuse transistor is not broken so that the first memory cell is programmed to a storage state with a high resistance value.

7. An anti-fuse type memory as described in claim 6, wherein during a reading action, the first bit line receives the ground voltage, the first word line receives the turn-on voltage, the first follower control line receives the conduction voltage, the first anti-fuse control line receives the read voltage, and the first storage unit generates a read current to the first bit line, and according to the size of the read current, it can be determined that the first storage unit is in the storage state of the high resistance value or the storage state of the low resistance value.

8. The anti-fuse memory as claimed in claim 7, wherein when the read current is less than a reference current, the first memory cell is in the storage state of the high resistance value; and when the read current is greater than the reference current, the first memory cell is in the storage state of the low resistance value.

9. The anti-fuse memory as claimed in claim 1, wherein the semiconductor substrate comprises a well region structure, the well region structure comprising: A first type region and a second type region; the side and bottom of the first type region are in contact with the second type region, the side and bottom of the first type region are covered by the second type region, and the first selection transistor, the first follower transistor and the first anti-fuse transistor are designed above the first type region.

10. The anti-fuse type memory as described in claim 9, wherein the first type region is a P type region, and the second type region is an N type region; and wherein the P type region is a P type well region, and the N type region includes a deep N type well region and an N type pick up well region; the N type pick up well region surrounds the P type well region, the upper portion of the N type pick up well region is exposed to the surface of the semiconductor substrate, and the bottom of the N type pick up well region contacts the deep N type well region; the side surface of the P type well region contacts the N type pick up well region, and the bottom of the P type well region contacts the deep N type well region.

11. The anti-fuse memory as claimed in claim 9, wherein the first type region is a P type region, and the second type region is an N type region; And, wherein the P-type region includes a P-type well region and a deep P-type well region, the N-type region includes an N-type buried layer and an N-type pickup well region; the bottom of the P-type well region contacts the deep P-type well region; The N-type pickup well region surrounds the P-type well region and the deep P-type well region, the upper portion of the N-type pickup well region is exposed to the surface of the semiconductor substrate, and the bottom of the N-type pickup well region contacts the N-type buried layer; The P-type well region and the side surfaces of the deep P-type well region are in contact with the N-type pickup well region, and the bottom of the deep P-type well region is in contact with the N-type buried layer. 12 . The anti-fuse memory as claimed in claim 1 , wherein the substrate voltage received by the semiconductor substrate is a negative voltage value.

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