Semiconductor device and method for forming EMI shielding material in two-step process using light sintering

Abstract

A semiconductor device has a substrate and an encapsulant deposited on the substrate. An electrical connector is disposed on the substrate external to the encapsulant. An antenna may be formed on a substrate. A first shielding material is disposed on a portion of the encapsulant without covering the electrical connector with the first shielding material. A first shielding material is disposed on the portion of the encapsulant and the portion of the substrate using a direct jet printer. A light source emitting ultraviolet light or intense pulsed light is directed at the first shielding material to initiate sintering. A cover is disposed over the electrical connector. A second shielding material is disposed on the encapsulant to prevent the second shielding material from reaching the electrical connector. The second shielding material overlaps the first shielding material and covers a side surface of the encapsulant and a side surface of the substrate.

Description

[0001] Domestic priority claim

[0002] This application is a continuation-in-part of U.S. patent application No. 17 / 812,339 filed on July 13, 2022, which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for forming electromagnetic interference (EMI) shielding materials in a two-step process using photosintering. Background Art

[0004] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0005] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communications, typically contain one or more integrated passive devices (IPDs) to perform the necessary electrical functions. Multiple semiconductor dies and IPDs can be integrated into a SiP module for higher density and expanded electrical functionality in a small space. Within a SIP module, the semiconductor dies and IPDs are disposed on a substrate for structural support and electrical interconnection. An encapsulant is deposited on the semiconductor dies, IPDs, and substrate. Electrical connectors are disposed on the substrate for electrical communication between electrical components and external devices. SIP modules are partially molded because the encapsulant does not extend to the electrical connectors. The electrical connectors are separate on the substrate.

[0006] SIP modules include high-speed digital and RF electrical components, are highly integrated for small size and low height, and operate at high clock frequencies. Electromagnetic shielding materials are usually conformally applied to the sealant. The electromagnetic shielding layer reduces or suppresses EMI, RFI, and other inter-device interference (such as interference radiated by high-speed digital devices) from affecting adjacent devices within or near the SIP module.

[0007] However, it is important that the electrical connector is kept free of parasitic shielding materials to avoid malfunctions. Selective EMI shielding with high precision is required, such as a cap or spraying. However, spraying can reduce productivity because the units per hour (UPH) are reduced. In the case of a sputtering method using a cap, in order to meet the minimum sputtering thickness with a shielding effect, a minimum gap between the shielding area and the cap is required, resulting in package design limitations.

[0008] In addition, for partially molded devices, conformal application of EMI shielding materials is difficult to control, especially with respect to independent electrical connectors. Conformal shielding materials can easily invade the space around the electrical connector and penetrate into the contacts of the connector, thereby causing electrical shorts or discontinuities when attempting to mate with the connector. Attempts have been made to mask or tape off the electrical connector while forming the shielding material. In some applications, masks and tapes are difficult to reliably isolate the electrical connector with tight component spacing and potentially may damage the electrical connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0010] Figure 2a-2d The process of forming a SiP module is illustrated;

[0011] Figure 3a-3d The process of forming an AoP module is illustrated;

[0012] Figure 4 The diagram shows a combination of an RF antenna substrate and a SIP module as a wafer;

[0013] Figure 5a-5h Illustration of applying shielding material to an AoP module using a two-step process;

[0014] Figure 6a-6c illustrates an alternative application of shielding material to an AoP module using a two-step process;

[0015] Figures 7a-7d illustrates an alternative application of shielding material to an AoP module using a two-step process;

[0016] Figures 8a-8d illustrates an alternative application of shielding material to an AoP module using a two-step process;

[0017] Fig. 9 The diagram shows Figure 4 Two-step shielding material on the AoP module;

[0018] Figures 10a-10k illustrates applying shielding material to an AoP module using a two-step process utilizing photosintering; and

[0019] Fig.11 A printed circuit board (PCB) is illustrated, with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0020] The present invention is described in one or more embodiments in the following description with reference to the drawings, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and accordingly may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0021] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of electrical current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit function.

[0022] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional areas of the wafer (called saw streets or scribes). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed on the semiconductor die are connected to the contact pads in the package. Electrical connection can be achieved with a conductive layer, a bump, a columnar bump, a conductive paste, or a wire bond. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0023] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0024] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuits may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0025] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 works as a contact pad electrically connected to the circuit on active surface 110.

[0026] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be compression bonded or thermocompressively bonded to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0027] exist Figure 1c 1 , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested to identify known good die or units (KGD / KGU) after singulation.

[0028] Figure 2a-2d The process of disposing electrical components and electrical connectors on an interconnect substrate is illustrated; Figure 2aA cross-sectional view of an interconnect substrate 120 including a conductive layer 122 and an insulating layer 124 is shown. The conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer may be formed using PVD, CVD, electrolytic plating, electroless plating processes or other suitable metal deposition processes. The conductive layer 122 provides horizontal electrical interconnections across the substrate 120 and vertical electrical interconnections between the top surface 126 and the bottom surface 128 of the substrate 120. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 122 may be electrically shared or electrically isolated. The insulating layer 124 may include one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO) and other materials having similar insulating and structural properties. The insulating layer may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. Insulating layer 124 provides isolation between conductive layers 122. There may be multiple conductive layers, such as 122, separated by insulating layer 124.

[0029] exist Figure 2b In FIG. 1 , a plurality of electrical components 130a-130d are disposed on the surface 126 of the interconnect substrate 120 and are electrically and mechanically connected to the conductive layer 122. A pick and place operation is used to position each of the electrical components 130a-130d on the substrate 120. For example, the electrical components 130a and 130c may be similar to those from FIG. Figure 1c 104, wherein the active surface 110 and the bumps 114 are oriented toward the surface 126 of the substrate 120. The electrical components 130b and 130d may be discrete electrical devices or IPDs, such as diodes, transistors, resistors, capacitors, and inductors, wherein the terminals 132 are disposed on the surface 126 of the interconnect substrate 120 and are electrically and mechanically connected to the conductive layer 122. Alternatively, the electrical components 130a-130d may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices, or IPDs.

[0030] The electrical components 130 a - 130 d are placed in contact with the surface 126 of the substrate 120 . Figure 2cThe electrical components 130a-130d are shown electrically and mechanically connected to the conductive layer 122 of the substrate 120. Electrical connectors 134 and 136 are disposed on the surface 126 of the interconnect substrate 120 and are electrically and mechanically connected to the conductive layer 122 using bumps or conductive paste 138. The electrical connector 134 is electrically connected to the electrical components 130a-130b through the conductive layer 122 of the substrate 120. The electrical connector 136 is electrically connected to the electrical components 130c-130d through the conductive layer 122 of the substrate 120. In one embodiment, the connectors 134 and 136 are board-to-board (B2B) connectors.

[0031] exist Figure 2d In the embodiment of the present invention, a sealant or molding compound 140 is deposited on and around the electrical components 130a-130b and the substrate 120 using slurry printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 140 is also deposited on and around the electrical components 130c-130d. The sealant 140 can be a polymer composite material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The sealant 140 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment.

[0032] Conductive bump material is deposited on conductive layer 122 on surface 128 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 144. In one embodiment, bump 144 is formed on a UBM having a wetting layer, a barrier layer and an adhesive layer. Bump 144 can also be compression bonded or thermocompressed to conductive layer 122. In one embodiment, bump 144 is a copper core bump for durability and maintaining its height. Bump 144 represents a type of interconnect structure that can be formed on conductive layer 122. The interconnect structure may also use bond wires, conductive paste, stud bumps, micro bumps, or other electrical interconnects.

[0033] like Figure 2d As shown in FIG. 1 , the combination of electrical components 130 a - 130 d disposed on substrate 120 and covered by encapsulant 140 constitutes a system-in-package (SiP) module 148 .

[0034] In another embodiment, if Figure 3aAs shown in, a cross-sectional view of an interconnect substrate 150 including a conductive layer 152 and an insulating layer 154 is shown. The conductive layer 152 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer may be formed using PVD, CVD, electrolytic plating, electroless plating processes or other suitable metal deposition processes. The conductive layer 152 provides horizontal electrical interconnections across the substrate 150 and vertical electrical interconnections between the top surface 156 and the bottom surface 158 of the substrate 150. Depending on the design and function of the semiconductor die 104 and other electrical components, portions of the conductive layer 152 may be electrically shared or electrically isolated. The insulating layer 154 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO and other materials having similar insulating and structural properties. The insulating layer 154 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer 154 provides isolation between conductive layers 152. There may be multiple conductive layers, such as 152, separated by insulating layer 154.

[0035] Conductive layer 160 is formed on surface 158 of substrate 150 and is electrically connected to conductive layer 152. Conductive layer 160 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials.

[0036] Figure 3b 1 is a top view of a conductive layer 160 on a surface 158 of an RF antenna interposer substrate 168. The conductive layer 160 includes an array of islands of conductive material suitable for providing transmission and reception of RF signals, i.e., an RF antenna. The conductive layer 160 operates as a plurality of RF antennas 166a and 166b exposed from the surface 158 of the RF antenna substrate 168. Specifically, an array of islands 162a, 162b of the conductive layer 160 is exposed from the surface 158 to improve RF transmission and reception performance and quality. In one embodiment, a first group of islands 162a of the conductive layer 160 is used as a first antenna 166a electrically connected through the conductive layer 152 to provide RF transmission and reception for a first electrical component. A second group of islands 162b of the conductive layer 160 is used as a second antenna 166b electrically connected through the conductive layer 152 to provide RF transmission and reception for a second electrical component. Although for the purpose of simplifying the description, the conductive layer 160 is described in detail below. Figure 3a-3b Two RF antennas 166a-166b are shown in FIG. 1 , but the RF antenna substrate 168 may have any number of RF antennas, such as 166a-166b.

[0037] exist Figure 3cIn FIG. 1 , a plurality of electrical components 130a-130d are disposed on the surface 156 of the RF antenna substrate 168 and are mechanically connected to the conductive layer 152. Figure 2b-2c , each of the electrical components 130a-130d is positioned on the substrate 120 using a pick and place operation. In the various figures, elements having similar functions are given the same reference numerals. Electrical connectors 134 and 136 are disposed on the surface 156 of the RF antenna substrate 168 and are electrically and mechanically connected to the conductive layer 152 using bumps or conductive paste 138. The electrical connector 134 is electrically connected to the electrical components 130a-130b through the conductive layer 152. The electrical connector 136 is electrically connected to the electrical components 130c-130d through the conductive layer 152.

[0038] exist Figure 3d In the embodiment of the present invention, a sealant or molding compound 170 is deposited on and around the electrical components 130a-130b on the interposer 168 using slurry printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. The sealant 170 is also deposited on and around the electrical components 130c-130d. The sealant 170 can be a polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 170 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0039] like Figure 3d As shown in FIG. 1 , the combination of electrical components 130a-130d disposed on an RF antenna substrate 168 and covered by an encapsulant 170 constitutes an RF antenna SiP wafer 174. In one embodiment, the RF antenna SiP wafer 174 includes millimeter wave devices suitable for 5G cellular networks.

[0040] Figure 4 Another embodiment is shown, in which Figure 2d The SiP module 148 is disposed on the RF antenna substrate 168, collectively referred to as an antenna-on-package (AoP) die 172. The electrical components 130a-130d are electrically connected to the RF antennas 166a-166b and the electrical connectors 134 and 136 through the interconnect substrate 120 and the bumps 144, respectively.

[0041] like Figure 5a As shown in FIG. 1 , a saw blade or laser cutting tool 175 is used to cut the Figure 3d The RF antenna SiP wafer 174 is singulated into individual RF AoP modules 176a and 176b. Figure 4The AoP wafer 172 can be singulated into individual RF AoP modules in a similar manner. Although the same description applies to RF AoP module 176b and the RF AoP modules from AoP wafer 172, the following discussion addresses RF AoP module 176a. As noted below, RF AoP module 176a includes electrical connector 134 as a B2B connector, which provides electrical connection to electrical components 130a-130b, RF antenna substrate 168 and other PCBs through the connector, possibly including other electrical components.

[0042] The electrical components 130a-130b may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components 130a-130b provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 130a-130b include digital circuits that switch at high frequencies, which may interfere with the operation of the IPDs in the RF AOP module 176a.

[0043] To address EMI, RFI, harmonic distortion and inter-device interference, the RF antenna SiP module 176a will be conformally covered with shielding material. However, the electrical connector 134 must remain free of shielding material and will need to be covered to protect the connector and avoid introducing shielding material into the contacts of the connector.

[0044] In a first step, electromagnetic shielding material 180 is applied to a portion of encapsulant 170 and a portion of surface 156 of substrate 150, such as Figure 5b . The electromagnetic shielding material 180 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 180 may be carbonyl iron, stainless steel, nickel silver, mild steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electrical connector 134 is mechanically and electrically connected to the conductive layer 152 of the substrate 150 using bumps or conductive paste 138. The electromagnetic shielding material 180 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 181, with sufficient control to avoid having the shielding material on the electrical connector 134. The shielding material 180 provides partial coverage of the RF AoP module 176a without encroaching on the area occupied by the electrical connector 134. In one embodiment, the applied shielding material 180 is kept separated from the electrical connector 134 by a distance D1 of at least 50 microns (μm).

[0045] exist Figure 5c In the embodiment shown in FIG. 1 , the cover mask 184 is located above the electrical connector 134. The cover mask 184 is placed in contact with the shielding material 180. Figure 5d A cover mask 184 is shown covering or surrounding the electrical connector 134 , with the vertical portion 184 a contacting the lower surface 180 a of the shielding material 180 . Figure 5e is a perspective view of a cover mask 184 that surrounds the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding material from reaching the connector.

[0046] In the second step, if Figure 5f As shown in , an electromagnetic shielding layer 186 is formed or provided on a surface 188 of the sealant 170 by conformal application of a shielding material. The electromagnetic shielding material 186 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 186 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI and other inter-device interference. The electromagnetic shielding material 186 overlaps a first portion of the electromagnetic shielding material 180, while a second portion of the shielding material 180 remains below the cover 184. In addition, the electromagnetic shielding material 186 covers the side surface 190 of the sealant 170 and the side surface 192 of the substrate 150. At least to some extent, the electromagnetic shielding material 186 covers the cover mask 184 that protects the electrical connector 134. During this second step, the electrical connector 134 remains free of shielding material.

[0047] exist Figure 5g , the cover mask 184 is removed, leaving the shielding materials 180 and 186 covering the RF sensitive portions of the RF AoP module 176a. The electrical connector 134 remains free of the shielding materials 180 and 186. Figure 5h RF AoP module 176a is shown with shielding materials 180 and 186 covering the RF sensitive portions of the RF AoP module and no shielding material on electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or devices that are not compatible with EMI shielding using a cover shielding approach.

[0048] In another embodiment, from Figure 5b Continue, as Figure 6a As shown in FIG. 1 , the cover mask 184 is disposed on the electrical connector 134. The cover mask 184 covers or surrounds the electrical connector 134, wherein the vertical portion 184a contacts the upper surface 180b of the shielding material 180. Figure 5e, the cover mask 184 covers or surrounds the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding materials from reaching the connector.

[0049] In the second step of substitution, Figure 6b As shown in , an electromagnetic shielding layer 190 is formed or disposed on a surface 193 of the sealant 170 by conformally applying a shielding material. The electromagnetic shielding material 190 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 190 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, silicon iron steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI and other inter-device interference. The electromagnetic shielding material 190 overlaps a first portion of the electromagnetic shielding material 180, while a second portion of the shielding material 180 remains below the cover 184. In addition, the electromagnetic shielding material 190 covers the side surface 194 of the sealant 170 and the side surface 196 of the substrate 150. At least to some extent, the electromagnetic shielding material 190 covers the cover mask 184 that protects the electrical connector 134. During this alternative second step, the electrical connector 134 remains free of shielding material.

[0050] exist Figure 6c , the cover mask 184 is removed, leaving the shielding materials 180 and 190 covering the RF sensitive portions of the RF AoP module 176a. The electrical connector 134 remains free of the shielding materials 180 and 190. The RF AoP module 176a having the shielding materials 180 and 190 covering the RF sensitive portions of the RF AoP module has no shielding material on the electrical connector 134, similar to Figure 5h The two-step shielding process described above is suitable for devices with strict design rules or devices that are not compatible with EMI shielding using the overlay shielding method.

[0051] In another embodiment, from Figure 5a Continue, as Figure 7a As shown in FIG. 1 , a cover mask 184 is disposed on the electrical connector 134. The cover mask 184 covers or surrounds the electrical connector 134, wherein the vertical portion 184a contacts the surface 156 of the substrate 150. Figure 5e , the cover mask 184 covers or surrounds the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding materials from reaching the connector.

[0052] In the first step, if Figure 7bAs shown in , an electromagnetic shielding layer 200 is formed or disposed on a surface 202 of the sealant 170 by conformally applying a shielding material. The electromagnetic shielding material 200 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 200 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 200 covers the side surface 204 of the sealant 170 and the side surface 206 of the substrate 150. At least to some extent, the electromagnetic shielding material 200 covers the cover mask 184 that protects the electrical connector 134. During this first step, the electrical connector 134 remains free of shielding material.

[0053] exist Figure 7c , the cover mask 184 is removed, leaving the shielding material 200 covering the RF sensitive portions of the RF AoP module 176a.

[0054] In a second step, electromagnetic shielding material 210 is applied to a portion of electromagnetic shielding material 200 and a portion of surface 156 of substrate 150, such as Figure 7d . The electromagnetic shielding material 210 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 210 may be carbonyl iron, stainless steel, nickel silver, mild steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 210 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 212, with sufficient control to avoid having the shielding material on the electrical connector 134. The shielding material 210 provides partial coverage of the RF AoP module 176a without encroaching on the area occupied by the electrical connector 134. The electrical connector 134 remains free of shielding materials 200 and 210. The RFAoP module 176a having shielding materials 200 and 210 covering the RF sensitive portions of the RF AoP module does not have shielding material on the electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or devices that are not compatible with EMI shielding using the cover shielding method.

[0055] In another embodiment, from Figure 5a Continue, as Figure 8aAs shown in FIG. 1 , a cover mask 184 is disposed on the electrical connector 134. The cover mask 184 covers or surrounds the electrical connector 134, wherein the vertical portion 184a contacts the surface 214 of the sealant 170. The cover mask 184 covers or surrounds the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding materials from reaching the connector.

[0056] In the first step, if Figure 8b As shown in , an electromagnetic shielding layer 220 is formed or disposed on the surface 214 of the sealant 170 by conformally applying a shielding material. The electromagnetic shielding material 220 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 220 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 220 covers the side surface 224 of the sealant 170 and the side surface 226 of the substrate 150. At least to some extent, the electromagnetic shielding material 220 covers the cover mask 184 that protects the electrical connector 134. During this first step, the electrical connector 134 remains free of shielding material.

[0057] exist Figure 8c , the cover mask 184 is removed, leaving the shielding material 220 covering the RF sensitive portions of the RF AoP module 176a.

[0058] In a second step, electromagnetic shielding material 230 is applied to a portion of electromagnetic shielding material 220 and a portion of surface 156 of substrate 150, such as Figure 8d . The electromagnetic shielding material 230 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 230 may be carbonyl iron, stainless steel, nickel silver, mild steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 230 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 232, with sufficient control to avoid having the shielding material on the electrical connector 134. The shielding material 230 provides partial coverage of the RF AoP module 176a without encroaching on the area occupied by the electrical connector 134. The electrical connector 134 remains free of shielding materials 220 and 230. The RFAoP module 176a having shielding materials 220 and 230 covering the RF sensitive portions of the RF AoP module does not have shielding material on the electrical connector 134. The two-step shielding process described above is suitable for devices with strict design rules or devices that are not compatible with EMI shielding using a cover shielding method.

[0059] The two-step masking process is suitable for Figure 2a-2d and Figure 4 semiconductor packaging. For example, Fig. 9 Shown from Figure 4 A singulated RF AoP module having a first step of shielding material 180 and a second step of shielding material 186. Again, the electrical connector 134 remains free of shielding materials 180 and 186.

[0060] In another embodiment, if Fig.10a As shown in , a thin layer 240 of powder material in the form of nanoparticles is applied directly to a portion of the sealant 170 and a portion of the surface 156 of the substrate 150 as a paste or ink. In the various figures, elements having similar functions are given the same reference numerals. The powder material 240 can be Ag, Cu, graphene-coated silver, graphene-coated copper, or a combination thereof having electromagnetic shielding properties. The powder material 240 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 242, with sufficient control to avoid getting the powder material on the electrical connector 134.

[0061] Alternatively, electromagnetic shielding material 244 is applied to a portion of encapsulant 170 and a portion of surface 156 of substrate 150, such as Fig.10b . The electromagnetic shielding material 244 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The electromagnetic shielding material 244 may also be carbonyl iron, stainless steel, nickel silver, mild steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electrical connector 134 is mechanically and electrically connected to the conductive layer 152 of the substrate 150 with a bump or conductive paste 138. The electromagnetic shielding material 244 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 246, with sufficient control to avoid having the shielding material on the electrical connector 134. The shielding material 244 provides partial coverage of the RF AoP module 176a without encroaching on the area occupied by the electrical connector 134. In one embodiment, the applied shielding material 244 is maintained at a distance D2 of at least 50.0 microns (μm) separated from the electrical connector 134.

[0062] exist Fig.10c In the embodiment of the present invention, a thin layer of powder material 248 is applied as a paste or ink to the electromagnetic shielding material 244. The powder material 248 is applied in a maskless manner, such as by direct jet printing using a direct jet printer 242, with sufficient control to avoid getting the powder material on the electrical connector 134.

[0063] exist Fig.10dIn the embodiment, the light source 250 is directed from Fig.10a Powder material 240 or from Fig.10c Ultraviolet light (UV) or intense pulsed light (IPL) is emitted on the powder material 248 to achieve the sintering process. When the powder material 240 or 248 is agglomerated or absorbed into the shielding material 254 by sintering, the UV or IPL causes local heating. The distance D3 from the light source 250 to the powder material 240 or the powder material 248 is about 14.0 mm. With a wavelength of 100-400 nanometers (nm) in the case of UV and a wavelength of 400-1200 nm in the case of IPL, the duration of the light source 250 is about 5.0 seconds to achieve the sintering process. The sintered electromagnetic shielding material 254 provides greater strength, durability, conductivity and adhesion.

[0064] exist Fig.10e In the embodiment of the present invention, the cover mask 256 is located above the electrical connector 134. The cover mask 256 is placed in contact with the post-sintering shielding material 254. In particular, the surface 258 of the cover mask 256 is placed in contact with the surface 260 of the post-sintering shielding material 254. Fig.10f A cover mask 256 is shown covering or surrounding the electrical connector 134 , with a surface 258 contacting a surface 260 of the post-sintering shield material 254 . Figure 10g is a perspective view of a cover mask 256 that surrounds the electrical connector 134 on all sides in a manner that prevents subsequently applied shielding material from reaching the connector.

[0065] In the second step, if Fig.10h As shown in , an electromagnetic shielding layer 262 is formed or disposed on a surface 264 of the sealant 170 by conformally applying a shielding material. The electromagnetic shielding material 262 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the electromagnetic shielding material 262 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI, and other inter-device interference. The electromagnetic shielding material 262 overlaps a first portion of the electromagnetic shielding material 254 after sintering, while a second portion of the shielding material 254 after sintering remains under the cover mask 256. In addition, the electromagnetic shielding material 262 covers the side surface 268 of the sealant 170 and the side surface 270 of the substrate 150. At least to some extent, the electromagnetic shielding material 262 covers the cover mask 256 that protects the electrical connector 134. Fig.10h Electromagnetic shielding material 262 is shown partially covering cover mask 256 . Fig.10i The electromagnetic shielding material 262 is shown completely covering the cover mask 256. During this second step, the electrical connector 134 remains free of shielding material.

[0066] exist Fig.10j , the cover mask 256 is removed, leaving the post-sintering shielding materials 254 and 262 covering the RF sensitive portions of the RF AoP module 176a. The electrical conductors 134 remain free of the shielding materials 254 and 262. Figure 10k An RF AoP module 280 is shown where post-sintering shielding materials 254 and 262 cover the RF sensitive portions of the RF AoP module, and there is no shielding material on the electrical connector 134. The two-step shielding process with photo-sintering described above is suitable for devices with strict design rules or devices that are not compatible with EMI shielding using a cover shielding approach.

[0067] Fig.11 An electronic device 300 is illustrated having a chip carrier substrate or PCB 302 with a plurality of semiconductor packages disposed on a surface of the PCB 302, including SiP module 148, RF AoP modules 176a-176b and 280, and AoP modules from AoP wafer 172, all including shielding materials 180, 186, 190, 200, 210, 220, 240, 244, 248, 254, 262, and 280 in the two-step process of the present invention. Depending on the application, the electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages.

[0068] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical component. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0069] exist Fig.11 , PCB 302 provides a common substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed on the surface or within a layer of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each semiconductor package, mounted components, and other external system components. Traces 304 also provide power and ground connections to each semiconductor package.

[0070] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first level packaging, wherein the die is mechanically and electrically disposed directly on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 302, including wire bonding packaging 306 and flip chip 308. In addition, several types of second level packaging including ball grid array (BGA) 310, bump chip carrier (BCC) 312, land grid array (LGA) 316, multi-chip module (MCM) or SIP module 318, quad flat no-lead package (QFN) 320, quad flat package 322, embedded wafer level ball grid array (eWLB) 324 and wafer level chip scale package (WLCSP) 326 are shown disposed on PCB 302. In one embodiment, eWLB 324 is a fan-out wafer level package (Fo-WLP) and WLCSP 326 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electronic components can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost for the consumer.

[0071] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate; depositing a sealant on the first surface of the substrate; disposing an electrical connector on the first surface of the substrate outside the encapsulant; disposing a first shielding material on a portion of the sealant without covering the electrical connector with the first shielding material; directing a light source toward the first shielding material to induce sintering; providing a cover on the electrical connector; and A second shielding material is disposed on the encapsulant, wherein the cover prevents the second shielding material from reaching the electrical connector. The method of claim 1 , further comprising providing electrical components on the substrate. 3 . The method of claim 1 , further comprising forming an antenna on a second surface of the substrate opposite to the first surface of the substrate. 4 . The method of claim 1 , wherein the first shielding material covers the portion of the encapsulant and a portion of the substrate while remaining separated from the electrical connector. 5 . The method of claim 1 , further comprising disposing a material on the first shielding material before directing the light source toward the first shielding material.

6. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing an electrical connector on the first surface of the substrate; disposing a first shielding material on a portion of the substrate a distance from the electrical connector; directing a light source toward the first shielding material to induce sintering; providing a cover on the electrical connector; and A second shielding material is disposed on the substrate, wherein the cover prevents the second shielding material from reaching the electrical connector.

7. The method according to claim 6, further comprising: disposing electrical components on the substrate; and An encapsulant is deposited over the electrical component and the substrate. 8 . The method of claim 6 , further comprising forming an antenna on a second surface of the substrate opposite to the first surface of the substrate.

9. The method of claim 6, wherein the first shielding material covers the portion of the substrate without covering the electrical connector with the first shielding material, and the second shielding material overlaps the first shielding material.

10. The method of claim 6, further comprising disposing a material on the first shielding material before directing the light source toward the first shielding material.

11. A semiconductor device comprising: substrate; an electrical connector disposed on the substrate; a first shielding material disposed on a portion of the substrate at a distance from the electrical connector; a light source directed toward the first shielding material to induce sintering; a cover disposed on the electrical connector; and A second shielding material is disposed on the substrate, wherein the cover prevents the second shielding material from reaching the electrical connector.

12. The semiconductor device according to claim 11, further comprising: an electrical component disposed on a substrate; and An encapsulant is deposited on the electrical components and the substrate.

13. The semiconductor device according to claim 11, further comprising an antenna formed on the substrate. The semiconductor device according to claim 11 , wherein the second shielding material overlaps the first shielding material. 15 . The semiconductor device of claim 11 , wherein the first shielding material covers the portion of the substrate without covering the electrical connector with the first shielding material.

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