Package and method of forming same

Abstract

The method includes forming a dummy component, including: forming a through substrate via (TSV) in a substrate; forming a thermal structure over the TSV, where the thermal structure includes a metal line in the dielectric layer; forming a bonding layer over the thermal structure; and forming a bonding pad within the bonding layer; bonding the dummy component to the package component; and bonding the semiconductor die to the package assembly. The embodiment of the invention also relates to a package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of forming the same. Background Art

[0002] As integrated circuits become more and more integrated, more and more devices are compressed into smaller areas. At the same time, in order to improve the speed of integrated circuits, the driving current of integrated circuits has also become higher. Therefore, the heat dissipation of integrated circuits has become more demanding. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a package, comprising: forming a dummy component, comprising: forming a plurality of through substrate vias (TSVs) in a substrate; forming a thermal structure above the plurality of substrate through vias, wherein the thermal structure comprises a plurality of metal wires in a plurality of dielectric layers; forming a bonding layer above the thermal structure; and forming a plurality of bonding pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

[0004] Other embodiments of the present application provide a method for forming a package, comprising: forming a first bonding layer on a first packaging component; forming a plurality of first bonding pads in the first bonding layer; forming a plurality of second bonding pads in the first bonding layer; bonding a thermal component to the first bonding layer and to the plurality of first bonding pads, wherein the thermal component comprises: a through substrate via (TSV) extending into a substrate; a second bonding layer located above the substrate and the substrate through via; and a plurality of third bonding pads located in the second bonding layer; and bonding an active packaging component to the first bonding layer and to the plurality of second bonding pads, wherein the active packaging component comprises: an active device; a third bonding layer located above the active device; and a plurality of fourth bonding pads located in the third bonding layer.

[0005] Still other embodiments of the present application provide a package, comprising: a dummy die bonded to a package component, wherein the dummy die comprises: a substrate; a first metal component extending into the substrate; a second metal component located above the first metal component and separated from the first metal component by a first dielectric layer; a second dielectric layer located above the second metal component; and a bonding pad located within the second dielectric layer; and a semiconductor die bonded to the package component adjacent to the dummy die. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of a package assembly according to some embodiments is shown.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 Cross-sectional views are shown of intermediate steps in the formation of a package in accordance with some embodiments.

[0009] Figure 7 , Figure 8 , Fig. 9 and Fig.10 Cross-sectional views are shown of intermediate steps in the formation of a thermal assembly according to some embodiments.

[0010] Fig.11A , Fig. 11B , Fig. 11C , Fig.11D and Fig.11E Various thermal components are shown according to some embodiments.

[0011] Fig. 12A , Fig. 12B , Fig. 12C , Fig.12D , Fig.12E , Fig.12F , Figure 12G and Fig.12H Various cross-sectional shapes of through substrate vias according to some embodiments are shown.

[0012] Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 Cross-sectional views are shown of intermediate steps in the formation of a package in accordance with some embodiments.

[0013] Fig.19 , Fig. 20 , Fig.21 and Fig. 22 Cross-sectional views are shown of intermediate steps in the formation of a package in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] A heat dissipation package assembly and a method for forming the same are provided. According to some embodiments of the present disclosure, a thermally conductive through substrate via (TSV) is formed to extend into a semiconductor substrate of a dummy component within a package. The TSV provides improved heat dissipation. The dummy component may also include thermally conductive components, such as metal lines, metal vias, etc., which may provide additional improvements in heat dissipation. Depending on the design of the package, the thermally conductive TSV and / or thermally conductive components may be configured to provide effective heat dissipation.

[0017] The embodiments discussed herein are intended to provide examples of the subject matter of the disclosed embodiments that can be manufactured or used, and those of ordinary skill in the art will readily appreciate the modifications that can be made while remaining within the contemplation of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order.

[0018] Figures 1 to 6 A package 200 (see FIG. Fig.18 ) is a cross-sectional view of an intermediate step in the formation of. Figure 1In the embodiment of the present invention, the first package component 40 is formed or provided in a wafer (not shown separately), for example. According to some embodiments, the first package component 40 is an independent device die (e.g., an integrated circuit die), a package in which one or more device dies are packaged, a system-on-chip (SoC) die including multiple integrated circuits integrated into a system, etc. The device die of the first package component 40 may be or may include a logic die, a memory die, an input-output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die of the first package component 40 may be a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die of the first package component 40 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The device die of the first package component 40 may include a semiconductor substrate and an interconnect structure.

[0019] According to some embodiments, the first package component 40 may include a substrate 42. The substrate 42 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 42 may be a wafer, such as a silicon wafer. Other substrates, such as a silicon on insulator (SOI) substrate, a multilayer substrate, or a gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate 42 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or a combination thereof. In some embodiments, a plurality of first package components 40 may be formed on the same substrate 42 and then separated into independent first package components 40 using a segmentation process (e.g., a sawing process, a cutting process, etc.).

[0020] Furthermore, in some embodiments, integrated circuit devices (not separately shown) may be formed at the front side surface of substrate 42. The integrated circuit devices may include active devices (e.g., NMOS and PMOS transistors, diodes, etc.), passive devices (e.g., resistors, capacitors, etc.), etc. Furthermore, through substrate vias (TSVs) 46 may be formed that extend partially through substrate 42.

[0021] In some embodiments, an interconnect structure 49 is formed over the front side of the substrate 42. The interconnect structure 49 includes a conductive component 48 (e.g., a metal line, a metal via, a metal pad, etc.) formed in one or more dielectric layers 44. The conductive component 48 of the interconnect structure 49 can be electrically connected to the integrated circuit device and / or the TSV 46. As shown, the interconnect structure 49 may include a multilayer conductive component 48 formed in a plurality of dielectric layers 44. The conductive component 48 may be formed using a damascene process, a dual damascene process, or another suitable technique. The conductive component 48 may include, for example, copper, aluminum, tungsten ruthenium, cobalt, their alloys, their combinations, etc. The dielectric layer 44 may be formed of a dielectric material or include a dielectric material, such as a polymer, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc., their combinations and / or their multilayers. Other materials are also possible. In some instances, the dielectric layer 44 may be an intermetallic dielectric (IMD) layer. Figure 1 The interconnect structure 49 shown in FIG. 4 is an example, and the interconnect structure 49 may include another number of layers or may have a different configuration than shown. In some embodiments, the interconnect structure 49 may include a seal ring (not shown).

[0022] According to some embodiments, a passivation layer 54 may be formed over interconnect structure 49. In some embodiments, passivation layer 54 may be formed of a non-low-k dielectric material having a dielectric constant equal to or greater than that of silicon oxide. Passivation layer 54 may be formed of or include an inorganic dielectric material, which may include a material selected from, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like, combinations thereof, and / or multilayers thereof. Other materials are also possible.

[0023] According to some embodiments, metal pads 50 may be formed on passivation layer 54. Metal pads 50 are formed on passivation layer 54 and may have portions of conductive features 48 extending through passivation layer 54 to physically and electrically contact interconnect structure 49. Metal pads 50 may help facilitate external electrical connections to the integrated circuits of first package assembly 40 during functional use and / or facilitate external electrical connections during, for example, wafer acceptance testing (e.g., circuit probe testing) of first package assembly 40. Some of metal pads 50 may be connected to TSVs 46 through interconnect structure 49. Some of metal pads 50 may be connected to integrated circuit devices at the surface of substrate 42 through interconnect structure 49.

[0024] As an example of forming metal pad 50, passivation layer 54 can be patterned using photolithography and etching techniques to expose interconnect structure 49. Patterned passivation layer 54 exposes the topmost conductive component 48 of interconnect structure 49. A seed layer (not shown) can be deposited above passivation layer 54 and on exposed conductive component 48. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above a titanium layer and a titanium layer. The seed layer can be formed using, for example, sputtering, evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), etc. A photoresist (not shown) is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metal pad 50. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can include metals, such as aluminum copper, copper, aluminum, nickel, tungsten, etc. or their alloys. Other conductive materials are also possible. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma. Once the photoresist is removed, an acceptable etching process, such as a wet etching process or a dry etching process, is used to remove the exposed portion of the seed layer. The remaining portion of the seed layer and the conductive material forms a metal pad 50.

[0025] In some embodiments, a dielectric layer 58 may be deposited over the passivation layer 54 and the metal pad 50. The dielectric layer 58 may protect the metal pad 50, for example, from oxidation. In some embodiments, the dielectric layer 58 is an anti-reflective coating (ARC) and includes an oxide or a nitride, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or any suitable material. In other embodiments, the dielectric layer 58 may include one or more materials, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), low-k dielectric materials, etc. The dielectric layer 58 may be formed using a suitable process, such as spin coating, flowable chemical vapor deposition (FCVD), PECVD, low pressure chemical vapor deposition (LPCVD), etc. Other materials or deposition techniques are also possible. In some embodiments, an optional planarization process (e.g., chemical mechanical polishing (CMP), grinding, etc.) is performed on the dielectric layer 58 so that the top surface of the dielectric layer 58 is approximately flat.

[0026] exist Figure 2In some embodiments, one or more first package components 40 are attached to a first carrier 20. The first carrier 20 may include a substrate carrier 22 and one or more dielectric bonding layers 24. In some embodiments, the substrate carrier 22 may be a wafer and may be a material similar to the substrate 42 of the first package component 40. In this way, during the process, warpage caused by the mismatch of the coefficient of thermal expansion (CTE) between the first carrier 20 and the first package component 40 may be reduced. For example, in some embodiments, the substrate carrier 22 may be formed of or include silicon. Other embodiments may use other materials such as laminates, ceramics, glass, silicate glass, organic cores, etc., or combinations thereof. According to some embodiments, the entire substrate carrier 22 is formed of a homogeneous material, wherein there is no other material different from the homogeneous material. In some embodiments, the entire substrate carrier 22 may be formed of silicon (doped or undoped), and there are no metal regions, dielectric regions, etc.

[0027] Before attaching the first package component 40 to the first carrier 20, a dielectric bonding layer 24 may be deposited on the substrate carrier 22. The dielectric bonding layer 24 may include one or more layers including one or more materials, such as oxide-based materials such as silicon oxide (SiO), PSG, BSG, BPSG, fluorine-doped silicate glass (FSG), etc.; nitride-based materials such as silicon nitride (SiN), etc.; oxynitride-based materials such as silicon oxynitride (SiON), etc.; or other materials such as silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc. The dielectric bonding layer 24 may be formed using spin coating, FCVD, PECVD, LPCVD, atomic layer deposition (ALD), etc., or a combination thereof. For example, in some embodiments, the dielectric bonding layer 24 may include: a lowermost layer including oxide (e.g., close to the substrate carrier 22); one or more intermediate layers including nitride and / or oxynitride; and an uppermost layer including oxynitride (e.g., away from the substrate carrier 22) (e.g., having a lower nitrogen to oxygen ratio than the intermediate layers). Although not separately shown, alignment marks may be formed in the dielectric bonding layer 24 (eg, the uppermost layer) using any suitable method.

[0028] In some embodiments, first package component 40 is attached to first carrier 20 using a direct bonding process, such as fusion bonding or dielectric-to-dielectric bonding. According to some embodiments, bonding first package component 40 to first carrier 20 includes: pre-treating dielectric bonding layer 24 and / or dielectric layer 58 with a process gas including oxygen (O2) and / or nitrogen (N2); performing a pre-bonding process to bond dielectric bonding layer 24 and dielectric layer 58 together; and performing an annealing process after the pre-bonding process to strengthen the bond.

[0029] According to some embodiments, during the pre-bonding process, the first package component 40 is in physical contact with the first carrier 20, wherein pressure is applied to press the first package component 40 against the first carrier 20. The pre-bonding process can be performed at room temperature (e.g., in a range of about 20°C to about 25°C), but higher temperatures can also be used. After the pre-bonding process, an annealing process is performed to bond the dielectric bonding layer 24 and the dielectric layer 58 together. According to some embodiments, the annealing process is performed at a temperature in a range of about 200°C to about 350°C. The annealing duration can be in a range of 30 minutes to 60 minutes. Other pre-bonding processes or bonding processes are also possible.

[0030] exist Figure 3 In some embodiments, a gap filling material 32 is deposited over the first package component 40 and the first carrier 20. The gap filling material 32 can seal, protect and / or insulate the first package component 40. In some embodiments, the gap filling material 32 may include an optional liner layer and a bulk layer (not shown separately). For example, the liner layer may be a conformal layer extending along the top surface and sidewalls of the first package component 40 and along the top surface of the dielectric bonding layer 24. The liner layer may also be referred to as a sealing ring and, in some embodiments, is used as an etch stop layer in subsequent steps. The liner layer may be formed of a dielectric material such as silicon nitride, silicon oxide, or the like, or a combination thereof. The liner layer may be deposited using a suitable conformal deposition process such as ALD, CVD, or the like. The bulk layer of the gap filling material 32 may be formed of a molding compound, an epoxy resin, a resin, a nitride such as silicon nitride, an oxide such as silicon oxide, an insulating material, or the like, or a combination thereof. The bulk layer may be deposited using a suitable process such as compression molding, spin coating, FCVD, PECVD, LPCVD, ALD, or the like.

[0031] In some embodiments, a planarization process is then performed to remove portions of the gap fill material 32. The planarization process may include, for example, a CMP process, a grinding process, and an etching process. The planarization process may remove the gap fill material 32, thereby exposing the first package component 40, such as Figure 3 In addition, the planarization process may remove a portion of the substrate 42 of the first package component 40, thereby exposing the TSV 46 of the first package component 40, as shown in FIG. Figure 3 In some embodiments, an etching process may be used to recess substrate 42 so that TSV 46 protrudes from the surface of substrate 42. After a planarization process is performed, the surfaces of gap fill material 32, substrate 42, and / or TSV 46 may be flush or coplanar (within process variations).

[0032] exist Figure 4In some embodiments, a dielectric bonding layer 60 is formed on the gap filling material 32 and the first package component 40. The dielectric bonding layer 60 may be deposited on the surface of the gap filling material 32, the substrate 42, and the TSV 46. The dielectric bonding layer 60 may include one or more layers. For example, the dielectric bonding layer 60 is shown as being formed by a first dielectric layer 60A deposited on the gap filling material 32 and the first package component 40 and a second dielectric layer 60B deposited on the first dielectric layer 60A. In other embodiments, the dielectric bonding layer 60 may be formed by a single layer or by more than two layers. In some embodiments, the dielectric bonding layer 60 may include one or more materials, which may include: oxide-based materials, such as silicon oxide (SiO), PSG, BSG, BPSG, FSG, USG, etc.; nitride-based materials, such as silicon nitride (SiN), etc.; nitride-based materials, such as silicon oxynitride (SiON), etc.; or other materials, such as silicon oxycarbide (SiOC), silicon carbonitride (SiCN), etc. The dielectric bonding layer 60 can be formed using spin coating, FCVD, PECVD, LPCVD, ALD, etc. or a combination thereof. For example, in some embodiments, the dielectric bonding layer 60 can include: a first dielectric layer 60A including silicon oxide and a second dielectric layer 60B including silicon oxynitride, but other combinations of materials are also possible.

[0033] exist Figure 5 In some embodiments, openings 61 (eg, openings 61A and 61B) are patterned in dielectric bonding layer 60. Bonding pads 62 are then formed in openings 61 (see FIG. Figure 6 ). The opening 61 may expose the TSV 46. For example, in Figure 5 In the embodiment, the opening 61 includes an opening 61B that exposes the TSV 46 and an opening 61A that does not expose the TSV 46. The opening 61 may be patterned using suitable photolithography and etching techniques. For example, a patterned mask may be formed over the dielectric bonding layer 60, and the dielectric bonding layer 60 may be etched using the patterned mask. The etching may include one or more etching steps, each of which may include a wet etching process and / or a dry etching process. In some embodiments, a thermal wiring 62C may also be subsequently formed in the opening 61 (see FIG. 1 ). Figures 19 to 22 ).

[0034] exist Figure 6 In some embodiments, bonding pads 62 (eg, bonding pads 62A and 62B) are formed in openings 61. Bonding pads 62 are used to form a connection to a subsequently bonded component (such as thermal component 100 or active package component 150 (see FIG. 1 )). Fig.13 )) physical, electrical and / or thermal connection. The bonding pad 62 can be electrically isolated or can be electrically connected to the TSV 46. For example, in Figure 6In FIG. 4 , bonding pad 62A is electrically isolated, and bonding pad 62B physically and electrically contacts TSV 46 .

[0035] The bonding pad 62 may be formed using a damascene process, a dual damascene process, or another suitable technique. The bonding pad 62 may include materials similar to those previously described for the metal pad 50 and may be formed using similar techniques. For example, in some embodiments, a seed layer may be deposited in the opening 61, and then a plating process may be used to deposit a conductive material on the seed layer. In some embodiments, a planarization process (e.g., CMP or grinding) may be performed. The planarization process may remove excess conductive material, and after the planarization process is performed, the surfaces of the bonding pad 62 and the dielectric bonding layer 60 may be approximately flush or coplanar.

[0036] Figures 7 to 10 1 shows a cross-sectional view of an intermediate step in the formation of a thermal assembly 100 according to some embodiments. The thermal assembly 100 is a package (e.g., Fig.18 The thermal assembly 100 is a package component that provides structural support and / or promotes heat dissipation within the package. In some embodiments, the thermal assembly 100 has no active and / or passive devices. In this way, in some instances, the thermal assembly 100 can be considered a dummy die.

[0037] According to some embodiments, thermal assembly 100 may include substrate 102. Substrate 102 may be a semiconductor substrate, which may be similar to those previously described for substrate 42. For example, in some embodiments, substrate 102 may be a silicon substrate, but other materials are also possible. In some embodiments, multiple thermal assemblies 100 may be formed on the same substrate 102 and then separated into independent thermal assemblies 100 using a segmentation process (e.g., a sawing process, a cutting process, etc.).

[0038] A through substrate via (TSV) 110 may be formed that extends partially through the substrate 102. The TSV 110 may be formed to facilitate heat transfer and heat dissipation within the package. The TSV 110 may be formed, for example, by etching the substrate 102 to form an opening and then filling the opening with a thermally conductive material. For example, in some embodiments, the thermally conductive material may include copper or the like. In some embodiments, the TSV 110 may also include a liner layer (not shown). In some embodiments, the TSV 110 is formed during the formation of the thermal structure 104, which will be described in more detail below. In such an embodiment, the TSV 110 may protrude from the surface of the substrate 102 and enter the thermal structure 104.

[0039] In some embodiments, a thermal structure 104 is formed over the front side of the substrate 102. The thermal structure 104 can facilitate heat dissipation within the thermal assembly 100. In some embodiments, the thermal structure 104 includes one or more layers of metal features 106 (e.g., metal lines, metal vias, metal pads, etc.) formed in one or more dielectric layers 105. The metal features 106 of the thermal structure 104 can allow for more efficient heat transfer and heat dissipation within the package. Figure 7 The thermal structure 104 is shown with a layer of conductive features 106 separated from the TSVs 110 by one or more dielectric layers 105, but other configurations of conductive features 106 and TSVs 110 are possible. FIG. 11A to FIG. 11E Some examples of thermal structures 104 and TSVs 110 having other configurations are described. Conductive features 106 may be formed using a damascene process, a dual damascene process, or another suitable technique, such as those used to form conductive features 48 of interconnect structure 49. Metal features 106 may include, for example, copper, aluminum, tungsten ruthenium, cobalt, alloys thereof, combinations thereof, and the like. Dielectric layer 105 may be formed of or include a dielectric material, such as a polymer, silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and the like, combinations thereof, and / or multilayers thereof. Other materials are also possible.

[0040] exist Figure 8 In some embodiments, a dielectric bonding layer 112 is formed on the thermal structure 104. The dielectric bonding layer 112 may include one or more layers. For example, the dielectric bonding layer 112 may be formed on the thermal structure 104. Figure 8 1 is shown as being formed of a first dielectric layer 112A deposited on the thermal structure 104 and a second dielectric layer 112B deposited on the first dielectric layer 112A. In other embodiments, the dielectric bonding layer 112 can be formed of a single layer or of more than two layers. The dielectric bonding layer 112 can include materials similar to those previously described for the dielectric bonding layer 60. For example, in some embodiments, the dielectric bonding layer 112 can include: a first dielectric layer 112A including silicon oxide and a second dielectric layer 112B including silicon oxynitride, but other combinations of materials are possible. In some embodiments, the dielectric bonding layer 112 can have a thickness of about 100 Å. to about The total thickness is within the range of , but other thicknesses are possible.

[0041] exist Fig. 9 In some embodiments, an opening 113 is patterned in the dielectric bonding layer 112. A bonding pad 114 is then formed in the opening 113 (see Fig.10). In some embodiments, the opening 113 can expose the metal component 106 of the thermal structure 104. The opening 113 can be patterned using suitable photolithography and etching techniques. For example, a patterned mask can be formed over the dielectric bonding layer 112, and the dielectric bonding layer 112 can be etched using the patterned mask. The etching can include one or more etching steps, each of which can include a wet etching process and / or a dry etching process.

[0042] exist Fig.10 In some embodiments, a bonding pad 114 is formed in the opening 113. The bonding pad 114 is used to form a physical, electrical and / or thermal connection to the first package component 40. Fig.10 In the thermal assembly 100 of FIG. 1 , the bonding pad 114 is separated from the metal component 106 by one or more dielectric layers 105, but in other embodiments, the bonding pad 114 can physically contact the metal component 106. The bonding pad 114 can be formed using a damascene process, a dual damascene process, or another suitable technique, such as those used to form the bonding pad 62. The bonding pad 114 can include materials similar to the bonding pad 62 or similar to those previously described for the metal pad 50. For example, in some embodiments, a seed layer can be deposited in the opening 113, and then a plating process can be used to deposit a conductive material on the seed layer. In some embodiments, a planarization process (e.g., CMP or grinding) can be performed. The planarization process can remove excess conductive material, and after the planarization process is performed, the surfaces of the bonding pad 114 and the dielectric bonding layer 112 can be approximately flush or coplanar.

[0043] FIG. 11A to FIG. 11E Various exemplary configurations of thermal assembly 100 are shown according to some embodiments. FIG. 11A to FIG. 11E The thermal assembly 100 described is intended as a non-limiting set of examples, and other configurations are possible. FIG. 11A to FIG. 11E The various components of the described thermal assembly 100 may have other arrangements, sizes, or configurations, and / or may be combined in any suitable manner. FIG. 11A to FIG. 11E The thermal assembly 100 described may be similar to that previously described for Fig.10 The thermal assembly 100 is described and may be formed using similar techniques. FIG. 11A to FIG. 11E Shows relative to Fig.10 The thermal assembly 100 shown in FIG. 1 is in an upside-down orientation.

[0044] Fig.11A Shows something like Fig.10 The thermal assembly 100 shown in FIG. 100 is a thermal assembly 100. For example, Fig.11AThe thermal assembly 100 includes a thermal structure 104 having a layer of metal features 106. In addition, the metal features 106 are isolated from each other, from the bonding pads 114, and from the TSVs 110. Fig.11A In the embodiment of the present invention, the metal component 106 includes a metal wire or the like.

[0045] The thermal assembly 100 may have Fig.11A The thermal structure 104 with different number of layers is shown in FIG. For example, Fig. 11B Shows something like Fig.11A The thermal assembly 100 of the thermal assembly 100 is different in that the thermal structure 104 does not include any metal components 106. In other words, Fig. 11B The thermal structure 104 includes one or more dielectric layers 105 , but no metal features 106 . Fig. 11B The TSV 110 is shown isolated from the bonding pad 114 by one or more dielectric layers 105, but in other embodiments, the TSV 110 may physically contact the bonding pad 114. As another example, Fig. 11C Shows something like Fig.11A The thermal assembly 100 of the thermal assembly 100 is different in that the thermal structure 104 includes two layers of metal components 106 separated by one or more dielectric layers 105. In particular, Fig. 11C The thermal structure 104 includes a first layer of metal features 106A (eg, metal lines) and a second layer of metal features 106B (eg, metal lines). In other embodiments, the thermal structure 104 may have more than two layers of metal features 106 .

[0046] Fig.11D Shows something like Fig.11A The thermal assembly 100 of the thermal assembly 100 is similar to the thermal assembly 100 of the thermal assembly 100, except that the metal features 106 of the thermal structure 104 include metal vias in addition to the metal lines. The metal vias can physically connect the metal features 106, the TSVs 110, and / or the metal lines of the bonding pads 114. The metal vias can provide a thermal path that can improve heat dissipation within the thermal assembly 100. In some examples, the location, size, or arrangement of the metal vias can be selected to provide appropriately effective heat dissipation, which can depend on the specific application or specific structure of the package. Fig.11D As shown in , the metal vias may extend between TSV 110 and the metal line, or may extend between the metal line and the bonding pad 114. In other embodiments, the metal vias may extend between metal lines formed in different layers.

[0047] The shape, size, configuration, location, or arrangement of the TSVs 110 or metal features 106 may be selected to provide effective heat dissipation in a package. For example, the size of some TSVs 110 in a region may be larger (e.g., having a larger height and / or width) to provide more effective heat dissipation in that region. As another example, the density of TSVs 110 in a region may be greater (e.g., having a smaller pitch) to provide more effective heat dissipation in that region. In this way, the metal features 106 and / or TSVs 110 of the thermal assembly 100 may be configured for a specific application or package.

[0048] As an example, Fig.11E The thermal assembly 100 is shown with TSVs 110 having different characteristics. This is an example, and the TSVs 110 or metal features 106 may have different characteristics or a different combination of characteristics in other embodiments. Fig.11E The thermal assembly 100 includes a TSV 110 having a height H1 and a TSV 110 having a height H2, wherein the height H1 and the height H2 are different. Fig.11E In some embodiments, height H2 is greater than height H1. In some embodiments, height H1 may be between about 70% and about 90% of height H2. In some embodiments, height H1 and / or H2 may be in a range of about 5 μm to about 150 μm, although other heights are possible. Fig.11E The thermal assembly 100 includes a TSV 110 having a width W1 and a TSV 110 having a width W2, wherein the width W1 and the width W2 are different. Fig.11E In some embodiments, width W2 is greater than width W1. In some embodiments, width W1 may be between about 5% and about 90% of width W2. In some embodiments, width W1 and / or W2 may be in a range of about 1 μm to about 50 μm, although other widths are possible. Fig.11E The thermal assembly 100 includes TSVs 110 with a pitch P1 and TSVs 110 with a pitch P2, wherein the pitch P1 and the pitch P2 are different. Fig.11E In some embodiments, pitch P2 is greater than pitch P1. In some embodiments, pitch P1 may be between about 20% and about 90% of pitch P2. In some embodiments, pitch P1 and / or P2 may be in the range of about 4 μm to about 30 μm, but other pitches are possible. In other embodiments, TSVs 110 of more than two different heights, more than two different widths, and / or more than two different pitches are possible.

[0049] The TSVs 110 of the thermal assembly 100 may be formed to have various shapes or configurations. Depending on the particular application or package, the shape of the TSVs 110 may be selected to provide effective heat dissipation. FIG. 12A to FIG. 12HAn exemplary cross section of a TSV 110 is shown in accordance with some embodiments. FIG. 12A to FIG. 12H The TSVs 110 shown in FIG. 1 are intended as non-limiting examples, and TSVs 110 having other shapes, cross-sections, or sizes are possible.

[0050] Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D Plan views of TSVs 110 with cross-sections of various shapes are shown in accordance with some embodiments. The cross-sections may have approximately equal lengths and widths, or may have lengths that are a different distance than their widths. Fig. 12A The TSV 110 is shown having an approximately circular shape according to some embodiments. In other examples, the TSV 110 may have an annular shape, an oval shape, an elliptical shape, or the like. Fig. 12B 1 shows a TSV 110 having an approximately square shape according to some embodiments. In other embodiments, the TSV 110 may have an approximately rectangular shape, such as Fig. 12C as shown in . Fig.12D TSVs 110 are shown having approximately a triangular shape according to some embodiments. Other shapes are possible, such as other rectangles, other quadrilaterals, other triangles, other polygons, etc.

[0051] Fig.12E , Fig.12F , Figure 12G and Fig.12H TSV 110 is shown having a cross section formed by a combination of shapes according to some embodiments. The cross section may have a shape that is a combination of other shapes, such as a combination of approximately rectangular segments. In some instances, a shape with a larger surface area (eg, cross-sectional perimeter) may provide improved heat dissipation. Fig.12E A cross section formed by two segments in a "+" configuration is shown. Fig.12F A cross section formed by two segments in an "L" configuration is shown. Figure 12G A cross section formed by multiple segments in a "C" configuration is shown. Fig.12H A cross section is shown formed of multiple segments in an "O" configuration with an "hole." In other examples, a cross section may have more than one "hole." Other configurations of segments or shapes are also possible.

[0052] Figures 13 to 18 A package 200 (see FIG. Fig.18 ) is a cross-sectional view of an intermediate step in the formation of. Fig.13In some embodiments, one or more thermal components 100 and one or more active components 150 are attached to the first package component 40. The active package component 150 may include a functional component, such as an integrated circuit, etc. The thermal component 100 may be similar to those previously described and may be included, for example, to provide structural integrity and / or heat dissipation.

[0053] In some embodiments, active package assembly 150 and / or thermal assembly 100 may be attached using a direct bonding process, such as a dielectric-to-dielectric bonding process and / or a metal-to-metal bonding process (eg, a fusion bonding process, a hybrid bonding process, etc.). Fig.13 One active package component 150 and one thermal component 100 are shown attached to first package component 40, but in other embodiments, any suitable number or type of active package components 150 and / or thermal components 100 may be attached to first package component 40. For example, in other embodiments, multiple active package components 150 of multiple types may be attached.

[0054] In some embodiments, the active package component 150 may be an independent device die (e.g., an integrated circuit die), a package in which one or more device dies are packaged, a system-on-chip (SoC) die including multiple integrated circuits (or device dies) integrated as a system, etc. The device die of the active package component 150 may include a logic die, a memory die, an input-output (I / O) die, an integrated passive device (IPD), etc., or a combination thereof. For example, the logic device die of the active package component 150 may include a central processing unit (CPU) die, a graphics processing unit (GPU) die, a mobile application die, a microcontroller unit (MCU) die, a baseband (BB) die, an application processor (AP) die, etc. The memory die of the active package component 150 may include a static random access memory (SRAM) die, a dynamic random access memory (DRAM) die, etc. The device die of the active package component 150 may include a semiconductor substrate and an interconnect structure. According to some embodiments, the first package component 40 is a SoC die, and the active package component 150 includes a memory die, such as a SRAM die.

[0055] According to some embodiments (not separately shown), the active package assembly 150 may include some components similar to those described above for the first package assembly 40. For example, the active package assembly 150 may include a semiconductor substrate, an integrated circuit device, and a plurality of dielectric layers formed over the semiconductor substrate and the integrated circuit device. The integrated circuit device may include active devices, passive devices, etc. The active package assembly 150 may include a dielectric bonding layer 152 that is subsequently bonded to the dielectric bonding layer 60. The active package assembly 150 may also include a bonding pad 154 formed within the dielectric bonding layer 152.

[0056] The dielectric bonding layer 152 can be similar to the dielectric bonding layer 60 and / or the dielectric bonding layer 112 and can be formed using similar techniques. For example, the dielectric bonding layer 152 can include one dielectric layer or multiple dielectric layers, which can include materials such as silicon oxide, silicon nitride, silicon oxynitride, polymers, etc. For example, in some embodiments, the dielectric bonding layer 152 can include: a first dielectric layer including silicon oxide and a second dielectric layer including silicon oxynitride, but other combinations of materials are also possible. In some embodiments, the dielectric bonding layer 152 of the active package component 150 can have a composition similar to the composition of the dielectric bonding layer 112 of the thermal component 100. In other embodiments, the dielectric bonding layer 152 can have a different dielectric material than the dielectric bonding layer 112.

[0057] In some embodiments, the dielectric bonding layer 152 and the dielectric bonding layer 112 may be formed of similar materials but in different proportions. For example, in some embodiments, the proportion of silicon oxide, silicon nitride, silicon oxynitride, and / or polymer within the dielectric bonding layer 152 may be different from the proportion of the same material within the dielectric bonding layer 112. In other words, the ratio of the thickness of the dielectric material layer of the dielectric bonding layer 152 to the total thickness of the dielectric bonding layer 152 may be different from the ratio of the thickness of the same dielectric material layer of the dielectric bonding layer 112 to the total thickness of the dielectric bonding layer 112. In this way, the dielectric layer of the dielectric bonding layer 152 may have a different relative thickness or a different absolute thickness than the corresponding dielectric layer of the dielectric bonding layer 112. In some examples, forming the layer of the dielectric bonding layer 152 to have a different thickness from the dielectric bonding layer 112 can reduce manufacturing costs, improve bonding, and improve heat dissipation. The total thickness of the dielectric bonding layer 152 may be greater than, approximately equal to, or less than the total thickness of the dielectric bonding layer 112. For example, in some embodiments, the total thickness of dielectric bonding layer 112 can be about 70% or less than the total thickness of dielectric bonding layer 152, but other relative thicknesses are possible. In some examples, forming dielectric bonding layer 112 thinner than dielectric bonding layer 152 can reduce manufacturing costs, improve bonding, and improve heat dissipation. In this way, the composition and / or thickness of the bonding layer of the package can be controlled to provide better thermal performance.

[0058] In some embodiments, a bonding pad 154 is formed in the dielectric bonding layer 152 of the active package component 150. The bonding pad 154 can be electrically connected to other components of the active package component 150, such as interconnect structures, circuits, TSVs, etc. (not separately shown). The bonding pad 154 can be similar to the previously described bonding pad 62 or bonding pad 114 and can be formed using similar techniques.

[0059] exist Fig.14 In some embodiments, the thermal component 100 and the active package component 150 are bonded to the dielectric layer 60 formed above the first package component 40. The dielectric bonding layer 112 of the thermal component 100 and the dielectric bonding layer 152 of the active package component 150 are directly bonded to the dielectric bonding layer 60 using dielectric-to-dielectric bonding. In addition, the bonding pad 114 of the thermal component 100 is directly bonded to the bonding pad 62A using metal-to-metal bonding, and the bonding pad 154 of the active package component 150 is directly bonded to the bonding pad 62B using metal-to-metal bonding. In some embodiments, the bonding may include a pre-bonding process and an annealing process. During the pre-bonding process, a small pressure may be applied to press the thermal component 100 and the active package component 150 against the dielectric bonding layer 60. The pre-bonding process may be performed at low temperature, such as room temperature (e.g., a temperature in the range of about 20°C to about 25°C). After the pre-bonding process, the dielectric bonding layer 112 and the dielectric bonding layer 152 are bonded to the dielectric bonding layer 60. The bond strength may then be improved in a subsequent annealing step, in which the dielectric bonding layers 60, 112, and 152 are annealed at an elevated temperature, such as a temperature in the range of about 200° C. to about 350° C. In this manner, the dielectric bonding layer 112 and the dielectric bonding layer 152 are bonded to the dielectric bonding layer 60 by dielectric-to-dielectric bonding. In addition, the annealing step also bonds the bond pads 114 and the bond pads 154 to the bond pads 62 by metal-to-metal bonding.

[0060] exist Fig.15 In some embodiments, a gap filler material 70 is deposited over the thermal component 100, the active packaging component 150, and the dielectric bonding layer 60. The gap filler material 70 can seal the thermal component 100 and the active packaging component 150. The gap filler material 70 can be similar to the gap filler material previously described for Figure 3 The gap filler material 70 may be formed by the gap filler material 32 described above and may be formed using similar techniques. For example, the gap filler material 70 may include an optional liner layer and a bulk layer (not separately shown). In some examples, the gap filler material 70 includes a different material than the gap filler material 32. In some embodiments, a planarization process (e.g., CMP, grinding, etc.) is performed to remove portions of the gap filler material 70. The planarization process may remove the gap filler material 70, thereby exposing the thermal assembly 100 and the active package assembly 150, as shown in FIG. Fig.15 After the planarization process is performed, the surfaces of the gap fill material 70 , the thermal component 100 , and the active package component 150 may be flush or coplanar (within process variations).

[0061] exist Fig.16In some embodiments, a second carrier 80 is attached. The second carrier 80 may include a substrate carrier 84 and one or more dielectric bonding layers 82. In some embodiments, the substrate carrier 84 and the dielectric bonding layer 82 may be similar to the substrate carrier 22 and the dielectric bonding layer 24 of the first carrier 20 previously described. For example, the substrate carrier 84 may be a material similar to the substrate carrier 22 to reduce warpage caused by CTE mismatch. Before attaching the second carrier 80, one or more dielectric bonding layers 82 are deposited on the substrate carrier 84, and one or more dielectric bonding layers 72 are deposited over the gap filling material 70, the thermal component 100, and the active package component 150. The second carrier 80 may be attached using dielectric-to-dielectric bonding. For example, according to some embodiments, bonding the second carrier 80 includes: pre-treating the dielectric bonding layers 72 and 82 in a process gas; performing a pre-bonding process to bond the dielectric bonding layers 72 and 82 together; and performing an annealing process after the pre-bonding process to strengthen the bonding.

[0062] exist Fig.17 In some embodiments, the first carrier 20 is removed. The first carrier 20 may be removed using any suitable method, such as using a planarization process and / or an etching process. The planarization process may include a CMP process, a grinding process, etc., or a combination thereof. The etching process may include a wet etching process, a dry etching process, or a combination thereof. Fig.17 As shown in FIG. 5 , removal of first carrier 20 exposes dielectric layer 58 and gap-fill material 32. In some embodiments, after removal of first carrier 20, surfaces of dielectric layer 58 and gap-fill material 32 are flush or coplanar (within process variations).

[0063] exist Fig.18 In some embodiments, an under bump metal (UBM) 92 and a conductive connector 94 are formed. In some embodiments, a passivation layer 90 is deposited over the first package component 40 and the gap fill material 32. The passivation layer 90 may include one or more dielectric material layers, such as silicon oxide, PSG, BSG, BPSG, FSG, USG, silicon oxynitride, silicon oxycarbide, silicon nitride, silicon carbonitride, polymers, etc. The passivation layer 90 may be deposited using a suitable technique, such as spin coating, FCVD, CVD, PECVD, etc. In some embodiments, an optional planarization process (e.g., CMP, grinding, etc.) is performed on the passivation layer 90 so that the top surface of the passivation layer 90 is flat (within process variations).

[0064] According to some embodiments, an opening (not shown separately) is then formed in the passivation layer 90. The opening can be formed using suitable photolithography and etching techniques. For example, a photoresist can be applied and patterned above the top surface of the passivation layer 90. The patterned photoresist is then used as an etching mask to etch portions of the passivation layer 90 to form an opening. The etching can include one or more dry etching processes and / or wet etching processes. The opening can also extend through the dielectric layer 58 to expose the metal pad 50.

[0065] According to some embodiments, an under-bump metal (UBM) 92 may then be formed in the opening. The UBM 92 may extend through the passivation layer 90 and / or the dielectric layer 58 to be electrically connected to the metal pad 50. As an example of forming the UBM 92, a seed layer (not shown separately) is formed over the exposed surface of the metal pad 50 and the passivation layer 90. In some embodiments, the seed layer is a metal layer that may be a single layer or a composite layer including a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer may be formed using, for example, PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating, etc., and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBM 92. Patterning forms an opening through the photoresist to expose the seed layer. A conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as electroplating or chemical plating, etc. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process. The remaining portion of the seed layer and the conductive material forms the UBM 92. In other embodiments, the UBM 92 may include a liner layer, such as an adhesive layer. In other embodiments, the UBM 92 may have a top surface flush with the top surface of the passivation layer 90.

[0066] According to some embodiments, a conductive connector 94 can then be formed on the UBM 92. The conductive connector 94 can include a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 94 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 94 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 94 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or combinations thereof and may be formed by a plating process. In some embodiments, some or all of the UBMs 92 are formed as part of the conductive connectors 94 .

[0067] According to some embodiments, after forming the conductive connectors 94 , a singulation process may be performed to separate the structure into individual packages 200 . Fig.18 A singulated package 200 is shown according to some embodiments. The singulation process may include a sawing process, a cutting process, an etching process, etc. In this manner, a package 200 including a thermal assembly 100 with improved heat dissipation is formed. This may improve the thermal performance, efficiency, and reliability of semiconductor packages such as package 200.

[0068] Figures 19 to 22 2 shows a cross-sectional view of an intermediate step in the formation of a package 200 according to some embodiments. Figures 19 to 22 The package 200 described is similar to the package 200 previously described for Fig.18 The package 200 described above is different in that a thermal wiring 62C is formed in addition to the bonding pads 62A and 62B. As described below, the thermal wiring 62C includes a dummy wiring that can extend between the bonding pad 114 and the bonding pad 154 to provide improved heat dissipation for the package 200. The thermal wiring 62C is formed using similar materials or techniques as previously described, and therefore some materials, steps and / or techniques may not be repeated below.

[0069] Fig.19 Shows something like Figure 5 , wherein an opening 61 is formed in a dielectric bonding layer 60, except that Fig.19The opening 61 includes one or more openings 61C, and then a thermal wiring 62C is formed in the opening 61C. The opening 61C can be formed using a method similar to that previously described for Figure 5 The above-described techniques for forming the openings 61A-61B may be used to form the above-described openings 61A-61B. Fig.19 As shown in FIG. 1 , opening 61C has a larger lateral extent than openings 61A- 61B. In some examples, opening 61C may expose one or more TSVs 46, such as Fig.19 In other examples, opening 61C may not expose TSV 46 . Fig.19 A single opening 62C is shown, but in other embodiments, a plurality of openings 62C may be formed.

[0070] exist Fig. 20 In the embodiment, bonding pads 62A-62B and thermal wiring 62C are formed in openings 61A-61B and opening 61C, respectively. In some embodiments, thermal wiring 62C can be formed together with bonding pads 62A-62B using the same processing steps. Thermal wiring 62C can be formed using a method similar to that for Figure 6 For example, a conductive material may be deposited in openings 61A-61C, and then a planarization process may be performed to remove excess conductive material. Fig. 20 As shown in FIG. 4 , in some embodiments, thermal routing wire 62C may physically contact one or more TSVs 46 . Fig. 20 A single thermal wiring 62C is shown, but in other embodiments, a plurality of thermal wirings 62C may be formed.

[0071] exist Fig.21 In some embodiments, thermal assembly 100 and active package assembly 150 are bonded to dielectric bonding layer 60. Thermal assembly 100 and active package assembly 150 may be bonded using a method similar to that described for Fig.14 For example, dielectric bonding layer 112 may be bonded to dielectric bonding layer 60 using dielectric-to-dielectric bonding, and dielectric bonding layer 152 may be bonded to dielectric bonding layer 60 using dielectric-to-dielectric bonding. In addition, bonding pad 114 may be bonded to bonding pad 62A using metal-to-metal bonding, and bonding pad 154 may be bonded to bonding pad 62B using metal-to-metal bonding. Fig.21As shown in , the bonding pads 114 and / or the bonding pads 154 can be bonded to the thermal routing wires 62C using metal-to-metal bonding. The thermal routing wires 62C can be bonded to one or more bonding pads 114 and / or one or more bonding pads 154. Any number of thermal routing wires 62C can extend between two or more bonding pads 62, between two or more bonding pads 154, and / or between any number of bonding pads 62 and any number of bonding pads 154. As a non-limiting example, Fig.21 A single thermal routing wire 62C is shown bonded to and extending between one bonding pad 114 and one bonding pad 154. Forming the thermal routing wire 62C in this manner can facilitate heat transfer and heat dissipation within the package 200. In some instances, the thermal routing wire 62C is a dummy routing wire that is not electrically connected to a functional circuit. In some instances, the thermal routing wire 62C can electrically connect the thermal assembly 100 to the active package assembly 150 and / or to the TSV 46.

[0072] Subsequent processing steps may then be performed to form the package 200, such as Fig. 22 For example, a package 200 similar to that previously described for Figures 15 to 18 In some embodiments, gap fill material 70 may physically contact the top surface of thermal routing wire 62C. In other examples, thermal routing wire 62C may be covered by thermal component 100 or active package component 150. Fig. 22 The package 200 shown in FIG. 2 is an example, and other packages or configurations of the thermal wiring 62C are possible.

[0073] Embodiments described herein can achieve advantages. Forming pseudo structures including through substrate vias (TSVs), metal lines, metal vias, etc. can provide improved heat dissipation within a package (such as a SoIC package, etc.). The arrangement or characteristics of the TSVs or metal components can be controlled to provide effective heat transfer for a specific application or package design. For example, the height, width, spacing, or shape of the TSVs can be controlled for heat dissipation within a specific package design. In addition, the thickness and / or composition of the bonding layer of the pseudo structure can be controlled to reduce manufacturing costs, provide improved heat transfer, and / or provide improved bonding. In some embodiments, thermal wiring is formed within the bonding layer to further improve heat dissipation.

[0074] According to some embodiments of the present disclosure, a method includes: forming a dummy component, including: forming a through substrate via (TSV) in a substrate; forming a thermal structure above the TSV, wherein the thermal structure includes a metal line in a dielectric layer; forming a bonding layer above the thermal structure; and forming a bonding pad within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component. In an embodiment, bonding the dummy component to the package component includes bonding the bonding layer to the package component using a dielectric to dielectric bonding and bonding the bonding pad to the package component using a metal to metal bonding. In an embodiment, forming the dummy component includes forming a metal via in a dielectric layer, wherein the metal via physically contacts the metal line and the TSV. In an embodiment, the metal via physically contacts the metal line and the bonding pad. In an embodiment, the TSV includes a first TSV group having a first height and a second TSV group having a second height different from the first height. In an embodiment, the TSV includes a third TSV group having a first spacing and a fourth TSV group having a second spacing different from the first spacing. In an embodiment, the TSVs include a fifth TSV group having a first width and a sixth TSV group having a second width different from the first width. In an embodiment, the dummy component is electrically connected to the semiconductor die through a dummy wiring within the package component.

[0075] According to some embodiments of the present disclosure, a method includes: forming a first bonding layer on a first package component; forming a first bonding pad in the first bonding layer; forming a second bonding pad in the first bonding layer; bonding a thermal component to the first bonding layer and to the first bonding pad, wherein the thermal component includes: a through substrate via (TSV) extending into the substrate; a second bonding layer located above the substrate and the TSV; and a third bonding pad located in the second bonding layer; and bonding an active package component to the first bonding layer and to the second bonding pad, wherein the active package component includes: an active device; a third bonding layer located above the active device; and a fourth bonding pad located in the third bonding layer. In an embodiment, the first bonding pad is electrically isolated. In an embodiment, the method includes forming a thermal wiring in the first bonding layer, wherein at least one third bonding pad is bonded to one thermal wiring. In an embodiment, at least one fourth bonding pad is bonded to one thermal wiring. In an embodiment, the second bonding layer is thinner than the third bonding layer. In an embodiment, the thickness of the layer of the first dielectric material in the second bonding layer is different from the thickness of the layer of the first dielectric material in the third bonding layer. In an embodiment, the first dielectric material is silicon oxide.

[0076] According to some embodiments of the present disclosure, a package includes: a dummy die bonded to a package assembly, wherein the dummy die includes: a substrate; a first metal component extending into the substrate; a second metal component located above the first metal component and separated from the first metal component by a first dielectric layer; a second dielectric layer located above the second metal component; and a bonding pad located within the second dielectric layer; and a semiconductor die bonded to the package assembly adjacent to the dummy die. In an embodiment, the dummy die is electrically isolated from the semiconductor die. In an embodiment, the dummy die includes at least two layers of second metal components. In an embodiment, the package assembly includes a bonding pad, wherein the bonding pad of the dummy die is directly bonded to the bonding pad of the package assembly. In an embodiment, at least one first metal component is electrically connected to at least one metal pad of the package assembly.

[0077] Some embodiments of the present application provide a method for forming a package, comprising: forming a dummy component, comprising: forming a plurality of through substrate vias (TSVs) in a substrate; forming a thermal structure above the plurality of substrate through vias, wherein the thermal structure comprises a plurality of metal wires in a plurality of dielectric layers; forming a bonding layer above the thermal structure; and forming a plurality of bonding pads within the bonding layer; bonding the dummy component to a package component; and bonding a semiconductor die to the package component.

[0078] In some embodiments, bonding the dummy component to the package component includes bonding the bonding layer to the package component using dielectric-to-dielectric bonding and bonding the plurality of bonding pads to the package component using metal-to-metal bonding.

[0079] In some embodiments, forming the dummy component further comprises forming a plurality of metal vias in the plurality of dielectric layers, wherein metal vias of the plurality of metal vias physically contact metal lines of the plurality of metal lines and substrate vias of the plurality of substrate vias.

[0080] In some embodiments, a metal via of the plurality of metal vias physically contacts a metal line of the plurality of metal lines and a bonding pad of the plurality of bonding pads.

[0081] In some embodiments, the plurality of through substrate vias include a first group of through substrate vias having a first height and a second group of through substrate vias having a second height different from the first height.

[0082] In some embodiments, the plurality of through substrate vias includes a third group of through substrate vias having a first pitch and a fourth group of through substrate vias having a second pitch different from the first pitch.

[0083] In some embodiments, the plurality of through substrate vias include a fifth through substrate via group having a first width and a sixth through substrate via group having a second width different from the first width.

[0084] In some embodiments, the dummy component is electrically connected to the semiconductor die through a dummy wiring within the package component.

[0085] Other embodiments of the present application provide a method for forming a package, comprising: forming a first bonding layer on a first packaging component; forming a plurality of first bonding pads in the first bonding layer; forming a plurality of second bonding pads in the first bonding layer; bonding a thermal component to the first bonding layer and to the plurality of first bonding pads, wherein the thermal component comprises: a through substrate via (TSV) extending into a substrate; a second bonding layer located above the substrate and the substrate through via; and a plurality of third bonding pads located in the second bonding layer; and bonding an active packaging component to the first bonding layer and to the plurality of second bonding pads, wherein the active packaging component comprises: an active device; a third bonding layer located above the active device; and a plurality of fourth bonding pads located in the third bonding layer.

[0086] In some embodiments, the first bonding pads of the plurality of first bonding pads are electrically isolated.

[0087] In some embodiments, the method further includes forming a plurality of thermal routing wires in the first bonding layer, wherein at least one third bonding pad is bonded to one thermal routing wire.

[0088] In some embodiments, the at least one fourth bonding pad is bonded to a thermal routing wire.

[0089] In some embodiments, the second bonding layer is thinner than the third bonding layer.

[0090] In some embodiments, the thickness of the layer of first dielectric material within the second bonding layer is different than the thickness of the layer of first dielectric material within the third bonding layer.

[0091] In some embodiments, the first dielectric material is silicon oxide.

[0092] Still other embodiments of the present application provide a package, comprising: a dummy die bonded to a package component, wherein the dummy die comprises: a substrate; a first metal component extending into the substrate; a second metal component located above the first metal component and separated from the first metal component by a first dielectric layer; a second dielectric layer located above the second metal component; and a bonding pad located within the second dielectric layer; and a semiconductor die bonded to the package component adjacent to the dummy die.

[0093] In some embodiments, the dummy die is electrically isolated from the semiconductor die.

[0094] In some embodiments, the dummy die includes at least two layers of second metal features.

[0095] In some embodiments, the package assembly includes a bonding pad, wherein the bonding pad of the dummy die is directly bonded to the bonding pad of the package assembly.

[0096] In some embodiments, at least one first metal feature is electrically connected to at least one metal pad of the package assembly.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a package, comprising: Form a pseudo component, including: forming a plurality of through substrate vias (TSVs) in the substrate; forming a thermal structure over the plurality of through substrate vias, wherein the thermal structure comprises a plurality of metal lines in a plurality of dielectric layers; forming a bonding layer over the thermal structure; and forming a plurality of bonding pads in the bonding layer; bonding the dummy component to a package component; and A semiconductor die is bonded to the package assembly.

2. The method according to claim 1, wherein: Bonding the dummy component to the package component includes bonding the bonding layer to the package component using dielectric-to-dielectric bonding and bonding the plurality of bonding pads to the package component using metal-to-metal bonding.

3. The method according to claim 1, wherein: Forming the dummy component further includes forming a plurality of metal vias in the plurality of dielectric layers, wherein metal vias of the plurality of metal vias physically contact metal lines of the plurality of metal lines and substrate vias of the plurality of substrate vias.

4. The method according to claim 3, wherein: A metal via of the plurality of metal vias physically contacts a metal line of the plurality of metal lines and a bonding pad of the plurality of bonding pads.

5. The method according to claim 1, wherein: The plurality of through substrate vias include a first group of through substrate vias having a first height and a second group of through substrate vias having a second height different from the first height.

6. The method according to claim 1, wherein: The plurality of through substrate vias include a third through substrate via group having a first pitch and a fourth through substrate via group having a second pitch different from the first pitch.

7. The method according to claim 1, wherein: The plurality of through substrate vias include a fifth through substrate via group having a first width and a sixth through substrate via group having a second width different from the first width.

8. The method according to claim 1, wherein: The dummy component is electrically connected to the semiconductor die through a dummy wiring within the package component.

9. A method of forming a package, comprising: forming a first bonding layer on the first package component; forming a plurality of first bonding pads in the first bonding layer; forming a plurality of second bonding pads in the first bonding layer; Bonding a thermal assembly to the first bonding layer and to the plurality of first bonding pads, wherein the thermal assembly comprises: Through-substrate vias (TSVs), extending into the substrate; a second bonding layer located above the substrate and the through substrate via; and a plurality of third bonding pads located in the second bonding layer; and Bonding an active package component to the first bonding layer and to the plurality of second bonding pads, wherein the active package component comprises: Active devices; a third bonding layer located above the active device; and A plurality of fourth bonding pads are located in the third bonding layer.

10. A package comprising: A dummy die is bonded to the package assembly, wherein the dummy die comprises: substrate; a first metal component extending into the substrate; a second metal component located above the first metal component and separated from the first metal component by a first dielectric layer; a second dielectric layer located above the second metal component; and a bonding pad located within the second dielectric layer; and A semiconductor die is bonded to the package assembly adjacent to the dummy die.

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