Ion implantation structure position determination method, apparatus, device, and medium

Abstract

The present disclosure relates to a method, device, equipment and medium for determining the position of ion implantation structure, wherein the position of each ion implantation structure is determined by the following steps: obtaining the first distance value, the second distance value and the current electrical property data of the memory on both sides of the ion implantation structure; determining the position offset direction of the ion implantation structure according to the difference between the current electrical property data and the target electrical property data of the memory; adjusting the forming position of the ion implantation structure according to the position offset direction of the ion implantation structure, so that the electrical property data of the memory reaches the target electrical property data. At least after reducing the structure size of the static random access memory (SRAM) memory, the correct position of the ion implantation structure can be accurately determined, and the performance of the static random access memory (SRAM) memory is ensured.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit design and testing technology, and in particular to a method, apparatus, equipment and medium for determining the location of ion implantation structures. Background Technology

[0002] Static Random Access Memory (SRAM) is widely used due to its low-voltage operation and high speed. The most common SRAM structure uses 6T (6 transistors) as a storage cell (e.g., ...). Figure 1 (As shown in the diagram). The 6T-SRAM layout consists of three types of MOS, including PU, PD, and PG. Among them, two PMOS make up the PU, and four NMOS make up the PD and PG.

[0003] The structure of a random access static memory (SRAM) includes an ion implantation structure (AA), a polysilicon layer (POLY), and a metal interconnect layer. The ion implantation structure and the polysilicon layer are used to define transistors, so the location of the ion implantation structure is more important.

[0004] With the improvement of etching precision, the structural size of SRAM has been continuously reduced. In the actual etching process of ion implantation structure, after reducing the structural size of SRAM, how to determine the position of ion implantation structure and ensure the electrical data of SRAM has become an urgent problem to be solved. Summary of the Invention

[0005] Therefore, it is necessary to provide a method, apparatus, device, and medium for determining the location of ion implantation structures to address the aforementioned technical problems. This method or apparatus can accurately determine the correct location of ion implantation structures after reducing the structural size of static random access memory (SRAM), thereby ensuring the performance of SRAM.

[0006] To achieve the above and other objectives, in a first aspect, this disclosure provides a method for determining the position of an ion implantation structure. The ion implantation structure is formed in a memory, which includes multiple ion implantation structures, multiple polysilicon layers, and multiple metal interconnect layers. The polysilicon layers are located above the ion implantation structures, and the metal interconnect layers are located above the polysilicon layers. The method involves determining the position of each ion implantation structure through the following steps: acquiring a first distance value and a second distance value on both sides of the ion implantation structure, and the current electrical data of the memory; determining the position offset direction of the ion implantation structure based on the difference between the current electrical data of the memory and the target electrical data; and adjusting the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure so that the electrical data of the memory reaches the target electrical data.

[0007] In the ion implantation structure location determination method in the above embodiments, the location of the ion implantation structure is adjusted by measuring the electrical data of the memory so that the electrical data of the memory reaches the target electrical data. Therefore, the embodiments of this disclosure can at least accurately determine the correct location of the ion implantation structure after reducing the structural size of the random access static memory (SRAM), thus ensuring the performance of the random access static memory (SRAM).

[0008] In one embodiment, the step of obtaining the first distance value and the second distance value on both sides of each ion implantation structure includes: performing a size scan of the ion implantation structure based on a critical size scanning electron microscope to determine the first distance value and the second distance value between the two sides of the ion implantation structure and other ion implantation structures.

[0009] In the method for determining the location of the ion implantation structure in the above embodiments, the ion implantation structure is scanned by a critical size scanning electron microscope to determine the specific location of the ion implantation structure.

[0010] In one embodiment, determining the position offset direction of each ion implantation structure based on the difference between the current electrical data and the target electrical data includes: determining the offset direction of the ion implantation structure based on the positive or negative value of the difference between the current electrical data and the target electrical data.

[0011] In the method for determining the position of the ion implantation structure in the above embodiments, the offset direction of the ion implantation structure is determined by the difference between the current electrical data and the target electrical data, which can provide the direction for adjusting the ion implantation structure. At the same time, the operator can also determine the moving distance of the ion implantation structure based on the magnitude of the difference.

[0012] In one embodiment, adjusting the formation position of each ion implantation structure includes: adjusting the etching parameters multiple times according to the offset direction of the ion implantation structure, and detecting the current electrical data of the memory after each adjustment of the etching parameters; when the current electrical data of the memory is the target electrical data, determining the position of the ion implantation structure formed under the etching parameters as the target position of the ion implantation structure.

[0013] In the ion implantation structure location determination method in the above embodiments, the target location of the ion implantation structure is determined by adjusting the etching parameters multiple times, thus ensuring the accuracy of the location of each ion implantation structure.

[0014] In one embodiment, the step of adjusting the etching parameters includes: determining the adjusted etching parameters based on a preset adjustment distance and the offset direction of the ion implantation structure; and determining the target etching parameters based on the etching parameters and the adjusted etching parameters, so that the ion implantation structure is offset by the adjustment distance in a direction opposite to the offset direction.

[0015] In the method for determining the position of the ion implantation structure in the above embodiments, by adjusting the etching parameters, the ion implantation structure is offset by a distance in a direction opposite to the offset direction, thus ensuring the accuracy of the ion implantation structure formed after etching.

[0016] In one embodiment, the electrical data of the memory includes a threshold voltage and a saturation current.

[0017] In the method for determining the location of the ion implantation structure in the above embodiments, the accuracy of electrical data detection is ensured by using threshold voltage and saturation current.

[0018] In one embodiment, the method further includes: detecting a first angle and a second angle on both sides of the ion implantation structure based on a critical-size scanning electron microscope.

[0019] In the method for determining the position of the ion implantation structure in the above embodiments, by detecting the first angle and the second angle on both sides of the ion implantation structure, the size of the ion implantation structure can be further detected, which can provide data support for adjusting the etching parameters.

[0020] Secondly, embodiments of this disclosure also provide a device for determining the location of an ion implantation structure. The ion implantation structure is formed in a memory, which includes multiple ion implantation structures, multiple polysilicon layers, and multiple metal interconnect layers. The polysilicon layers are located above the ion implantation structures, and the metal interconnect layers are located above the polysilicon layers. The device includes:

[0021] The data acquisition module is used to acquire the first distance value, the second distance value, and the current electrical data of the memory on both sides of the ion implantation structure.

[0022] The position offset direction determination module is used to determine the position offset direction of the ion implantation structure based on the difference between the electrical data in the memory and the target electrical data.

[0023] The position determination module is used to adjust the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure, so that the electrical data of the memory reaches the target electrical data. This ensures that the correct position of the ion implantation structure can be accurately determined even after reducing the structural size of the SRAM (Static Random Access Memory), thus guaranteeing the performance of the SRAM.

[0024] This disclosure also provides an electronic device, including a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the ion implantation structure location determination method described above are performed.

[0025] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the ion implantation structure location determination method described above.

[0026] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A flowchart illustrating the determination of the position of an ion implantation structure provided in one embodiment of this application;

[0029] Figure 2 This is a schematic diagram of a memory provided in one embodiment of this application;

[0030] Figure 3 This is a global schematic diagram of a memory provided in one embodiment of this application;

[0031] Figure 4 This is a partial enlarged view of a memory provided in one embodiment of this application;

[0032] Figure 5 This is a partially enlarged schematic diagram of a storage cell of a memory provided in one embodiment of this application;

[0033] Figure 6 This is a comparative schematic diagram of the ion implantation structure adjustment of the memory provided in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures:

[0035] M1, First NMOS; M2, First PMOS; M3, Second NMOS; M4, Second PMOS; M5, Third NMOS; M6, Fourth NMOS; 301, PU; 302, PD; 303, PG; 401, Ion implantation structure; 402, Polysilicon layer; 403, Metal interconnect layer; 601, Metal contact hole; 602, Ion implantation structure. Detailed Implementation

[0036] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, they identify the presence of features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0042] Please see Figures 1-6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] Please see Figure 2 , Figure 2The schematic diagram of a memory provided in one embodiment of this application is shown below. As an example, a 6T-SRAM is used as an example, and a schematic diagram of a 6T-SRAM is provided. The first NMOSM1, first PMOSM2, second NMOSM3, and second PMOSM4 constitute a bistable circuit for latching digital signals. The third NMOSM5 and fourth NMOSM6 are transmission transistors used to connect or disconnect the memory from the peripheral circuits during read / write operations. Memory access is enabled via the word line (WL). When the word line WL is high, the transmission transistors are turned on, allowing the memory content to be transferred to the bit line BL, and the memory read value to be transferred to the bit line ¯BL. The peripheral circuits read information through BL and ¯BL. During a write operation, the peripheral circuits of the SRAM cell array transfer voltage to BL and ¯BL as input. After the word line WL is enabled, information is written to the memory.

[0044] The memory includes multiple storage units.

[0045] For example, please refer to Figure 3-5 , Figure 3 This is a global schematic diagram of a memory provided in one embodiment of this application. The smallest SRAM cell is called a bit, which can only store one signal, 0 or 1. Such a bit consists of 6 transistors: 2 PMOS (PU301) and 4 NMOS (PD302, PG303). PU301 and PD302 form an inverter, and the two inverters form an interlocked structure, using this characteristic to achieve data storage. PU301 (pull-up), also called a load transistor, functions to achieve a high potential (1) for the node. PD302 (pull-down), also called a drive transistor, functions to achieve a low potential (0) for the node. By switching the high and low potentials of the two nodes in a bit, both 0 and 1 states can be stored. PG303 (pass gate), also called an access transistor, functions to connect the bitline for read and write operations.

[0046] Please see Figure 5 , Figure 5 This is a partially enlarged schematic diagram of a storage cell of a memory provided in one embodiment of this application. For example... Figure 5As shown, the size of PU301 is 110-89.5=20.5nm, the size of PD302 is 211-110=101nm, and the size of PG303 is 229-141=88nm. Deviations in PD302 will lead to etching loading effects, ultimately affecting the feature size of PD302 after etching and the lateral angles of the ion implantation structure 401 after etching. Figure 4 As shown, Figure 4 This is a partial enlarged view of a memory provided in one embodiment of the present application. The metal interconnect layer 403 is formed on the polysilicon layer 402, and the polysilicon layer 402 is formed on the ion implantation structure 401. Figure 4 The angles on both sides of the ion implantation structure 401 after etching are different, which can lead to a series of problems such as reduced current (Ioff) in the cutoff state of PD302. Therefore, when the environment on both sides of the ion implantation structure 401 changes, it is crucial to determine the correct etching parameters to ensure that the ion implantation structure 401 is formed in the correct position and that the electrical data of each memory cell reaches the target electrical data.

[0047] Please see Figure 1 As an example, one aspect of this application provides a method for determining the location of an ion implantation structure 401, comprising:

[0048] S1000: Obtain the first distance value, the second distance value, and the current electrical data of the memory on both sides of the ion implantation structure 401.

[0049] S2000: Determine the position offset direction of the ion implantation structure 401 based on the difference between the current electrical data in the memory and the target electrical data.

[0050] S3000: Adjust the formation position of the ion implantation structure 401 according to the position offset direction of the ion implantation structure 401 so that the electrical data of the memory reaches the target electrical data.

[0051] In the method for determining the position of the ion implantation structure 401 in the above embodiments, the position of the ion implantation structure 401 is adjusted by measuring the electrical data of the memory so that the electrical data of the memory reaches the target electrical data. Therefore, the embodiments of this disclosure can at least accurately determine the correct position of the ion implantation structure 401 after reducing the structural size of the random access static memory (SRAM), thus ensuring the performance of the random access static memory (SRAM).

[0052] In step S1000, as an example, the ion implantation structure 401 can first be etched to position each ion implantation structure 401 at the target location, and the current electrical data of each ion implantation structure 401 at the target location can be detected. For example, please refer to [link to example]. Figure 6, Figure 6 In Figure a, each ion implantation structure 401 is in a standard position.

[0053] In step S1000, since the etching condition may deviate when the environment on both sides of the ion implantation structure 401 changes, CD-SEM can be used to inspect the memory. The size of the ion implantation structure 401 can be increased by using DOE splitting experiments, and the size of PG303 can be increased so that the post-etching inspection (AEI) size of PD302 reaches the standard position.

[0054] Here, CD-SEM (Critical Dimension Scanning Electron Microscopy) is a technique used for measuring critical dimensions in semiconductor manufacturing processes. It combines the capabilities of scanning electron microscopy (SEM) and critical dimension (CD) measurement. CD-SEM is used to precisely measure the dimensions of various structures on semiconductor chips, especially minute pattern features. Critical dimensions (CD) refer to dimensions in semiconductor devices that require strict control. CD-SEM leverages the high resolution of scanning electron microscopy to perform fine dimensional measurements at the nanometer scale. During semiconductor manufacturing, CD-SEM can monitor and measure critical dimension changes in real time during process steps such as photolithography and etching. CD-SEM uses an electron beam to scan the sample surface. The electron beam interacts with atoms on the sample surface, generating secondary electrons, which are received by a detector and converted into images. By scanning different areas, high-resolution images of the sample are generated. From the acquired images, image processing software is used to measure critical dimensions. The software can automatically identify and measure the dimensions of specific pattern features and calculate the deviation between the actual and design dimensions.

[0055] As the memory size is reduced, the environment on both sides of the ion implantation structure 401 becomes more complex. Changes in the environment on both sides of the ion implantation structure 401 can lead to a significant difference between the etched and developed dimensions of the ion implantation structure 401. Therefore, CD-SEM is required to detect the position of the ion implantation structure 401.

[0056] Specifically, when adjusting the etching parameters of the ion implantation structure 401, the DOE splitting experiment can be used to adjust the etching parameters of the ion implantation structure 401. By gradually changing the post-etching position of the ion implantation structure 401, the post-etching inspection (AEI) size of PD302 can be made to reach the standard position.

[0057] Here, DOE (Design of Experiments) is an experimental design method in semiconductor manufacturing and process development, used to study the impact of different factors on the production process or product performance. DOE is a statistical method designed to systematically plan experiments and analyze the impact of multiple variables on the output results. Through DOE, it is possible to effectively identify which variables have a significant impact on the output and to discover the interactions between variables. It is widely used in the semiconductor field, including material selection, equipment parameter optimization, and process optimization. The typical structure of a split experiment is divided into two levels: (1) Whole-Plot: For factors that are difficult to change, the whole-plot determines the combination of these factors and then tests them in a larger experimental unit; (2) Sub-Plot: For factors that are easy to adjust, the sub-plot is conducted based on the whole-plot. The sub-plot is conducted multiple times within the same whole-plot to examine the impact of these easily adjustable factors on the results. For example, etching machine type, etching time, etc. In the split experiment, experiments were first conducted on different etching machine types (overall test), and then the etching time was changed under each etching machine type (sub-test) to observe the effect of time on the etching effect, so that the PDSEM can reach the standard position.

[0058] In one embodiment, the step of obtaining the first distance value and the second distance value on both sides of each ion implantation structure 401 includes: performing a size scan of the ion implantation structure 401 based on a critical size scanning electron microscope, and determining the first distance value and the second distance value between the two sides of the ion implantation structure 401 and other ion implantation structures 401.

[0059] In the method for determining the position of the ion implantation structure 401 in the above embodiments, the ion implantation structure 401 is scanned by a critical size scanning electron microscope to determine the specific position of the ion implantation structure 401.

[0060] In one embodiment, the method further includes: detecting a first angle and a second angle on both sides of the ion implantation structure 401 using a critical-size scanning electron microscope.

[0061] In the method for determining the position of the ion implantation structure 401 in the above embodiments, by detecting the first angle and the second angle on both sides of the ion implantation structure 401, the size of the ion implantation structure 401 can be further detected, which can provide data support for the adjustment of etching parameters.

[0062] Here, by detecting the first and second angles on both sides of the ion implantation structure 401, the size data of the ion implantation structure 401 can be determined, and the characteristic size of PD302 can be determined.

[0063] In step S2000, the position offset direction of each ion implantation structure 401 is determined based on the difference between the current electrical data and the target electrical data, including: determining the offset direction of the ion implantation structure 401 based on the positive or negative value of the difference between the current electrical data and the target electrical data.

[0064] In the position determination method of the ion implantation structure 401 in the above embodiments, the offset direction of the ion implantation structure 401 is determined by the difference between the current electrical data and the target electrical data, which can provide the direction for adjusting the ion implantation structure 401. At the same time, the operator can also determine the moving distance of the ion implantation structure 401 based on the magnitude of the difference.

[0065] As an example, the offset direction of the ion implantation structure 401 can be determined based on the positive and negative values ​​of the difference, where positive and negative values ​​correspond to two opposite directions on both sides of the ion implantation structure 401.

[0066] In step S3000, adjusting the formation position of each ion implantation structure 401 includes: adjusting the etching parameters multiple times according to the offset direction of the ion implantation structure 401, and detecting the current electrical data of the memory after each adjustment of the etching parameters; when the current electrical data of the memory is the target electrical data, determining the position of the ion implantation structure 401 formed under the etching parameters as the target position of the ion implantation structure 401.

[0067] In the method for determining the position of the ion implantation structure 401 in the above embodiments, the target position of the ion implantation structure 401 is determined by adjusting the etching parameters multiple times, thus ensuring the accuracy of the position of each ion implantation structure 401.

[0068] As an example, the position of the ion implantation structure 401 can be shifted by 2nm to one side of the ion implantation structure 401 by adjusting the parameters each time, and the electrical data of the memory can be detected after each parameter adjustment until the target position of the ion implantation structure 401 is determined.

[0069] For example, please refer to Figure 6 Figure b in Figure 6 In Figure b, the distances between the two sides of an ion implantation structure 401 and other ion implantation structures 401 are X1 and X2, respectively. It should be noted that, normally, the distances between the two sides of an ion implantation structure 401 and other ion implantation structures 401 should be the same. However, as the size of the memory shrinks, the changes in the environment on both sides of the ion implantation structure 401 will affect the electrical data of the memory. In this case, the target location of the ion implantation structure 401 can only be determined through DOE experiments.

[0070] Please continue reading. Figure 6 Metal contact holes 601 are also formed on the ion implantation structure 401.

[0071] In step S3000, the step of adjusting the etching parameters includes: determining the adjusted etching parameters according to the preset adjustment distance and the offset direction of the ion implantation structure 401; and determining the target etching parameters according to the etching parameters and the adjusted etching parameters, so that the ion implantation structure 401 is offset by the adjustment distance in the direction opposite to the offset direction.

[0072] In the method for determining the position of the ion implantation structure 401 in the above embodiments, by adjusting the etching parameters, the ion implantation structure 401 is offset by a distance in a direction opposite to the offset direction, thereby ensuring the accuracy of the ion implantation structure 401 formed after etching.

[0073] In one embodiment, the electrical data of the memory includes a threshold voltage and a saturation current.

[0074] In the method for determining the position of the ion implantation structure 401 in the above embodiments, the accuracy of electrical data detection is ensured by using threshold voltage and saturation current.

[0075] Secondly, this disclosure also provides a device for determining the position of an ion implantation structure 401. The ion implantation structure 401 is formed in a memory, which includes a plurality of ion implantation structures 401, a plurality of polysilicon layers 402 and a plurality of metal interconnect layers 403, wherein the polysilicon layers 402 are located above the ion implantation structures 401 and the metal interconnect layers 403 are located above the polysilicon layers 402.

[0076] The device for determining the location of the ion implantation structure includes:

[0077] The data acquisition module is used to acquire the first distance value, the second distance value, and the current electrical data of the memory on both sides of the ion implantation structure.

[0078] The position offset direction determination module is used to determine the position offset direction of the ion implantation structure based on the difference between the electrical data in the memory and the target electrical data.

[0079] The position determination module is used to adjust the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure, so that the electrical data of the memory reaches the target electrical data. This ensures that the correct position of the ion implantation structure can be accurately determined even after reducing the structural size of the SRAM (Static Random Access Memory), thus guaranteeing the performance of the SRAM.

[0080] This disclosure also provides an electronic device, including a processor, a memory, and a bus. The memory stores machine-readable instructions that can be executed by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the position determination method of the ion implantation structure 401 described above are performed.

[0081] Fourthly, embodiments of this disclosure also provide a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the ion implantation structure location determination method described above.

[0082] This application provides a method, apparatus, device, and medium for determining the location of an ion implantation structure 401, which can accurately determine the correct location of the ion implantation structure 401 after reducing the structural size of the SRAM (Static Random Access Memory), thus ensuring the performance of the SRAM.

[0083] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. The above embodiments only illustrate several implementation methods of this disclosure, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those skilled in the art, several modifications and improvements can be made without departing from the concept of this disclosure, and these all fall within the protection scope of this disclosure. Therefore, the protection scope of this patent disclosure should be determined by the appended claims.

Claims

1. A method for determining the location of an ion implantation structure, characterized in that, The ion implantation structure is formed in the memory, which includes multiple ion implantation structures, multiple polysilicon layers, and multiple metal interconnect layers, wherein the polysilicon layers are located above the ion implantation structures, and the metal interconnect layers are located above the polysilicon layers. The location of each ion implantation structure is determined through the following steps: Acquire the first distance value, the second distance value, and the current electrical data of the memory on both sides of the ion implantation structure; The position offset direction of the ion implantation structure is determined based on the difference between the current electrical data and the target electrical data of the memory. Based on the positional offset direction of the ion implantation structure, the formation position of the ion implantation structure is adjusted so that the electrical data of the memory reaches the target electrical data.

2. The location determination method according to claim 1, characterized in that, The steps for obtaining the first and second distance values ​​on both sides of each ion implantation structure include: Using critical size scanning electron microscopy, the ion implantation structure was dimensionally scanned to determine the first and second distance values ​​between the two sides of the ion implantation structure and other ion implantation structures.

3. The location determination method according to claim 1, characterized in that, Based on the difference between the current electrical data and the target electrical data, the position offset direction of each ion implantation structure is determined, including: The offset direction of the ion implantation structure is determined based on the sign of the difference between the current electrical data and the target electrical data.

4. The location determination method according to claim 1, characterized in that, Adjusting the formation location of each ion implantation structure, including: Based on the offset direction of the ion implantation structure, the etching parameters are adjusted multiple times, and after each adjustment of the etching parameters, the current electrical data of the memory is detected. When the current electrical data of the memory is the target electrical data, the position of the ion implantation structure formed under the etching parameters is determined as the target position of the ion implantation structure.

5. The location determination method according to claim 4, characterized in that, The steps for adjusting etching parameters include: The etching parameters are determined based on the preset adjustment distance and the offset direction of the ion implantation structure. Based on the etching parameters and the adjusted etching parameters, the target etching parameters are determined so that the ion implantation structure is offset by an adjustment distance in a direction opposite to the offset direction.

6. The location determination method according to claim 1, characterized in that, The electrical data of the memory includes threshold voltage and saturation current.

7. The location determination method according to claim 1, characterized in that, The method further includes: The first and second angles on both sides of the ion implantation structure were detected using a critical-size scanning electron microscope.

8. A device for determining the location of an ion implantation structure, characterized in that, The ion implantation structure is formed in the memory, which includes multiple ion implantation structures, multiple polysilicon layers, and multiple metal interconnect layers, wherein the polysilicon layers are located above the ion implantation structures, and the metal interconnect layers are located above the polysilicon layers. The device includes: The data acquisition module is used to acquire the first distance value, the second distance value, and the current electrical data of the memory on both sides of the ion implantation structure. The position offset direction determination module is used to determine the position offset direction of the ion implantation structure based on the difference between the electrical data of the memory and the target electrical data. The position determination module is used to adjust the formation position of the ion implantation structure according to the position offset direction of the ion implantation structure, so that the electrical data of the memory reaches the target electrical data.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is in operation, the processor communicates with the memory via the bus, and the processor executes the machine-readable instructions to perform the steps of the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the method as described in any one of claims 1 to 7.

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