Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a plurality of first contacts spaced apart from each other by a predetermined distance in a semiconductor substrate; a plurality of conductive structures formed over the first contact portions, extending in a first direction and spaced apart in a second direction perpendicular to the first direction, each of the plurality of conductive structures partially overlapping each of the first contact portions, each of the plurality of conductive structures has a top surface of a portion overlapping with each of the first contact portions at a lower level than a top surface of a portion not overlapping with each of the first contact portions; a plurality of second contact portions disposed between adjacent conductive structures; and a plurality of spacer structures disposed between the conductive structure and the second contact.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0090664, filed on Jul. 12, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention generally relate to semiconductor devices and methods for fabricating the same, and more particularly, to semiconductor devices including conductive structures and methods for fabricating the same. Background Art

[0004] Recently, as semiconductor devices become more highly integrated, process margins continue to decrease, resulting in processing difficulties. In particular, one such processing difficulty relates to forming contacts because contact openings and bridging margins have a trade-off relationship. Summary of the invention

[0005] Embodiments of the present invention relate to a semiconductor device that can prevent a contact non-open defect and can prevent a bridge from being formed between adjacent conductive structures, and a method for manufacturing the semiconductor device.

[0006] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: providing a semiconductor substrate; forming a plurality of first contacts spaced apart from each other by a predetermined distance above the semiconductor substrate; forming a plurality of conductive structures above the first contacts, the plurality of conductive structures extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, and respectively overlapping with the first contacts; forming a first spacer covering two side walls of each of the conductive structures; forming a plurality of plug material layers arranged between adjacent conductive structures and extending in the first direction; forming a mask pattern partially covering a top portion of the conductive structure and a top portion of the plug material layer; etching the plug material layer exposed by the mask pattern to form a plurality of second contacts spaced apart from each other in the first direction, and providing spacer holes between the first spacers and the second contacts; and forming a second spacer to gap-fill the spacer holes.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a plurality of first contact portions, which are spaced apart from each other by a predetermined distance in a semiconductor substrate; a plurality of conductive structures, which are formed above the first contact portions, extend in a first direction and are spaced apart in a second direction perpendicular to the first direction, each of the plurality of conductive structures partially overlapping with each of the first contact portions, and a top surface of a portion of each of the plurality of conductive structures that overlaps with each of the first contact portions is at a lower level than a top surface of a portion that does not overlap with each of the first contact portions; a plurality of second contact portions, which are arranged between adjacent conductive structures; and a plurality of spacer structures, which are arranged between the conductive structures and the second contact portions.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a plurality of first contact portions, which are spaced apart from each other by a predetermined distance in a semiconductor substrate; a plurality of first conductive structures, which are formed above the first contact portions; a plurality of second conductive structures, which are arranged alternately with the first conductive structures and are formed above a hard mask; a plurality of second contact portions, which are arranged between the first conductive structures and the second conductive structures; a plurality of first spacer structures, which are arranged between the first conductive structures and the second contact portions; and a plurality of second spacer structures, which are arranged between the second contact portions and the second conductive structures, wherein the top surface of the first conductive structure is at a lower level than the top surface of the second conductive structure.

[0009] These and other features and advantages of the present invention will become better understood to those skilled in the art from the detailed description taken in conjunction with the following drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic simplified plan view illustrating a semiconductor device according to one embodiment of the present invention.

[0011] Figure 2A and Figure 2B is a schematic simplified cross-sectional view illustrating a semiconductor device in accordance with one embodiment of the present invention.

[0012] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B is a schematic simplified cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0014] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, throughout the various drawings and embodiments of the present invention, similar reference numerals refer to similar parts.

[0015] The drawings are not necessarily to scale, and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, this refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0016] Figure 1 is a schematic simplified plan view illustrating a semiconductor device according to one embodiment of the present invention. Figure 2A and Figure 2B is a schematic simplified cross-sectional view illustrating a semiconductor device in accordance with one embodiment of the present invention. Figure 2A is along Figure 1 A cross-sectional view taken along line AA' is shown in FIG. Figure 2B is along Figure 1 A cross-sectional view taken along line BB' is shown.

[0017] refer to Figure 1 , Figure 2A and Figure 2B , the semiconductor device may include a plurality of memory cells. Each memory cell may include a conductive structure arranged at a different level. For example, each memory cell may include a cell transistor. The cell transistor may include a buried word line WL, a bit line BL, and a memory element ME.

[0018] The isolation layer 102 may be formed in the substrate 101 and define an active region 103. A plurality of active regions 103 may be defined by the isolation layer 102. Each active region 103 may have a stripe shape having a major axis and a minor axis. The active regions 103 may be disposed to be spaced apart from each other by a predetermined distance.

[0019] The substrate 101 may be formed of a silicon-containing material including, for example, silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, or multilayers thereof. The substrate 101 may also include another semiconductor material, such as, for example, germanium. The substrate 101 may include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as, for example, gallium arsenide (GaAs). The substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0020] A linear buried word line WL extending in the second direction D2 may be formed over the substrate 101. The buried word line WL may include a buried gate structure BG. The buried gate structure BG may include: a gate dielectric layer 106 conformally formed on a surface of the gate trench 105, and a gate electrode 107 and a gate capping layer 108 formed over the gate dielectric layer 106 to fill the gate trench 105.

[0021] For example, a linear gate trench 105 passing through the active area 103 and the isolation layer 102 in the second direction D2 may be formed above the substrate 101. The gate trench 105 may be formed to a predetermined depth in a region defined by a hard mask layer 104 formed on the surface of the substrate 101. The bottom surface of the gate trench 105 may be disposed at a higher level than the bottom surface of the isolation layer 102. In other words, the gate trench 105 may have a shallower depth than the isolation layer 102. According to another embodiment of the present invention, a bottom portion of the gate trench 105 may have a curvature. According to another embodiment of the present invention, the isolation layer 102 in the direction in which the gate trench 105 extends may be etched to a predetermined depth to form a fin in the active area 103.

[0022] The gate dielectric layer 106 may be conformally formed on the surface of the gate trench 105. A gate electrode 107 partially filling the gate trench 105 may be formed above the gate dielectric layer 106. A gate capping layer (sealing layer) 108 filling the remaining portion of the gate trench 105 may be formed above the gate electrode 107. The top surface of the gate capping layer 108 may be disposed at the same level as the top surface of the hard mask layer 104. The top surface of the gate electrode 107 may be disposed at a level lower than the top surface of the substrate 101. The gate electrode 107 may be a low resistance metal material. The gate electrode 107 may include, for example, titanium nitride and tungsten sequentially stacked therein. According to one embodiment of the present invention, the gate electrode 107 may be formed only of titanium nitride (may be only TiN).

[0023] The first impurity region 109 and the second impurity region 110 may be formed over the substrate 101. The first impurity region 109 and the second impurity region 110 may be referred to as "first source / drain region and second source / drain region". The first impurity region 109 and the second impurity region 110 may be provided to be spaced apart from each other by the gate trench 105. Therefore, the gate electrode 107 and the first impurity region 109 and the second impurity region 110 may become a cell transistor. The cell transistor may improve a short channel effect by the gate electrode 107 having a buried gate structure.

[0024] A first contact 111 may be formed over the substrate 101. The first contact 111 may be coupled to the first impurity region 109. The first contact 111 may be disposed in a contact hole having a bottom surface lower than the surface of the substrate 101. In other words, the bottom surface of the first contact 111 may be lower than the top surface of the substrate 101. The bottom surface of the first contact 111 may be lower than the top surface of the active region 103 including the first impurity region 109 and the second impurity region 110. A portion of the first contact 111 may have a line width smaller than the diameter of the contact hole. Therefore, a gap G may be formed on both sides of the first contact 111. The gap G may be independently formed on both sides of the first contact 111. In other words, a pair of hemispherical gaps G facing each other may be disposed on both sides of the first contact 111, and the pair of gaps G may be separated by the first contact 111. The first contact 111 may include a conductive material. For example, the first contact 111 may be formed of polysilicon or a metal material. The first contact 111 may be referred to as a “bit line contact 111 ”.

[0025] The conductive structure BL may be formed over the first contact 111 . The conductive structure BL may be referred to as a “bit line structure BL.” The conductive structure BL may include a stack structure of a bit line 112 and a bit line hard mask 113 . The bit line 112 may be coupled to the substrate 101 through the first contact 111 .

[0026] The bit line 112 and the bit line hard mask 113 may be linear extending in the first direction D1. The conductive structures BL may be arranged to be spaced apart from each other in the second direction D2. A portion of the bit line 112 may be coupled to the first contact portion 111. The line width of the bit line 112 and the line width of the first contact portion 111 may be the same. Therefore, the bit line 112 may extend in one direction while covering the top surface of the first contact portion 111. The bit line 112 may include a metal material. The bit line hard mask 113 may include a dielectric material.

[0027] According to the embodiment of the present invention, the top surface of the conductive structure BL overlapping the first contact 111 may be disposed at a lower level than the top surface of the conductive structure BL not overlapping the first contact 111. The height of the bit line hard mask 113 overlapping the first contact 111 may be lower than the height of the bit line hard mask 113 not overlapping the first contact 111.

[0028] Spacer structures may be formed on sidewalls of the first contact 111 and the conductive structure BL. According to this embodiment of the present invention, the spacer structures of the conductive structure BL overlapping the first contact 111 and the conductive structure BL not overlapping the first contact 111 may be different.

[0029] The spacer structure of the conductive structure BL overlapping the first contact portion 111 may be as follows.

[0030] First, a gap filling spacer 114 may be disposed on both sides of the first contact 111 to fill the gap G. A first spacer 115 formed on both sidewalls of the conductive structure BL and extending in parallel in the direction in which the conductive structure BL extends may be disposed above the gap filling spacer 114. A top surface of the first spacer 115 may be disposed at the same level as a top surface of the conductive structure BL. In other words, a top surface of the first spacer 115 disposed next to the bit line 112 overlapping the first contact 111 may be disposed at a lower level than a top surface of the first spacer 115 disposed next to the bit line 112 not overlapping the first contact 111. A second spacer 117 may be disposed above the first spacer 115. The second spacer 117 may be disposed between the first spacer 115 and the second contact 121. Moreover, the second spacer 117 may cover the top portion of the first spacer 115 and the conductive structure BL. The second spacer 117 may include an air gap spacer 116. The air gap spacer 116 may be disposed to at least partially overlap the bit line 112 in a direction parallel to the substrate surface, but the concept and scope of the present invention are not limited thereto.

[0031] The spacer structure disposed next to the conductive structure BL not overlapping the first contact portion 111 may include a first spacer 115 covering both sides of the conductive structure BL.

[0032] The gap-filling spacers 114, the first spacers 115, and the second spacers 117 may include a dielectric material. For example, the dielectric material may include one selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, and a low-k material, and a combination thereof.

[0033] The second contact 121 may be disposed between adjacent conductive structures BL. The second contact 121 may have a column shape. The second contact 121 may be coupled to the second impurity region 110. The second contact 121 may include a conductive material. For example, the conductive material may include a semiconductor material or a metal material. For example, the semiconductor material may include polysilicon. For example, the metal material may include tungsten (W). According to another embodiment of the present invention, the second contact 121 may include a stacked structure of a semiconductor material and a metal material. According to yet another embodiment of the present invention, the second contact 121 may include a stacked structure of a semiconductor material, an ohmic contact layer, and a metal material. The second contact 121 may be referred to as a "storage node contact 121".

[0034] The conductive structure BL and the second contact 121 may be disposed to be spaced apart from each other by a spacer structure. The spacer structure disposed between the second contact 121 and the conductive structure BL overlapping the first contact 111 may be different from the spacer structure disposed between the second contact 121 and the conductive structure BL not overlapping the first contact 111. For example, the spacer structure between the second contact 121 and the conductive structure BL overlapping the first contact 111 may include a gap-filling spacer 114, a first spacer 115, a second spacer 117, and an air gap spacer 116. The spacer structure between the second contact 121 and the conductive structure BL not overlapping the first contact 111 may include a first spacer 115.

[0035] refer to Figure 2A In the cross-sectional view through the second direction, the spacer structure including the gap filling spacer 114, the first spacer 115, the second spacer 117 and the air gap spacer 116 can be set on one side of the second contact portion 121 to be adjacent to the conductive structure BL overlapping with the first contact portion 111, and the first spacer 115 can be set on the other side of the second contact portion 121 to be adjacent to the conductive structure BL not overlapping with the first contact portion 111.

[0036] refer to Figure 2B In a cross-sectional view through the first direction, the second contact portions 121 may be disposed to be spaced apart from each other by the plug isolation layer 118. The isolation layer 118 may include a dielectric material. The isolation layer 118 may include the same material as the second spacer 117. The isolation layer 118 may be formed simultaneously with the second spacer 117. The isolation layer 118 may be a material formed to be integrated and continuous with the second spacer 117 through a single process.

[0037] The landing pad 123 may be formed over the second contact 121. Adjacent landing pads 123 may be isolated by the interlayer dielectric layer 122. The landing pad 123 may be a structure for interconnection between the second contact 121 and the memory element ME. The landing pad 123 may include a conductive material.

[0038] The memory element ME may be formed above the landing pad 123. The memory element ME may include a capacitor including a storage node. The storage node may include a column type, but the concept and scope of the present invention are not limited thereto. A dielectric layer and a plate node may also be formed above the storage node. In addition to the column shape, the storage node may have a barrel shape. The storage node may be coupled to the second contact portion 121 through the landing pad 123.

[0039] According to another embodiment of the present invention, a differently implemented memory element may be coupled to an upper portion of the second contact 121 .

[0040] Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B is a schematic simplified cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0041] refer to Figure 3A and Figure 3B , an isolation layer 12 may be formed over the substrate 11 to define active regions 13. Each active region 13 may have an elongated strip shape.

[0042] The isolation layer 12 may be formed by a shallow trench isolation (STI) process. The STI process may include etching the substrate 11 to form an isolation trench. The isolation trench may be filled with a dielectric material, and as a result, the isolation layer 12 may be formed. The isolation layer 12 may include silicon oxide, silicon nitride, or a combination thereof. Chemical vapor deposition (CVD) or other deposition processes may be used to fill the isolation trench with a dielectric material. A planarization process such as chemical mechanical polishing (CMP) may be additionally performed.

[0043] Subsequently, a buried gate structure BG may be formed over the substrate 11. The buried gate structure BG may be referred to as a buried word line structure. The buried gate structure BG may be a line type extending in the second direction D2.

[0044] Subsequently, the first impurity region 15 and the second impurity region 16 may be formed. The first impurity region 15 and the second impurity region 16 may be formed by a doping process such as, for example, an implantation process. Hereinafter, the first impurity region 15 and the second impurity region 16 may be referred to as "first source / drain region 15 and second source / drain region 16". The first source / drain region 15 and the second source / drain region 16 may have the same depth. According to another embodiment of the present invention, the first source / drain region 15 may be deeper than the second source / drain region 16. The first source / drain region 15 may be a region to which a bit line contact is to be coupled. The second source / drain region 16 may be a region to which a storage contact is to be coupled.

[0045] Subsequently, a conductive structure BL coupled to the first source / drain region 15 may be formed. The conductive structure BL may be referred to as a “bit line structure BL”. The conductive structure BL may include a stacked structure of a bit line 22 and a bit line hard mask 23. The conductive structure BL may be electrically coupled to the first source / drain region 15 through a first contact 21.

[0046] The method of forming the conductive structure BL may be performed as follows.

[0047] First, the hard mask layer 14 may be etched to form a contact hole. From the perspective of a plan view, the contact hole may have a circular shape or an elliptical shape. A portion of the substrate 11 may be exposed through the contact hole. The contact hole may have a diameter controlled to be a constant line width. The contact hole may have a form that exposes a portion of the active area 13. For example, the first source / drain region 15 may be exposed through the contact hole. The contact hole may have a diameter greater than the width of the short axis of the active area 13. Therefore, in the etching process for forming the contact hole, a portion of the first source / drain region 15 and a portion of the isolation layer 12 may be etched. In other words, the first source / drain region 15 and the isolation layer 12 below the contact hole may be recessed to a predetermined depth. As a result, the bottom portion of the contact hole may be expanded into the substrate 11. Due to the expansion of the contact hole, the first source / drain region 15 may be recessed, and the top surface of the first source / drain region 15 may be set at a level lower than the top surface of the second source / drain region 16.

[0048] Subsequently, a preliminary plug may be formed to gap-fill the contact hole. The preliminary plug may be formed by a selective epitaxial growth (SEG) process. For example, the preliminary plug may include a SEG SiP. In this way, a preliminary plug may be formed without a void by a selective epitaxial growth process. According to another embodiment of the present invention, a preliminary plug may be formed by a polysilicon deposition process and a CMP process. The preliminary plug may fill the contact hole. The top surface of the preliminary plug may be set at the same level as the top surface of the hard mask layer 14.

[0049] Subsequently, a conductive layer and a hard mask material layer may be stacked above the hard mask layer 14 including the preliminary plug. The conductive layer and the hard mask material layer may be sequentially stacked above the preliminary plug and the hard mask layer 14. The conductive layer may include a metal-containing material. The conductive layer may include a metal, a metal nitride, a metal silicide, or a combination thereof. According to this embodiment of the present invention, the conductive layer may include tungsten (W). According to another embodiment of the present invention, the conductive layer may include a stack of titanium nitride and tungsten (TiN / W). In this article, titanium nitride may be used as a barrier. The hard mask material layer may be formed of a dielectric material having an etching selectivity relative to the conductive layer and the preliminary plug. The hard mask material layer may include silicon oxide or silicon nitride.

[0050] Subsequently, a bit line mask layer may be formed over the hard mask material layer. The bit line mask layer may be a mask pattern defining a bit line region. The bit line mask layer may be formed of a material having an etching selectivity relative to the conductive layer and the hard mask material layer. The bit line mask layer may include a photoresist film pattern. The bit line mask layer may be formed by a patterning method such as a spacer patterning technique (SPT) or a double patterning technique (DPT). From the perspective of a plan view, the bit line mask layer may have a line shape extending in a first direction D1.

[0051] Subsequently, the hard mask material layer, the conductive layer, and the preliminary plug may be sequentially etched. As a result, a first contact 21 contacting the substrate 11 and a conductive structure BL may be formed, which is electrically coupled to the substrate 11 through the first contact 21 and includes a bit line 22 and a bit line hard mask 23 stacked therein.

[0052] The line width of the conductive structure BL may be smaller than the diameter of the contact hole. Therefore, a gap G may be formed around the first contact portion 21. The gap G may not have a surrounding shape surrounding the first contact portion 21, but may be independently formed on both sidewalls of the first contact portion 21. As a result, one first contact portion 21 and a pair of gaps G may be provided in the contact hole, and the pair of gaps G may be separated by the first contact portion 21. The bottom surface of the gap G may be provided at the same level as the recessed top surface of the first source / drain region 15. According to another embodiment of the present invention, the bottom surface of the gap G may extend into the isolation layer 12. In other words, the bottom surface of the gap G may be provided at a level lower than the recessed top surface of the first source / drain region 15.

[0053] refer to Figure 4A and Figure 4B , gap-filling spacers 24 filling the gap G may be formed on both sides of the first contact part 21 .

[0054] Subsequently, a first spacer layer 25A may be formed The first spacer layer 25A may be conformally formed along the entire surface including the sidewalls of the bit line 22 and the bit line hard mask 23 .

[0055] The gap-filling spacer 24 and the first spacer layer 25A may include a dielectric material. For example, the dielectric material may include one selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, a low-k material, and a combination thereof.

[0056] refer to Figure 5A and Figure 5B , a first spacer 25 covering both sidewalls of the conductive structure BL may be formed. Etching the first spacer 25 may be performed by, for example, an etch-back process. An etching process for forming the first spacer 25 may be performed, the goal of which is to expose the hard mask layer 14 between adjacent conductive structures BL. The first spacer 25 may extend in a first direction D1 in which the conductive structure BL extends.

[0057] Subsequently, a recess R exposing a portion of the active region 13 may be formed by etching the exposed hard mask layer 14. To form the recess R, the hard mask layer 14, the isolation layer 12, and the second source / drain region 16 may be etched to a predetermined depth. The recess R may extend into the substrate 11. A bottom surface of the recess R may be disposed at a lower level than a top surface of the first contact portion 21. A bottom surface of the recess R may be disposed at a higher level than a bottom surface of the first contact portion 21.

[0058] The second contact region SH may be exposed due to the formation of the first spacer 25 and the recess R. The first spacer 25 may be formed on the sidewall of the line-type conductive structure BL extending in the first direction D1. Therefore, the region exposed by the first spacer 25 and the recess R may be a line-type spaced apart by the conductive structure BL in the second direction D2 and extending in the first direction D1.

[0059] refer to Fig. 6A and Figure 6B , a plug material layer 31A may be formed to gap-fill the second contact region SH (see Figure 5B The plug material layer 31A may be formed so that all line-type second contact regions SH exposed by the conductive structure BL (see Figure 5B ) is gap-filled. As a result, a plug material layer 31A of a line type extending in the first direction D1 may be formed. The plug material layers 31A of a line type may be spaced apart from each other in the second direction D2. The plug material layer 31A may be spaced apart from the conductive structure BL and the first contact portion 21 by a distance d1 in the second direction D2.

[0060] The plug material layer 31A may include a conductive material. The plug material layer 31A may include a material having an etch selectivity with respect to the bit line hard mask 23 and the first spacer 25. For example, the plug material layer 31A may include polysilicon, but the concept and scope of the present invention are not limited thereto.

[0061] refer to Fig. 7A and Figure 7B , a mask pattern MP may be formed. The mask pattern MP may be provided to define the second contact portion. The mask pattern MP may have an elliptical shape, but the concept and scope of the present invention are not limited thereto. The mask pattern MP may partially cover the top surface of the plug material layer 31A and the top surface of the conductive structure BL. The mask pattern MP may cover a portion of the plug material layer 31A. The mask pattern MP may cover the top surface of the conductive structure BL that does not overlap with the first contact portion 21. In other words, the elliptical mask pattern MP may cover the plug material layer 31A disposed on both sides of the conductive structure BL that does not overlap with the first contact portion 21.

[0062] In other words, the mask pattern MP may be patterned so that all regions except the plug material layer 31A to be coupled to the memory element in a subsequent process may be open. The mask pattern MP may expose: the first spacer 25 and the plug material layer 31A contacting both sidewalls of the conductive structure BL overlapping the first contact portion 21, and the conductive structure BL overlapping the first contact portion 21.

[0063] refer to Fig. 8A and Figure 8B, the second contact portion 31 may be formed. The plug material layer 31A exposed by the mask pattern MP may be etched (see Figure 7B ) to form the second contact 31. The second contact 31 may be referred to as a “storage node contact 31”.

[0064] The second contact portions 31 may be disposed to be spaced apart from each other in the first direction D1. Also, a spacer hole BSH may be formed between the second contact portion 31 and the first spacer 25 of the conductive structure BL overlapping the first contact portion 21. The spacer hole BSH may be formed by a self-aligned etching process performed by the conductive structure BL. In other words, the spacer hole BSH may be formed between the first spacer 25 and the second contact portion 31 because the plug material layer 31A exposed by the mask pattern MP is etched, and the top surface of the conductive structure BL exposed by the mask pattern MP and overlapping the first contact portion 21 is not etched but maintained.

[0065] For this reason, even if the first contact 21 and the conductive structure BL are misaligned in the previous process, since the first contact 21 exposed by the self-aligned etching process can be etched, bridging between the first contact 21 and the second contact 31 due to the misalignment can be prevented.

[0066] Also, by covering the minimum area with the mask pattern MP and performing a self-aligned etching process, process difficulty may be reduced, and non-opening may be prevented by increasing an etching area.

[0067] In addition, despite the Figure 6B The distance between the plug material layer 31A and the first contact portion 21 and the conductive structure BL is "d1", but the distance between the second contact portion 31 and the first contact portion 21 and the conductive structure BL may be "d2" which is greater than d1. Therefore, bridging between the second contact portion 31 and the first contact portion 21 may be prevented, and parasitic capacitance between the second contact portion 31 and the first contact portion 21 and the conductive structure BL may be prevented.

[0068] When forming the second contact 31, a portion of the thickness of the conductive structure BL and the first spacer 25 exposed by the mask pattern MP and overlapping the first contact 21 may be etched. Therefore, the top surface of the conductive structure BL exposed by the mask pattern MP may be disposed at a lower level than the top surface of the conductive structure BL covered by the mask pattern MP. In other words, the top surface of the conductive structure BL overlapping the first contact 21 may be disposed at a lower level than the top surface of the conductive structure BL not overlapping the first contact 21.

[0069] refer to Fig.9A and Fig. 9B, a second spacer 27 may be formed to gap-fill the spacer hole BSH (see Figure 8B The second spacer 27 may cover the spacer hole BSH (see Figure 8B ) and the top surface of the conductive structure BL that overlaps with the first contact portion 21. The second spacer 27 may be a plug isolation layer that gap-fills the space between the second contacts 31 spaced apart in the first direction D1. In other words, the second spacer 27 and the plug isolation layer may be an integrated material that is simultaneously formed by a single process. Therefore, the second spacer 27 may be continuous with the plug isolation layer. The second spacer 27 may be formed of the same material as that of the plug isolation layer. The top surface of the second spacer 27 may be disposed at the same level as the top surface of the second contact portion 31 and the top surface of the conductive structure BL that does not overlap with the first contact portion 21.

[0070] The second spacer 27 may include a dielectric material. For example, the dielectric material may include one selected from the group consisting of silicon nitride, silicon oxide, silicon oxynitride, and low-k materials, and combinations thereof. In particular, according to this embodiment of the present invention, the second spacer 27 may include a material having poor gap filling properties.

[0071] The second spacer 27 may provide an air gap spacer 26. When forming the second spacer 27, the air gap spacer 26 may be formed by a gap-filling margin of a dielectric material. The air gap spacer 26 may partially overlap the bit line 22 in a direction parallel to the substrate surface, but the concept and scope of the present invention are not limited thereto.

[0072] refer to Fig. 10A and Fig. 10B , the landing pad 33 may be formed over the second contact portion 31. The landing pad 33 may be disposed to be spaced apart by the interlayer dielectric layer 32. From a plan view perspective, the landing pad 33 may be formed in an island type.

[0073] Subsequently, a memory element 34 may be formed over the landing pad 33 .

[0074] The memory element 34 may include a capacitor including a storage node. The storage node may include a column shape, but the concept and scope of the present invention are not limited thereto. A dielectric layer and a plate node may also be formed above the storage node. In addition to the column shape, the storage node may have a barrel shape.

[0075] According to the embodiments of the present invention, non-opening of contacts and bridging between adjacent conductive structures can be prevented, which improves the reliability of semiconductor devices.

[0076] While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate; forming a plurality of first contacts spaced apart from each other by a predetermined distance over the semiconductor substrate; forming a plurality of conductive structures above the first contact portion, the plurality of conductive structures extending in a first direction, being spaced apart from each other in a second direction perpendicular to the first direction, and respectively overlapping with the first contact portion; forming a first spacer covering two sidewalls of each of the conductive structures; forming a plurality of plug material layers disposed between adjacent conductive structures and extending in the first direction; forming a mask pattern partially covering a top portion of the conductive structure and a top portion of the plug material layer; etching the plug material layer exposed by the mask pattern to form a plurality of second contacts spaced apart from each other in the first direction and to provide a spacer hole between the first spacer and the second contact; as well as A second spacer is formed to gap-fill the spacer hole. 2 . The method of claim 1 , wherein the spacer hole is formed by a self-aligned etching process using the conductive structure exposed by the mask pattern. 3 . The method of claim 1 , wherein the conductive structure exposed by the mask pattern is the conductive structure overlapping each of the first contacts. The method according to claim 1 , wherein the mask pattern has an elliptical shape. 5 . The method of claim 1 , wherein the mask pattern has an elliptical shape covering the plug material layer disposed on both sides of the conductive structure not overlapping the first contact portion. The method of claim 1 , wherein the second spacer covers a top portion of the conductive structure overlapping the first contact. 7 . The method of claim 1 , wherein forming the second spacer is performed simultaneously with forming a plug isolation layer formed to gap-fill a space between the second contacts spaced apart from each other in the first direction. 8 . The method of claim 1 , wherein the second spacer comprises a dielectric material having poor gap-filling properties.

9. The method of claim 1, wherein the second spacer provides an air gap spacer. 10 . The method of claim 9 , wherein the air gap spacer partially overlaps the conductive structure in a direction parallel to a surface of the substrate.

11. The method according to claim 1, wherein in forming the second contact portion, The top portion of the conductive structure exposed by the mask pattern is etched to a predetermined thickness to have a top surface lower than a top surface of the conductive structure covered by the mask pattern.

12. The method of claim 1, wherein the first contact comprises a bit line contact, and The second contact includes a storage node contact. 13 . The method according to claim 1 , wherein the conductive structure comprises a stack structure of a bit line and a bit line hard mask.

14. The method according to claim 1, further comprising: forming a landing pad over the second contact; as well as A memory element is formed over the landing pad.

15. The method according to claim 1, further comprising: Before forming the first contact portion, forming a buried gate structure in the substrate; as well as Impurity regions spaced apart from each other by the buried gate structure are formed in the substrate.

16. A semiconductor device comprising: a plurality of first contacts spaced apart from each other by a predetermined distance in the semiconductor substrate; a plurality of conductive structures formed above the first contacts, extending in a first direction and spaced apart in a second direction perpendicular to the first direction, each of the plurality of conductive structures partially overlapping with each of the first contacts, and each of the plurality of conductive structures having a portion overlapping with each of the first contacts having a top surface at a lower level than a portion not overlapping with each of the first contacts; a plurality of second contact portions disposed between adjacent conductive structures; as well as A plurality of spacer structures are disposed between the conductive structure and the second contact portion. 17 . The semiconductor device of claim 16 , wherein the spacer structure has different stacking structures on a sidewall of the conductive structure overlapping the first contact and a sidewall of the conductive structure not overlapping the first contact.

18. The semiconductor device according to claim 16, wherein in the spacer structure, The thickness of the sidewall of the conductive structure overlapping the first contact portion is greater than the thickness of the sidewall of the conductive structure not overlapping the first contact portion.

19. The semiconductor device of claim 16, wherein the spacer structure comprises: A stacked structure of a gap-fill spacer, a first spacer, an air-gap spacer, and a second spacer on a sidewall of the conductive structure overlapping the first contact. 20 . The semiconductor device of claim 19 , wherein the air gap spacer partially overlaps the conductive structure in a direction parallel to a surface of the substrate. 21 . The semiconductor device of claim 16 , wherein the spacer structure comprises a first spacer on a sidewall of the conductive structure that does not overlap the first contact. 22 . The semiconductor device of claim 16 , wherein a bottom surface of the first contact is disposed at a lower level than a top surface of the substrate.

23. The semiconductor device according to claim 16, wherein the second contacts are spaced apart from each other in the first direction, and the semiconductor device further comprises: A plug isolation layer has a gap filling space between the second contact portions spaced apart from each other in the first direction. 24 . The semiconductor device of claim 16 , wherein the first contact is a bit line contact, and the second contact is a storage node contact. 25 . The semiconductor device of claim 16 , wherein the conductive structure comprises a stacked structure of a bit line and a bit line hard mask.

26. A semiconductor device comprising: a plurality of first contacts spaced apart from each other by a predetermined distance in the semiconductor substrate; a plurality of first conductive structures formed above the first contacts; a plurality of second conductive structures arranged alternately with the first conductive structures and formed over the hard mask; a plurality of second contact portions, which are arranged between the first conductive structure and the second conductive structure; a plurality of first spacer structures disposed between the first conductive structure and the second contact portion; as well as a plurality of second spacer structures disposed between the second contact portion and the second conductive structure, Wherein a top surface of the first conductive structure is at a lower level than a top surface of the second conductive structure.

27. The semiconductor device of claim 26, wherein the first conductive structure and the second conductive structure are a single continuous conductive line in a first direction. 28 . The semiconductor device of claim 26 , wherein the first spacer structure and the second spacer structure have different stack structures.

29. The semiconductor device of claim 26, wherein a thickness of the first spacer structure is greater than a thickness of the second spacer structure. 30 . The semiconductor device of claim 26 , wherein the first spacer structure comprises a stack structure of a gap-filling spacer, a first spacer, an air-gap spacer, and a second spacer.

31. The semiconductor device of claim 26, wherein the second spacer structure comprises a first spacer. 32 . The semiconductor device of claim 26 , wherein a bottom surface of the first contact is disposed at a lower level than a bottom surface of the hard mask.

33. The semiconductor device of claim 26, wherein the first contact is a bit line contact, and the second contact is a storage node contact.

34. The semiconductor device of claim 26, wherein the first conductive structure and the second conductive structure include a stacked structure of a bit line and a bit line hard mask.

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