Semiconductor package

Abstract

A semiconductor package is provided. The semiconductor package includes: a first lead frame and a second lead frame opposite to each other; and a semiconductor element disposed between the first lead frame and the second lead frame, in which the semiconductor element is connected to the first lead frame through a first contact portion and to the second lead frame through a second contact portion. The second lead frame includes a plurality of protrusions protruding toward the semiconductor element.

Description

Technical Field

[0001] The following description relates to a semiconductor package. Background Art

[0002] As semiconductor elements are developed, highly integrated semiconductor packages are being produced.

[0003] If heat is generated internally when a semiconductor element included in a semiconductor package operates and the internal heat is not dissipated to the outside, the temperature of the semiconductor element may rise and a failure rate of the semiconductor element may increase.

[0004] In particular, since a power semiconductor package can be driven using a high voltage and a high current, the heat generated when the semiconductor element is driven increases. The performance of the power semiconductor element may deteriorate and energy loss may occur, or the insulating layer inside the power semiconductor may be damaged, so that the reliability is reduced due to the heat generated when the power semiconductor package is driven.

[0005] On the other hand, it is necessary to maintain thermal durability and physical strength of a support substrate supporting a semiconductor element within a semiconductor package, and at the same time, efforts are required to prevent a complicated manufacturing process or defects such as disconnection of a connection portion.

[0006] The above information is presented only as background information to help understand the present disclosure. The above description should not be interpreted as these contents belonging to the prior art of the present disclosure. Summary of the invention

[0007] This summary is provided to introduce selected concepts in a simplified form, and these concepts are further described in the following detailed description. This summary is neither intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] According to one aspect of the present disclosure, a semiconductor package includes: a first lead frame and a second lead frame, which are opposite to each other; and a semiconductor element, which is arranged between the first lead frame and the second lead frame, wherein the semiconductor element is connected to the first lead frame through a first contact portion and connected to the second lead frame through a second contact portion, and wherein the second lead frame includes a plurality of protrusions protruding toward the semiconductor element.

[0009] The second lead frame may include a hole overlapping the second contact portion.

[0010] A cross section of each of the plurality of protrusions cut in a direction parallel to the height direction may have a semicircular shape.

[0011] The second lead frame may include a first portion and a second portion spaced apart from each other, and the plurality of protrusions may include a first protrusion included in the first portion and a second protrusion included in the second portion.

[0012] A width of the first protrusion may be substantially equal to a width of the second protrusion.

[0013] The hole may overlap with the second protrusion.

[0014] Lower surfaces of the plurality of protrusions may be flat.

[0015] The second lead frame may include a first portion and a second portion spaced apart from each other, the plurality of protrusions may include a first protrusion in the first portion and a second protrusion in the second portion, and the hole may include a first hole overlapping the first protrusion in the first portion and a second hole overlapping the second protrusion in the second portion.

[0016] A width of the first protrusion in the first portion may be substantially equal to a width of the second protrusion in the second portion.

[0017] The width of the first hole may be substantially equal to the width of the second hole.

[0018] A width of the first protrusion in the first portion may be different from a width of the second protrusion in the second portion.

[0019] The width of the first hole may be different from the width of the second hole.

[0020] The first lead frame may include: a first frame portion, on which the semiconductor element is mounted; a second frame portion, which is spaced apart from the first frame portion, is configured to receive a first signal from an external source, and is arranged in a non-overlapping manner relative to the semiconductor element; and a third frame portion, which is spaced apart from the first frame portion and is arranged in a non-overlapping manner relative to the semiconductor element, wherein the semiconductor package further includes: a third contact portion, which is arranged between the second lead frame and the semiconductor element; a fourth contact portion, which is arranged between the second frame portion and the second lead frame and is configured to have conductivity; and a spacer, which is arranged between the third frame portion and the second lead frame.

[0021] A thickness of the fourth contact portion may be substantially equal to a thickness of the spacer.

[0022] According to another aspect of the present disclosure, a semiconductor package includes: a first lead frame, including a first frame portion, a second frame portion and a third frame portion, a semiconductor element is mounted on the first frame portion, the second frame portion is spaced apart from the first frame portion, is configured to receive a first signal from an external source, and is arranged in a non-overlapping manner relative to the semiconductor element, the third frame portion is spaced apart from the first frame portion and is arranged in a non-overlapping manner relative to the semiconductor element; a second lead frame, opposite to the first lead frame; a contact portion, arranged between the second frame portion and the second lead frame and configured to have conductivity; and a spacer, arranged between the third frame portion and the second lead frame.

[0023] A thickness of the contact portion may be substantially equal to a thickness of the spacer.

[0024] The second lead frame includes a plurality of protrusions protruding toward the semiconductor element.

[0025] A cross section of each of the plurality of protrusions cut in a direction parallel to the height direction may have a semicircular shape.

[0026] Lower surfaces of the plurality of protrusions may be flat.

[0027] The second lead frame may include a first portion and a second portion spaced apart from each other, the plurality of protrusions may include a first protrusion and a second protrusion, the first protrusion being included in the first portion, the second protrusion being included in the second portion, and a width of the first protrusion in the first portion being different from a width of the second protrusion in the second portion.

[0028] Other features and aspects will be readily apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An exploded perspective view of an example semiconductor package according to one or more embodiments is shown.

[0030] Figure 2 Shown along Figure 1 A cross-sectional view taken along line II'.

[0031] Figure 3 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0032] Figure 4 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0033] Figure 5A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0034] Figure 6 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0035] Figure 7 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0036] Figure 8 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0037] Fig. 9 A cross-sectional view of an example semiconductor package is shown in accordance with one or more embodiments.

[0038] Throughout the drawings and detailed description, like reference numerals refer to like elements unless otherwise described. The drawings may not be drawn to scale, and the relative size, proportion, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0039] Hereinafter, although examples of the present disclosure will be described in detail with reference to the accompanying drawings, it should be noted that the examples are not limited thereto.

[0040] The following specific embodiments are provided to help the reader gain a comprehensive understanding of the methods, devices and / or systems described herein. However, after understanding the present disclosure, various changes, modifications and equivalents of the methods, devices and / or systems described herein will be readily understood. For example, the order of operations described herein is merely an example and is not limited to the order of operations set forth herein, but in addition to operations that must occur in a particular order, changes that will be readily understood after understanding the present disclosure may be made. In addition, for increased clarity and brevity, descriptions of features known in the art may be omitted.

[0041] The features described herein may be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many possible ways to implement the methods, devices, and / or systems described herein that will be readily understood after understanding the present disclosure.

[0042] Throughout the specification, when an element such as a layer, a region, or a substrate is described as being "on", "connected to", or "coupled to" another element, the element may be directly "on", "connected to", or "coupled to" another element, or one or more other elements may be present between the element and the other element. In contrast, when an element is described as being "directly on", "directly connected to", or "directly coupled to" another element, there are no other elements present between them.

[0043] As used herein, the term "and / or" includes any one of the associated listed items or any combination of any two or more items; similarly, "at least one of..." includes any one of the associated listed items or any combination of any two or more items.

[0044] Although terms such as "first", "second", and "third" may be used herein to describe various members, components, regions, layers, or portions, these members, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or portion from another member, component, region, layer, or portion. Therefore, without departing from the teachings of the examples described herein, the first member, first component, first region, first layer, or first portion referred to in the examples may also be referred to as the second member, second component, second region, second layer, or second portion.

[0045] For ease of description, spatially relative terms such as "above," "above," "below," and "below" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. Such spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, an element described as being "above" or "above" relative to another element will be "below" or "below" relative to the other element. Therefore, the term "above" includes both above and below orientations depending on the spatial orientation of the device. The device may also be positioned in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used herein will be interpreted accordingly.

[0046] The terms used herein are only used to describe various examples and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, singular expressions (e.g., "a", "an", and "the" are also intended to include plural expressions. The terms "include", "comprises", and "have" list the existence of stated features, quantities, operations, components, elements, and / or combinations thereof, but do not exclude the existence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0047] Variations in the shapes shown in the drawings may occur due to manufacturing techniques and / or tolerances. Therefore, the examples described herein are not limited to the specific shapes shown in the drawings but include variations in shapes that occur during manufacturing.

[0048] Here, it is noted that use of the term “may” with respect to an example (eg, with respect to what an example may include or implement) means that there is at least one example that includes or implements such a feature, but is not limited to all examples including or implementing such a feature.

[0049] The features of the examples described herein can be combined in various ways that will be readily understood after understanding the present disclosure. In addition, although the examples described herein have various configurations, other configurations that will be readily understood after understanding the present disclosure are feasible.

[0050] Throughout one or more examples, patterns, vias, surfaces, lines, and electrical connection structures may include metal materials (e.g., conductive materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc.), and may be formed according to plating methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, subtractive process, additive process, semi-additive process (SAP), modified semi-additive process (MSAP), etc., but this is not restrictive.

[0051] Throughout one or more examples, the dielectric layer and / or the insulating layer may be implemented with a thermosetting resin such as FR-4, liquid crystal polymer (LCP), low temperature co-fired ceramic (LTCC) or epoxy resin, a thermoplastic resin such as polyimide, a resin formed by impregnating an inorganic filler and / or a core material such as glass fiber (e.g., glass fabric with glass cloth as an example) in a thermosetting resin or a thermoplastic resin, for example, the dielectric layer and / or the insulating layer may be implemented with a prepreg, Ajinomoto built-up film (ABF), FR-4, bismaleimide triazine (BT), a photosensitive dielectric (PID) resin, a typical copper clad laminate (CCL), glass, a ceramic-based insulating material, etc.

[0052] Throughout one or more examples, the radio frequency (RF) signal may have a format according to, by way of example only, the following protocols: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), Enhanced High Speed ​​Packet Access (HSPA+), Enhanced High Speed ​​Downlink Packet Access (HSDPA+), Enhanced High Speed ​​Uplink Packet Access (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G), fourth generation mobile communication technology (4G), fifth generation mobile communication technology (5G), and any other wireless and wired protocols specified hereinafter.

[0053] One or more examples may provide a semiconductor package that can dissipate heat inside the semiconductor package without complicating a manufacturing process.

[0054] Reference Figure 1 and Figure 2 , an example semiconductor package CHPK1 according to one or more embodiments will be described. Figure 1 is an exploded perspective view of an example semiconductor package according to one or more embodiments, and Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0055] Reference Figure 1 and Figure 2 , an example semiconductor package CHPK1 according to one or more embodiments may include first and second lead frames LF1 and LF2 opposite to each other, a plurality of semiconductor components SCP disposed between the first and second lead frames LF1 and LF2, and a molding part ML sealing the plurality of semiconductor components SCP.

[0056] Reference Figure 1 The first lead frame LF1 may include a mounting portion MP on which a plurality of semiconductor elements SCP are mounted, a wiring portion LP spaced apart from the mounting portion MP, a lead portion DL extending from the wiring portion LP to the outside and receiving a signal from the outside, a first connection portion CP1 extending outward from the mounting portion MP to assemble and connect to the semiconductor elements, and a first connection hole CPH1 formed at the first connection portion CP1.

[0057] The second lead frame LF2 may include a mounting portion MP on which the plurality of semiconductor elements SCP are mounted, a second connection portion CP2 extending outwardly from the mounting portion MP to assemble and connect to the semiconductor elements, and a second connection hole CPH2 formed at the second connection portion CP2.

[0058] The first lead frame LF1 and the second lead frame LF2 may include metal and may be made using a single layer. In an example, the first lead frame LF1 and the second lead frame LF2 may include at least one of copper (Cu), nickel (Ni), and iron (Fe). However, the embodiment is not limited thereto.

[0059] Reference Figure 2 , the first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0060] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1. The first frame portion LF1A of the first lead frame LF1 may be Figure 1 The mounting portion MP is provided, but the embodiment is not limited thereto.

[0061] The first signal may be applied from the outside to the second frame portion LF1B of the first lead frame LF1 through the lead-out portion DL, and the second frame portion LF1B of the first lead frame LF1 may be Figure 1 However, the embodiment is not limited thereto. The second frame portion LF1B of the first lead frame LF1 may not overlap the semiconductor component SCP along the height direction DRH.

[0062] The electrical signal may not be applied to the third frame portion LF1C of the first lead frame LF1. However, the embodiment is not limited thereto. The third frame portion LF1C of the first lead frame LF1 may not overlap the semiconductor component SCP in the height direction DRH.

[0063] The semiconductor component SCP may be physically and / or electrically connected to the fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 through the second contact portion SP2A and the third contact portion SP2B.

[0064] The second frame portion LF1B of the first lead frame LF1 may be physically and / or electrically connected to the fourth frame portion LF2A of the second lead frame LF2 through the fourth contact portion SP3, so that the first signal applied to the second frame portion LF1B of the first lead frame LF1 through the lead-out portion DL is applied to the semiconductor element SCP through the fourth contact portion SP3, the fourth frame portion LF2A of the second lead frame LF2, and the second contact portion SP2A. In an example, the semiconductor element SCP may be a power semiconductor element, the semiconductor element SCP may receive the first signal applied to the second frame portion LF1B of the first lead frame LF1 through the fourth contact portion SP3, and the first signal may be a power signal.

[0065] The second signal may be applied to the fifth frame portion LF2B of the second lead frame LF2, and the second signal applied to the fifth frame portion LF2B of the second lead frame LF2 may be applied to the semiconductor element SCP through the third contact portion SP2B.

[0066] Each of the first contact portion SP1 , the second contact portion SP2A, the third contact portion SP2B, and the fourth contact portion SP3 may include solder paste, but the embodiment is not limited thereto.

[0067] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0068] The thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0069] In an example, the spacer SPS may include an insulating material.

[0070] Therefore, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 can be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0071] Surfaces of the fourth and fifth frame portions LF2A and LF2B of the second lead frame LF2 that are physically and / or electrically connected to the semiconductor element SCP through the second and third contact portions SP2A and SP2B, respectively, may include a plurality of first protrusions PR1 protruding toward the semiconductor element SCP along the height direction DRH.

[0072] The second and third contact portions SP2A and SP2B may contact the plurality of first protrusions PR1 of surfaces of the fourth and fifth frame portions LF2A and LF2B, respectively.

[0073] A cross section of the plurality of first protrusions PR1 of the surfaces of the fourth frame portion LF2A and the fifth frame portion LF2B taken in a direction parallel to the height direction DRH may have a semicircular shape, but the embodiment is not limited thereto.

[0074] The width of the first protrusion PR1 of the fourth frame portion LF2A may be almost the same as the width of the first protrusion PR1 of the fifth frame portion LF2B. For example, throughout the specification, the maximum width of the first protrusion PR1 of the fourth frame portion LF2A in the above-mentioned cross section may be almost the same as the maximum width of the first protrusion PR1 of the fifth frame portion LF2B in the above-mentioned cross section.

[0075] The surface of the fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 that is physically connected and / or electrically connected to the semiconductor element SCP may include a plurality of first protrusions PR1, thereby increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2 to improve bonding reliability. The interval between the semiconductor element SCP and the second lead frame LF2 may be maintained so that heat generated in the semiconductor element SCP is easily transferred to the outside.

[0076] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0077] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0078] like Figure 1 As shown, the lead portion DL, the first connection portion CP1, and the first connection hole CPH1 of the first lead frame LF1 and the second connection portion CP2 and the second connection hole CPH2 of the second lead frame LF2 may be exposed to the outside of the molding portion ML.

[0079] As only an example, in an example, the molded portion ML may include a polymer having excellent insulation and protection properties, and in an example, the molded portion ML may include an epoxy mold compound (EMC) or a polyimide-based material.

[0080] In the semiconductor package CHPK1 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0081] In the semiconductor package CHPK1 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a plurality of first protrusions PR1, so that the bonding reliability is improved by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 can be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0082] In the semiconductor package CHPK1 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0083] Reference Figure 3 , an example semiconductor package CHPK2 according to one or more embodiments will be described. Figure 3 is a cross-sectional view of a semiconductor package according to one or more embodiments.

[0084] Reference Figure 3 , the semiconductor package CHPK2 according to one or more embodiments is similar to the semiconductor package CHPK2 according to the previous reference Figure 1 and Figure 2 The semiconductor package CHPK1 of the described embodiment is similar, and detailed description of the same constituent elements is omitted.

[0085] The semiconductor package CHPK2 according to one or more embodiments may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor components SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor components SCP.

[0086] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0087] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0088] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0089] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0090] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0091] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0092] Surfaces of the fourth and fifth frame portions LF2A and LF2B of the second lead frame LF2 that are physically and / or electrically connected to the semiconductor element SCP through the second and third contact portions SP2A and SP2B, respectively, may include a plurality of first protrusions PR1 protruding toward the semiconductor element SCP along the height direction DRH.

[0093] The second and third contact portions SP2A and SP2B may contact the plurality of first protrusions PR1 of surfaces of the fourth and fifth frame portions LF2A and LF2B, respectively.

[0094] The plurality of first protrusions PR1 of the surfaces of the fourth frame portion LF2A and the fifth frame portion LF2B may have a hemispherical shape, but the embodiment is not limited thereto.

[0095] The width of the first protrusion PR1 of the fourth frame portion LF2A and the width of the first protrusion PR1 of the fifth frame portion LF2B may be almost the same.

[0096] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0097] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0098] Unlike the semiconductor package CHPK1 according to the above-described embodiment, in the semiconductor package CHPK2 according to the present embodiment, at least one of the plurality of first protrusions PR1 of the second lead frame LF2 may include a first alignment hole (or first alignment hole) SPH1. For example, the first protrusion PR1 of the fourth frame portion LF2A of the second lead frame LF2 may include the first alignment hole SPH1, and the first filling layer FL1 may be disposed in the first alignment hole SPH1. As an example, the first protrusion PR1 may include the first alignment hole SPH1 may mean that the first protrusion PR1 overlaps the first alignment hole SPH1.

[0099] The alignment accuracy of the semiconductor component SCP and the second lead frame LF2 overlapping each other in the height direction DRH may be improved by the first alignment hole SPH1 formed at the first protrusion PR1 of the second lead frame LF2, thereby reducing misalignment.

[0100] As an example only, the first alignment hole SPH1 of the second lead frame LF2 may be formed by any one of stamping, drilling and etching. The first filling layer FL1 may include a conductive material, but the embodiment is not limited thereto. The first filling layer FL1 may include a conductive material to prevent degradation of the connection characteristics between the first protrusion PR1 of the second lead frame LF2 and the semiconductor element SCP.

[0101] In the semiconductor package CHPK2 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0102] In the semiconductor package CHPK2 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a plurality of first protrusions PR1, thereby improving the bonding reliability by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 may be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0103] In the semiconductor package CHPK2 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 is prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0104] In the semiconductor package CHPK2 according to the embodiment, alignment accuracy of the semiconductor component SCP and the second lead frame LF2 overlapping each other in the height direction DRH may be improved by the first alignment hole SPH1 formed at the first protrusion PR1 of the second lead frame LF2, thereby reducing misalignment.

[0105] Many features of the example semiconductor package CHPK1 according to the above-described embodiments are applicable to the example semiconductor package CHPK2 according to the present embodiment.

[0106] Reference Figure 4 , an example semiconductor package CHPK3 according to one or more embodiments will be described. Figure 4 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0107] Reference Figure 4 , the example semiconductor package CHPK3 according to one or more embodiments is similar to the example semiconductor packages CHPK1 and CHPK2 according to the above-described embodiments. Detailed descriptions of the same constituent elements are omitted.

[0108] The example semiconductor package CHPK3 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor elements SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor elements SCP.

[0109] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B spaced apart from each other.

[0110] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0111] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0112] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0113] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0114] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0115] Surfaces of the fourth and fifth frame portions LF2A and LF2B of the second lead frame LF2 that are physically and / or electrically connected to the semiconductor element SCP through the second and third contact portions SP2A and SP2B, respectively, may include a plurality of second protrusions PR2 protruding toward the semiconductor element SCP along the height direction DRH.

[0116] The second and third contact portions SP2A and SP2B may contact the plurality of second protrusions PR2 of surfaces of the fourth and fifth frame portions LF2A and LF2B, respectively.

[0117] Unlike the first protrusions PR1 of the example semiconductor packages CHPK1 and CHPK2 according to the above-described embodiments, in the semiconductor package CHPK3 according to the present embodiment, the plurality of second protrusions PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0118] In a non-limiting example, a width of the second protrusion PR2 of the fourth frame portion LF2A and a width of the second protrusion PR2 of the fifth frame portion LF2B may be almost the same.

[0119] Since the lower surfaces of the plurality of second protrusions PR2 facing the semiconductor element SCP may be flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP may be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0120] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0121] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0122] In the example semiconductor package CHPK3 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0123] In the example semiconductor package CHPK3 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a plurality of second protrusions PR2, thereby improving the bonding reliability by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 may be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0124] In the example semiconductor package CHPK3 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0125] Many features of the example semiconductor packages CHPK1 and CHPK2 according to the above-described embodiments are applicable to the example semiconductor package CHPK3 according to the present embodiment.

[0126] Reference Figure 5 , an example semiconductor package CHPK4 according to one or more embodiments will be described. Figure 5 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0127] Reference Figure 5 , the example semiconductor package CHPK4 according to one or more embodiments is similar to the semiconductor package CHPK4 according to the previous reference Figure 4 The exemplary semiconductor package CHPK3 of the described embodiment is similar, and detailed descriptions of the same constituent elements are omitted.

[0128] The example semiconductor package CHPK4 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor elements SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor elements SCP.

[0129] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0130] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0131] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0132] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0133] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0134] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0135] Surfaces of the fourth and fifth frame portions LF2A and LF2B of the second lead frame LF2 that are physically and / or electrically connected to the semiconductor element SCP through the second and third contact portions SP2A and SP2B, respectively, may include a plurality of second protrusions PR2 protruding toward the semiconductor element SCP along the height direction DRH.

[0136] The second and third contact portions SP2A and SP2B may contact the plurality of second protrusions PR2 of surfaces of the fourth and fifth frame portions LF2A and LF2B, respectively.

[0137] Unlike the first protrusions PR1 , the plurality of second protrusions PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0138] In an example, the width of the second protrusion PR2 of the fourth frame portion LF2A and the width of the second protrusion PR2 of the fifth frame portion LF2B may be almost the same.

[0139] Since the lower surfaces of the plurality of second protrusions PR2 facing the semiconductor element SCP may be flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP may be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0140] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0141] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0142] Unlike the example semiconductor package CHPK3 according to the above-described embodiment, in the semiconductor package CHPK4 according to the present embodiment, at least one of the plurality of second protrusions PR2 of the second lead frame LF2 may include a second alignment hole (or second alignment hole) SPH2. In the example, the second protrusion PR2 of the fourth frame portion LF2A of the second lead frame LF2 may include a second alignment hole SPH2, and the second filling layer FL2 may be disposed in the second alignment hole SPH2.

[0143] The alignment accuracy of the semiconductor component SCP and the second lead frame LF2 overlapping each other in the height direction DRH may be improved by the second alignment hole SPH2 formed at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0144] As an example only, the second alignment hole SPH2 of the second lead frame LF2 can be formed by any one of stamping, drilling and etching. The second filling layer FL2 may include a conductive material. However, the embodiment is not limited thereto. The second filling layer FL2 may include a conductive material to prevent the degradation of the connection characteristics between the second protrusion PR2 of the second lead frame LF2 and the semiconductor element SCP.

[0145] In the example semiconductor package CHPK4 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0146] In the example semiconductor package CHPK4 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a plurality of second protrusions PR2, thereby improving the bonding reliability by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 may be maintained so that the heat generated in the semiconductor element SCP can be easily transferred to the outside.

[0147] In the example semiconductor package CHPK4 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0148] In the example semiconductor package CHPK4 according to the embodiment, alignment accuracy of the semiconductor element SCP and the second lead frame LF2 overlapping each other along the height direction DRH may be improved by forming a second alignment hole SPH2 at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0149] Many features of the example semiconductor packages CHPK1 , CHPK2 , and CHPK3 according to the above-described embodiments are applicable to the example semiconductor package CHPK4 according to the present embodiment.

[0150] Reference Figure 6 , an example semiconductor package CHPK5 according to one or more embodiments will be described. Figure 6 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0151] Reference Figure 6 The example semiconductor package CHPK5 according to the present embodiment is similar to the example semiconductor packages CHPK1, CHPK2, CHPK3, and CHPK4 according to the above-described embodiments. Detailed descriptions of the same constituent elements are omitted.

[0152] The semiconductor package CHPK5 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor components SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor components SCP.

[0153] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0154] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0155] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0156] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0157] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0158] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0159] Unlike the semiconductor packages CHPK1, CHPK2, CHPK3 and CHPK4 according to the above-mentioned embodiments, in the semiconductor package CHPK5 according to the present embodiment, the surface of the fifth frame portion LF2B of the second lead frame LF2 that is physically connected and / or electrically connected to the semiconductor element SCP through the third contact portion SP2B may include a third protrusion PR3 protruding toward the semiconductor element SCP along the height direction DRH, and the surface of the fourth frame portion LF2A of the second lead frame LF2 that is physically connected and / or electrically connected to the semiconductor element SCP through the second contact portion SP2A may include a second protrusion PR2 protruding toward the semiconductor element SCP along the height direction DRH.

[0160] The second contact portion SP2A and the third contact portion SP2B may contact the second protrusion PR2 of the surface of the fourth frame portion LF2A and the third protrusion PR3 of the surface of the fifth frame portion LF2B, respectively.

[0161] Unlike the first protrusion PR1 , the third protrusion PR3 and the second protrusion PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0162] In an example, the width of the third protrusion PR3 may be greater than the width of the second protrusion PR2 .

[0163] A planar area of ​​a lower surface of the third protrusion PR3 may be greater than a planar area of ​​a lower surface of the second protrusion PR2 .

[0164] Since the lower surfaces of the third protrusion PR3 and the second protrusion PR2 facing the semiconductor element SCP may be flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP may be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0165] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0166] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0167] In the semiconductor package CHPK5 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0168] In the semiconductor package CHPK5 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a third protrusion PR3 and a second protrusion PR2, thereby improving the bonding reliability by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 can be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0169] In the semiconductor package CHPK5 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 is prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0170] Many features of the semiconductor packages CHPK1 , CHPK2 , CHPK3 , and CHPK4 according to the above-described embodiments are applicable to the semiconductor package CHPK5 according to the present embodiment.

[0171] Reference Figure 7 , an example semiconductor package CHPK6 according to one or more embodiments will be described. Figure 7 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0172] Reference Figure 7 , the semiconductor package CHPK6 according to the present embodiment is similar to the semiconductor package CHPK5 according to the above-described embodiment. Detailed description of the same constituent elements is omitted.

[0173] The semiconductor package CHPK6 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor components SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor components SCP.

[0174] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0175] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0176] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0177] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0178] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0179] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0180] The surface of the fourth frame portion LF2A of the second lead frame LF2 that is physically and / or electrically connected to the semiconductor element SCP through the second contact portion SP2A may include a second protrusion PR2 that protrudes toward the semiconductor element SCP along the height direction DRH, and the surface of the fifth frame portion LF2B of the second lead frame LF2 that is physically and / or electrically connected to the semiconductor element SCP through the third contact portion SP2B may include a third protrusion PR3 that protrudes toward the semiconductor element SCP along the height direction DRH.

[0181] The second contact portion SP2A and the third contact portion SP2B may contact the second protrusion PR2 of the surface of the fourth frame portion LF2A and the third protrusion PR3 of the surface of the fifth frame portion LF2B, respectively.

[0182] Unlike the first protrusion PR1 , the third protrusion PR3 and the second protrusion PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0183] In an example, the width of the third protrusion PR3 may be greater than the width of the second protrusion PR2 .

[0184] In an example, a planar area of ​​a lower surface of the third protrusion PR3 may be greater than a planar area of ​​a lower surface of the second protrusion PR2 .

[0185] Since the lower surfaces of the third protrusion PR3 and the second protrusion PR2 facing the semiconductor element SCP are flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP can be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0186] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0187] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0188] Unlike the semiconductor package CHPK5 according to the above-described embodiment, in the semiconductor package CHPK6 according to the present embodiment, the second protrusion PR2 of the second lead frame LF2 may include a second alignment hole (or second alignment hole) SPH2. For example, the second protrusion PR2 of the fourth frame portion LF2A of the second lead frame LF2 may include a second alignment hole SPH2, and the second filling layer FL2 may be disposed in the second alignment hole SPH2.

[0189] The alignment accuracy of the semiconductor component SCP and the second lead frame LF2 overlapping each other in the height direction DRH may be improved by the second alignment hole SPH2 formed at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0190] As an example only, the second alignment hole SPH2 of the second lead frame LF2 can be formed by any one of stamping, drilling and etching. The second filling layer FL2 may include a conductive material, but the embodiment is not limited thereto. The second filling layer FL2 may include a conductive material to prevent the degradation of the connection characteristics between the second protrusion PR2 of the second lead frame LF2 and the semiconductor element SCP.

[0191] In the semiconductor package CHPK6 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0192] In the semiconductor package CHPK6 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a third protrusion PR3 and a second protrusion PR2, so that the bonding reliability is improved by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 can be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0193] In the semiconductor package CHPK6 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0194] In the semiconductor package CHPK6 according to the embodiment, alignment accuracy of the semiconductor element SCP and the second lead frame LF2 overlapping each other along the height direction DRH may be improved by forming a second alignment hole SPH2 at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0195] Many features of the example semiconductor packages CHPK1 , CHPK2 , CHPK3 , CHPK4 , and CHPK5 according to the above-described embodiments are applicable to the example semiconductor package CHPK6 according to the present embodiment.

[0196] Reference Figure 8 , an example semiconductor package CHPK7 according to another embodiment will be described. Figure 8 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0197] Reference Figure 8 The exemplary semiconductor package CHPK7 according to the present embodiment is similar to the exemplary semiconductor packages CHPK5 and CHPK6 according to the above-described embodiments. Detailed descriptions of the same constituent elements are omitted.

[0198] The example semiconductor package CHPK7 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor elements SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor elements SCP.

[0199] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0200] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0201] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0202] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0203] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0204] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0205] The surface of the fourth frame portion LF2A of the second lead frame LF2 that is physically and / or electrically connected to the semiconductor element SCP through the second contact portion SP2A may include a second protrusion PR2 that protrudes toward the semiconductor element SCP along the height direction DRH, and the surface of the fifth frame portion LF2B of the second lead frame LF2 that is physically and / or electrically connected to the semiconductor element SCP through the third contact portion SP2B may include a third protrusion PR3 that protrudes toward the semiconductor element SCP along the height direction DRH.

[0206] The second contact portion SP2A and the third contact portion SP2B may contact the second protrusion PR2 of the surface of the fourth frame portion LF2A and the third protrusion PR3 of the surface of the fifth frame portion LF2B, respectively.

[0207] Unlike the first protrusion PR1 , the third protrusion PR3 and the second protrusion PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0208] In an example, the width of the third protrusion PR3 may be greater than the width of the second protrusion PR2 .

[0209] In an example, a planar area of ​​a lower surface of the third protrusion PR3 may be greater than a planar area of ​​a lower surface of the second protrusion PR2 .

[0210] Since the lower surfaces of the third protrusion PR3 and the second protrusion PR2 facing the semiconductor element SCP may be flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP may be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0211] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0212] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0213] Unlike the example semiconductor package CHPK5 according to the above-described embodiment, in the semiconductor package CHPK7 according to the present embodiment, the second protrusion PR2 of the second lead frame LF2 may include a second alignment hole (or second alignment hole) SPH2. In the example, the second protrusion PR2 of the fourth frame portion LF2A of the second lead frame LF2 may include a second alignment hole SPH2, and the second filling layer FL2 may be disposed in the second alignment hole SPH2.

[0214] In addition, the third protrusion PR3 of the second lead frame LF2 may include a third alignment hole (or third alignment hole) SPH3, and the third filling layer FL3 may be disposed in the third alignment hole SPH3. In an example, the third protrusion PR3 of the fifth frame part LF2B of the second lead frame LF2 may include a third alignment hole SPH3, and the third filling layer FL3 may be disposed in the third alignment hole SPH3.

[0215] In an example, a width of the third alignment hole SPH3 of the second lead frame LF2 may be wider than a width of the second alignment hole SPH2 of the second lead frame LF2.

[0216] The alignment accuracy of the semiconductor element SCP and the second lead frame LF2 stacked on each other along the height direction DRH can be improved by forming a second alignment hole SPH2 at the second protrusion PR2 of the second lead frame LF2 and a third alignment hole SPH3 formed at the third protrusion PR3 of the second lead frame LF2, thereby reducing misalignment.

[0217] As only an example, the second and third alignment holes SPH2 and SPH3 of the second lead frame LF2 may be formed by any one method of punching, drilling, and etching.

[0218] Each of the second filling layer FL2 and the third filling layer FL3 may include a conductive material, but the embodiment is not limited thereto. The second filling layer FL2 and the third filling layer FL3 may include a conductive material to prevent degradation of connection characteristics between the second protrusion PR2 and the third protrusion PR3 of the second lead frame LF2 and the semiconductor element SCP.

[0219] In the semiconductor package CHPK7 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first and second lead frames LF1 and LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0220] In the example semiconductor package CHPK7 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a third protrusion PR3 and a second protrusion PR2, thereby improving the bonding reliability by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 can be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0221] In the example semiconductor package CHPK7 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 is prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0222] In the example semiconductor package CHPK7 according to the embodiment, the alignment accuracy of the semiconductor element SCP and the second lead frame LF2 stacked on each other along the height direction DRH can be improved by the second alignment hole SPH2 formed at the second protrusion PR2 of the second lead frame LF2 and the third alignment hole SPH3 formed at the third protrusion PR3, thereby reducing misalignment.

[0223] Many features of the example semiconductor packages CHPK1 , CHPK2 , CHPK3 , CHPK4 , CHPK5 , and CHPK6 according to the above-described embodiments are applicable to the example semiconductor package CHPK7 according to the present embodiment.

[0224] Reference Fig. 9 , an example semiconductor package CHPK8 according to one or more embodiments will be described. Fig. 9 is a cross-sectional view of an example semiconductor package according to one or more embodiments.

[0225] Reference Fig. 9The semiconductor package CHPK8 according to the present embodiment is similar to the semiconductor package CHPK8 according to the above reference Figure 5 The exemplary semiconductor package CHPK4 of the described embodiment is similar, and detailed descriptions of the same constituent elements are omitted.

[0226] The example semiconductor package CHPK8 according to the present embodiment may include first and second lead frames LF1 and LF2 facing each other, a plurality of semiconductor elements SCP disposed between the first and second lead frames LF1 and LF2 , and a molding part ML sealing the plurality of semiconductor elements SCP.

[0227] The first lead frame LF1 may include a first frame portion LF1A, a second frame portion LF1B, and a third frame portion LF1C, and the second lead frame LF2 may include a fourth frame portion LF2A and a fifth frame portion LF2B.

[0228] The semiconductor component SCP may be mounted on the first frame portion LF1A of the first lead frame LF1. The semiconductor component SCP may be physically and / or electrically connected to the first lead frame LF1 through the first contact portion SP1.

[0229] The fourth frame portion LF2A and the fifth frame portion LF2B of the second lead frame LF2 may be physically and / or electrically connected to the semiconductor component SCP through the second contact portion SP2A and the third contact portion SP2B, respectively.

[0230] The second frame part LF1B of the first lead frame LF1 may be physically and / or electrically connected to the second lead frame LF2 through the fourth contact portion SP3 .

[0231] The spacer SPS may be disposed between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 .

[0232] In an example, the thickness of the spacer SPS may be almost the same as the thickness of the fourth contact portion SP3 connecting the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2.

[0233] Surfaces of the fourth and fifth frame portions LF2A and LF2B of the second lead frame LF2 that are physically and / or electrically connected to the semiconductor element SCP through the second and third contact portions SP2A and SP2B, respectively, may include a plurality of second protrusions PR2 protruding toward the semiconductor element SCP along the height direction DRH.

[0234] The second and third contact portions SP2A and SP2B may contact the plurality of second protrusions PR2 of surfaces of the fourth and fifth frame portions LF2A and LF2B, respectively.

[0235] Unlike the first protrusions PR1 , the plurality of second protrusions PR2 of the surface of the second lead frame LF2 may have a flat lower surface facing the semiconductor component SCP.

[0236] Since the lower surfaces of the plurality of second protrusions PR2 facing the semiconductor element SCP may be flat, the bonding surface area between the second lead frame LF2 and the semiconductor element SCP may be increased, thereby improving the bonding reliability between the second lead frame LF2 and the semiconductor element SCP.

[0237] The molded part ML may surround and seal the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0238] The molded part ML may protect the first lead frame LF1, the second lead frame LF2, and the semiconductor element SCP.

[0239] The second protrusion PR2 of the fourth frame portion LF2A of the second lead frame LF2 may include a second alignment hole SPH2, each of the multiple second protrusions PR2 of the fifth frame portion LF2B of the second lead frame LF2 may include a fourth alignment hole (or fourth alignment hole) SPH4, the second filling layer FL2 may be set in the second alignment hole SPH2, and the fourth filling layer FL4 may be set in the fourth alignment hole SPH4.

[0240] In the example, the width of the second protrusion PR2 of the fifth frame portion LF2B and the width of the second protrusion PR2 of the fourth frame portion LF2A may be almost the same, and the width of the second alignment hole SPH2 of the fourth frame portion LF2A and the width of the fourth alignment hole SPH4 of the fifth frame portion LF2B may be almost the same.

[0241] The alignment accuracy of the semiconductor component SCP and the second lead frame LF2 overlapping each other in the height direction DRH may be improved by the second alignment hole SPH2 and the fourth alignment hole SPH4 formed at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0242] As an example only, the second alignment hole SPH2 and the fourth alignment hole SPH4 of the second lead frame LF2 may be formed by any one of stamping, drilling and etching. Each of the second filling layer FL2 and the fourth filling layer FL4 may include a conductive material, but the embodiment is not limited thereto. The second filling layer FL2 and the fourth filling layer FL4 may include a conductive material to prevent degradation of the connection characteristics between the second lead frame LF2 and the semiconductor element SCP.

[0243] In the semiconductor package CHPK8 according to the embodiment, a plurality of semiconductor elements SCP may be mounted on the first lead frame LF1 and the second lead frame LF2 without a complicated process of forming a separate mounting substrate, so that the manufacturing process may be simplified and an increase in manufacturing cost may be prevented.

[0244] In the semiconductor package CHPK8 according to the embodiment, the first lead frame LF1 and the second lead frame LF2 may be respectively arranged below and above the semiconductor element SCP along the height direction DRH, so that heat can be transferred above and below the semiconductor element SCP. The surface of the second lead frame LF2 connected to the semiconductor element SCP may include a plurality of second protrusions PR2, so that the bonding reliability is improved by increasing the bonding surface area between the semiconductor element SCP and the second lead frame LF2. The interval between the semiconductor element SCP and the second lead frame LF2 can be maintained so that the heat generated in the semiconductor element SCP is easily transferred to the outside.

[0245] In the semiconductor package CHPK8 according to the embodiment, the interval between the third frame portion LF1C of the first lead frame LF1 and the fifth frame portion LF2B of the second lead frame LF2 separated by the spacer SPS and the interval between the second frame portion LF1B of the first lead frame LF1 and the fourth frame portion LF2A of the second lead frame LF2 separated by the fourth contact portion SP3 may be almost the same. Therefore, the height of the fifth frame portion LF2B of the second lead frame LF2 can be prevented from being relatively lowered due to the non-provision of the fourth contact portion SP3, thereby preventing the second lead frame LF2 from warping.

[0246] In the semiconductor package CHPK8 according to the embodiment, the alignment accuracy of the semiconductor element SCP and the second lead frame LF2 overlapping each other along the height direction DRH can be improved by forming the second alignment hole SPH2 and the fourth alignment hole SPH4 at the second protrusion PR2 of the second lead frame LF2, thereby reducing misalignment.

[0247] Many features of the example semiconductor packages CHPK1 , CHPK2 , CHPK3 , CHPK4 , CHPK5 , CHPK6 , and CHPK7 according to the above-described embodiments are applicable to the example semiconductor package CHPK8 according to the present embodiment.

[0248] With reference to Table 1 below, an experimental example is described.

[0249] In this experimental example, the loss energy of the semiconductor element is measured for a first example according to the prior art and a second example of an example semiconductor package according to one or more embodiments. In the first example, the semiconductor element is mounted on a mounting substrate, the mounting substrate and the lead frame are connected by wire bonding, and the semiconductor element and the lead frame are packaged with a molded portion. In the second example, the semiconductor element is mounted between a lower lead frame and an upper lead frame without a complicated process of forming a separate mounting substrate, a plurality of protrusions are formed on the surface of the upper lead frame, and then the semiconductor element, the lower lead frame, the upper lead frame and the plurality of protrusions are packaged with a molded portion, and the measurement results are shown in Table 1 below.

[0250] Table 1: Referring to Table 1, it can be seen that the loss energy of the semiconductor element of the second example of the semiconductor package according to the embodiment is reduced by about 14% or more compared with the loss energy of the semiconductor element according to the first example of the related art.

[0251] Although specific examples have been shown and described above, it will be readily understood after understanding the present disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are considered to be descriptive only and not for limiting purposes. The description of the features or aspects in each example will be considered to apply to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described systems, architectures, devices, or circuits are combined in different ways, and / or replaced or supplemented by other components or their equivalents, suitable results may be achieved. Therefore, the scope of the present disclosure is not limited by specific embodiments, but by the claims and their equivalents, and all changes within the scope of the claims and their equivalents should be interpreted as included in the present disclosure.

Claims

1. A semiconductor package, comprising: A first lead frame and a second lead frame facing each other; as well as A semiconductor element is disposed between the first lead frame and the second lead frame, wherein the semiconductor element is connected to the first lead frame via a first contact portion and connected to the second lead frame via a second contact portion, and The second lead frame includes a plurality of protrusions protruding toward the semiconductor element.

2. The semiconductor package according to claim 1, wherein: The second lead frame includes a hole overlapping the second contact portion.

3. The semiconductor package according to claim 2, wherein: A cross section of each of the plurality of protrusions cut in a direction parallel to the height direction has a semicircular shape.

4. The semiconductor package according to claim 3, wherein: The second lead frame includes a first portion and a second portion spaced apart from each other, and the plurality of protrusions include a first protrusion included in the first portion and a second protrusion included in the second portion.

5. The semiconductor package according to claim 4, wherein: The width of the first protrusion is equal to the width of the second protrusion.

6. The semiconductor package according to claim 5, wherein: The hole overlaps the second protrusion.

7. The semiconductor package according to claim 2, wherein: The lower surfaces of the plurality of protrusions are flat.

8. The semiconductor package according to claim 7, wherein: The second lead frame includes a first portion and a second portion spaced apart from each other, the plurality of protrusions include a first protrusion in the first portion and a second protrusion in the second portion, and the hole includes a first hole overlapping the first protrusion in the first portion and a second hole overlapping the second protrusion in the second portion.

9. The semiconductor package according to claim 8, wherein: A width of the first protrusion in the first portion is equal to a width of the second protrusion in the second portion.

10. The semiconductor package according to claim 9, wherein: The width of the first hole is equal to the width of the second hole.

11. The semiconductor package according to claim 8, wherein: A width of the first protrusion in the first portion is different from a width of the second protrusion in the second portion.

12. The semiconductor package according to claim 11, wherein The width of the first hole is different from the width of the second hole.

13. The semiconductor package according to claim 1, wherein: The first lead frame comprises: a first frame portion on which the semiconductor element is mounted; a second frame portion spaced apart from the first frame portion, configured to receive a first signal from an external source, and disposed in a non-overlapping manner with respect to the semiconductor element; and a third frame portion, spaced apart from the first frame portion and disposed in a non-overlapping manner relative to the semiconductor element, Wherein, the semiconductor package further comprises: a third contact portion disposed between the second lead frame and the semiconductor element; a fourth contact portion provided between the second frame portion and the second lead frame and configured to have conductivity; and A spacer is provided between the third frame portion and the second lead frame.

14. The semiconductor package according to claim 13, wherein: The thickness of the fourth contact portion is equal to the thickness of the spacer.

15. A semiconductor package, comprising: a first lead frame including a first frame portion, a second frame portion, and a third frame portion, the semiconductor element being mounted on the first frame portion, the second frame portion being spaced apart from the first frame portion, being configured to receive a first signal from an external source, and being disposed in a non-overlapping manner relative to the semiconductor element, the third frame portion being spaced apart from the first frame portion and being disposed in a non-overlapping manner relative to the semiconductor element; a second lead frame, opposite to the first lead frame; a contact portion provided between the second frame portion and the second lead frame and configured to have conductivity; and A spacer is provided between the third frame portion and the second lead frame.

16. The semiconductor package according to claim 15, wherein: The thickness of the contact portion is equal to the thickness of the spacer.

17. The semiconductor package according to claim 16, wherein: The second lead frame includes a plurality of protrusions protruding toward the semiconductor element.

18. The semiconductor package according to claim 17, wherein: A cross section of each of the plurality of protrusions cut in a direction parallel to the height direction has a semicircular shape.

19. The semiconductor package according to claim 17, wherein: The lower surfaces of the plurality of protrusions are flat.

20. The semiconductor package according to claim 19, wherein The second lead frame includes a first portion and a second portion spaced apart from each other, the plurality of protrusions include a first protrusion and a second protrusion, the first protrusion is included in the first portion, the second protrusion is included in the second portion, and a width of the first protrusion in the first portion is different from a width of the second protrusion in the second portion.

21. The semiconductor package according to claim 17, wherein: The semiconductor package further includes another contact portion disposed between the semiconductor element and the plurality of protrusions and configured to have conductivity.

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