Low dielectric absorption, low mismatch precision linear MIM capacitors and their integration methods

Abstract

This invention discloses a low-dielectric-absorption, low-mismatch precision linear MIM capacitor and its integration technology. The integration steps are as follows: 1) Forming an active region and an isolation field oxide region. 2) Forming a thick gate oxide layer and a thin gate oxide layer. 3) Depositing a polysilicon layer and constructing the polysilicon gate of the MOSFET. 4) Completing photolithographic implantation of the multi-mode gate oxide high and low voltage BiCMOS / CMOS source and drain electrodes. 5) Chemical mechanical planarization to improve the flatness of the surface region under the metal thin film resistor. 6) High resistivity microcrystalline titanium thin film sputtering of the lower electrode of the metal MIM capacitor using PVD method. 7) PECVD silicon nitride Si for the dielectric layer of the metal MIM capacitor. x N y H z 8) Sputtering of high resistivity microcrystalline titanium thin film on the top electrode of the metal MIM capacitor using PVD method. 9) Sputtering of aluminum-copper film layer and completion of metal interconnect etching. This invention not only optimizes the precision matching problem of metal MIM capacitors, but also improves the packaging functional density and device density of integrated circuits, promoting the miniaturization and lightweighting of high-performance integrated circuits.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuits, specifically to low dielectric absorption, low mismatch precision linear MIM capacitors and integration technology. Background Technology

[0002] In the field of high-performance analog or mixed-signal integrated circuit manufacturing, the accuracy of integrated capacitors used in AD / DA data converters, smart sensors, and other signal processing circuits directly limits the accuracy and performance of these integrated circuits. Metal-based MIM capacitors possess excellent electrical characteristics such as ideal self-limiting of parasitic substrate capacitance noise and no depletion effect on the capacitor plates. Furthermore, metal-based MIM capacitors are easily integrated with standard analog integrated circuit metal interconnect processes. The mismatch of metal-based MIM capacitors calibrated using nonlinear processes can be controlled within ±0.001%. Therefore, integrating near-ideal linear metal-based MIM capacitors into high-performance integrated circuits has become an important task in the development of BiCMOS / CMOS / Bipolar specialty processes.

[0003] To meet the demands of miniaturization and lightweighting of integrated circuits, capacitor dielectric materials such as SiN or TaN, which have higher dielectric constants than SiO2, are required to improve the capacitance per unit area of ​​metal-interconnected metal (MIM) capacitors. However, due to limitations in the thermal budget of the applicable processes for the metal interconnect layers, the dielectric films of MIM capacitors exhibit higher rates of defects such as microcracks and pinholes compared to materials with the same chemical composition processed at higher temperatures. Therefore, the bulk trap density of the dielectric film in metal-interconnected metal (MIM) capacitors, the dielectric-metal interface states, and the stress mismatch between the capacitor dielectric and the metal film become the main sources affecting the performance of metal capacitors.

[0004] On the other hand, the capacitance value of metal MIM capacitors can shift with operating frequency and bias voltage, leading to analog signal distortion. This capacitance shift can even propagate to higher operating frequencies, ultimately creating positive feedback and causing circuit failure. Therefore, using process calibration techniques to improve dielectric strength and reduce the dielectric absorption coefficient to mitigate hysteresis, mismatch, and nonlinear effects in metal MIM capacitors has always been a hot topic and a challenging area of ​​academic research and technological innovation. Summary of the Invention

[0005] The purpose of this invention is to provide a low dielectric absorption, low mismatch precision linear MIM capacitor and integration technology, comprising the following steps:

[0006] 1) A well is formed on the substrate surface, and an active region is formed on the surface of the well. An isolation oxide layer is formed in the region outside the active region.

[0007] 2) Select the regions for metal thin film resistors, high-voltage active devices, medium-voltage active devices, and low-voltage active devices that require low temperature coefficients;

[0008] 3) Thick gate oxide layers are formed in the active regions of high-voltage devices and medium-voltage devices, respectively; thin gate oxide layers are formed in the active regions of low-voltage devices.

[0009] 4) Form the polysilicon gate of the MOSFET and select the doped source and drain regions of the MOSFET;

[0010] 5) Photolithographic implantation of dual-gate oxygen high and low voltage CMOS source and drain is completed in the doped source and drain regions of the MOS transistor, and the doped impurities are activated by rapid annealing process;

[0011] 6) Deposit a silicon nitride layer and a BPSG low dielectric constant filling film;

[0012] 7) Complete the film planarization process and the device contact hole processing;

[0013] 8) Complete the tungsten plug filling process for the device contact holes; sputter an aluminum-silicon-copper film layer, denoted as the first metal layer, and complete the etching process for the first metal layer interconnects;

[0014] 9) Repeat steps 6)-8) as needed for circuit design until the second-to-last layer of metal is sputtered, which is denoted as the (n-1)th layer of metal.

[0015] 10) After completing the argon atom sputtering cleaning, sputter the h1 angstrom titanium film, and then deposit the h2 angstrom amorphous silicon nitride SixNyHz film;

[0016] 11) After argon atom sputtering cleaning, h3 angstrom microcrystalline titanium thin film is sputtered on silicon nitride film layer;

[0017] 12) Deposit h4 Å semi-crystalline titanium / h5 Å titanium nitride in an integrated magnetron sputtering chamber;

[0018] 13) PVD sputtering is used to deposit aluminum alloy thin films and anti-reflective titanium nitride films suitable for planarization processes;

[0019] 14) Based on the mask pattern, expose, develop, and dry etch the titanium / titanium nitride / aluminum silicon copper / titanium nitride on the upper electrode of the MIM capacitor to form an integrated metal-silicon nitride-metal capacitor.

[0020] The resulting integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs(QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs(LVC) ≤ 1.5ppm / V.

[0021] 15) Deposition of low dielectric constant filled film (USG thin film), CMP planarization of intermetallic dielectric layer, via etching, tungsten plug chemical mechanical planarization,

[0022] 16) Sputter the top layer metal, denoted as the nth layer metal, and complete the etching process of the nth layer metal interconnects to form the metal interconnects of the circuit components;

[0023] 17) PECVD is used to deposit the passivation composite dielectric layer, and the passivation protective layer is exposed, developed and etched.

[0024] Further, in step 4), the step of forming the polysilicon gate of the MOS transistor is as follows: depositing a polysilicon gate layer on the surface, doping the polysilicon layer, and then etching the polysilicon gate structure. Thus, the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS transistor.

[0025] Further, in step 6), a silicon nitride layer is deposited using low-pressure chemical vapor deposition; and a BPSG low-dielectric-coefficient filling film is deposited using PECVD.

[0026] In step 7), chemical mechanical polishing (CMP) is used to planarize the film layer; dry etching is used to process the device contact holes.

[0027] In step 8), tungsten sputtering and tungsten chemical mechanical planarization processes are used to complete the tungsten plug filling of the device contact holes;

[0028] In step 10), a 1 Å titanium film is sputtered using magnetron plasma physical vapor deposition (PVD); a 2 Å amorphous silicon nitride SixNyHz film is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0029] In step 11), a h3 angstrom microcrystalline titanium thin film is sputtered using magnetron plasma physical vapor deposition (PVD).

[0030] In step 12), h4 Å semi-crystalline titanium / h5 Å titanium nitride is deposited by PVD using a surface chemical reaction in-situ method.

[0031] In step 15), a low dielectric constant filled film, USG thin film, is deposited using PECVD.

[0032] Furthermore, in step 9), the interconnect structure film of the (n-1)th metal layer is tungsten / titanium / aluminum-silicon-copper / titanium nitride;

[0033] In step 16), the circuit components include MOS devices and MIM capacitors.

[0034] Furthermore, n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0035] Furthermore, the impurity is a P-type impurity or an N-type impurity.

[0036] Furthermore, a chemical mechanical planarization process is used to planarize the (n-1) intermetallic dielectric layer to form a globally planarized dielectric layer and a tungsten plug structure.

[0037] Furthermore, a high-dielectric-coefficient silicon-rich silicon nitride thin film deposited by PECVD is used as the dielectric layer of the metal MIM capacitor.

[0038] Furthermore, a high selectivity tungsten-silica chemical mechanical planarization process was used to complete the fabrication of the tungsten plug structure.

[0039] The metal MIM capacitor module obtained by utilizing the aforementioned low dielectric absorption, low mismatch precision linear MIM capacitor and integration technology mainly includes a substrate, a well, a field oxide layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer, a polysilicon gate, and a metal thin film layer.

[0040] The substrate is located at the bottom; a well is formed on the surface of the substrate;

[0041] The field oxide layer forms outside the active region;

[0042] The active region includes the high-voltage device region, the medium-voltage device region, and the low-voltage device region;

[0043] Thick gate oxide layers are present in the high-voltage device region and the medium-voltage device region;

[0044] The low-voltage device region has a thin gate oxide layer;

[0045] Metal MIM capacitors are formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer;

[0046] The polysilicon gate of a MOSFET is constructed on a thick gate oxide layer and a thin gate oxide layer.

[0047] The technical effects of this invention are undeniable. This invention solves the problems of nonlinear process calibration of metal MIM capacitors, reduction of dielectric absorption coefficient of metal MIM capacitors, and precise matching of metal MIM capacitors.

[0048] This invention reduces parasitic substrate capacitance crosstalk noise in metal MIM capacitors by generating metal MIM capacitors in the intermediate region between the second-to-top metal and the top metal dielectric film layer of a multi-mode gate oxide high-low voltage compatible BiCMOS / CMOS process, while improving the functional density of integrated circuit packaging.

[0049] This invention solves the problem of precisely controlling the non-planarity of metal thin-film MIM capacitors by chemically and mechanically planarizing the lower surface region of the metal MIM capacitor, reducing the step and interlayer stress of the metal MIM capacitor film, and improving the long-term stability of the matched metal MIM capacitor.

[0050] This invention improves the interfacial trap density between the metal electrode film and the dielectric of a metal MIM capacitor, thereby enhancing the dielectric polarization and depolarization performance of the metal MIM capacitor, improving the capacitance value shift caused by changes in operating frequency and bias voltage, and optimizing problems such as nonlinear mismatch in metal MIM capacitors.

[0051] This invention improves the electrode film system of metal capacitors by sputtering microcrystalline titanium films of suitable thickness using magnetron plasma PVD. It reduces the compressive stress of the aluminum alloy film layer under the electrode in metal MIM capacitors, improves surface unevenness phenomena such as Hilllock defects in the metal film layer, and facilitates PECVD silicon nitride (Si) dielectric layer deposition. x N y H z It provides an excellent film-forming environment, reduces the probability of interlayer interconnected pinhole defects, and further improves the performance of silicon nitride (Si). x N y H z Dielectric strength and capacitor operating voltage range.

[0052] This invention improves the bonding between the metal film and the dielectric silicon nitride (Si) by using in-situ PVD deposition of a semi-crystalline titanium / titanium nitride composite film within an integrated magnetron sputtering chamber. x N y H z Dry etching selectivity can ensure the precision of the electrode geometry control process for metal MIM capacitors, avoid problems such as short circuits in metal capacitors, and, more importantly, reduce the thickness of the dielectric film between capacitors to increase the capacitance per unit, thereby increasing the device density of integrated circuits and promoting the miniaturization and lightweighting of integrated circuits. Attached Figure Description

[0053] Figure 1 A cross-sectional view of the shielding oxide layer grown after conventional CMOS processes such as well implantation, annealing, and field oxidation.

[0054] Figure 2 A cross-sectional view after the growth of the thick gate oxide layer required for high-voltage devices;

[0055] Figure 3 A cross-sectional view showing the growth of a thin gate oxide layer after the thick gate oxide layer has been stripped away;

[0056] Figure 4A cross-sectional view of the MOS transistor after light doping implantation of the source and drain regions and etching of the gate polycrystalline sidewalls to form a gate polycrystalline sidewall protection structure.

[0057] Figure 5 To complete the global planarization of the silicon-metal inter-dielectric filling layer, the tungsten plug structure, and the cross-sectional view after etching the first metal layer;

[0058] Figure 6 To complete the global planarization of the second-layer metal (denoted as the (n-1)th layer) after sputtering deposition, tungsten plug structure cross-section diagram;

[0059] Figure 7 This is a cross-sectional view of a microcrystalline titanium metal film deposited by magnetron plasma physical vapor deposition (PVD) on the second-to-top metal layer (denoted as the (n-1)th layer).

[0060] Figure 8 This is a cross-sectional view of a plasma-enhanced chemical vapor deposition (PECVD) silicon-rich silicon nitride film deposited on a microcrystalline titanium metal film of the second-top metal layer (denoted as the (n-1)th layer).

[0061] Figure 9 This is a cross-sectional view of a microcrystalline titanium metal thin film deposited by magnetron plasma physical vapor deposition (PVD) on a silicon nitride film layer, which is the dielectric of a metal MIM capacitor.

[0062] Figure 10 This is a cross-sectional view of the sputtered deposition of the metal film system (semi-crystalline titanium / titanium nitride / aluminum silicon copper / titanium nitride) on the upper electrode of a metal MIM capacitor.

[0063] Figure 11 Cross-sectional view of a metal MIM capacitor structure after completing process steps such as exposure, etching, dielectric filling, tungsten plug filling, and planarization;

[0064] Figure 12 Metal MIM capacitor modules are compatible with multi-mode gate oxide high and low voltage.

[0065] A schematic diagram of the integrated BiCMOS / CMOS process platform;

[0066] In the figure, 101 is the second-to-top layer metal; 102 is the high-resistivity microcrystalline titanium film (preferred) for the lower electrode of the metal MIM capacitor; 103 is the PECVD silicon-rich silicon nitride film layer of the metal MIM capacitor dielectric; 104 is the high-resistivity microcrystalline titanium film (preferred) for the upper electrode of the metal MIM capacitor; 105 is the tungsten plug for the interconnection between the top layer metal and the second-to-top layer metal; 201 is the tungsten plug for the interconnection between the lower electrode and the top layer metal of the metal MIM capacitor; 202 is the top layer metal system; 203 is the metal system of the upper electrode of the metal MIM capacitor; 204 is the low-resistivity semi-crystalline titanium film layer of the upper electrode of the metal MIM capacitor; and 205 is the titanium nitride film layer of the barrier layer of the upper electrode of the metal MIM capacitor. Detailed Implementation

[0067] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0068] Example 1:

[0069] See Figures 1-12 A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors includes the following steps:

[0070] 1) A well is formed on the substrate surface, and an active region is formed on the surface of the well. An isolation oxide layer is formed in the region outside the active region.

[0071] 2) Select the regions for metal thin film resistors, high-voltage active devices, medium-voltage active devices, and low-voltage active devices that require low temperature coefficients;

[0072] 3) Thick gate oxide layers are formed in the active regions of high-voltage devices and medium-voltage devices, respectively; thin gate oxide layers are formed in the active regions of low-voltage devices.

[0073] 4) Form the polysilicon gate of the MOSFET and select the doped source and drain regions of the MOSFET;

[0074] 5) Photolithographic implantation of dual-gate oxygen high and low voltage CMOS source and drain is completed in the doped source and drain regions of the MOS transistor, and the doped impurities are activated by rapid annealing process;

[0075] 6) Deposit a silicon nitride layer and a BPSG low dielectric constant filling film;

[0076] 7) Complete the film planarization process and the device contact hole processing;

[0077] 8) Complete the tungsten plug filling process for the device contact holes; sputter an aluminum-silicon-copper film layer, denoted as the first metal layer, and complete the etching process for the first metal layer interconnects;

[0078] 9) Repeat steps 6)-8) as needed for circuit design until the second-to-last layer of metal is sputtered, which is denoted as the (n-1)th layer of metal.

[0079] 10) After completing the argon atom sputtering cleaning, sputter the h1 angstrom titanium film, and then deposit the h2 angstrom amorphous silicon nitride SixNyHz film;

[0080] 11) After argon atom sputtering cleaning, h3 angstrom microcrystalline titanium thin film is sputtered on silicon nitride film layer;

[0081] 12) Deposit h4 Å semi-crystalline titanium / h5 Å titanium nitride in an integrated magnetron sputtering chamber;

[0082] 13) PVD sputtering is used to deposit aluminum alloy thin films and anti-reflective titanium nitride films suitable for planarization processes;

[0083] 14) Based on the mask pattern, expose, develop, and dry etch the titanium / titanium nitride / aluminum silicon copper / titanium nitride on the upper electrode of the MIM capacitor to form an integrated metal-silicon nitride-metal capacitor.

[0084] The resulting integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs(QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs(LVC) ≤ 1.5ppm / V.

[0085] 15) Deposition of low dielectric constant filled film (USG thin film), CMP planarization of intermetallic dielectric layer, via etching, tungsten plug chemical mechanical planarization,

[0086] 16) Sputter the top layer metal, denoted as the nth layer metal, and complete the etching process of the nth layer metal interconnects to form the metal interconnects of the circuit components;

[0087] 17) PECVD is used to deposit the passivation composite dielectric layer, and the passivation protective layer is exposed, developed and etched.

[0088] In step 4), the step of forming the polysilicon gate of the MOS transistor is as follows: depositing a polysilicon gate layer on the surface, doping the polysilicon layer, and then etching the polysilicon gate structure. Thus, the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS transistor.

[0089] In step 6), a silicon nitride layer is deposited using low-pressure chemical vapor deposition; a BPSG low-dielectric-coefficient filling film is deposited using PECVD.

[0090] In step 7), chemical mechanical polishing (CMP) is used to planarize the film layer; dry etching is used to process the device contact holes.

[0091] In step 8), tungsten sputtering and tungsten chemical mechanical planarization processes are used to complete the tungsten plug filling of the device contact holes;

[0092] In step 10), a 1 Å titanium film is sputtered using magnetron plasma physical vapor deposition (PVD); a 2 Å amorphous silicon nitride SixNyHz film is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0093] In step 11), a h3 angstrom microcrystalline titanium thin film is sputtered using magnetron plasma physical vapor deposition (PVD).

[0094] In step 12), h4 Å semi-crystalline titanium / h5 Å titanium nitride is deposited by PVD using a surface chemical reaction in-situ method.

[0095] In step 15), a low dielectric constant filled film, USG thin film, is deposited using PECVD.

[0096] In step 9), the interconnect structure film of the (n-1)th metal layer is tungsten / titanium / aluminum-silicon-copper / titanium nitride;

[0097] In step 16), the circuit components include MOS devices and MIM capacitors.

[0098] n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0099] The impurity is either a P-type impurity or an N-type impurity.

[0100] A chemical mechanical planarization process was used to planarize the (n-1) intermetallic dielectric layer to form a globally planarized dielectric layer and a tungsten plug structure.

[0101] High dielectric constant silicon-rich silicon nitride thin films deposited by PECVD are used as the dielectric layer of metal MIM capacitors.

[0102] The tungsten plug structure was fabricated using a high selectivity tungsten-silica chemical mechanical planarization process.

[0103] Example 2:

[0104] A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors includes the following steps:

[0105] 1) A 300-500 mm thick oxygen film is grown on the substrate, and a silicon nitride and silicon dioxide composite film is deposited using LPCVD process;

[0106] 2) The isolation trench pattern is formed by exposure and dry etching process, and then the photoresist is stripped off;

[0107] 3) Using a silicon dioxide-silicon nitride-silicon dioxide hard mask, an isolation trench is formed using a silicon etching dry process;

[0108] 4) An oxide film layer is generated on the sidewall using an oxidation process containing chlorine atmosphere, and then an isolation medium is filled in;

[0109] 5) A planarization process is used to remove excess tank filling medium, and an oxidation process is used to form a smooth corner structure of the isolation tank, ultimately forming a complete isolation tank structure;

[0110] The other technical details are the same as in Example 1.

[0111] In step 1), the substrate can be an SOI structure material sheet;

[0112] In step 3), the isolation trench can be either an STI shallow trench isolation structure or a DTI deep trench isolation structure;

[0113] In step 4), the trench filling material can be either a silicon dioxide-silicon nitride composite dielectric or an amorphous polycrystalline silicon dielectric.

[0114] In step 5), the tank filling medium planarization can be performed using either CMP chemical mechanical global planarization or thermal oxidation planarization.

[0115] Example 3:

[0116] The method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors is the same as any one of Embodiments 1-2. Further, in step 4), the step of forming the polysilicon gate of the MOS transistor is as follows: a polysilicon gate layer is deposited on the surface, and the polysilicon layer is doped, followed by etching of the polysilicon gate structure. Thus, the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS transistor.

[0117] Example 4:

[0118] A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors, with the same technical content as any one of Examples 1-3, further comprising the following steps: in step 6), a silicon nitride layer is deposited using low-pressure chemical vapor deposition; and a BPSG low dielectric constant filling film layer is deposited using PECVD.

[0119] In step 7), chemical mechanical polishing (CMP) is used to planarize the film layer; dry etching is used to process the device contact holes.

[0120] In step 8), tungsten sputtering and tungsten chemical mechanical planarization processes are used to complete the tungsten plug filling of the device contact holes;

[0121] In step 10), a 1 Å titanium film is sputtered using magnetron plasma physical vapor deposition (PVD); a 2 Å amorphous silicon nitride SixNyHz film is deposited using plasma-enhanced chemical vapor deposition (PECVD).

[0122] In step 11), a h3 angstrom microcrystalline titanium thin film is sputtered using magnetron plasma physical vapor deposition (PVD).

[0123] In step 12), h4 Å semi-crystalline titanium / h5 Å titanium nitride is deposited by PVD using a surface chemical reaction in-situ method.

[0124] In step 15), a low-dielectric-coefficient filled USG film is deposited using PECVD; Example 5:

[0125] The method for integrating a precision linear MIM capacitor with low dielectric absorption and low mismatch is the same as any one of Examples 1-4. Further, in step 9), the interconnect structure film of the (n-1)th metal layer is tungsten / titanium / aluminum-silicon-copper / titanium nitride.

[0126] In step 16), the circuit components include MOS devices and MIM capacitors.

[0127] Example 6:

[0128] A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors, with the same technical content as any one of Examples 1-5, further wherein n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0129] Example 7:

[0130] The method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors is the same as any one of Examples 1-6, and further, the impurity is a P-type impurity or an N-type impurity.

[0131] Example 8:

[0132] The method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors is the same as any one of Examples 1-7. Further, a chemical mechanical planarization process is used to planarize the (n-1) intermetallic dielectric layer to form a globally planarized dielectric layer and a tungsten plug structure.

[0133] Example 9:

[0134] A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors, with the same technical content as any one of Examples 1-3, further comprising using a high dielectric constant silicon-rich silicon nitride thin film deposited by PECVD as the dielectric layer of the metal MIM capacitor.

[0135] Example 10:

[0136] The method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors is the same as any one of Examples 1-9. Further, a high selectivity tungsten-silica chemical mechanical planarization process is used to complete the tungsten plug structure processing.

[0137] Example 11:

[0138] The metal MIM capacitor module obtained by using the low dielectric absorption, low mismatch precision linear MIM capacitor and integration technology described in any one of Examples 1-10 mainly includes a substrate, a well, a field oxide layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer, a polysilicon gate, and a metal thin film layer.

[0139] The substrate is located at the bottom; a well is formed on the surface of the substrate;

[0140] The field oxide layer forms outside the active region;

[0141] The active region includes the high-voltage device region, the medium-voltage device region, and the low-voltage device region;

[0142] Thick gate oxide layers are present in the high-voltage device region and the medium-voltage device region;

[0143] The low-voltage device region has a thin gate oxide layer;

[0144] Metal MIM capacitors are formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer;

[0145] The polysilicon gate of a MOSFET is constructed on a thick gate oxide layer and a thin gate oxide layer.

[0146] Example 12:

[0147] The low dielectric absorption, low mismatch precision linear MIM capacitor and integration technology compatible with multi-layer metal wiring, multi-mode gate oxide, high and low voltage BiCMOS / CMOS processes mainly include the following steps:

[0148] 1) A well is formed on the substrate surface, and an active region is formed on the surface of the well. An isolation field is formed in the region outside the active region. A shielding protective layer is formed on the surface of the active region and the field oxide layer, wherein the shielding protective layer can be a thermal oxide layer.

[0149] MOSFETs can be divided into NMOS transistors and PMOS transistors. Therefore, in this embodiment of the invention, the structure may include a metal thin-film resistor integrated with an NMOS transistor, a metal thin-film resistor integrated with a PMOS transistor, or a metal thin-film resistor integrated with both an NMOS transistor and a PMOS transistor. When the metal thin-film resistor is integrated with an NMOS transistor, the "well" in this step refers to a P-well. When the metal thin-film resistor is integrated with a PMOS transistor, the "well" in this step refers to an N-well. When the metal thin-film resistor is integrated with both an NMOS transistor and a PMOS transistor, the "well" in this step is a general term for both N-wells and P-wells.

[0150] 2) Complete the photolithography implantation process for the source and drain of dual-gate oxide high and low voltage CMOS, and select the regions for metal thin film resistors, active regions for high voltage devices, active regions for medium voltage devices, and active regions for low voltage devices.

[0151] 3) Thick gate oxide layers are formed in the active regions of both the high-voltage and medium-voltage devices. A thin gate oxide layer is formed after a stripped gate oxide layer is formed in the low-voltage device region not covered by the selected field oxide layer.

[0152] An LPCVD polysilicon layer is deposited on the surfaces of the thick gate oxide layer and the thin gate oxide layer, so that the polysilicon formed on the surface of the gate oxide layer and the gate oxide layer together form the polysilicon gate of the MOS transistor.

[0153] Photolithography and etching processes, such as dry polysilicon etching, are used to etch the polysilicon layer. Except for selected areas, the polysilicon on other surfaces is etched away, leaving the polysilicon on the gate oxide surface to form the polysilicon gate of the MOSFET. End-point detection is used in the gate polysilicon etching process. During oxide over-etching, the etching gas is modified by increasing the oxygen concentration to improve the selectivity ratio of polysilicon to gate oxide. This avoids...

[0154] Excessive silicon damage in the source and drain regions of the MOSFET.

[0155] 4) Photolithographic implantation of the dual-gate oxide high and low voltage CMOS source and drain in the doped source and drain regions of the MOS transistor is completed.

[0156] The impurity is either a P-type impurity or an N-type impurity.

[0157] First, lightly doped source / drain regions are formed using photolithography and ion implantation processes. (See also...) Figure 4 The "-" in the diagram indicates a low ion content. Next, two thin films of the same material as the first and second dielectric layers are deposited, and the two dielectric films are anisotropically etched to form sidewalls on both sides of the polysilicon gate.

[0158] See Figure 5 The heavily doped source / drain regions of the PMOS transistor are formed using photolithography and ion implantation processes. The "+" symbols in the diagram indicate a high ion content. A rapid annealing process is then performed, thus forming the doped source / drain regions of the PMOS transistor.

[0159] See Figure 5First, a low-pressure chemical vapor deposition (LPCVD) process is used to deposit a third dielectric layer. Then, a global chemical mechanical process (CMP) is employed to planarize the third dielectric layer. Following this, photolithography and etching processes are used to etch the third dielectric layer, forming contact holes for metal deposition. Tungsten metal is then deposited within these contact holes. After the tungsten metal is chemically and mechanically planarized, aluminum-silicon-copper alloys (Al-Si-Co) are sputtered. Finally, photolithography and etching processes are used to form metal interconnects in the desired areas.

[0160] After planarization using a chemical mechanical process for the third dielectric layer, the depth of the contact holes used for metal deposition ranges from several thousand angstroms to tens of thousands of angstroms. If a conventional reflow process is used to complete the planarization of the third dielectric layer, the subsequent photolithography exposure window for the contact holes will be relatively small, ultimately leading to fluctuations in device performance.

[0161] 5) A silicon oxynitride layer was deposited using low-pressure chemical vapor deposition (PECVD). A BPSG low-dielectric-coefficient filler layer was deposited using PECVD.

[0162] 6) The film planarization process is completed by chemical mechanical polishing (CMP), followed by dry etching process to complete the device contact hole processing.

[0163] 7) The device contact hole filling process is completed using tungsten sputtering and tungsten chemical mechanical planarization processes. An aluminum-silicon-copper film layer is sputtered, and the first layer of metal interconnect etching is completed.

[0164] 8) According to the circuit design requirements, repeat the following metal interconnect process steps: PECVD low dielectric constant filling film USG deposition, intermetallic dielectric layer CMP planarization, via etching, tungsten plug chemical mechanical planarization, and interconnect aluminum-silicon-copper metal sputtering etching. Continue until the next layer metal is sputtered, denoted as the (n-2)th metal layer, and complete the (n-2)th metal interconnect etching process.

[0165] Currently, analog integrated circuits are developing towards higher integration density and thinner, lighter sizes. High-performance analog integrated circuits require more than three layers of metal wiring. Therefore, CMP planarization of inter-metal dielectrics and tungsten plug structures have become basic process requirements.

[0166] 9) Deposit a low dielectric constant filled film USG, and use chemical mechanical polishing (CMP) process to complete the planarization of the intermetallic dielectric film, forming an m1 angstrom USG dielectric layer on the (n-2)th layer.

[0167] Dielectric chemical mechanical planarization ensures the flatness (DOP) of the lower surface region of the metal MIM capacitor to be manufactured, effectively controlling the non-planarity problem of the metal MIM capacitor and improving the processing accuracy and device stability of the metal MIM capacitor.

[0168] 10) According to the circuit design requirements, repeat the following metal interconnection process steps: PECVD deposition of low-dielectric-coefficient USG filler layer, CMP planarization of intermetallic dielectric layer, via etching, tungsten plug chemical mechanical planarization, and aluminum-silicon-copper metal sputtering etching. Continue until the next layer metal is sputtered, denoted as the (n-1)th layer. See [link to relevant documentation]. Figure 6 The metal interconnect structure film layer is tungsten / titanium / aluminum-silicon-copper / titanium nitride;

[0169] 11) After argon atom sputtering cleaning, an h1 Å titanium film was sputtered using magnetron plasma physical vapor deposition (PVD). See [link to relevant documentation]. Figure 7 Next, plasma-enhanced chemical vapor deposition (PECVD) was used to deposit h2 Å amorphous silicon nitride (Si). x N y H z Membrane layer, see Figure 8 ;

[0170] Preferably, sputtering a microcrystalline titanium film with a thickness of h1 Å using magnetron plasma PVD can effectively optimize the metal film layer system of the lower electrode of a metal capacitor.

[0171] Preferably, sputtering a microcrystalline titanium film with a thickness of h1 angstroms can reduce the compressive stress of the aluminum alloy film layer of the lower electrode in a metal MIM capacitor and improve surface unevenness such as Hilllock defects in the metal film layer.

[0172] Sputtering a 1 angstrom-thick microcrystalline titanium film as the dielectric layer using PECVD silicon nitride

[0173] Si x N y H z It provides an excellent film-forming environment, reduces the density of interlayer traps, and thus further improves the performance of silicon nitride (Si). x N y H z Dielectric strength and capacitor operating voltage range.

[0174] 12) After argon atom sputtering cleaning, h3 angstrom microcrystalline titanium thin films were sputtered onto the silicon nitride film using magnetron plasma physical vapor deposition (PVD). See [link to relevant documentation]. Figure 9 ;

[0175] Sputtering a 3 Å thick microcrystalline titanium film onto a silicon nitride film using magnetron plasma PVD can effectively optimize and reduce the dielectric film thickness of metal MIM capacitors. x N y H z The stress;

[0176] Sputtering a 3 Å thick microcrystalline titanium film on a silicon nitride film using magnetron plasma PVD can reduce the probability of series pinhole defects in the capacitor dielectric film, providing an excellent film formation environment and further improving the performance of silicon nitride. x N y H z Dielectric strength and capacitor operating voltage range.

[0177] 13) In the integrated magnetron sputtering chamber, h4 Å semi-crystalline titanium / h5 Å titanium nitride is deposited by in-situ PVD deposition using surface chemical reaction.

[0178] Depositing low-resistivity semi-crystalline titanium / titanium nitride on high-resistivity microcrystalline titanium films using in-situ magnetron sputtering PVD can improve the adhesion between the dielectric film of a metal MIM capacitor and the metal alloy system of the upper electrode of the metal MIM capacitor.

[0179] Low-resistivity semi-crystalline titanium / titanium nitride was deposited on a high-resistivity microcrystalline titanium film using an integrated magnetron sputtering in-situ PVD method, which acted as a barrier layer and ensured the excellent conductivity of the metal alloy system of the upper electrode of the metal MIM capacitor.

[0180] 14) PVD sputtering is used to deposit aluminum alloy thin films and anti-reflective titanium nitride films suitable for planarization processes. See [link to relevant documentation]. Figure 10 ;

[0181] 15) Based on the mask pattern, perform exposure, development, and dry etching on the upper electrode of the MIM capacitor using titanium / titanium nitride / aluminum silicon copper / titanium nitride.

[0182] 16) Based on the mask pattern, perform exposure, development, and dry etching on the lower electrode of the MIM capacitor and the (n-1)th layer of metal interconnect wiring;

[0183] 17) The resulting integrated metal-silicon nitride-metal capacitor exhibits characteristics such as dielectric absorption coefficient DA, second-order voltage coefficient QVC, and linear voltage coefficient LVC. See [reference needed]. Figure 11 ;

[0184] Figure 11In the above, 101 is the second-to-top layer metal; 102 is the high-resistivity microcrystalline titanium film (preferred) for the lower electrode of the metal MIM capacitor; 103 is the PECVD silicon-rich silicon nitride film layer for the dielectric of the metal MIM capacitor; 104 is the high-resistivity microcrystalline titanium film (preferred) for the upper electrode of the metal MIM capacitor; 105 is the tungsten plug for the interconnection between the top layer metal and the second-to-top layer metal; 201 is the tungsten plug for the interconnection between the lower electrode and the top layer metal of the metal MIM capacitor; 202 is the top layer metal system; 203 is the metal system for the upper electrode of the metal MIM capacitor; 204 is the low-resistivity semi-crystalline titanium film layer for the upper electrode of the metal MIM capacitor; and 205 is the titanium nitride film layer as the barrier layer for the upper electrode of the metal MIM capacitor.

[0185] 18) PECVD was used to deposit a low-dielectric-coefficient filled USG thin film, followed by CMP planarization of the intermetallic dielectric layer, via etching, and tungsten plug chemical mechanical planarization.

[0186] By employing a high-selectivity tungsten-silica chemical mechanical planarization process to complete the tungsten plug structure processing, the steps on the lower surface of the top metal can be controlled, and the consistency of the dielectric layer thickness within and between the metal MIM capacitors can be ensured. This effectively improves the quality factor of the metal MIM capacitors, and enhances their consistency and yield.

[0187] 19) Sputter the top layer metal, denoted as the nth layer metal, and complete the etching process of the nth layer metal interconnect to form the metal interconnect of MIM capacitors and other circuit components;

[0188] 20) PECVD is used to deposit the passivation composite dielectric layer, and the passivation protective layer is then exposed, developed, and etched. See [link to documentation]. Figure 12 .

Claims

1. A method for integrating low dielectric absorption and low mismatch precision linear MIM capacitors, characterized in that, Includes the following steps: 1) A well is formed on the substrate surface, and an active region is formed on the surface of the well. An isolation oxide layer is formed in the region outside the active region. 2) Select the regions for metal thin film resistors, high-voltage active devices, medium-voltage active devices, and low-voltage active devices that require low temperature coefficients; 3) Thick gate oxide layers are formed in the active regions of high-voltage devices and medium-voltage devices, respectively; thin gate oxide layers are formed in the active regions of low-voltage devices. 4) Form the polysilicon gate of the MOSFET and select the doped source and drain regions of the MOSFET; 5) Photolithographic implantation of dual-gate oxygen high and low voltage CMOS source and drain is completed in the doped source and drain regions of the MOS transistor, and the doped impurities are activated by rapid annealing process; 6) Deposit a silicon nitride layer and a BPSG low dielectric constant filling film; 7) Complete the film planarization process and the device contact hole processing; 8) Complete the tungsten plug filling process for the device contact holes; sputter an aluminum-silicon-copper film layer, denoted as the first metal layer, and complete the etching process for the first metal layer interconnects; 9) Repeat steps 6)-8) as needed for circuit design until the second-to-last layer of metal is sputtered, denoted as the (n-1)th layer of metal; n≥2; 10) After completing the argon atom sputtering cleaning, sputter the h1 angstrom titanium film, and then deposit the h2 angstrom amorphous silicon nitride SixNyHz film; 11) After argon atom sputtering cleaning, h3 angstrom microcrystalline titanium thin film is sputtered on silicon nitride film layer; 12) Deposit h4 Å semi-crystalline titanium / h5 Å titanium nitride in an integrated magnetron sputtering chamber; 13) PVD sputtering is used to deposit aluminum alloy thin films and anti-reflective titanium nitride films suitable for planarization processes; 14) Based on the mask pattern, expose, develop, and dry etch the titanium / titanium nitride / aluminum silicon copper / titanium nitride on the upper electrode of the MIM capacitor to form an integrated metal-silicon nitride-metal capacitor. The resulting integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs(QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs(LVC) ≤ 1.5ppm / V. 15) Deposition of low dielectric constant filled film USG thin film, CMP planarization of intermetallic dielectric layer, via etching, and tungsten plug chemical mechanical planarization; 16) Sputter the top layer metal, denoted as the nth layer metal, and complete the etching process of the nth layer metal interconnects to form the metal interconnects of the circuit components; 17) PECVD is used to deposit the passivation composite dielectric layer, and the passivation protective layer is exposed, developed and etched.

2. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: In step 4), the step of forming the polysilicon gate of the MOS transistor is as follows: depositing a polysilicon gate layer on the surface, doping the polysilicon layer, and then etching the polysilicon gate structure, so that the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS transistor.

3. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: In step 6), a silicon nitride layer is deposited using low-pressure chemical vapor deposition; a BPSG low-dielectric-coefficient filling film is deposited using PECVD. In step 7), chemical mechanical polishing (CMP) is used to planarize the film layer; dry etching is used to process the device contact holes. In step 8), tungsten sputtering and tungsten chemical mechanical planarization processes are used to complete the tungsten plug filling of the device contact holes; In step 10), a 1 Å titanium film is sputtered using magnetron plasma physical vapor deposition (PVD); a 2 Å amorphous silicon nitride SixNyHz film is deposited using plasma-enhanced chemical vapor deposition (PECVD). In step 11), a h3 angstrom microcrystalline titanium thin film is sputtered using magnetron plasma physical vapor deposition (PVD). In step 12), h4 Å semi-crystalline titanium / h5 Å titanium nitride is deposited by PVD using a surface chemical reaction in-situ method. In step 15), a low dielectric constant filled film, USG film, is deposited using the PECVD method.

4. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: In step 9), the interconnect structure film of the (n-1)th metal layer is tungsten / titanium / aluminum-silicon-copper / titanium nitride; In step 16), the circuit components include MOS devices and MIM capacitors.

5. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: h1 = 50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 Å.

6. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: The impurity is either a P-type impurity or an N-type impurity.

7. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: A chemical mechanical planarization process was used to planarize the (n-1) intermetallic dielectric layer to form a globally planarized dielectric layer and a tungsten plug structure.

8. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: High dielectric constant silicon-rich silicon nitride thin films deposited by PECVD are used as the dielectric layer of metal MIM capacitors.

9. The integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to claim 1, characterized in that: The tungsten plug structure was fabricated using a high selectivity tungsten-silica chemical mechanical planarization process.

10. A MIM capacitor obtained using the integration method of the low dielectric absorption, low mismatch precision linear MIM capacitor according to any one of claims 1 to 9, characterized in that, This includes a substrate, a well, a field oxide layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer, a polysilicon gate, and a metal thin film layer; The substrate is located at the bottom; The well is formed on the substrate surface; The field oxide layer forms outside the active region; The active region includes the high-voltage device region, the medium-voltage device region, and the low-voltage device region; Thick gate oxide layers are present in the high-voltage device region and the medium-voltage device region; The low-voltage device region has a thin gate oxide layer; Metal MIM capacitors are formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer; The polysilicon gate of a MOSFET is constructed on a thick gate oxide layer and a thin gate oxide layer.

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