Semiconductor package with glass core substrate and method of manufacturing the same

Abstract

A semiconductor package includes a wiring substrate and a first semiconductor chip disposed on the wiring substrate. The wiring substrate includes: a first core portion including glass and having a cavity vertically penetrating the first core portion; first core vias, each of the first core vias vertically penetrating the first core portion; a passive device in the cavity of the first core portion; a buried material on the first core portion and the first core via and covering a top surface and an outer side surface of the first core portion; and an upper build-up portion disposed on the buried material. The upper build-up portion includes a first dielectric pattern and a first wiring pattern penetrating the first dielectric pattern and the buried material and coupled to the first core via.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0091122 filed on July 13, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor package, and more particularly, to a semiconductor package including a package substrate including a glass core and a method of manufacturing the semiconductor package. Background Art

[0003] As the electronics industry develops, electronic products become more powerful, faster, and more compact in size. To meet this trend, a packaging technology that mounts a plurality of semiconductor chips in a single package has recently been developed.

[0004] Semiconductor packaging is a device used to house and protect integrated circuit chips and facilitate the interconnection of chips with electronic products. Typically, semiconductor packaging is configured so that the semiconductor chip is mounted on a printed circuit board (PCB) and the packaged semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. Summary of the invention

[0005] A semiconductor package includes a wiring substrate and a first semiconductor chip arranged on the wiring substrate. The wiring substrate includes a first core portion, the first core portion including glass. The first core portion includes a cavity vertically penetrating the first core portion. A plurality of first core vias vertically penetrate the first core portion. Passive devices are arranged in the cavity of the first core portion. A buried material is arranged on the first core portion and the first core via. The buried material fills the cavity and covers the top surface and the outer side surface of the first core portion. An upper buildup portion is arranged on the buried material. The upper buildup portion includes a first dielectric pattern and a first wiring pattern, the first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the first core via.

[0006] A semiconductor package includes a first interposer substrate. A second interposer substrate is disposed on the first interposer substrate. A first semiconductor chip is disposed on the second interposer substrate. A chip stack is disposed on the second interposer substrate and is spaced apart from the first semiconductor chip. The chip stack includes a plurality of second semiconductor chips stacked vertically. A plurality of connection terminals are disposed below the first interposer substrate. The first interposer substrate includes a lower buildup portion. A first core portion is disposed on the lower buildup portion and includes glass, the first core portion including a cavity vertically penetrating the first core portion. A buried material is disposed on the lower buildup portion and covers the first core portion. An upper buildup portion is disposed on the buried material. A passive device is disposed in the cavity of the first core portion. An outer side surface of the first core portion is positioned more inward than an outer side surface of the buried material. The second interposer substrate includes a second core portion. The second core portion includes a material different from that of the first core portion.

[0007] A semiconductor package includes a wiring substrate. A first semiconductor chip is arranged on the wiring substrate. The wiring substrate includes a lower buildup portion. An upper buildup portion is arranged on the lower buildup portion. A buried material fills a space between the lower buildup portion and the upper buildup portion. A first core portion is arranged in the buried material. The first core portion includes a cavity that vertically penetrates the first core portion. The distance between the outer surface of the first core portion and the outer surface of the buried material is in the range of about 0.1 mm to about 3 mm. A plurality of first core vias vertically penetrate the first core portion. A passive device is arranged in the cavity of the first core portion. The upper buildup portion includes a first dielectric pattern and a first wiring pattern, the first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the first core via. The lower buildup portion includes a second dielectric pattern. The second wiring pattern penetrates the second dielectric pattern and is coupled to the first core via. The stiffness of the first material included in the first core portion is greater than the stiffness of the second material included in the first dielectric pattern and the stiffness of the third material included in the second dielectric pattern.

[0008] A method for manufacturing a semiconductor package includes arranging a core portion including glass on a carrier substrate. An etching process is performed on the core portion to form a plurality of cavities, a plurality of via holes and a plurality of grooves. The cavities, via holes and grooves vertically penetrate the core portion. The grooves define a plurality of substrate regions spaced apart from each other. The cavities and via holes are arranged in the substrate regions. A conductive material fills the via holes to form a plurality of core vias. A plurality of passive devices are placed in the cavities. A buried material is formed that fills the cavities and grooves and covers the core portion and the core vias. The carrier substrate is removed to expose the bottom surface of the buried material, the bottom surface of the core portion and the bottom surface of the passive devices. A lower buildup portion is formed on the bottom surface of the buried material and the bottom surface of the core portion. The lower buildup portion is electrically connected to the core vias. An upper buildup portion is formed on the buried material. A wiring pattern of the upper buildup portion penetrates the buried material and is electrically connected to the core vias. A cutting process is performed on the buried material, the upper buildup portion and the lower buildup portion to separate a plurality of wiring substrates from each other. The cutting process is performed along the grooves. The semiconductor chip is mounted on the wiring substrate. A cutting surface of the cutting process is horizontally spaced apart from the core part. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0010] Figure 2 yes Figure 1 An enlarged view of portion "A".

[0011] Figure 3 is a plan view of a semiconductor package according to an embodiment of the inventive concept.

[0012] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0013] Figure 5 yes Figure 4 An enlarged view of portion "B" of FIG.

[0014] Figure 6 and Figure 7 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0015] Figure 8 yes Figure 7 An enlarged view of portion "C".

[0016] Fig. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0017] Fig.10 yes Fig. 9 An enlarged view of portion "D" of FIG.

[0018] Fig.11 and Fig.12 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0019] FIG. 13A to FIG. 19A is a cross-sectional view of a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0020] FIG. 13B to FIG. 19B is a plan view of a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] A semiconductor package according to the inventive concept will be described below with reference to the accompanying drawings.

[0022] Figure 1 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. Figure 2 yes Figure 1 An enlarged view of portion "A". Figure 3 is a plan view of a semiconductor package according to an embodiment of the inventive concept.

[0023] Reference Figures 1 to 3 , a semiconductor package may include a semiconductor chip and a package substrate for mounting the chip to an external device or an external substrate.

[0024] A package substrate may be provided. The package substrate may include a core portion 110 , a lower buildup portion 120 disposed on a bottom surface of the core portion 110 , an upper buildup portion 130 disposed on a top surface of the core portion 110 , and a buried material 140 .

[0025] The lower build-up portion 120 may cover the bottom surface of the core portion 110. The lower build-up portion 120 may include one or more first substrate wiring layers sequentially stacked on the bottom surface of the core portion 110. For example, the lower build-up portion 120 may include three first substrate wiring layers. Each first substrate wiring layer may include a lower dielectric pattern 122 and a lower wiring pattern 124 in the lower dielectric pattern 122. The lower wiring pattern 124 of a specific first substrate wiring layer may be electrically connected to the lower wiring pattern 124 of another first substrate wiring layer adjacent to the specific first substrate wiring layer.

[0026] The material included in the lower dielectric pattern 122 may have a stiffness smaller than that of the material included in the core portion 110. The lower dielectric pattern 122 may include a dielectric polymer or a photo-imaging dielectric (PID). Alternatively, the lower dielectric pattern 122 may include a prepreg, an Ajinomoto built-up film (ABF), a flame retardant 4 (FR-4), or a bismaleimide triazine (BT).

[0027] The lower wiring pattern 124 may include a circuit pattern. The lower wiring pattern 124 may be arranged on the lower dielectric pattern 122. The lower wiring pattern 124 may be arranged on the bottom surface of the lower dielectric pattern 122. The lower wiring pattern 124 may protrude onto the bottom surface of the lower dielectric pattern 122. The lower wiring pattern 124 may extend horizontally on the bottom surface of the lower dielectric pattern 122. Below the lower dielectric pattern 122, the lower wiring pattern 124 may be covered by another lower dielectric pattern 122. The lower wiring pattern 124 may be a pad or line portion of the first substrate wiring layer. The lower wiring pattern 124 may include a conductive material. For example, the lower wiring pattern 124 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and any combination thereof.

[0028] The lower wiring pattern 124 may have a mosaic structure. For example, the lower wiring pattern 124 may have a via protruding onto its top surface. The via may be a component for vertical connection between the lower wiring patterns 124 of adjacent first substrate wiring layers. For example, the via may extend from the top surface of the lower wiring pattern 124 through the lower dielectric pattern 122, and may be coupled to the bottom surface of the lower wiring pattern 124 of another first substrate wiring layer covered thereon. The lower portion of the lower wiring pattern 124 disposed below the lower dielectric pattern 122 may be a head used as a horizontal wiring line or pad, and the via of the lower wiring pattern 124 may be a tail. The lower wiring pattern 124 may have an inverted T shape.

[0029] The lower substrate protective layer 126 may be disposed below the lower buildup portion 120. The lower substrate protective layer 126 may cover the lowermost first substrate wiring layer. On the bottom surface of the lowermost first substrate wiring layer, the lower substrate protective layer 126 may cover the lower wiring pattern 124. The lower substrate protective layer 126 may include a prepreg, an Ajinomoto built-up film (ABF), a flame retardant 4 (FR-4), or bismaleimide triazine (BT). The lower substrate protective layer 126 may not be disposed as needed.

[0030] The lower substrate pad 128 may be disposed on the bottom surface of the lower substrate protective layer 126. The lower substrate pad 128 may vertically penetrate the lower substrate protective layer 126, and may be coupled to the lower wiring pattern 124 of the lowermost first substrate wiring layer.

[0031] According to an embodiment, the lower substrate protection layer 126 may cover the bottom surface of the lowermost first substrate wiring layer, and may expose the bottom surface of the lower wiring pattern 124 exposed on the bottom surface of the lowermost first substrate wiring layer. In this case, the exposed lower wiring pattern 124 may be used as a substrate pad. The following description will focus on Figure 1 Embodiment of the invention.

[0032] The external terminal 102 may be disposed on the bottom surface of the lower substrate pad 128. The external terminal 102 may include a solder ball or a solder bump. Based on the type and arrangement of the external terminal 102, the semiconductor package may be disposed in the form of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, or a land grid array (LGA) type.

[0033] The core part 110 may be disposed on the lower buildup part 120. The core part 110 may extend in one direction. In a plan view, the core part 110 may include a single core pattern. For example, the core part 110 may have a plate shape. Although the core part 110 having a single core pattern is discussed by way of example, the inventive concept is not necessarily limited thereto. According to an embodiment, the core part 110 may include two or more core patterns. For example, the package substrate may include a plurality of core patterns spaced apart from each other in a plan view. The core part 110 may contact the top surface of the lower buildup part 120. The width of the core part 110 may be smaller than the width of the lower buildup part 120. For example, the planar shape of the core part 110 may be smaller than the planar shape of the lower buildup part 120. In a plan view, the core part 110 may be disposed inside the lower buildup part 120. For example, the core part 110 may have an outer side surface 110a that is spaced apart from the outer side surface 120a of the lower buildup part 120 in an inward direction. The rigidity of the material included in the core portion 110 may be greater than the rigidity of the material included in the lower dielectric pattern 122 and the rigidity of the material included in the upper dielectric pattern 132, which will be discussed below. The core portion 110 may include a dielectric material. For example, the core portion 110 may include glass fiber. For example, the package substrate may be a glass-based wiring substrate.

[0034] The core part 110 may include one or more cavities CA that pass through the core part 110. For example, the cavity CA may be shaped like an opening connecting the top surface and the bottom surface of the core part 110. The cavity CA may be defined as indicating a space in which an internal device 150 is disposed, and the internal device 150 will be discussed below. In a plan view, each cavity CA may be disposed adjacent to a central portion of the core part 110.

[0035] The core part 110 may include vertical connection terminals 112, each vertical connection terminal 112 vertically penetrating the core part 110. The vertical connection terminal 112 may extend from the bottom surface of the core part 110 to the top surface of the core part 110. For example, the vertical connection terminal 112 may be a core via for vertical electrical connection in the core part 110. The vertical connection terminal 112 may be exposed on the bottom surface of the core part 110 and the top surface of the core part 110. The vertical connection terminal 112 may have a bottom surface coplanar with the bottom surface of the core part 110. The vertical connection terminal 112 may have a top surface coplanar with the top surface of the core part 110. In a plan view, the vertical connection terminal 112 may be disposed outside the cavity CA. For example, the vertical connection terminal 112 may be disposed between the cavity CA and the outer side surface 110a of the core part 110. In addition, in a plan view, the vertical connection terminal 112 may be disposed between the cavities CA. The vertical connection terminal 112 may electrically connect the upper buildup part 130 to the lower buildup part 120. The lower wiring pattern 124 of the uppermost first substrate wiring layer in the lower buildup part 120 may penetrate the lower dielectric pattern 122 and may be coupled to the vertical connection terminal 112. Therefore, the vertical connection terminal 112 may be electrically connected to the lower buildup part 120. The vertical connection terminal 112 may include a metal, such as copper (Cu) or tungsten (W).

[0036] One or more internal devices 150 may be disposed on the lower buildup portion 120. The internal devices 150 may be disposed in the cavity CA of the core portion 110, respectively. Figure 1 Depicted is an internal device 150 disposed in a cavity CA, but the inventive concept is not necessarily limited thereto. According to an embodiment, two or more internal devices 150 may be disposed in a cavity CA. The internal device 150 may be disposed on the lower stacking portion 120 exposed by the cavity CA. The internal device 150 may be in contact with the top surface of the lower stacking portion 120. The internal device 150 may be spaced apart from the core portion 110. For example, the internal device 150 may be spaced apart from the inner sidewall of the cavity CA accordingly. The top surface of the internal device 150 may be located at a level that is the same as the level of the top surface of the core portion 110 or lower than the level of the top surface of the core portion 110 relative to the lower stacking portion 120. The internal device 150 may be a passive device. For example, the internal device 150 may include a resistor, a capacitor, or an inductor. According to an embodiment, the internal device 150 may be a memory chip or a logic chip.

[0037] The internal device 150 may be electrically connected to the lower build-up portion 120. Direct bonding may be employed to mount the internal device 150 on the lower build-up portion 120. For example, each internal device 150 may include a semiconductor layer 152 having a passive device on its bottom surface, a device wiring layer 154 disposed on the bottom surface of the semiconductor layer 152 and electrically connected to the passive device, and a chip pad 156 disposed on the bottom surface of the device wiring layer 154 and electrically connected to the passive device through the device wiring layer 154. The chip pad 156 may be disposed on the bottom surface of the internal device 150. For example, the bottom surface of the internal device 150 may be an active surface. The internal device 150 may be disposed on the lower build-up portion 120 in a face-down state. The chip pad 156 may protrude from the bottom surface of the device wiring layer 154. The internal device 150 may be in contact with the lower build-up portion 120. The chip pad 156 may vertically separate the device wiring layer 154 from the lower build-up portion 120. For example, the chip pads 156 of the internal device 150 may contact the top surface of the lower build-up part 120, and between the chip pads 156, an empty space may be provided between the lower build-up part 120 and the device wiring layer 154 of the internal device 150. The lower wiring pattern 124 of the first substrate wiring layer in the lower build-up part 120 may penetrate the uppermost lower dielectric pattern 122 and may be coupled to the chip pads 156 of the internal device 150. Therefore, the internal device 150 may be electrically connected to the lower build-up part 120.

[0038] The buried material 140 may be disposed on the lower build-up portion 120. On the lower build-up portion 120, the buried material 140 may cover the core portion 110. On the lower build-up portion 120, the buried material 140 may completely bury the core portion 110. For example, the buried material 140 may cover the top surface and the outer side surface 110a of the core portion 110. The buried material 140 may have an outer side surface 140a spaced apart from the outer side surface 110a of the core portion 110. For example, the outer side surface 110a of the core portion 110 may be positioned more inwardly than the outer side surface 140a of the buried material 140. A length L of about 0.1 mm to about 3 mm may be disposed between the outer side surface 110a of the core portion 110 and the outer side surface 140a of the buried material 140. The buried material 140 may cover the top surface of the core portion 110, and neither the core portion 110 nor the vertical connection terminal 112 may be exposed by the buried material 140. The buried material 140 may fill the cavity CA. For example, in the cavity CA, the buried material 140 may cover the internal device 150. The buried material 140 may fill the space between the internal device 150 and the inner wall of the cavity CA and the space between the internal device 150 and the lower build-up portion 120. For example, the buried material 140 may fill the unoccupied portion of the cavity CA in which the internal device 150 is disposed. The bottom surface of the buried material 140 may be coplanar with the bottom surface of the core portion 110. The buried material 140 may have a width substantially the same as the width of the lower build-up portion 120. For example, the outer side surface 140a of the buried material 140 may be vertically aligned with the outer side surface 120a of the lower build-up portion 120. The outer side surface 140a of the buried material 140 may be substantially coplanar with the outer side surface 120a of the lower build-up portion 120. The buried material 140 may include a dielectric material. For example, the burying material 140 may include Ajinomoto build-up film (ABF) or epoxy molding compound (EMC).

[0039] According to an embodiment of the present invention, the core portion 110 may contact the top surface of the lower buildup portion 120, and on the lower buildup portion 120, the buried material 140 may bury the core portion 110. Therefore, the buried material 140 may contact all edge EDGs of the core portion 110. Therefore, the buried material 140 may protect the edge EDGs of the core portion 110. When the core portion 110 is formed of glass, the edge EDG may be more fragile than any other portion (e.g., the surface or the interior). According to the present invention, the buried material 140 may protect the core portion 110, in particular the edge EDGs of the core portion 110, from external impacts and / or stresses, and a package substrate having improved structural stability and a semiconductor package including the package substrate may be provided.

[0040] The upper build-up portion 130 may be disposed on the top surface of the buried material 140. The upper build-up portion 130 may cover the top surface of the buried material 140. The upper build-up portion 130 may include one or more second substrate wiring layers sequentially stacked on the top surface of the buried material 140. For example, the upper build-up portion 130 may include two "second substrate wiring layers". Each second substrate wiring layer may include an upper dielectric pattern 132 and an upper wiring pattern 134 in the upper dielectric pattern 132. The upper dielectric pattern 132 of a specific second substrate wiring layer may be electrically connected to the upper dielectric pattern 132 of another second substrate wiring layer adjacent to the specific second substrate wiring layer.

[0041] The material included in the upper dielectric pattern 132 may have a stiffness less than that of the material included in the core portion 110. The upper dielectric pattern 132 may include a dielectric polymer or a photo-imaging dielectric (PID). Alternatively, the upper dielectric pattern 132 may include a prepreg, an Ajinomoto built-up film (ABF), a flame retardant 4 (FR-4), or a bismaleimide triazine (BT).

[0042] The upper wiring pattern 134 may include a circuit pattern. The upper wiring pattern 134 may be arranged on the upper dielectric pattern 132. The upper wiring pattern 134 may be arranged on the top surface of the upper dielectric pattern 132. The upper wiring pattern 134 may protrude onto the top surface of the upper dielectric pattern 132. The upper wiring pattern 134 may extend horizontally on the top surface of the upper dielectric pattern 132. On the upper dielectric pattern 132, the upper wiring pattern 134 may be covered by another upper dielectric pattern 132. The upper wiring pattern 134 may be a pad or a line portion of the second substrate wiring layer. The upper wiring pattern 134 may include a conductive material. For example, the upper wiring pattern 134 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and any combination thereof.

[0043] The upper wiring pattern 134 may have a mosaic structure. For example, the upper wiring pattern 134 may have a via protruding onto its bottom surface. The via may be a component for vertical connection between the upper wiring patterns 134 of the adjacent second substrate wiring layers. For example, the via may extend from the bottom surface of the upper wiring pattern 134 through the upper dielectric pattern 132 and couple to the top surface of the upper wiring pattern 134 of another second substrate wiring layer below. The upper portion of the upper wiring pattern 134 located on the upper dielectric pattern 132 may be a header used as a horizontal wiring line or pad, and the via of the upper wiring pattern 134 may be a tail. The upper wiring pattern 134 may have a T shape.

[0044] The upper buildup part 130 may be electrically connected to the vertical connection terminal 112. The upper wiring pattern 134 of the lowermost second substrate wiring layer in the upper buildup part 130 may penetrate the upper dielectric pattern 132 and the buried material 140, and may be coupled to the vertical connection terminal 112. Therefore, the upper buildup part 130 may be electrically connected to the lower buildup part 120 through the vertical connection terminal 112.

[0045] The upper substrate protection layer 136 may be disposed on the upper buildup portion 130. The upper substrate protection layer 136 may cover the uppermost second substrate wiring layer. On the top surface of the uppermost second substrate wiring layer, the upper substrate protection layer 136 may cover the upper wiring pattern 134. The upper substrate protection layer 136 may include a prepreg, an Ajinomoto built-up film (ABF), a flame retardant 4 (FR-4), or bismaleimide triazine (BT). The upper substrate protection layer 136 may not be disposed as required.

[0046] The upper substrate pad 138 may be disposed on the top surface of the upper substrate protective layer 136. The upper substrate pad 138 may vertically penetrate the upper substrate protective layer 136, and may be coupled to the upper wiring pattern 134 of the uppermost second substrate wiring layer.

[0047] According to an embodiment, the upper substrate protection layer 136 may cover the top surface of the uppermost second substrate wiring layer and may expose the top surface of the upper wiring pattern 134 exposed on the top surface of the uppermost second substrate wiring layer. In this case, the exposed upper wiring pattern 134 may be used as a substrate pad.

[0048] In the following examples, with reference to Figures 1 to 3 Components discussed that are identical may be assigned the same reference numerals, and where an element is not described in detail with reference to the figure, it is understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure. The following description will focus on Figures 1 to 3 The differences between the embodiment and other embodiments described below.

[0049] Figures 1 to 3 The vertical connection terminals 112 are depicted to be disposed in the core portion 110. For example, the top surface of the vertical connection terminals 112 is shown to be coplanar with the top surface of the core portion 110, and the bottom surface of the vertical connection terminals 112 is coplanar with the bottom surface of the core portion 110. However, the inventive concept is not necessarily limited thereto.

[0050] Figure 4 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. Figure 5 Shows Figure 4 An enlarged view of portion "B" of FIG.

[0051] Reference Figure 4 and Figure 5 , a portion of each vertical connection terminal 112 may extend to the top surface of the core portion 110 or the bottom surface of the core portion 110. One vertical connection terminal 112 will be described below.

[0052] The vertical connection terminal 112 may include a via hole 114 vertically penetrating the core portion 110. The via hole 114 may be a portion of the vertical connection terminal 112 located in the core portion 110.

[0053] A portion of the vertical connection terminal 112 may extend onto the bottom surface of the core portion 110. A portion of the vertical connection terminal 112 protruding onto the bottom surface of the core portion 110 may correspond to a first land contact 116, which is a pad for coupling the lower buildup portion 120 to the core portion 110. For example, a lower wiring pattern 124 of the uppermost first substrate wiring layer in the lower buildup portion 120 may penetrate the lower dielectric pattern 122 and may be coupled to the first land contact 116. The first land contact 116 may separate the core portion 110 from the lower buildup portion 120. For example, the interval between the bottom surface of the core portion 110 and the top surface of the lower buildup portion 120 may correspond to the thickness of the first land contact 116. The space between the core portion 110 and the lower buildup portion 120 may be filled with a buried material 140. The buried material 140 may at least partially surround the first land contact 116 between the core portion 110 and the lower buildup portion 120.

[0054] According to an embodiment of the inventive concept, the buried material 140 may cover all top surfaces, outer side surfaces 110a, and bottom surfaces of the core portion 110. The buried material 140 may be in contact with all edge EDGs of the core portion 110. For example, the core portion 110 may be completely buried in the buried material 140, and the buried material 140 may protect the edge EDGs of the core portion 110 from external impact and stress, and a package substrate having improved structural stability and a semiconductor package including the package substrate having improved structural stability may be provided.

[0055] Another portion of the vertical connection terminal 112 may extend onto the top surface of the core portion 110. The other portion of the vertical connection terminal 112 protruding onto the top surface of the core portion 110 may correspond to the second contact portion 118, which is a pad to which the upper buildup portion 130 is coupled. For example, the upper wiring pattern 134 of the lowermost second substrate wiring layer in the upper buildup portion 130 may penetrate the upper dielectric pattern 132 and the buried material 140, and may be coupled to the vertical connection terminal 112. The buried material 140 may cover the second contact portion 118 and the top surface of the core portion 110.

[0056] Figure 4 and Figure 5 The first contact portion 116, the second contact portion 118, and the via 114 are depicted as being provided as a single entity, but the inventive concept is not necessarily limited thereto. According to an embodiment, the first contact portion 116 and the second contact portion 118 may be provided as discrete components relative to the via 114. For example, the first contact portion 116 may be provided on the bottom surface of the core portion 110, and the second contact portion 118 may be provided on the top surface of the core portion 110. The via 114 may vertically penetrate the core portion 110 and may connect the first contact portion 116 and the second contact portion 118 to each other.

[0057] According to an embodiment, the protection pattern may be provided on one or both of the top surface and the bottom surface of the core portion 110. The protection pattern may at least partially surround the first contact portion 116 or the second contact portion 118. The first contact portion 116 or the second contact portion 118 may be exposed on one surface of the protection pattern. One surface of the protection pattern may be coplanar with the top surface of the first contact portion 116 or the bottom surface of the second contact portion 118. In this case, the protection pattern at least partially surrounding the first contact portion 116 may contact the lower buildup portion 120. For example, the space between the core portion 110 and the lower buildup portion 120 may be filled with the protection pattern.

[0058] Figure 6 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0059] Reference Figure 6 , the lower build-up portion 120 may not be disposed on the package substrate in the semiconductor package. For example, the bottom surface of the buried material 140 may be exposed, the bottom surface of the internal device 150 may be exposed, and the bottom surface of the core portion 110 may be exposed. The buried material 140 may cover the bottom surface of the device wiring layer 154 included in the internal device 150, and the chip pad 156 may be exposed on the bottom surface of the buried material 140. When the vertical connection terminal 112 is as shown in FIG. Figure 4and Figure 5 When the first contact portion 116 and the second contact portion 118 are included as in the embodiment of the present invention, the buried material 140 may cover the bottom surface of the core portion 110, and the first contact portion 116 may be exposed on the bottom surface of the buried material 140. For example, the chip pad 156 and the first contact portion 116 may be exposed on the bottom surface of the buried material 140.

[0060] The external terminal 102 may be disposed under the core portion 110 and the internal device 150. The external terminal 102 may be coupled to a bottom surface of the chip pad 156 and a bottom surface of the vertical connection terminal 112 (or a bottom surface of the first land contact portion 116).

[0061] According to an embodiment, when the core portion 110 is buried in the burying material 140, even when the lower buildup portion 120 is not provided below the core portion 110, the edge of the core portion 110 can be protected by the burying material 140. In addition, since the lower buildup portion 120 is not provided, the package substrate can have a reduced thickness. Therefore, a package substrate whose structural stability is improved and whose size is reduced can be provided, and a semiconductor package including the package substrate can also be provided.

[0062] Figure 7 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. Figure 8 yes Figure 7 An enlarged view of portion "C".

[0063] Figures 1 to 6 It is depicted that the internal device 150 is disposed on the lower stacking portion 120 in a face-down state, but the present inventive concept is not necessarily limited thereto.

[0064] Reference Figure 7 and Figure 8 , the internal device 150 may be disposed on the lower build-up portion 120 in a face-up state. For example, each internal device 150 may include a semiconductor layer 152 having a passive device on its top surface, a device wiring layer 154 disposed on the top surface of the semiconductor layer 152 and electrically connected to the passive device, and a chip pad 156 disposed on the top surface of the device wiring layer 154 and electrically connected to the passive device through the device wiring layer 154. The chip pad 156 may be disposed on the top surface of the internal device 150. For example, the top surface of the internal device 150 may be an active surface. The internal device 150 may have an inactive surface or a bottom surface in contact with the lower build-up portion 120. If necessary, an adhesive layer may be disposed on the bottom surface of the internal device 150.

[0065] Since the inactive surface of the inner device 150 contacts the lower buildup part 120, the inner device 150 may not be directly electrically connected to the lower buildup part 120. For example, the inner device 150 may be electrically connected to the lower buildup part 120 through the upper buildup part 130 and the core part 110.

[0066] The internal device 150 may be electrically connected to the upper buildup part 130. For example, the upper wiring pattern 134 of the lowermost second substrate wiring layer in the upper buildup part 130 may penetrate the upper dielectric pattern 132 and the buried material 140 and may be coupled to the chip pad 156.

[0067] Fig. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept. Fig.10 yes Fig. 9 An enlarged view of portion "D" of FIG.

[0068] Reference Fig. 9 and Fig.10 , each internal device 150 may include a chip via 158 and a chip backside pad 159 .

[0069] The chip via 158 may vertically penetrate the semiconductor layer 152 and may be electrically connected to the device wiring layer 154. The chip via 158 may be exposed on the non-active surface or top surface of the internal device 150. The chip via 158 may include a conductive material. For example, the chip via 158 may include a metal such as copper (Cu) or tungsten (W).

[0070] The chip backside pads 159 may be disposed on the top surface of the semiconductor layer 152. Each chip backside pad 159 may be electrically connected to one of the chip vias 158 on the top surface of the semiconductor layer 152. The chip backside pads 159 may include a conductive material. For example, the chip backside pads 159 may include a metal such as copper (Cu) or tungsten (W).

[0071] A back protective layer may be disposed on the top surface of the semiconductor layer 152. The back protective layer may cover the top surface of the semiconductor layer 152. The back protective layer may at least partially surround the chip back pad 159. The top surface of the back protective layer may be substantially flat and coplanar with the top surface of the chip back pad 159. The back protective layer may include a dielectric material. For example, the back protective layer may include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). As needed, a back protective layer may not be provided.

[0072] Fig.11 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0073] Reference Fig.11The semiconductor package may further include a package substrate 100 and a first semiconductor chip 200 .

[0074] The package substrate 100 may be Figures 1 to 10 The package substrate discussed is the same or similar. For example, the package substrate 100 may include a core portion 110, a lower build-up portion 120, an upper build-up portion 130, and a buried material 140. The buried material 140 may bury the core portion 110 between the lower build-up portion 120 and the upper build-up portion 130, and the internal device 150 may be inserted into the cavity CA formed in the core portion 110.

[0075] The first semiconductor chip 200 may be disposed on the package substrate 100 . The first semiconductor chip 200 may include a first chip base layer 210 and a first chip wiring layer 220 .

[0076] The first chip substrate layer 210 may include a semiconductor substrate. For example, the first chip substrate layer 210 may be a semiconductor substrate such as a semiconductor wafer. The first integrated circuit may be disposed on the bottom surface of the first chip substrate layer 210. The first integrated circuit may include a logic circuit or a memory circuit. For example, the first semiconductor chip 200 may be a logic chip or a memory chip. The bottom surface of the first semiconductor chip 200 may be an active surface, and the top surface of the first semiconductor chip 200 may be an inactive surface. For example, the first semiconductor chip 200 may be disposed on the package substrate 100 in a face-down state.

[0077] The first chip wiring layer 220 may be disposed on the bottom surface of the first chip substrate layer 210. For example, the first chip wiring layer 220 may include a first chip dielectric pattern 222 and a first chip wiring pattern 224 formed on the bottom surface of the first chip substrate layer 210. If necessary, the first chip substrate layer 210 may further include a circuit pattern or a protective layer.

[0078] A first chip dielectric pattern 222 may cover the first integrated circuit on the bottom surface of the first chip substrate layer 210. The first chip dielectric pattern 222 may include a dielectric material.

[0079] The first chip wiring pattern 224 may be disposed in the first chip dielectric pattern 222. The first chip wiring pattern 224 may be electrically connected to the first integrated circuit formed on the bottom surface of the first chip substrate layer 210. The first chip wiring pattern 224 may include a conductive material. A portion of the first chip wiring pattern 224 exposed on the bottom surface of the first chip wiring layer 220 may be a chip pad 226 of the first semiconductor chip 200.

[0080] The first semiconductor chip 200 may be disposed on the package substrate 100. For example, the first semiconductor chip 200 may be flip-chip mounted on the package substrate 100. The first semiconductor chip 200 may be electrically connected to the package substrate 100 through the first connection terminal 202. The first connection terminal 202 may be disposed between the chip pad 226 of the first semiconductor chip 200 and the upper substrate pad 138 of the package substrate 100. The first semiconductor chip 200 may be electrically connected to the internal device 150, and the upper build-up portion 130, the core portion 110, and the lower build-up portion 120 of the package substrate 100 through the first connection terminal 202.

[0081] Fig.12 is a cross-sectional view of a semiconductor package according to an embodiment of the inventive concept.

[0082] Reference Fig.12 The semiconductor package may be a semiconductor module. The semiconductor module may include, for example, a memory module including a module substrate 300 corresponding to an external substrate, a first interposer substrate 100 on the module substrate 300, a second interposer substrate 400 mounted on the first interposer substrate 100, and a graphics processing unit 500 and a chip stack 600 mounted on the second interposer substrate 400.

[0083] A module substrate 300 may be provided. The module substrate 300 may include a printed circuit board (PCB) having a signal pattern on a top surface thereof.

[0084] The module terminal may be provided below the module substrate 300. The module terminal may include a solder ball or a solder bump, and based on the type and arrangement of the module terminal, the semiconductor module may be provided in the form of one of a ball grid array (BGA) type, a fine ball grid array (FBGA) type, and a land grid array (LGA) type. According to an embodiment, the module terminal may not be provided.

[0085] The first interposer substrate 100 may be disposed on the module substrate 300. The first interposer substrate 100 may have a Figures 1 to 10 The structure of the package substrate 100 discussed above is the same as or similar to that of the package substrate 100. For example, the first interposer substrate 100 may include a core portion 110, a lower build-up portion 120, an upper build-up portion 130, and a buried material 140. The buried material 140 may bury the core portion 110 between the lower build-up portion 120 and the upper build-up portion 130, and the internal device 150 may be inserted into the cavity CA formed in the core portion 110.

[0086] The first interposer substrate 100 may redistribute the second interposer substrate 400, which will be discussed below. The first interposer substrate 100 may be flip-chip mounted on the module substrate 300. For example, the first external terminal 102 may be disposed on the lower substrate pad 128 of the first interposer substrate 100, and the first external terminal 102 may be coupled to the module substrate 300.

[0087] The second interposer substrate 400 may be disposed on the first interposer substrate 100 . The second interposer substrate 400 may include a second core portion 410 and a redistribution layer 420 .

[0088] The second core portion 410 may extend in one direction. In a plan view, the second core portion 410 may include a core pattern. For example, the second core portion 410 may have a plate shape. The second core portion 410 may include a dielectric material. The second core portion 410 may include silicon (Si). For example, the second interposer substrate 400 may be a silicon-based interposer.

[0089] The second core portion 410 may include core vias 412 each vertically penetrating the second core portion 410. The core vias 412 may extend from the bottom surface of the second core portion 410 to the top surface of the second core portion 410. For example, the core vias 412 may be used for vertical electrical connections in the second core portion 410. The core vias 412 may be exposed on the bottom surface and the top surface of the second core portion 410. The core vias 412 may have a bottom surface coplanar with the bottom surface of the second core portion 410. The core vias 412 may have a top surface coplanar with the top surface of the second core portion 410. The core vias 412 may include a metal, such as copper (Cu) or tungsten (W).

[0090] The redistribution layer 420 may be disposed on the second core portion 410. The redistribution layer 420 may cover the top surface of the second core portion 410. The redistribution layer 420 may include one or more third substrate wiring layers sequentially stacked on the top surface of the second core portion 410. For example, the redistribution layer 420 may include two "third substrate" wiring layers. Each third substrate wiring layer may include a redistribution dielectric pattern 422 and a redistribution pattern 424 in the redistribution dielectric pattern 422. The redistribution pattern 424 of a specific third substrate wiring layer may be electrically connected to the redistribution pattern 424 of another third substrate wiring layer adjacent to the specific third substrate wiring layer.

[0091] The redistribution dielectric pattern 422 may include a dielectric polymer or a photo-imageable dielectric (PID). Alternatively, the redistribution dielectric pattern 422 may include a prepreg, an Ajinomoto built-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT).

[0092] The redistribution pattern 424 may include a circuit pattern. The redistribution pattern 424 may be disposed on the redistribution dielectric pattern 422. The redistribution pattern 424 may be disposed on the top surface of the redistribution dielectric pattern 422. The redistribution pattern 424 may protrude onto the top surface of the redistribution dielectric pattern 422. The redistribution pattern 424 may extend horizontally on the top surface of the redistribution dielectric pattern 422. On the redistribution dielectric pattern 422, the redistribution pattern 424 may be covered by another redistribution dielectric pattern 422. The redistribution pattern 424 may be a pad or line portion of a third substrate wiring layer. The redistribution pattern 424 may include a conductive material. For example, the redistribution pattern 424 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and any combination thereof.

[0093] The redistribution pattern 424 may have a mosaic structure. For example, the redistribution pattern 424 may have a via protruding onto its bottom surface. The via may be a component for vertical connection between the redistribution patterns 424 of adjacent third substrate wiring layers. For example, the via may extend from the bottom surface of the redistribution pattern 424 through the redistribution dielectric pattern 422, and may be coupled to the top surface of the redistribution pattern 424 of another third substrate wiring layer below. The upper portion of the redistribution pattern 424 located on the redistribution dielectric pattern 422 may be a header used as a horizontal wiring line or pad, and the via of the redistribution pattern 424 may be a tail. The redistribution pattern 424 may have a T shape.

[0094] The redistribution pattern 424 may be electrically connected to the core via 412. The redistribution pattern 424 of the lowermost third substrate wiring layer in the redistribution layer 420 may penetrate the redistribution dielectric pattern 422 and may be coupled to the core via 412.

[0095] The redistribution pad 426 may be disposed on the top surface of the redistribution dielectric pattern 422 of the uppermost third substrate wiring layer. The redistribution pad 426 may vertically penetrate the redistribution dielectric pattern 422 and may be coupled to the redistribution pattern 424 of the uppermost third substrate wiring layer. Alternatively, the redistribution pad 426 may be a portion of the redistribution pattern 424 exposed on the top surface of the redistribution dielectric pattern 422.

[0096] The second interposer substrate 400 may redistribute the graphics processing unit 500 and the chip stack 600. The second interposer substrate 400 may be flip-chip mounted on the first interposer substrate 100. For example, the second external terminal 402 may be disposed on the bottom surface of the core via 412 of the second interposer substrate 400, and the second external terminal 402 may be coupled to the upper substrate pad 138 of the first interposer substrate 100.

[0097] The graphics processing unit 500 may be disposed on the second interposer substrate 400. The graphics processing unit 500 may include a logic circuit. For example, the graphics processing unit 500 may be a logic chip. The graphics processing unit 500 may have a second circuit layer 502 disposed on the bottom surface of the graphics processing unit 500. The second circuit layer 502 may be electrically connected to the logic circuit. The first bump 506 may be disposed on the bottom surface of the graphics processing unit 500 or on the bottom surface of the second circuit layer 502. The graphics processing unit 500 may be coupled to the redistribution pad 426 of the second interposer substrate 400 through the first bump 506. The first bottom fill layer 508 may be disposed between the second interposer substrate 400 and the graphics processing unit 500. The first bottom fill layer 508 may at least partially surround the first bump 506 while filling the space between the second interposer substrate 400 and the graphics processing unit 500.

[0098] The chip stack 600 may be disposed on the second interposer substrate 400. The chip stack 600 may be spaced apart from the graphics processing unit 500. The thickness of the graphics processing unit 500 may be greater than the thickness of the semiconductor chips 610 and 620 of the chip stack 600. The top surface of the chip stack 600 may be located at the same level as or higher than the level of the top surface of the graphics processing unit 500.

[0099] The chip stack 600 may include a base substrate, a second semiconductor chip 620 stacked on the base substrate, and a mold layer 630 at least partially surrounding the second semiconductor chip 620. The configuration of the chip stack 600 will be described in detail below.

[0100] The base substrate may be a base semiconductor chip 610. For example, the base substrate may be a wafer-level semiconductor substrate formed of a semiconductor material such as silicon (Si). In the following description, the base semiconductor chip 610 and the base substrate may represent the same component and may be assigned the same reference numerals.

[0101] The base semiconductor chip 610 may include a base circuit layer 612 and a base through electrode 614. The base circuit layer 612 may be disposed on the bottom surface of the base semiconductor chip 610. The base circuit layer 612 may include an integrated circuit. For example, the base circuit layer 612 may be a memory circuit. The base semiconductor chip 610 may be a memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), or a flash memory. Alternatively, the base semiconductor chip 610 may be a logic chip. The base through electrode 614 may penetrate the base semiconductor chip 610 in a direction perpendicular to the top surface of the second interposer substrate 400. The base through electrode 614 may be electrically connected to the base circuit layer 612. The bottom surface of the base semiconductor chip 610 may be an active surface. According to an embodiment, the base substrate may be a wiring substrate that does not include the base semiconductor chip 610.

[0102] The base semiconductor chip 610 may further include a protective layer. The protective layer may be disposed on the bottom surface of the base semiconductor chip 610 so as to cover the base circuit layer 612. The protective layer may include silicon nitride (SiN).

[0103] The second semiconductor chip 620 may be mounted on the base semiconductor chip 610 . For example, the second semiconductor chip 620 and the base semiconductor chip 610 may constitute a chip on wafer (COW) structure. The width of the second semiconductor chip 620 may be smaller than that of the base semiconductor chip 610 .

[0104] The second semiconductor chip 620 may include a third circuit layer 622 and a chip through electrode 624. The third circuit layer 622 may include a memory circuit. For example, the second semiconductor chip 620 may be a memory chip such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a magnetic random access memory (MRAM), or a flash memory. The third circuit layer 622 may include a circuit that is the same as the circuit of the substrate circuit layer 612, but the inventive concept is not necessarily limited thereto. The chip through electrode 624 may penetrate the second semiconductor chip 620 in a direction perpendicular to the top surface of the second interposer substrate 400. The chip through electrode 624 may be electrically connected to the third circuit layer 622. The bottom surface of the second semiconductor chip 620 may be an active surface.

[0105] The second semiconductor chip 620 may be bonded to the base semiconductor chip 610. For example, the pads of the third circuit layer 622 of the second semiconductor chip 620 may contact the top surface of the base through-electrode 614 exposed on the top surface of the base semiconductor chip 610. Alternatively, the second semiconductor chip 620 may be mounted on the top surface of the base through-electrode 614 through a terminal provided on the pads of the third circuit layer 622.

[0106] A plurality of second semiconductor chips 620 may be provided. For example, a plurality of second semiconductor chips 620 may be stacked on the base semiconductor chip 610. The number of stacked second semiconductor chips 620 may be about 8 to 32. The uppermost second semiconductor chip 620 may not include a chip through-electrode 624. In addition, the thickness of the uppermost second semiconductor chip 620 may be greater than the thickness of other lower second semiconductor chips 620.

[0107] Adjacent second semiconductor chips 620 may be bonded to each other. For example, the pads of the third circuit layer 622 of each second semiconductor chip 620 may contact the top surface of the chip through electrode 624 exposed on the top surface of the second semiconductor chip 620 below. Alternatively, the second semiconductor chip 620 may be mounted on the top surface of the chip through electrode 624 by a terminal provided on the pads of the third circuit layer 622.

[0108] The mold layer 630 may be disposed on the top surface of the base semiconductor chip 610. The mold layer 630 may cover the base semiconductor chip 610 and at least partially surround the second semiconductor chip 620. The top surface of the mold layer 630 may be coplanar with the top surface of the uppermost second semiconductor chip 620, and the uppermost second semiconductor chip 620 may be exposed from the mold layer 630. The mold layer 630 may include a dielectric polymer material. For example, the mold layer 630 may include an epoxy molding compound (EMC).

[0109] The chip stack 600 may be provided as described above.

[0110] The second bumps 606 may be disposed on the bottom surface of the chip stack 600 or on the bottom surface of the base circuit layer 612. The chip stack 600 may be coupled to the redistribution pads 426 of the second interposer substrate 400 through the second bumps 606. The second underfill layer 608 may be disposed between the second interposer substrate 400 and the chip stack 600. The second underfill layer 608 may at least partially surround the second bumps 606 while filling the space between the second interposer substrate 400 and the chip stack 600.

[0111] The outer mold layer may be disposed on the second interposer substrate 400. The outer mold layer may cover the top surface of the second interposer substrate 400. The outer mold layer may at least partially surround the graphics processing unit 500 and the chip stack 600. The top surface of the outer mold layer may be located at the same level as the top surface of the chip stack 600. The outer mold layer may include a dielectric material. For example, the outer mold layer may include an epoxy molding compound (EMC).

[0112] According to an embodiment, the second interposer substrate 400 formed of silicon (Si) may have a high degree of integration. The first interposer substrate 100 formed of glass may have high rigidity and may have a manufacturing cost lower than that of the second interposer substrate 400. The semiconductor package may be configured such that the silicon-based second interposer substrate 400 and the glass-based first interposer substrate 100 are all provided as interposers for redistribution of the graphics processing unit 500 and the chip stack 600. For example, when the second interposer substrate 400 is disposed adjacent to the graphics processing unit 500 and the chip stack 600, the highly integrated wiring lines of the graphics processing unit 500 and the chip stack 600 may be easily redistributed. In addition, the first interposer substrate 100 may be disposed below the second interposer substrate 400, so the semiconductor package may have excellent electrical properties, structural stability may be improved, and manufacturing costs may be reduced.

[0113] Furthermore, since the internal device 150 is embedded in the core portion 110 of the first interposer substrate 100, the semiconductor package may not separately require a planar area for mounting passive devices. For example, the semiconductor package may be smaller in size and may have a planar area.

[0114] FIG. 13A to FIG. 19A is a cross-sectional view of a method of manufacturing a semiconductor package according to an embodiment of the inventive concept. FIG. 13B to FIG. 19B is a plan view of a method of manufacturing a semiconductor package according to an embodiment of the inventive concept.

[0115] Reference Fig.13A and Fig. 13B , a first carrier substrate 900 may be provided. The first carrier substrate 900 may be a dielectric substrate including glass or polymer, or may be a conductive substrate including metal. An adhesive may be disposed on a top surface of the first carrier substrate 900. For example, the adhesive may include an adhesive tape.

[0116] The core part 110 may be attached to the first carrier substrate 900. The core part 110 may have a plate shape. The core part 110 may include a dielectric material. For example, the core part 110 may include glass fiber. In this case, the package substrate 100 described later may be a glass-based wiring substrate. The core part 110 may have one or more substrate regions SR and a groove region TR. In a plan view, the groove region TR may have a quadrilateral shape or a grid shape. The substrate region SR may be located inside the groove region TR. For example, each substrate region SR may be at least partially surrounded by the groove region TR. The substrate region SR may be defined within the groove region TR. The substrate region SR may be defined as an area indicating the core part 110 of the package substrate is formed in a subsequent process. For example, the core part 110 of a package substrate may be formed on a substrate region SR. The groove region TR may have a width of about 0.2 mm to about 10 mm. For example, the interval between adjacent substrate regions SR may be in the range of about 0.2 mm to about 10 mm.

[0117] Reference Fig.14A and Fig. 14B , the cavity CA, the via TH, and the trench T may be formed on the core portion 110. For example, the core portion 110 may undergo an etching process to form the cavity CA, the via TH, and the trench T. The cavity CA, the via TH, and the trench T may be formed using a laser process. The trench T may be formed by performing an etching process on the trench region TR of the core portion 110. Therefore, the core portion 110 may be divided into a plurality of separate core portions 110 correspondingly retained on the substrate region SR. The trench T may be located between the core portions 110 on the first carrier substrate 900. On the substrate region SR, the via TH and the trench T may be formed on the core portion 110.

[0118] Reference Fig.15A and Fig. 15B , the via holes TH may be filled with a conductive material to form the vertical connection terminals 112. For example, a plating process may be performed to form the vertical connection terminals 112. The vertical connection terminals 112 may include a metal, such as copper (Cu) or tungsten (W).

[0119] Reference Fig.16A and Fig. 16B , the internal device 150 may be disposed on the first carrier substrate 900. The internal device 150 may be correspondingly disposed in the cavity CA of the core portion 110. The internal device 150 may be disposed so that a chip pad 156 disposed at a lower portion thereof may face the first carrier substrate 900. The internal device 150 may have an active surface on which the chip pad 156 is disposed, and the active surface of the internal device 150 may be attached to the first carrier substrate 900.

[0120] The buried material 140 may be formed on the first carrier substrate 900. For example, a dielectric may be coated on the core portion 110 and the internal device 150, and then the dielectric may be cured to form the buried material 140. The buried material 140 may cover the top surface of the core portion 110 and the top surface of the internal device 150. The dielectric may be introduced into the space between the core portion 110 and the internal device 150, and the buried material 140 may fill the space between the core portion 110 and the internal device 150. For example, the buried material 140 may fill the unoccupied portion of the cavity CA in the core portion 110. The dielectric may be introduced into the trench T, and the buried material 140 may fill the trench T. Therefore, the buried material 140 may cover the edge EDG of the core portion 110. The dielectric may include an Ajinomoto deposited film (ABF). Alternatively, the dielectric may include a dielectric polymer such as an epoxy polymer or a polymer material such as a thermosetting resin.

[0121] Then, the first carrier substrate 900 may be removed to expose the bottom surfaces of the buried material 140, the core portion 110, and the internal device 150. When an adhesive is present on the first carrier substrate 900, the adhesive may also be removed together with the first carrier substrate 900.

[0122] Reference Fig.17A and Fig. 17B , the second carrier substrate 910 may be disposed on the burying material 140. The second carrier substrate 910 may be attached to the top surface of the burying material 140. For example, a tape or an adhesive may also be disposed on the bottom surface of the second carrier substrate 910.

[0123] The lower buildup portion 120 may be formed below the buried material 140, the core portion 110, and the internal device 150. For example, a lower dielectric pattern 122 and a lower wiring pattern 124 may be formed on the bottom surface of the buried material 140, the bottom surface of the core portion 110, and the bottom surface of the internal device 150, thereby forming a first substrate wiring layer of the lower buildup portion 120. For example, a dielectric layer may be formed on the bottom surface of the buried material 140, the bottom surface of the core portion 110, and the bottom surface of the internal device 150, the dielectric layer may be patterned to form a lower dielectric pattern exposing the vertical connection terminal 112 of the core portion 110 and the chip pad 156 of the internal device 150, a conductive layer may be formed on the lower dielectric pattern 122, and the conductive layer may be patterned to form a lower wiring pattern 124 electrically connected to the vertical connection terminal 112 and the chip pad 156. The formation of the first substrate wiring layer may be repeatedly performed to form the lower buildup portion 120.

[0124] Thereafter, the second carrier substrate 910 may be removed to expose the top surface of the buried material 140. When an adhesive is present on the second carrier substrate 910, the adhesive may also be removed together with the second carrier substrate 910.

[0125] Reference Fig.18A and Fig.18B , the third carrier substrate 920 may be disposed under the lower buildup part 120. The third carrier substrate 920 may be attached to the bottom surface of the lower buildup part 120. For example, a tape or an adhesive may also be disposed on the top surface of the third carrier substrate 920.

[0126] The upper buildup portion 130 may be formed on the buried material 140. For example, an upper dielectric pattern 132 and an upper wiring pattern 134 may be formed on the top surface of the buried material 140, thereby forming a second substrate wiring layer of the upper buildup portion 130. For example, a dielectric layer may be formed on the top surface of the buried material 140, the dielectric layer and the buried material 140 may be patterned to form an upper dielectric pattern 132 exposing the vertical connection terminal 112 of the core portion 110, a conductive layer may be formed on the upper dielectric pattern 132, and the conductive layer may be patterned to form an upper wiring pattern 134 electrically connected to the vertical connection terminal 112. The formation of the second substrate wiring layer may be repeatedly performed to form the upper buildup portion 130.

[0127] Reference Fig.19A and Fig.19B , the lower build-up portion 120, the buried material 140, and the upper build-up portion 130 may be cut to separate the package substrates 100 individually from each other. For example, the lower build-up portion 120, the buried material 140, and the upper build-up portion 130 may undergo a segmentation process performed along a sawing line. The sawing line may be located in the groove region TR and may extend along the groove region TR in a plan view. For example, the lower build-up portion 120, the buried material 140, and the upper build-up portion 130 may be sawed to separate a plurality of package substrates 100 from each other. The core portion 110 of each package substrate 100 may not be cut. For example, the core portion 110 may be horizontally spaced apart from each other from the cutting surface CS that appears through the segmentation process. The distance between the cutting surface CS and the core portion 110 may be in the range of about 0.1 mm to about 3 mm.

[0128] Thereafter, the third carrier substrate 920 may be removed to expose the bottom surface of the lower buildup part 120. When an adhesive is present on the third carrier substrate 920, the adhesive may also be removed together with the third carrier substrate 920.

[0129] Return to reference Figure 1 , the external pads 102 may be attached to the lower substrate pads 128 of the lower buildup portion 120 .

[0130] According to an embodiment, similar to Fig.11 and Fig.12 In the embodiment of the present invention, the package substrate 100 may be provided with various devices or substrates thereon, such as a first semiconductor chip 200 , a module substrate 300 , a graphics processing unit 500 , and / or a chip stack 600 .

[0131] In a semiconductor package, according to an embodiment of the inventive concept, a buried material may protect an edge of a core portion from external impact and stress, and may provide a package substrate whose structural stability is improved, and may also provide a semiconductor package including the package substrate.

[0132] In addition, the second interposer substrate formed of silicon (Si) can have a high degree of integration, and the first interposer substrate formed of glass can have high rigidity and a manufacturing cost lower than the manufacturing cost of the second interposer substrate. For example, when the second interposer substrate is arranged adjacent to the graphics processing unit and the chip stack, the highly integrated wiring lines of the graphics processing unit and the chip stack can be easily redistributed. The first interposer substrate can be arranged below the second interposer substrate, so the semiconductor package can have excellent electrical properties, structural stability can be improved, and manufacturing costs can be reduced. In addition, since the internal devices are embedded in the core part of the first interposer substrate, the semiconductor package may not need a planar area for mounting passive devices separately. For example, the semiconductor package can be smaller in size and can have a planar area.

[0133] Although the present inventive concept has been described with reference to the embodiments of the present inventive concept illustrated in the drawings, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and essential characteristics of the present inventive concept.

Claims

1. A semiconductor package, comprising: Wiring substrate; as well as A first semiconductor chip is provided on the wiring substrate. Wherein, the wiring substrate comprises: a first core portion comprising glass, wherein the first core portion comprises a cavity vertically penetrating the first core portion; a plurality of first core vias, each of the first core vias vertically penetrating the first core portion; a passive device disposed in the cavity of the first core portion; a buried material disposed on the first core portion and the first core via, wherein the buried material fills the cavity and covers a top surface and an outer side surface of the first core portion; and an upper accumulation portion disposed on the burying material, and Wherein, the upper stacking part comprises: a first dielectric pattern; and A first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the first core via.

2. The semiconductor package according to claim 1, wherein Each of the first core vias comprises: an upper contact point contact portion disposed on the top surface of the first core portion; a lower contact portion disposed on a bottom surface of the first core portion; and A via hole vertically penetrates the first core portion to connect the upper contact portion and the lower contact portion to each other.

3. The semiconductor package according to claim 1 , further comprising a lower build-up portion disposed below the first core portion and the buried material, in, The lower stacking part comprises: a second dielectric pattern; and A second wiring pattern passes through the second dielectric pattern and is coupled to the first core via.

4. The semiconductor package according to claim 3, wherein: The active surface of the passive device faces the lower build-up portion, and The second wiring pattern penetrates the second dielectric pattern and is coupled to the passive device.

5. The semiconductor package according to claim 3, wherein: The first semiconductor chip is disposed on the upper buildup portion of the wiring substrate.

6. The semiconductor package according to claim 1, wherein The embedding material includes Ajinomoto build-up film ABF or epoxy molding compound EMC.

7. The semiconductor package according to claim 1, wherein: The active surface of the passive device faces the upper build-up portion, and The first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the passive device.

8. The semiconductor package according to claim 1, wherein A bottom surface of the buried material is coplanar with a bottom surface of the first core portion.

9. The semiconductor package according to claim 1, wherein: A distance between the outer side surface of the first core portion and the outer side surface of the burying material is in a range of about 0.1 mm to about 3 mm.

10. The semiconductor package according to claim 1, further comprising a chip stack disposed on the wiring substrate, in, The chip stack includes a plurality of second semiconductor chips vertically stacked on the wiring substrate.

11. The semiconductor package according to claim 10, further comprising: an interposer substrate disposed between the first semiconductor chip and the wiring substrate and between the chip stack and the wiring substrate; as well as a module substrate, the wiring substrate being arranged on the module substrate, wherein the intermediate substrate is disposed on the upper stacking portion of the wiring substrate, Wherein, the intermediate substrate comprises: The second core part; a second core via vertically penetrating the second core portion; and a redistribution layer disposed on a top surface of the second core portion and electrically connected to the second core via, and Wherein, the first semiconductor chip and the chip stack are both arranged on the redistribution layer.

12. A semiconductor package, comprising: a first interposer substrate; a second intermediate substrate, disposed on the first intermediate substrate; A first semiconductor chip is disposed on the second interposer substrate; a chip stack disposed on the second interposer substrate and spaced apart from the first semiconductor chip, the chip stack comprising a plurality of second semiconductor chips stacked vertically; as well as A plurality of connection terminals are arranged below the first intermediate substrate, Wherein, the first intermediate substrate comprises: Lower accumulation part; a first core portion disposed on the lower buildup portion and comprising glass, wherein the first core portion comprises a cavity vertically penetrating the first core portion; a burying material disposed on the lower buildup portion and covering the first core portion; an upper accumulation portion disposed on the burying material; and a passive device disposed in the cavity of the first core portion, wherein the outer side surface of the first core portion is arranged more inwardly than the outer side surface of the embedding material, wherein the second intermediate substrate comprises a second core portion, and Wherein, the second core portion comprises a material different from that of the first core portion.

13. The semiconductor package according to claim 12, wherein: The burying material fills the cavity and covers the top surface and the outer side surface of the first core portion.

14. The semiconductor package according to claim 12, wherein: The upper stacking part comprises: a first dielectric pattern; and A first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the first core portion.

15. The semiconductor package according to claim 12, wherein: The active surface of the passive device faces the upper build-up portion, and The first wiring pattern penetrates the first dielectric pattern and the buried material and is coupled to the passive device.

16. The semiconductor package according to claim 12, wherein: The first interposer substrate further includes a plurality of first core vias, each of the first core vias vertically penetrating the first core portion, Wherein, each of the first core vias comprises: an upper contact portion disposed on a top surface of the first core portion; a lower contact portion disposed on a bottom surface of the first core portion; and A via hole vertically penetrates the first core portion and connects the upper contact portion and the lower contact portion to each other.

17. The semiconductor package according to claim 12, wherein: The lower stacking part comprises: a second dielectric pattern; and A second wiring pattern penetrates the second dielectric pattern and is coupled to the first core portion.

18. The semiconductor package according to claim 12, wherein: The first core portion is in contact with the lower buildup portion, and A bottom surface of the buried material is coplanar with a bottom surface of the first core portion.

19. A semiconductor package, comprising: Wiring substrate; as well as A first semiconductor chip is provided on the wiring substrate. Wherein, the wiring substrate comprises: Lower accumulation part; an upper stacking portion, disposed on the lower stacking portion; a burying material filling a space between the lower buildup portion and the upper buildup portion; a first core portion in the embedding material, wherein the first core portion includes a cavity penetrating the first core portion, and wherein a distance between an outer side surface of the first core portion and an outer side surface of the embedding material is in a range of about 0.1 mm to about 3 mm; a plurality of first core vias, each of the first core vias vertically penetrating the first core portion; and a passive device disposed in the cavity of the first core portion, Wherein, the upper stacking part comprises: a first dielectric pattern; and a first wiring pattern penetrating the first dielectric pattern and the buried material and coupled to the first core via, Wherein, the lower stacking part comprises: a second dielectric pattern; and a second wiring pattern penetrating the second dielectric pattern and coupled to the first core via, and wherein the stiffness of the first material included in the first core portion is greater than each of the stiffness of the second material included in the first dielectric pattern and the stiffness of the third material included in the second dielectric pattern.

20. The semiconductor package according to claim 19, wherein The second core portion includes silicon Si.

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