Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device may include a lower structure including a chip region and a scribe lane region surrounding the chip region; a first alignment pattern including first alignment keys extending parallel to each other in a first direction on the scribe lane region; and a support pattern including a first sub-support pattern arranged in a second direction crossing the first direction between the first alignment keys.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device including an alignment pattern on a scribe lane and a method of manufacturing the semiconductor device. Background Art

[0002] A plurality of semiconductor chip regions may be formed on a semiconductor substrate by a semiconductor integration process. A plurality of semiconductor chip regions may be separated from each other by using a scribe lane region as a boundary. A plurality of semiconductor chip regions may be separated from each other by a cutting process on a semiconductor substrate to manufacture a plurality of semiconductor chips.

[0003] In addition, when performing a photolithography operation of a semiconductor integration process, the alignment pattern can be used to align a photomask at a predetermined position of a semiconductor substrate. The alignment pattern is positioned on a scribe channel region so that the integration of the semiconductor chip is not degraded. Summary of the invention

[0004] Various embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the semiconductor device, in which structural stability of a region where an alignment pattern is formed can be improved, thereby reducing the occurrence of defects.

[0005] According to one embodiment of the present disclosure, a semiconductor device is provided, which includes: a lower structure, which includes a chip area and a scribe line area surrounding the chip area; a first alignment pattern, which includes first alignment keys extending parallel to each other along a first direction on the scribe line area; and a support pattern, which includes a first sub-support pattern arranged between the first alignment keys along a second direction intersecting the first direction.

[0006] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising the following steps: forming a stacked structure by alternately stacking a first material layer and a second material layer on a lower structure, the lower structure comprising a chip area and a scribe line area surrounding the chip area; forming a sub-support pattern of the stacked structure penetrating the scribe line area, the sub-support pattern being arranged along a first direction; forming grooves of the stacked structure penetrating the scribe line area, the grooves extending parallel to each other along a second direction intersecting the first direction; forming a recessed portion by removing the first material layer exposed through the groove; forming a third material layer in the recessed portion through the groove; and forming an alignment pattern by filling a fourth material layer in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art.

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals represent the same elements throughout.

[0009] Figure 1 is a diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0011] 3A to 3H is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 4 to 7 is a diagram illustrating the structure of a semiconductor device according to various embodiments of the present disclosure.

[0013] Figure 8 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0014] Fig. 9 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied. DETAILED DESCRIPTION

[0015] The specific structural or functional descriptions disclosed herein are merely illustrative and are used for the purpose of describing the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily realize the technical idea of ​​the present disclosure.

[0017] Figure 1 is a diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure.

[0018] Reference Figure 1, the semiconductor device may include a substrate SST. The substrate SST may include a chip area CHA and a scribe lane area SLA. For example, the substrate SST may include a plurality of chip areas CHA spaced apart from each other at regular intervals and a scribe lane area SLA surrounding the chip areas CHA. The substrate SST may be a semiconductor substrate such as a silicon wafer, a silicon-germanium ("SiGe") wafer, or an SOI (silicon on insulator) wafer. In one embodiment of the present disclosure, the substrate SST may be designed as a lower structure.

[0019] The chip area CHA may be an area where semiconductor chips are formed separately. The chip area CHA may be arranged in multiple columns and rows in the X direction and the Y direction. The semiconductor chips may be formed separately by a semiconductor integration process performed on the chip area CHA. The semiconductor chips formed separately in the chip area CHA may be substantially the same. After completing the semiconductor integration process on the substrate SST, the substrate SST is separated for each of the chip areas CHA so that each of the chip areas CHA may be separated into a semiconductor chip form.

[0020] The scribe lane area SLA may be positioned outside the chip area CHA. The scribe lane area SLA may be positioned between the chip areas CHA. After the semiconductor integration process is completed, the scribe lane area SLA may be cut in a dicing process for separating semiconductor chips from each other. The substrate SST is cut along the scribe lane area SLA so that each of the chip areas CHA can be separated. A process such as a sawing process using a blade, a laser process using a laser, or an invisible dicing process may be used as a process for cutting the substrate SST. A chip protection member, an electrical test pattern, a process monitoring pattern, and an alignment pattern AP for protecting the chip area CHA may be provided in the scribe lane area SLA.

[0021] Reference Figure 1 , an alignment key region AKA may be defined in an area in the scribe lane area SLA. The alignment key area AKA may be an area in which an alignment pattern AP is formed. The alignment pattern AP may be a pattern structure formed on the substrate SST for the purpose of alignment between a photomask and a substrate SST in a photolithography operation of a semiconductor integration process. For example, the alignment pattern AP may be used when forming one or more of a cell plug (cell plug), a contact plug (contact plug), a bit line, and a slit insulating layer of a semiconductor chip. However, the present disclosure is not limited thereto, and the alignment pattern AP may be formed to form various structures in a semiconductor chip.

[0022] exist Figure 1In the embodiment, for ease of description, six chip regions CHA are illustrated as being arranged in two columns and three rows. However, the scope of the present disclosure is not limited thereto. For example, the substrate SST may include various numbers of chip regions CHA, that is, seven or more chip regions CHA. In addition, Figure 1 In the example, six alignment key areas AKA are included in the scribe lane area SLA. However, the scope of the present disclosure is not limited thereto. The positions and number of the alignment key areas AKA included in the scribe lane area SLA may be modified in various ways. For example, the alignment key areas AKA may even be formed at any position on the periphery of the chip area CHA. In another example, at least two alignment key areas AKA may be positioned adjacent to the chip area CHA. In addition, in Figure 1 , each chip area CHA has a square shape, however, the scope of the present disclosure is not limited thereto.

[0023] Figure 2A and Figure 2B is a diagram illustrating a structure of a semiconductor device according to one embodiment of the present disclosure. Figure 2A is a plan view illustrating a layout of an alignment pattern AP formed in the alignment key area AKA. Figure 2B It is along Figure 2A A cross-sectional view taken along line AA' shown in FIG.

[0024] Reference Figure 2A The alignment patterns AP1, AP2, AP3, and AP4 and the support patterns SP1, SP2, SP3, and SP4 may be positioned in the alignment key area AKA. Figure 1 The alignment pattern AP shown in FIG. 1 may include Figure 2A The alignment patterns AP1, AP2, AP3, and AP4 shown in FIG. The alignment patterns AP1, AP2, AP3, and AP4 may be Vernier key patterns. The Vernier key pattern is a key pattern used to measure the alignment between the upper layer and the lower layer during the photolithography operation. The alignment patterns AP1, AP2, AP3, and AP4 and the support patterns SP1, SP2, SP3, and SP4 may be formed on Figure 1 The scribe line area SLA is shown in FIG.

[0025] The alignment patterns AP1, AP2, AP3 and AP4 may be arranged in a windmill shape so that each of the alignment patterns AP1, AP2, AP3 and AP4 faces the X direction or the Y direction. The four alignment patterns AP1, AP2, AP3 and AP4 may be arranged clockwise in sequence. For example, the first alignment pattern AP1 may be arranged at the upper right position, the second alignment pattern AP2 may be arranged at the lower right position, the third alignment pattern AP3 may be arranged at the lower left position, and the fourth alignment pattern may be arranged at the upper left position. Each alignment pattern may have an overall rectangular shape and may be oriented at a 90-degree angle to its adjacent alignment pattern. For example, the first alignment pattern AP1 may be arranged at the upper right position and may be oriented in the X direction, the second alignment pattern AP2 may be arranged at the lower right position and may be oriented in the Y direction, the third alignment pattern AP3 may be arranged at the lower left position and may be oriented in the X direction, and the fourth alignment pattern may be arranged at the upper left position and may be oriented in the Y direction. However, this is merely exemplary, and the scope of the present disclosure is not limited thereto. For example, the alignment patterns AP1, AP2, AP3, and AP4 may be arranged in a chessboard shape instead of a windmill shape. When the alignment patterns AP1, AP2, AP3, and AP4 are arranged in a chessboard shape, the second alignment pattern AP2 may be arranged below the first alignment pattern AP1, the third alignment pattern AP3 may be arranged in a left diagonal direction of the first alignment pattern AP1, and the fourth alignment pattern AP4 may be arranged on the left side of the first alignment pattern AP1. Alternatively, at least one of the alignment patterns AP1, AP2, AP3, and AP4 may be omitted so that two or three alignment patterns are formed in the alignment key area AKA. Alternatively, the alignment patterns AP1, AP2, AP3, and AP4 may be arranged to be reversed laterally or vertically. Figure 2A The shape obtained is the shape shown in .

[0026] The alignment patterns AP1, AP2, AP3 and AP4 may respectively include alignment keys AK1, AK2, AK3 and AK4 arranged in parallel with each other. Each of the alignment keys AK1, AK2, AK3 and AK4 may extend parallel to each other in the corresponding alignment pattern among the alignment patterns AP1, AP2, AP3 and AP4. For example, the first alignment pattern AP1 may include first alignment keys AK1 extending parallel to each other along the Y direction. In addition, the second alignment pattern AP2 may include second alignment keys AK2 extending parallel to each other along the X direction. In addition, the third alignment pattern AP3 may include third alignment keys AK3 extending parallel to each other along the Y direction. In addition, the fourth alignment pattern AP4 may include fourth alignment keys AK4 extending parallel to each other along the X direction. The number of alignment keys AK1, AK2, AK3 or AK4 included in each of the alignment patterns AP1, AP2, AP3 and AP4 and the distance between the alignment keys AK1, AK2, AK3 or AK4 included in each of the alignment patterns AP1, AP2, AP3 and AP4 are not limited to Figure 2A Those quantities and distances shown in .

[0027] Each of the alignment keys AK1, AK2, AK3 or AK4 may have a rectangular cross-section. The length of the cross-section of each of the alignment keys AK1, AK2, AK3 or AK4 in one direction may be longer than the length of the cross-section of each of the alignment keys AK1, AK2, AK3 or AK4 in another direction. For example, the cross-section of each of the first alignment keys AK1 may be provided as a rectangular shape having a long side in the Y direction and a short side in the X direction. In addition, the cross-section of each of the second alignment keys AK2 may be provided as a rectangular shape having a long side in the X direction and a short side in the Y direction. In addition, the cross-section of each of the third alignment keys AK3 may be provided as a rectangular shape having a long side in the Y direction and a short side in the X direction. In addition, the cross-section of each of the fourth alignment keys AK4 may be provided as a rectangular shape having a long side in the X direction and a short side in the Y direction. Figure 2A In the embodiment, each of the alignment keys AK1, AK2, AK3, or AK4 is illustrated as having a rectangular shape. However, the scope of the present disclosure is not limited thereto. For example, each of the alignment keys AK1, AK2, AK3, or AK4 may have a cross section of various shapes such as an ellipse and a rectangle with rounded corners.

[0028] The support patterns SP1, SP2, SP3 and SP4 may include sub-support patterns SSP1, SSP2, SSP3 and SSP4 positioned between the alignment keys AK1, AK2, AK3 and AK4. For example, the first support pattern SP1 may include a first sub-support pattern SSP1 (e.g., SSP11, SSP12, SSP13 or SSP14), and the first sub-support pattern SSP1 is arranged along the X direction between the first alignment keys AK1. In addition, the second support pattern SP2 may include a second sub-support pattern SSP2, and the second sub-support pattern SSP2 is arranged along the Y direction between the second alignment keys AK2. The third support pattern SP3 may include a third sub-support pattern SSP3, and the third sub-support pattern SSP3 is arranged along the X direction between the third alignment keys AK3. In addition, the fourth support pattern SP4 may include a fourth sub-support pattern SSP4, and the fourth sub-support pattern SSP4 is arranged along the Y direction between the fourth alignment keys AK4. In Figure 2A However, this is for the convenience of description, and the description of the first supporting pattern SP1 can be applied to the second to fourth supporting patterns SP2 to SP4 except for the limitation to the X or Y direction.

[0029] The first support pattern SP1 may include a first sub-support pattern SSP1 positioned between the first alignment keys AK1. The first sub-support pattern SSP1 may be arranged along the X direction and the Y direction. The first sub-support pattern SSP1 may be divided according to the direction in which the first sub-support pattern SSP1 is arranged. For example, the first sub-support pattern SSP1 may be divided into an eleventh sub-support pattern SSP11, a twelfth sub-support pattern SSP12 positioned in the Y direction relative to the eleventh sub-support pattern SSP11, a thirteenth sub-support pattern SSP13 positioned in the Y direction relative to the twelfth sub-support pattern SSP12, and a fourteenth sub-support pattern SSP14 positioned in the Y direction relative to the thirteenth sub-support pattern SSP13. The number of first sub-support patterns SSP1 arranged in the Y direction is not limited to Figure 2A The quantity shown in .

[0030] The eleventh sub-support pattern SSP11 may be positioned parallel to each other along the X direction. The twelfth sub-support pattern SSP12 may be positioned parallel to each other along the X direction. The thirteenth sub-support pattern SSP13 may be positioned parallel to each other along the X direction. The fourteenth sub-support pattern SSP14 may be positioned parallel to each other along the X direction. The number of each of the eleventh to fourteenth sub-support patterns SSP11 to SSP14 arranged in the X direction is not limited to Figure 2A The quantity shown in .

[0031] The first sub-support pattern SSP1 may be positioned between the first alignment keys AK1. In one embodiment, at least two eleventh sub-support patterns SSP11 (or SSP12, SSP13, or SSP14) may be positioned between two alignment keys adjacent to each other among the first alignment keys AK1. For example, three eleventh sub-support patterns SSP11 may be arranged parallel to each other in the X direction between two alignment keys adjacent to each other among the first alignment keys AK1. However, this is merely illustrative. In another embodiment, only one eleventh sub-support pattern SSP11, only one twelfth sub-support pattern SSP12, only one thirteenth sub-support pattern SSP13, and only one fourteenth sub-support pattern SSP14 may be positioned between two alignment keys adjacent to each other among the first alignment keys AK1. This will be referred to later. Figure 5 and Figure 6 Give a description.

[0032] In one embodiment, the cross-section of each of the first sub-support patterns SSP1 may have a circular shape. For example, the cross-section of each of the first sub-support patterns SSP1 may be a circle having the same length in the X direction and the Y direction. In another embodiment, the cross-section of each of the first sub-support patterns SSP1 may be a rectangle, a quadrilateral with rounded corners, or an ellipse. Various embodiments of the cross-section of each of the first sub-support patterns SSP1 will be described later with reference to Figures 4 to 6 Give a description.

[0033] Each of the first sub-support patterns SSP1 and each of the first alignment keys AK1 may be spaced apart from each other. For example, the first sub-support pattern SSP1 may be spaced apart from each of the first alignment keys AK1. In addition, the first sub-support patterns SSP1 may be positioned to be spaced apart from each other.

[0034] Reference Figure 2A, the direction in which the first alignment key AK1 extends (e.g., the Y direction) and the direction in which the eleventh sub-support pattern SSP11 (or SSP12, SSP13, or SSP14) is arranged (e.g., the X direction) may be substantially perpendicular to each other. That is, the angle θ formed by the direction in which the first alignment key AK1 extends and the direction in which each of the eleventh sub-support pattern SSP11 to the fourteenth sub-support pattern SSP14 is arranged may be 90 degrees. According to an embodiment of the present disclosure, since the eleventh sub-support pattern SSP11 is arranged in a direction (e.g., the X direction) substantially perpendicular to the direction in which the first alignment key AK1 extends (e.g., the Y direction), the support patterns SP1, SP2, SP3, and SP4 may have no influence during the alignment operation performed using the alignment patterns AP1, AP2, AP3, and AP4. That is, although the support patterns SP1, SP2, SP3, and SP4 are formed, the support patterns SP1, SP2, SP3, and SP4 have no influence when the overlay is measured by the alignment patterns AP1, AP2, AP3, and AP4. Therefore, an operation of adjusting the alignment between the substrate SST and the photomask using the alignment patterns AP1 , AP2 , AP3 , and AP4 is possible.

[0035] Figure 2B is along with Figure 2A The cross-sectional view corresponds to the cross-sectional view taken along the line AA' shown in FIG. Figure 2B The cross-sections of the third alignment key AK3 and the third sub-support pattern SSP3 are illustrated, but the cross-sectional structures of the first to fourth alignment patterns AP1 to AP4 are substantially the same, and the cross-sectional structures of the first to fourth support patterns SP1 to SP4 are substantially the same. Figure 2B In the description, the alignment key or the sub-support pattern will be described without distinguishing the alignment key or the sub-support pattern from each other. Figure 2B The description of the align key AK and the sub-support pattern SSP illustrated in FIG. 1 may be applied to the first to fourth align keys AK1 to AK4 and the first to fourth sub-support patterns SSP1 to SSP4 .

[0036] Reference Figure 2B The stacked structure STK may be positioned on a substrate (not shown) or a lower structure (not shown) of the scribe line area SLA. The stacked structure STK may include conductive layers CD and interlayer insulating layers IL that are alternately stacked. Figure 1 Refer to Figure 2BTogether with the stacked structure formed on the chip area CHA, a stacked structure STK may be formed on the scribe lane area SLA. For example, the materials stacked in the stacked structure on the chip area CHA and the materials stacked in the stacked structure STK on the scribe lane area SLA (e.g., the conductive layer CD and the interlayer insulating layer IL) may be substantially the same.

[0037] The alignment keys AK may be positioned to be spaced apart from each other in the X direction. Each of the alignment keys AK may extend in the Y direction. The alignment keys AK may be formed parallel to each other in the X direction. In addition, each of the alignment keys AK may penetrate the stacked structure STK in the Z direction. The alignment keys AK may be formed of an insulating material such as an oxide layer, but the present disclosure is not limited thereto.

[0038] The sub-support patterns SSP may be arranged along the X direction between the alignment keys AK. In addition, each of the sub-support patterns SSP may extend along the Z direction to penetrate the stack structure STK. For example, each of the sub-support patterns SSP may have a circular column shape extending vertically from the substrate SST. Each of the sub-support patterns SSP may be made of a conductive material.

[0039] 3A to 3H is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. 3A to 3H Each of which includes Figure 2A 2 and a cross-sectional view of the cell array area CA which is a part of the chip area CHA.

[0040] Reference Figure 3A , the first material layer M1 and the second material layer M2 may be alternately stacked on the substrate SST. The stacked structure STK may be formed on each of the cell array area CA included in the chip area CHA and the alignment key area AKA included in the scribe line area SLA. The stacked structure STK of the cell array area CA and the stacked structure STK of the alignment key area AKA may be formed at the same time. The first material layer M1 and the second material layer M2 on the cell array area CA may be formed of the same material as the first material layer M1 and the second material layer M2 on the alignment key area AKA, respectively.

[0041] The first material layer M1 may be formed of a material that can be selectively removed in a subsequent process. Therefore, the first material layer M1 may be formed of a material having an etching selectivity different from that of the second material layer M2. For example, the first material layer M1 may be formed of a nitride layer. The second material layer M2 may be formed of an insulating material. For example, the second material layer M2 may be formed of an oxide layer (e.g., a silicon oxide layer). The second material layer M2 may be formed at each of the lowermost end and the uppermost end of the stacked structure STK in which the first material layer M1 and the second material layer M2 are stacked,

[0042] Reference Figure 3B , a unit hole CPH penetrating the stack structure STK in the Z direction may be formed in the unit array area CA. Each of the unit holes CPH may penetrate the first material layer M1 and the second material layer M2. The unit holes CPH may be spaced apart from each other along the X direction. An anisotropic dry etching process may be performed to form the unit holes CPH at designated locations.

[0043] In addition, support holes H1 penetrating the stack structure STK in the Z direction may be formed in the alignment key area AKA. Each of the support holes H1 may penetrate the first material layer M1 and the second material layer M2. The support holes H1 may be arranged along the X direction. An anisotropic dry etching process may be performed to form the support holes H1 at designated positions.

[0044] Reference Figure 3C , the cell plug CP may be formed in the cell hole CPH formed in the cell array region CA. Each of the cell plugs CP may include: a barrier layer BX having a cylindrical shape, a charge capture layer CT formed along the inner wall of the barrier layer BX, a tunnel insulating layer TX formed along the inner wall of the charge capture layer CT, a channel layer CH formed along the inner wall of the tunnel insulating layer TX, and a core column CO formed in a circular column shape in an area surrounded by the channel layer CH. The barrier layer BX and the tunnel insulating layer TX may be formed of an oxide layer (e.g., a silicon oxide layer). The charge capture layer CT may be formed of a nitride layer. The channel layer CH may be formed of a doped silicon layer. The core column CO may be formed of an insulating layer or a conductive layer. The barrier layer BX, the charge capture layer CT, the tunnel insulating layer TX, the channel layer CH, and the core column CO formed in the cell plug CP may extend in a vertical direction (e.g., a Z direction). A capping layer for improving the electrical characteristics of the selection transistor may also be formed on the top of the core column CO.

[0045] The sub-support pattern SSP may be formed in the support hole H1 formed in the align key area AKA For example, a support material layer (eg, a conductive material) is filled in the support hole H1, thereby forming the sub-support pattern SSP.

[0046] exist Figure 3C In the present invention, the sub-support pattern SSP may be formed in the support hole H1 after the cell plug CP is formed in the cell hole CPH, and the cell plug CP may be formed in the cell hole CPH after the sub-support pattern SSP is formed in the support hole H1. Alternatively, the cell plug CP and the sub-support pattern SSP may be formed simultaneously.

[0047] In addition, despite Figure 3B and Figure 3C , the case where the support hole H1 is formed simultaneously with the cell hole CPH is mainly illustrated, but various embodiments may be possible. For example, after the cell plug CP is formed in the cell array region CA, the support hole H1 may be formed while forming a contact plug on the top of the cell plug CP. Thereafter, a support material layer is filled in the support hole H1, thereby forming a sub-support pattern SSP.

[0048] Reference Figure 3D , a slit trench SLT may be formed, the slit trench SLT penetrating the stacked structure STK of the cell array region CA. The first material layer M1 may be exposed through the slit trench SLT. The slit trench SLT may extend along the Y direction. The cell array region CA may be divided into a plurality of memory blocks through the slit trench SLT. An anisotropic dry etching process may be performed to form the slit trench SLT at a designated position.

[0049] A trench T1 penetrating the stack structure STK may be formed in the alignment key area AKA. The first material layer M1 may be exposed through the trench T1. The trenches T1 may extend parallel to each other along the Y direction. The trenches T1 may be formed to be spaced apart from each other along the X direction. An anisotropic dry etching process may be performed to form the trench T1 at a designated position.

[0050] The trench T1 may be formed such that at least one sub-support pattern SSP is positioned between two trenches T1 adjacent to each other. For example, the trench T1 may be formed at both sides of the sub-support pattern SSP arranged along the X direction (eg, the X direction and the opposite direction of the X direction).

[0051] In one embodiment, the slit trench SLT and the trench T1 may be formed simultaneously by an etching process. For example, the slit trench SLT may be formed in the cell array area CA and the trench T1 may be formed in the alignment key area AKA by one etching process. In another embodiment, the slit trench SLT and the trench T1 may be formed by separate etching processes.

[0052] Reference Figure 3E, the first material layer M1 exposed by the slit trench SLT in the cell array region CA may be removed. An etching process for removing the first material layer M1 through the slit trench SLT may be performed. The etching process may be a wet etching process for allowing the second material layer M2 to remain and selectively removing the first material layer M1.

[0053] In addition, the first material layer M1 exposed through the trench T1 in the align key area AKA may be removed. An etching process for removing the first material layer M1 through the trench T1 may be performed. The etching process may be a wet etching process for allowing the second material layer M2 to remain and selectively removing the first material layer M1.

[0054] The etching process of removing the first material layer M1 through the slit trench SLT and the trench T1 may be simultaneously performed. The first material layer M1 may be selectively removed through the isotropic etching process performed through the slit trench SLT and the trench T1.

[0055] As the first material layer M1 is removed through the trench T1 in the alignment key area AKA, the first recessed portion RC1 may open between the second material layers M2. The first recessed portion RC1 may correspond to the position where the first material layer M1 on the alignment key area AKA is removed. In addition, as the first material layer M1 is removed through the slit trench SLT in the cell array area CA, the second recessed portion RC2 may open between the second material layers M2. The second recessed portion RC2 may correspond to the position where the first material layer M1 on the cell array area CA is removed.

[0056] The first recess RC1 may expose a portion of a sidewall of each of the sub-support patterns SSP. In addition, the second recess RC2 may expose a portion of a sidewall of each of the cell plugs CP.

[0057] Although the first material layer M1 is removed in the cell array region CA, the second material layer M2 may be supported by the cell plug CP. For example, although the second recess RC2 is formed in the cell array region CA, the cell plug CP supports the second material layer M2. Therefore, the second material layer M2 does not collapse, or the second material layers M2 in different layers are not connected to each other.

[0058] According to one embodiment of the present disclosure, even when the first material layer M1 is removed in the alignment key area AKA, the second material layer M2 can be supported by the sub-support pattern SSP. For example, although the first recess RC1 is formed in the alignment key area AKA, the sub-support pattern SSP supports the second material layer M2. Therefore, the second material layer M2 does not collapse, or the second material layers M2 in different layers are not connected to each other (for example, there is no bridging phenomenon). Therefore, compared with the case where the sub-support pattern SSP is not formed in the alignment key area AKA, the structural stability of the semiconductor device can be improved. In addition, when at least some of the second material layer M2 collapses in the state where the first recess RC1 is formed, various defects such as cracks, ruptures, dishing, and slurry jamming may occur due to subsequent processes. However, according to an embodiment of the present disclosure, the occurrence of defects is prevented, so that the yield of the semiconductor device can be improved.

[0059] Reference Figure 3F , the third material layer M3 may be formed in the region between the second material layers M2 where the first material layer M1 is removed. That is, the third material layer M3 may be formed in the first recessed portion RC1 and the second recessed portion RC2. Since the third material layer M3 formed in the region between the second material layers M2 is used as a gate line, the third material layer M3 may be formed of a conductive material. For example, the third material layer M3 may be formed of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), and polycrystalline silicon (poly-Si).

[0060] Although the third material layer M3 is formed in the first and second recesses RC1 and RC2, the third material layer M3 may be formed even in the slit trench SLT and the trench T1. For example, the third material layer M3 may be formed even on the inner wall and bottom surface of the slit trench SLT and the inner wall and bottom surface of the trench T1.

[0061] Reference Figure 3G , the third material layer M3 formed in the slit trench SLT and the trench T1 may be removed. For example, the third material layer M3 formed in the slit trench SLT and the trench T1 may be removed by anisotropic dry etching or isotropic wet etching of the slit trench SLT and the trench T1. As the third material layer M3 formed on the inner wall and bottom surface of the slit trench SLT and the inner wall and bottom surface of the trench T1 is removed, the third material layers M3 in the region between the second material layers M2 may be insulated from each other.

[0062] Reference Figure 3H, a fourth material layer may be formed in the trench T1 of the alignment key area AKA. The alignment key AK may include a fourth material layer filled in the trench T1. Each of the fourth material layers may be an insulating layer. In a subsequent process, the alignment key AK may be used for alignment between the substrate SST and the photomask.

[0063] The slit SL may be formed in the slit trench SLT of the cell array region CA. The slit SL may include a slit material layer filled in the slit trench SLT. The slit material layer may be a single layer or multiple layers. For example, the slit SL may include a single layer formed of an insulating layer or amorphous silicon. In another example, the slit SL may include a slit insulating layer formed along the inner wall of the slit trench SLT and a slit conductive layer surrounded by the slit insulating layer.

[0064] The alignment key AK and the slit SL may be formed simultaneously or sequentially. For example, the process of filling the trench T1 with the fourth material layer and the process of filling the slit trench SLT with the slit material layer may be performed simultaneously. In another example, after forming the alignment key AK by filling the trench T1 with the fourth material layer, the slit SL may be formed by filling the slit trench SLT with the slit material layer. In yet another example, after forming the slit SL by filling the slit trench SLT with the slit material layer, the alignment key AK may be formed by filling the trench T1 with the fourth material layer.

[0065] Despite 3A to 3H The case where the semiconductor device according to the present disclosure is a memory device is mainly described in the above description, but the scope of the present disclosure is not limited thereto. For example, even if the semiconductor memory device is a non-memory device, the semiconductor device may include an alignment pattern AP on the scribe lane area SLA, and a sub-support pattern SSP and an alignment key AK according to the present disclosure may be formed in the scribe lane area SLA while a semiconductor integration process is performed in the chip area CHA.

[0066] Figures 4 to 7 is a diagram illustrating the structure of a semiconductor device according to various embodiments of the present disclosure. Figures 4 to 7 4 to 4 are plan views illustrating the layout of the sub-support pattern SSP formed in the alignment key area AKA. Figure 7 In the Figure 2A The components shown in the figure repeat the description of the components.

[0067] Reference Figure 4 and Figure 5, the cross section of each of the sub-support patterns SSPa may be rectangular. The length of the cross section of each of the sub-support patterns SSPa in one direction may be longer than the length of the cross section of each of the sub-support patterns SSPa in another direction. For example, the cross section of one of the sub-support patterns SSPa may have a major axis in the X direction and a minor axis in the Y direction. In addition, the cross section of another of the sub-support patterns SSPa may have a major axis in the Y direction and a minor axis in the X direction. Each of the sub-support patterns SSPa may extend in a direction perpendicular to the substrate SST (e.g., the Z direction).

[0068] Reference Figure 4 Even when the cross section of each of the sub-support patterns SSPa is not circular, at least two sub-support patterns SSPa may be positioned between two adjacent alignment keys among the alignment keys AK. For example, two sub-support patterns SSPa may be arranged parallel to each other in the X direction between two adjacent alignment keys among the alignment keys AK.

[0069] Reference Figure 5 , each of the sub-support patterns SSPa arranged along the X direction may be positioned between two alignment keys AK adjacent to each other. For example, the sub-support patterns SSPa arranged along the X direction may be arranged alternately with the alignment keys AK arranged along the X direction. Alternatively, the alignment keys AK may be positioned between the sub-support patterns SSPa arranged along the X direction, respectively.

[0070] The sub-support pattern SSPa may be formed by filling a support material layer (eg, a conductive material) in support grooves each extending in the X direction (or the Y direction). Each of the support grooves may penetrate the stacked structure (eg, Figure 3A The stacked structure STK shown in FIG. 1 and extending along the X direction (or the Y direction). The supporting grooves may be arranged along the X direction (or the Y direction).

[0071] Refer to Figure 2A , Figure 4 and Figure 5 , the number of the sub-support patterns SSP1 or SSPa positioned between two align keys AK adjacent to each other may be formed in various ways. Figure 2A , Figure 4 and Figure 5 In addition to the arrangement of the sub-support patterns SSP1 and SSPa shown in FIG, various embodiments are possible. For example, the sub-support pattern SSP1 or SSPa may be positioned between the alignment keys AK in various forms, as long as the direction in which the alignment key AK extends (e.g., the Y direction) and the direction in which the sub-support pattern SSPa extends (or the direction in which the sub-support pattern SSPa or SSP1 is arranged) (e.g., the X direction) are formed perpendicular to each other.

[0072] Reference Figures 4 to 6 The cross section of each of the sub-support patterns SSPa or SSPb may be a quadrangular shape or an elliptical shape with rounded corners in addition to a rectangular shape. In addition, each of the sub-support patterns SSPa or SSPb may be formed in various shapes capable of supporting the stack structure STK between the align keys AK.

[0073] Reference Figure 7 In addition to the sub-support pattern, additional support pillars SPP may be formed in the alignment key area AKA. Figure 2A and Figure 7 , the support pillars SPP spaced apart from the first to fourth alignment patterns AP1 to AP4 may be positioned on the alignment key area AKA. For example, the support pillars SPP may be substantially formed in the central area of ​​the alignment key area AKA. The number and position of the support pillars SPP are not limited to Figure 7 The quantities and locations are shown in .

[0074] The support pillars SPP may have a shape similar to or different from that of the sub-support patterns SSP1, SSP2, SSP3, and SSP4. For example, each of the support pillars SPP may have a circular pillar shape. In another example, each of the support pillars SPP may have a circular pillar shape having a larger diameter in cross section than the first to fourth sub-support patterns SSP1 to SSP4. The shape of the support pillars SPP is not limited to Figure 7 The shape shown in .

[0075] The support pillars SPP may support the stack structure STK together with the first to fourth support patterns SP1 to SP4. Figure 3E When the first recessed portion RC1 is formed as shown in FIG. 8 , the sub-support patterns SSP and the support pillars SPP may support the stack structure STK so that the second material layer M2 of the stack structure STK does not collapse.

[0076] Figure 8 is a diagram illustrating a memory card system to which the memory device of the present disclosure is applied.

[0077] Reference Figure 8 , the memory card system 3000 includes a controller 3100 , a memory device 3200 , and a connector 3300 .

[0078] The controller 3100 may be connected to the memory device 3200. The controller 3100 may access the memory device 3200. For example, the controller 3100 may control a write operation, a read operation, or an erase operation, or control a background operation of the memory device 3200. The controller 3100 may provide an interface between the memory device 3200 and a host. The controller 3100 may drive firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0079] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. The controller 3100 can communicate with an external device (e.g., a host) through at least one of various communication standards or interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), Firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards or interfaces mentioned above.

[0080] The memory device 3200 may include a memory cell.

[0081] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 may constitute a memory card such as a personal computer (PC) card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, micro MMC, and eMMC), an SD card (SD, mini SD, micro SD, and SDHC), and a universal flash storage (UFS).

[0082] Fig. 9 is a diagram illustrating a solid state drive (SSD) system to which the memory device of the present disclosure is applied.

[0083] Reference Fig. 9, the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 through a signal connector 4001, and receive power through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0084] The controller 4210 may control the plurality of memory devices 4221 to 422n in response to a signal received from the host 4100. The signal may be a signal based on an interface between the host 4100 and the SSD 4200. For example, the signal may be a signal defined by at least one of a communication interface or standard such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), a firewire, a universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0085] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. The plurality of memory devices 4221 to 422n may communicate with the controller 4210 through channels CH1 to CHn.

[0086] The auxiliary power supply 4230 may be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 may receive power input from the host 4100 and charge the power. When the power supply from the host 4100 is not stable, the auxiliary power supply 4230 may provide power to the SSD 4200. The auxiliary power supply 4230 may be located in the SSD 4200, or located outside the SSD 4200. For example, the auxiliary power supply 4230 may be located on the mainboard and provide auxiliary power to the SSD 4200.

[0087] The buffer memory 4240 may be used as a buffer memory of the SSD 4200. For example, the buffer memory 4240 may temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. The buffer memory 4240 may include a volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or a nonvolatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0088] According to the embodiments of the present disclosure, the structural stability of a region where an alignment pattern is formed may be improved, thereby reducing the occurrence of defects in a semiconductor device.

[0089] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited by the above-mentioned embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0090] In the above-mentioned embodiments, all operations may be selectively performed, or a part of the operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0091] In addition, embodiments of the present disclosure are described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not limited by the above-mentioned embodiments, and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure. In addition, the embodiments may be combined to form additional embodiments.

[0092] CROSS-REFERENCE TO RELATED APPLICATIONS

[0093] This application claims priority to Korean Patent Application No. 10-2023-0090357, filed on Jul. 12, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A lower structure, the lower structure comprising a chip area and a scribe lane area surrounding the chip area; a first alignment pattern including first alignment keys extending parallel to each other along a first direction on the scribe lane region; as well as A support pattern includes first sub-support patterns arranged between the first alignment keys along a second direction crossing the first direction.

2. The semiconductor device according to claim 1, wherein Each of the first sub-support patterns has a circular column shape extending vertically to the lower structure.

3. The semiconductor device according to claim 1, wherein Each of the first sub-support patterns has a plane having a major axis in the second direction and a minor axis in the first direction and extends vertically to the lower structure.

4. The semiconductor device according to claim 1, wherein At least two of the first sub-support patterns are positioned between two first alignment keys adjacent to each other among the first alignment keys.

5. The semiconductor device according to claim 1, wherein Each of the first sub-support patterns is positioned between two first alignment keys adjacent to each other among the first alignment keys.

6. The semiconductor device according to claim 1, wherein Each of the first alignment keys and each of the first sub-support patterns are spaced apart from each other. 7 . The semiconductor device according to claim 1 , further comprising a second sub-support pattern arranged along the second direction and positioned in the first direction relative to the first sub-support pattern.

8. The semiconductor device according to claim 1, wherein The angle between the first direction and the second direction is 90 degrees.

9. The semiconductor device according to claim 1, further comprising a stacked structure including conductive layers and interlayer insulating layers alternately stacked on the scribe street region, in, Each of the first alignment key and the first sub-support pattern penetrates the stack structure.

10. The semiconductor device according to claim 1, wherein Each of the first alignment keys includes an insulating layer.

11. The semiconductor device according to claim 1, wherein Each of the first sub-support patterns includes a conductive material.

12. The semiconductor device according to claim 1, further comprising: a second alignment pattern including second alignment keys extending parallel to each other along the second direction on the scribe lane region; as well as A second supporting pattern includes second sub-support patterns arranged along the first direction between the second alignment keys. 13 . The semiconductor device of claim 12 , further comprising a support column spaced apart from the first alignment pattern and the second alignment pattern.

14. A method for manufacturing a semiconductor device, the method comprising the steps of: forming a stacked structure by alternately stacking a first material layer and a second material layer on a lower structure, the lower structure including a chip region and a scribe lane region surrounding the chip region; forming a sub-support pattern of the stacked structure penetrating the scribe line area, wherein the sub-support pattern is arranged along a first direction; forming grooves penetrating the stacked structure in the scribe lane region, the grooves extending parallel to each other along a second direction intersecting the first direction; forming a recessed portion by removing the first material layer exposed through the groove; forming a third material layer in the recessed portion through the groove; as well as An alignment pattern is formed by filling a fourth material layer in the trench.

15. The method according to claim 14, wherein: The step of forming the sub-support pattern comprises: forming support holes arranged along the first direction; and The sub-support patterns are formed by filling a support material layer in the support holes.

16. The method according to claim 14, wherein: The step of forming the sub-support pattern comprises: forming supporting grooves each extending along the first direction; and The sub-support patterns are formed by filling a support material layer in the support grooves.

17. The method according to claim 14, wherein: The step of forming the sub-support patterns includes forming a first sub-support pattern arranged along the first direction and a second sub-support pattern arranged along the first direction and positioned in the second direction relative to the first sub-support pattern.

18. The method according to claim 14, wherein: In the step of forming the trenches, the trenches are formed such that at least one of the sub-support patterns is positioned between two trenches adjacent to each other among the trenches.

19. The method according to claim 14, wherein: The recessed portion exposes the sub-support pattern.

20. The method according to claim 14, wherein: In the step of forming the recessed portion, the stacked structure is supported by the sub-support pattern.

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