Transferring sensed inductor current information from power stage to phase controller in multiphase switching converter

Abstract

The present invention provides a power stage of a multiphase switching converter and a multiphase switching converter, the power stage comprising: a high-side switch and a low-side switch for periodically driving an inductor within a first interval and a second interval, respectively, based on a control signal, where the inductor is coupled to a node of the high-side switch and the low-side switch; the current sensing module is used for generating information on an output node of the power stage, and the information is used for representing the inductor current flowing through the inductor; and a switch coupled between the output node and an output pin of the power stage; wherein, when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in an energized state, and the switch is opened to disconnect the output node from the output pin.

Description

[0001] Priority Claim

[0002] This patent application is related to and claims priority to the co-pending provisional Indian patent application entitled “Current Sensing Offset in APM (Automatic Phase Management)”, Serial No.: 202341077437, filed on November 14, 2023; Case No.: AURA-348-INPR, which is incorporated herein in its entirety to the extent not inconsistent with the description herein. Technical Field

[0003] The present application relates to the field of power supply circuits, and more specifically to a process of transmitting sensed inductor current information from a power stage to a phase controller in a multi-phase switching converter. More specifically, the present application relates to a power stage of a multi-phase switching converter and a multi-phase switching converter. Background Art

[0004] A switching converter refers to a component that generates a regulated DC (direct current) voltage from an input power source by using one or more switches, which is well known in the relevant art. Generally, a switching converter converts the voltage of an input power source (input power supply voltage) into a pulse voltage by operating a switch, and then smoothes the pulse voltage using capacitors, inductors, and other components to generate a regulated DC voltage. Power is supplied from the input terminal to the output terminal by turning on and off a switch (such as a MOSFET) to generate and regulate the required voltage. Switching converters are used in components such as regulated power supplies, which in turn are used in devices such as computers and mobile phones, which is also well known in the relevant art.

[0005] A switching converter typically contains a pair of switches that drive an inductor. Each switch is typically implemented as a transistor (e.g., a MOSFET), and the switches are connected in series between an input supply voltage and a reference terminal (e.g., ground). The switch that is coupled closer to the input voltage (the converter's input supply) is called a high-side switch, while the other is called a low-side switch. The switches are operated by a control circuit that turns on the transistors for consecutive non-overlapping durations so that the currently turned-on switch drives the inductor for the corresponding duration.

[0006] A multiphase switching converter includes multiple pairs of such switches, and associated circuits for each pair of switches. Each pair of switches is typically controlled by a corresponding phase in a series of phases, and each switch in the switch pair is controlled simultaneously to produce a desired regulated voltage, and can support higher load currents with higher efficiency and provide other advantages, which is well known in the art. Each of such switch pairs, together with associated circuits, is referred to as a power stage of a multiphase switching converter. A phase controller operates to control the specific time at which each power stage operates when producing a desired output voltage.

[0007] The phase controller usually needs to communicate the current magnitude provided to the output by each power stage through the corresponding inductor, which is called inductor current information. Therefore, each power stage obtains (senses) the current through the inductor corresponding to the power stage and provides the inductor current information to the phase controller.

[0008] The present application relates to a process of transmitting sensed inductor current information from a power stage to a phase controller in a multi-phase switching converter, and also relates to a power stage of the multi-phase switching converter and the multi-phase switching converter in the process. Summary of the invention

[0009] The present invention provides a power stage of a multi-phase switching converter and a multi-phase switching converter, wherein the power stage comprises: a high-side switch and a low-side switch, for periodically driving an inductor in a first interval and a second interval respectively based on a control signal, wherein the inductor is coupled to a node between the high-side switch and the low-side switch; a current sensing module, for generating information at an output node of the power stage, the information being used to represent the magnitude of the inductor current flowing through the inductor; and a switch coupled between the output node and an output pin of the power stage; wherein, when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in a powered-on state, and the switch is disconnected to disconnect the output node from the output pin.

[0010] In some embodiments, the component of the current sensing module is an amplifier.

[0011] In some embodiments the information is a current; when the power stage is in an inactive state, the amplifier has a non-zero output offset voltage such that the current is non-zero.

[0012] In some embodiments, the switch is closed when the power stage is in an active state; and the high-side switch and the low-side switch drive the inductor in the first interval and the second interval respectively only when the power stage is in an active state.

[0013] In some embodiments, the control signal indicates whether the power stage is in an active state or an inactive state.

[0014] In some embodiments, a high impedance (Hi-Z) state of the control signal indicates that the power stage is in an inactive state.

[0015] In some embodiments, the power stage also includes a gate driver for receiving the control signal, the gate driver being used to generate a corresponding output signal based on the logic level of the control signal to control the high-side switch and the low-side switch to be opened or closed accordingly; wherein, if the state of the control signal is the high impedance (Hi-Z) state, the gate driver generates an output signal having a value that causes the switch to be opened.

[0016] In some embodiments, the current sensing module includes: a fully differential amplifier coupled to a differential input terminal to receive a voltage across the low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch, and a third switch; wherein a first current terminal of the first transistor is coupled to a first constant reference potential, a second current terminal of the first transistor is coupled to the output node, a first current terminal of the second transistor is coupled to a second constant reference potential, and a second current terminal of the second transistor is coupled to the output node; the first capacitor is coupled between a control terminal of the first transistor and the first constant reference potential, and the second capacitor is coupled between a control terminal of the second transistor and the second constant reference potential; the first switch is coupled between a first differential output terminal of a differential output pair of the fully differential amplifier and the control terminal of the first transistor, the second switch is coupled between a second differential output terminal of the differential output pair and the control terminal of the second transistor, and the third switch is coupled between the differential input terminals, wherein the first switch is closed when the power stage is in an inactive state, and either of the first switch and the second switch may be closed in the first interval and the second interval except for a blanking interval between the first interval and the second interval.

[0017] An embodiment of the present application provides a multi-phase switching converter, which includes: a plurality of power stages, which are used together to generate a regulated power supply voltage on a power rail; a phase controller, which is used to control each of the plurality of power stages to generate the regulated power supply voltage; wherein a first power stage among the plurality of power stages includes: a high-side switch and a low-side switch, which are used to periodically drive an inductor in a first interval and a second interval respectively based on a control signal, wherein the inductor is coupled to a node between the high-side switch and the low-side switch; a current sensing module, which is used to generate information at an output node of the power stage, the information being used to represent the magnitude of the inductor current flowing through the inductor; a switch coupled between the output node and an output pin of the power stage, wherein, when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in a powered-on state, and the switch is opened to disconnect the output node from the output pin.

[0018] In some embodiments, the component of the current sensing module is an amplifier.

[0019] In some embodiments, the information is a current, wherein the amplifier also has a non-zero output offset voltage when the power stage is in an inactive state such that the current is non-zero.

[0020] In some embodiments, the switch is closed when the power stage is in an active state; and the high-side switch and the low-side switch are used to drive the inductor in the first interval and the second interval respectively only when the power stage is in an active state.

[0021] In some embodiments, the control signal indicates whether the power stage is in an active state or an inactive state.

[0022] In some embodiments, a high impedance (Hi-Z) state of the control signal indicates that the power stage is in an inactive state.

[0023] In some embodiments, the multi-phase switching converter also includes a gate driver for receiving the control signal, the gate driver being used to generate a corresponding output signal based on the logic level of the control signal to control the high-side switch and the low-side switch to open or close accordingly; wherein, if the state of the control signal is the high impedance (Hi-Z) state, the gate driver generates an output signal having a value that causes the switch to open.

[0024] In some embodiments, the current sensing module includes: a fully differential amplifier coupled to a differential input terminal to receive a voltage across the low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch, and a third switch; wherein a first current terminal of the first transistor is coupled to a first constant reference potential, a second current terminal of the first transistor is coupled to the output node, a first current terminal of the second transistor is coupled to a second constant reference potential, a second current terminal of the second transistor is coupled to the output node, the first capacitor is coupled between a control terminal of the first transistor and the first constant reference potential, and the second capacitor is coupled between a control terminal of the second transistor and the second constant reference potential; the first switch is coupled between a first differential output terminal of a differential output pair of the fully differential amplifier and the control terminal of the first transistor, the second switch is coupled between a second differential output terminal of the differential output pair and the control terminal of the second transistor, and the third switch is coupled between the differential input terminals, wherein the first switch is closed when the power stage is in an inactive state, and either of the first switch and the second switch may be closed in the first interval and the second interval except during a blanking interval between the first interval and the second interval.

[0025] An embodiment of the present application provides a power stage of a multi-phase switching converter, wherein the power stage includes: a high-side switch and a low-side switch, for periodically driving an inductor in a first interval and a second interval respectively based on a control signal, wherein the inductor is coupled to a node between the high-side switch and the low-side switch; and a current sensing module, for generating information at an output node of the power stage, the information being used to represent a magnitude of an inductor current flowing through the inductor, wherein when the power stage is in an inactive state, no current flows from the output node to a phase controller of the multi-phase switching converter.

[0026] In some embodiments, when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in an energized state; the power stage further includes a switch coupled between the output node and an output pin of the power stage, wherein the output pin is coupled to the phase controller; when the power stage is in an inactive state, the switch is opened to disconnect the output node from the output pin. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments of the present application will be described with reference to the accompanying drawings which are briefly described below.

[0028] Figure 1 is a schematic block diagram of a system provided in an embodiment of the present application;

[0029] Figure 2A It is a schematic block diagram of the details of the voltage regulation module (VRM) in the embodiment of the present application.

[0030] Figure 2B The waveform of the power level signal in the embodiment of the present application is shown as follows Figure 1 .

[0031] Figure 3A It is a detailed schematic diagram of the power level in the embodiment of the present application.

[0032] Figure 3B Schematic diagram 2 of the waveform of the power level signal in the embodiment of the present application.

[0033] Figure 4 Schematic diagram of relevant details of the current sensing module in the embodiment of the present application.

[0034] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0035] Overview

[0036] According to one aspect of the present application, a power stage of a multiphase switching converter includes a high-side switch, a low-side switch, a current sensing module and a switch. The high-side switch and the low-side switch are used to periodically drive an inductor in a first interval and a second interval respectively based on a control signal. The inductor is connected to the node of the high-side switch and the low-side switch. The power stage includes a current sensing module to generate information on the output node of the power stage, and the information is used to indicate the magnitude of the inductor current flowing through the inductor. The power stage includes a switch connected between the output node and the output pin of the power stage. When the power stage is in an inactive state, a part of the current sensing module for driving the output node remains in an energized state, and the switch is disconnected to disconnect the output node from the output pin.

[0037] In one embodiment, the component of the current sensing module for driving the output node is an amplifier, and the information provided on the output pin is a current. The amplifier has a non-zero output offset voltage that causes the current provided on the output node to be non-zero even when the power stage is in an inactive state.

[0038] Several aspects of the present application are described below with reference to examples. However, those skilled in the relevant art will recognize that the present application can be practiced without one or more specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown in detail to avoid confusing the features of the present application. In addition, the described features / aspects can be practiced in various combinations, although only some combinations are described herein for the sake of brevity.

[0039] Example System

[0040] Figure 1 1 is a block diagram of an example system in which several aspects of the present application may be implemented. System 100 is shown as including a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and peripherals 150. In one embodiment, system 100 corresponds to a computer (desktop, laptop, etc.), although in other embodiments system 100 may represent other types of systems. It is understood that system 100 may include more than one computer. Figure 1 More or fewer modules may be shown.

[0041] CPU 120 generally represents a processor or system on a chip (SoC), and is shown as receiving a pair of supply voltages (Va and Vb) from power supply 110 on respective paths 112A and 112B. For example, Va may be a smaller voltage than Vb and may be used to power the core portion of the CPU, which may include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb may be used to power the remainder of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals to power supply 110 (via path 121) specifying, among other things, its power requirements. Examples of such signals may be signals specifying a particular operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc., which refer to "power saving states for improved efficiency."

[0042] Memory 130 represents a memory that may include volatile and non-volatile memory. For example, in a personal computer, the memory may include magnetic memory (hard disk) as well as solid-state memory (RAM, flash memory, etc.). Memory 130 is shown as receiving a power supply voltage on path 113 for powering various circuits and blocks therein.

[0043] The network interface 140 is used to provide two-way communication between the system 100 and a computer network or the general Internet. The network interface 140 implements the use of a network such as Ethernet or Wi-Fi. TMThe network interface 140 may also include the electronic circuits required to communicate with specific physical layer and data link layer standards such as . The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN) and large-scale network communication through routable protocols such as the Internet Protocol (IP). The network interface 140 receives power on path 114 for powering internal circuits and modules. The network interface 140 receives / transmits from the external system and CPU 120 via path 141 and path 124, respectively.

[0044] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power on path 115 and communicates with external devices on path 151 .

[0045] The power supply 110 receives power from one or more power sources (e.g., a battery) on the path 101 and provides the required power supply voltage to the paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is designed to include one or more multi-phase DC-DC converters therein to generate the power supply voltage. The power supply 110 responds to the signal from the CPU 120 received from the path 121 to control the multi-phase converter to reduce / increase the current output based on specific signals (e.g., PS1, PS2, and PS3).

[0046] In an embodiment, the power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more step-down switching (buck) converters to generate several smaller voltages from a higher voltage power supply. However, in other embodiments, other types of DC-DC converters may be implemented, such as boost, buck-boost, hysteretic converters, etc., instead of buck converters. Using a VRM, multiple devices / ICs requiring different power supply voltages can be mounted on the same platform, such as a computer motherboard of a personal computer (PC). Therefore, continuing with the description of the VRM, as shown in FIG. Figure 2A shown.

[0047] Voltage Regulator Module (VRM)

[0048] Figure 2A 1 is a block diagram illustrating the details of the VRM in the embodiment of the present application. Figure 1 ) is implemented as a voltage regulator module in the form of a multi-phase switching converter that generates two regulated voltages Va (240) and Vb (250).

[0049] The VRM 110 includes a phase controller 210, smart power stages (SPS) SPSA-1 (220-1) to SPSA-6 (220-6), SPSB-1 ​​(230-1) to SPS B-3 (230-3), inductors 225A-1 to 225A-6 and 227B-1 to 227B-3, capacitors 226A-1 to 226A-6 and 228B-1 to 228B-3. The power supply Va (240) (Rail-A) is generated by a 6-phase buck converter (there are six SPSA-220-1 to 220-6), and the power supply Vb (250) (Rail-B) is generated by a 3-phase buck converter (there are three SPSB-230-1 to 230-3). The nodes / paths 240 and 250 may correspond to Figure 1 For simplicity, Figure 2A Other power supply circuits that generate power on paths 113, 114 and 115 are not shown.

[0050] In the present embodiment, each power stage and phase controller are implemented as separate integrated circuits (ICs). However, in other embodiments, the implementation of the power stage and phase controller may be different.

[0051] The phase controller 210 is combined with one or more power stages on the power rail to produce a regulated supply voltage as an output. Figure 2A In the example of , the phase controller 210 and one or more power stages of Rail-A, i.e., SPSA-1 to SPSA-6, generate a regulated voltage Va (240). Similarly, the phase controller 210 and one or more power stages of Rail-B, i.e., SPSB-1 ​​to SPSB-3, generate a regulated voltage Vb (250). Therefore, Va (240) and Vb (250) are input to the phase controller 210, enabling one or more feedback loops within the phase controller 210 to regulate the voltages Va and Vb. The phase controller 210 also receives information about the inductor current (i.e., the magnitude of the inductor current flowing through each inductor) from each SPS, thereby implementing various operations such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS of the same converter (or "rail") so that the current from each SPS of the converter is substantially equal in magnitude. Other signals flowing between the phase controller 210 and the SPS are described below.

[0052] The combination of phase controller 210, SPS, and corresponding inductors and capacitors (corresponding circuits within) form one "phase" on the power rail. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions within phase controller 210 form a single buck converter and one phase of a 6-phase buck converter. It is noted here that while each phase is shown as having its own separate capacitor (e.g., 226A-1), in another embodiment, only a single larger capacitor (larger capacitance) may be used at node 240 (and 250). In other embodiments, multiple capacitors are placed near the load powered by the corresponding supply voltage.

[0053] Each SPS (or "power stage" in general) can be implemented to include a high-side switch, a low-side switch, gate drive circuits for both switches, a temperature monitoring circuit, and an inductor current sensing module to provide information indicative of the magnitude of the inductor current to the phase controller 210. The current provided by the SPS, and the corresponding inductor current, typically depends on the load current drawn from the supply voltage, although the high-side switch and low-side switch of the SPS can be viewed as "driving" the inductor. Each SPS receives a power supply (which can be the same power supply) as an input connected to the high-side switch (shown in detail in the following section). In Figure 2A In FIG. 1 , the power supply is numbered 201 and the voltage is Vin. In the embodiment of VRM 110, an example value of Vin is approximately 21 volts (V).

[0054] Each SPS communicates with the phase controller 210 via respective signals PWM, SYNC, CS and TMP. Thus, SPSA-1 is shown connected to the phase controller 210 via signals / paths PWMA-1 (211), SYNC-A (212), CSA-1 (213) and TMPA (214). SPSA-6 communicates with the phase controller 210 via signals PWMA-6, SYNC-A, CSA-6 and TMP (214), although in Figure 2A , the respective connections of signals PWMA6, SYNC-B, and CSA-6 to the phase controller are not shown. Similarly, SPSB-1 ​​is shown connected to the phase controller 210 via signals / paths PWMB-1 (216), SYNC-B (217), CSB-1 (218), and TMPB (219). SPSB-3 communicates with the phase controller 210 via signals PWMB-3, SYNC-B, CSB-3, and TMP (219), although in Figure 2A, not shown are the respective connections of signals PWMB-2, SYNC-A, and CSB-3 to phase controller 210. Other SPSs will have similar connections to phase controller 210. Each SPS has a PWM, SYNC, CS, and TMP that are received / transmitted via the pins on .

[0055] The signal PWM is an input to the SPS from the phase controller 210 and represents a pulse width modulated (PWM) signal. The PWM signal can be generated to have a logic high state, a logic low state, or a high impedance (Hi-Z) state. Typically, the logic high and logic low states of the PWM signal correspond to the voltages of the positive and negative rails of the power supply of the circuit generating the PWM signal, respectively (within the error / noise tolerance), and the Hi-Z state corresponds to the mid-rail voltage of the power supply (or the voltage window around the mid-rail voltage), which is well known in the art. However, other conventions can be used for the three states of the PWM signal, which is obvious to those skilled in the art. Typically, the PWM signal needs to remain within the above-mentioned voltage window for a predetermined minimum duration of the power level to correctly identify the Hi-Z state.

[0056] The PWM signal controls the opening and closing of the high-side switch and the low-side switch of the phase / power stage through the logic high and logic low states. Generally, the logic high state is used to turn on (i.e., close) the high-side switch and turn off (i.e., open) the low-side switch (the corresponding duration can be referred to as the "first interval"), while the logic low state is used to turn on the low-side switch and turn off the high-side switch (the corresponding duration can be referred to as the "second interval"). Each cycle of the PWM signal has a "first interval" and a "second interval".

[0057] The Hi-Z state of the PWM signal indicates to the power stage that the power stage is not used to generate an output voltage, i.e., "inactive". Therefore, when the PWM is in the Hi-Z state, both the high-side and low-side switches of the stage are disconnected, and the power stage can enter a low power / power-down mode. Typically, the phase controller 210 is designed to generate a PWM signal in a manner that can indicate three states, wherein one of the three states indicates that the corresponding power stage will be shut down. For those skilled in the relevant art, such three states may be implemented in other ways. For example, the phase controller 210 may be implemented to generate PWM as a traditional binary signal, wherein the power stage is implemented to identify the Hi-Z state when the PWM signal is disconnected (OFF), i.e., the PWM signal is not generated.

[0058] The duty cycle of the PWM signal is set by the phase controller 210 to produce the desired supply voltage and / or control / change the current provided by that phase. For example, PWMA-1 will have the magnitude of Va and the duty cycle required for the current provided by SPSA-1. It will be apparent to those skilled in the art that the PWM signals to each SPS of the same converter can be staggered, i.e., delayed in phase with respect to each other, so that two high-side switches (i.e., in each SPS) that would normally not be on track are turned on at the same time. The reason for this technique is to ensure that the peak instantaneous current drawn from Vin is always relatively low.

[0059] The signal TMP is an output (e.g., a voltage) from the SPS to the phase controller 210 and provides information about the temperature in the SPS. The phase controller 210 can process the TMP signal (or the information contained therein) to adjust the current provided by the phase, or to shut down the VRM in the event of a fault. The TMP outputs of each phase of the converter are connected together, and a single input (e.g., TMPA 214) is connected to the phase controller 210. The maximum value of the TMP output of one phase is driven on the wired connection.

[0060] The signal SYNC is an input to the SPS and can be used by the phase controller 210 to wake up the SPS when the power supply 110 is powered on, and is also used to indicate the power mode (e.g., PS2, PS3) of the multi-phase converter, i.e., the output current requirement. Typically, all SPSs of the same converter share a single SYNC signal (e.g., SYNC-a 212).

[0061] The signal CS (current sense) is an input from the SPS / phase to the phase controller 210 and contains information about the magnitude of the inductor current of that phase. Depending on the specific implementation of the power stage and the phase controller 210, the information can be in the form of current, voltage, digital value, etc. The CS block in the SPS implements the current sensing operation and sends the signal CS to the phase controller 210.

[0062] In one embodiment of the present application, the current sensing module of the power stage sends the sensed inductor current information to the phase controller 210 in the form of a current, which may be the same magnitude as the current magnitude of the inductor, or a numerical value (in terms of magnitude) of the inductor current scaled down. Accordingly, in this embodiment, the phase controller 210 is designed to receive information in the form of a current, wherein the scaling factor is known to the phase controller 210 and the (corresponding) power stage when scaling is used.

[0063] The phase controller 210 may be designed to implement automatic phase management (APM). Thus, the specific number of power stages (or phases) operated by the phase controller 210 may vary depending, for example, on the magnitude of the load current drawn from the rail (e.g., Va 240). Typically, the smaller the load current, the smaller the number of power stages used / operated, and vice versa.

[0064] For example, for very low load currents drawn from Track-A (Va 240), the phase controller 210 may use / operate only one power stage (referred to as the "active" power stage) to generate Va, and keep the other five power stages in "non-active" mode. Therefore, the phase controller 210 generates a PWM signal to control the switching of the high-side and low-side switches of only one active power stage to generate Va, and keeps the PWM signals to the other five power stages in a Hi-Z state. Therefore, the high-side and low-side switches of the five non-active state power stages will all be disconnected (not switched). An example situation in which the load current can be very small and the phase controller 210 can only keep a small number (e.g., one) of the power stages in an active state is when the VRM 110 is operated in DCM (discontinuous conduction mode). As is well known in the relevant art, DCM refers to a mode in which the inductor current of a power stage drops to zero during a PWM logic low interval and remains zero until the next logic high transition of the PWM signal.

[0065] When a power stage is in an inactive state (i.e., inactive), one or more circuits / blocks in the power stage (including the current sensing module) may be powered off or maintained in a low power / sleep mode to reduce power consumption. However, in some specific situations (e.g., a sudden increase in load current demand), a certain delay is required to restore the corresponding module to a powered and operable state. Therefore, at least some circuits / blocks of the "inactive" power stage of the VRM 110 (i.e., a power stage whose PWM input signal is in a Hi-Z state) may be maintained in a fully powered state.

[0066] For example, a current sensing (CS) amplifier in an inactive CS block (whose output is connected to the CS pin) can be maintained in a reset state (i.e., the input signal to the amplifier can be disconnected or set to a predetermined fixed level, such as zero volts), but maintained in a fully powered state (meaning that all circuit portions of the CS amplifier are powered on). Alternatively, all portions of the CS block can be maintained in a fully powered state. In this case (particularly when the CS amplifier is maintained in a full power state), the DC offset current of the CS amplifier will still flow into the CS pin and, therefore, into the corresponding input pin of the phase controller 210. The term "DC offset current" for a CS amplifier refers to the magnitude (usually a constant value) of the output current produced by the CS amplifier when the input signal to the CS amplifier is maintained at zero volts or some other fixed voltage as described above.

[0067] For example, refer to Figure 2A , if SPSA-1 is inactive, some (non-zero) offset current may still flow through the CSA-1 (213) pin / path. Such an offset current may be added to the total inductor current provided to the phase controller 210, thereby affecting the phase controller 210. As described above, the phase controller 210 uses the inductor current information from the power stage for various purposes. For example, the non-zero offset current can affect the various control loops (including the voltage regulation control loop) controlled by the phase controller 210. When the load current is small, the error contributed by the offset current may be particularly significant.

[0068] Figure 2B 1 is a diagram illustrating example PWM waveforms and sense current (CS current) waveforms of three power stages of the same power rail, such as power stages SPSA-1, SPSA-2, and SPSA-3 of Rail-A among the power stages of VRM 110. For ease of illustration, Figure 2B In the example, it is assumed that the power supply Rail-A only contains three power supply stages SPSA-1, SPSA-2 and SPSA-3. Waveform PWMA-1 ( Figure 2A 211) and CSA-1( Figure 2A 213) represent the PWM signal provided as input to SPSA-1 and the sensed inductor current provided by SPSA-1 to phase controller 210, respectively. Similarly, waveforms PWMA-2 and CSA-2 represent the PWM signal provided as input to SPSA-2 and the sensed inductor current provided by SPSA-2 to phase controller 210, respectively. Waveforms PWMA-2 and CSA-2 represent the PWM signal provided as input to SPSA-2 and the sensed inductor current provided by SPSA-2 to phase controller 210, respectively.

[0069] Assume that all three phases SPSA-1, SPSA-2, and SPSA-3 are activated before time t24. Therefore, PWMA-1, PWMA-2, and PWMA-3 are shown as switching between logic high and logic low states until t24. Specifically, signal PWMA-1 is logic high in intervals t20-t21 and t22-t23, and is logic low in intervals t21-t22 and t23-t24. PWMA-2 and PWMA-3 also switch between logic high and logic low states until time t24. The three PWM signals are shown as interlaced. When the corresponding PWM signal is logic high and logic low, the corresponding sense inductor current waveform provided by each stage increases and decreases, respectively.

[0070] At or slightly before t24, assuming that the load current has significantly decreased, the phase controller 210 deactivates SPSA-1 and SPSA-2 and keeps only SPSA-3 turned on. Therefore, PWMA-1 and PWMA-2 are in a high impedance (Hi-Z) state starting from t24. However, since the phase controller 210 continues to keep SPSA-3 turned on, PWMA-3 continues to switch between logic high and logic low even after t24 (part of the next PWM cycle such as Figure 2B ), and CSA-3 represents the sensed inductor current of SPSA-3. On the other hand, the magnitudes of CSA-1 and CSA-2 are the respective offset currents of the respective current sensing (CS) amplifiers of SPSA-1 and SPSA-2, respectively. The respective offset current magnitudes are represented by reference numerals 210 and 220, which are assumed to be equal for simplicity. As mentioned above, such offset currents on the CS pin of the power stage in an inactive state are undesirable.

[0071] As described below, embodiments of the present application overcome the above-mentioned problems.

[0072] Power Stage (SPS)

[0073] Figure 3A Detailed schematic diagram of the implementation of the power stage in the embodiment of the present invention. The power stage 300 is shown to include a gate driver 310 , a high-side (HS) switch 320 , a low-side (LS) switch 330 , a current sensing module 350 and a switch 360 . Figure 3A Also shown in FIG. 3 are an inductor 325 and a capacitor 326 corresponding to the power stage. Current "IL" represents the inductor current and current "ICS" represents the sensed current provided as an output on the CS pin (361). The power stage 300 is connected to the inductor 325 and the capacitor 326 and a controller (eg, Figure 2A The power stage 300 is combined with the phase controller 210 to provide a regulated voltage (Vout) as an output at node 340. The power stage 300 may include various other modules / circuits, such as temperature sensors, level converters, etc. Figure 3A The pins / circuitry in the power stage 300 connected to process the SYNC input signal and provide a temperature indicating output are not shown.

[0074] Power level 300 can replace Figure 2A The nodes PWM (311) and CS (361) will correspond to Figure 2A The power stage 300 is implemented in the form of an integrated circuit (IC). However, in other embodiments, the power stage 300 can be implemented in a different form, for example, using discrete components.

[0075] The gate driver 310 receives a PWM signal 311 (e.g., from the phase controller 210) and generates appropriate voltages in response to the logic level of the PWM to turn on and off the HS switch 320 and the LS switch 330 in corresponding intervals indicated by the logic level of the PWM signal. The HS switch 320 and the LS switch 330 are each shown as an N-channel MOSFET (metal oxide semiconductor field effect transistor), and the gate driver 310 drives the gate terminal of the MOSFET. Other types of switch implementations are also possible. Figure 3A In the example of , when PWM 311 is at a logic high level, gate driver 310 generates appropriate voltages on paths 312 (en-HS) and 313 (en-LS), respectively, to turn on MOSFET 320 and turn off MOSFET 330. When PWM 311 is at a logic low level, gate driver 310 generates corresponding appropriate voltages on paths 312 and 313 to turn off MOSFET 320 and turn on MOSFET 330. When PWM 311 is in a Hi-Z state, gate driver 310 generates corresponding appropriate voltages on paths 312 and 313 to turn off MOSFET 320 and MOSFET 330. In addition, gate driver 310 is designed to generate signal 314 to turn off switch 360 when PWM 311 is in a Hi-Z state, and to close switch 360 otherwise.

[0076] The current sensing module 350 is used to determine the magnitude (e.g., instantaneous magnitude) of the inductor current (through the inductor 325) and provide information indicating the magnitude of the inductor current as an output at a node 351. The current sensing module 350 determines the magnitude of the inductor current in one of several known ways. For example, in Figure 3A , current sensing module 350 is shown receiving inputs 325 and 335 from HS switch 320 and LS switch 330, respectively. In one embodiment, signals 325 and 335 represent the respective voltage drops across the HS and LS switches when the corresponding switches are turned on and current flows through them and inductor 325. Current sensing module 350 obtains the instantaneous magnitude of the inductor current (or a scaled-down value thereof) based on the voltage drops. Figure 4 In another embodiment described, the current sensing module 350 uses the voltage drop across the LS switch 330 to directly obtain the inductor current magnitude (or a scaled-down value thereof) when the LS switch is turned on, and "builds" (or simulates) the inductor current magnitude when the HS switch 320 is turned on. The current sensing module 350 provides information representative of the inductor voltage magnitude at its output node 351. In one embodiment, this information is in the form of a (replica) current (denoted as ICS) having a magnitude that is scaled down relative to the instantaneous inductor current magnitude.

[0077] As described above, when the PWM signal (311) is in the Hi-Z state, the power stage 300 is in an inactive state to generate Vout, and the switches 320 and 330 are open. However, as described above, all current sensing modules 350 or at least one current sensing amplifier (whose output is provided at the node 351) within the current sensing module 350 remain in a full power state. Therefore, even when the power stage 300 is in an inactive state, a non-zero offset current of the amplifier may exist at the node 351.

[0078] Switch 360 is connected between node 351 and CS pin / pad (361) and can be operated to be closed or open. Figure 3A In the example of , the gate driver 310 includes a circuit for detecting whether the signal PWM (311) is in the Hi-Z state. In one embodiment, if the signal PWM (311) is in the Hi-Z state continuously for a predetermined duration, the circuit power stage 300 will switch to an inactive state. If the PWM (311) is in the Hi-Z state, the circuit opens the switch 360, otherwise the circuit closes (or remains closed) the switch 360. The circuit controls the opening and closing of the switch 360 via a control signal on the path 314. The circuit can be implemented in a known manner. The switch 360 can be implemented, for example, as a metal oxide semiconductor field effect transistor (MOSFET) or other types of transistors.

[0079] Due to the provision and operation of switch 360, an offset current can be prevented from being provided on CS pin 361, thereby preventing an offset current from being provided to the phase controller. One or more disadvantages caused by providing a non-zero offset current to the phase controller when the power stage is in an inactive state (e.g., as described above) are overcome.

[0080] Figure 3B is a diagram illustrating example PWM waveforms and sensed current (CS current) waveforms of power stages SPSA-1, SPSA-2, and SPSA-3 of Rail-A, each of which is implemented as power stage 300 described above. Figure 3B In the example, the waveform labels are Figure 2B The labels in are the same. Figure 3B Most of the details are Figure 2B are similar to those shown, so only the differences are noted here. Figure 2B The difference in details.

[0081] At or slightly before t31, it is assumed that the load current has significantly decreased, so the phase controller 210 deactivates SPSA-1 and SPSA-2 and keeps only SPSA-3 turned on. Therefore, PWMA-1 and PWMA-2 are in a high impedance (Hi-Z) state starting from t31. Even after t31, PWMA-3 continues to switch between logic high and logic low (part of the next PWM cycle such as Figure 2B ), and CSA-3 continues to represent the sensed inductor current of SPSA-3. However, unlike Figure 2B Differently, each of the signals CSA-1 and CSA-2 has an amplitude equal to zero (as indicated by reference numerals 380 and 390) because when the power stages SPSA-1 and SPSA-2 are in the inactive state, the corresponding switches (corresponding to Figure 3A The switch 360) is open.

[0082] Next, implementation details of the current sensing module 350 in the embodiment of the present application are provided.

[0083] Current sensing block

[0084] Figure 4 3 is a diagram illustrating relevant details of the current sensing module in an embodiment of the present application. For the sake of brevity, only the portion for sensing the inductor current in the LS interval (i.e., the "second interval" / when the LS switch is turned on) is shown. The sensing of the inductor current in the HS interval (i.e., the "first interval" / when the HS switch is turned on) by the amplifier 450 (described below) can be implemented in a known manner. In an embodiment of the present application, the current sensing module 350 (more specifically, the amplifier 450) is implemented to measure the inductor current during the first interval and the second interval, and generate sensed current information based on this.

[0085] However, in other embodiments, the current sensing module 350 may be implemented to employ measurement / sensing of the inductor current whenever the LS switch 330 is on (the "second interval" described above), and to use a simulated value (or estimate rather than measurement) of the inductor current whenever the HS switch 320 is on (the "first interval" described above). This "simulation" is typically employed when the duration of the PWM on-state is very short. Figure 4 All switch control signals in can be generated in a known manner by appropriate circuits (not shown).

[0086] The current sensing module 350 is shown to include the circuit 40 and transistors 420 and 421, where the transistors are collectively referred to as an "output module". The transistors 420 and 421 are shown to be connected in series between the power supply voltage 410 (Vcc) and the ground terminal. The output node 351 of the current sensing module 350 is the junction of the transistors 420 and 421 connected in series. Figure 4 Also shown are switch 360, signal 314 and Figure 3A Pin CS(361).

[0087] The circuit 40 of the current sensing module 350 is shown to include an amplifier 450, switches 451, 480 and 485, and capacitors 430 and 435. Amplifier 450 is a fully differential amplifier (i.e., differential input and differential output). For clarity, LS switch 330 is also shown as part of the circuit 40, although it is not generally part of the current sensing module 350. The voltage across LS switch 330 (given by Figure 3A The inductor 325 is also shown as Figure 4 shown.

[0088] Transistor 420 is shown as a P-channel metal oxide semiconductor field effect transistor (PMOS), and transistor 421 is shown as an N-channel metal oxide semiconductor field effect transistor (NMOS). Supply voltage Vcc (401) may be provided by phase controller 210 or generated in VRM 110 in a known manner.

[0089] Amplifier 450 receives the voltage across LS switch 330 in the "second interval" (i.e., when the LS switch is closed) and provides an amplified output voltage as an output across terminals 458 and 459, so that amplifier 450 "drives" the sensed current Ics whenever amplifier 450 is operating. Figure 4 In the example of , amplifier 450 does not drive the output node during the blanking interval. By way of example only, amplifier 450 is a fully differential amplifier. Other amplifier types and topologies may also be used. In one embodiment, amplifier 450 is a fully differential amplifier with a gain determined by a feedback network (not shown, but using, for example, two pairs of resistors as known in the art) that will be used to operate amplifier 450 in a closed loop mode.

[0090] LS switch 330 is switched on by signal “en LS” ( Figure 3A 313) is turned on (and therefore conducting). Thus, by measuring / obtaining the voltage drop across LS switch 330 in the second interval of each PWM cycle, circuit 40 senses the current (IL) through inductor 325. However, other techniques for obtaining a measurement of the magnitude of the inductor current in the second interval may also be used.

[0091] Now for Figure 4 The "second interval" when the power stage 300 of the illustrated circuit is in an active state is described.

[0092] Second interval:

[0093] LS switch 330 is turned on by control input en LS (313) at the beginning of the second interval. The second interval itself begins with a "blanking interval" to allow transients in the output of amplifier 450 to settle and prevent the output of amplifier 450 from propagating to output node 351 during the transient. Control signal en- / LSBLK causes switches 480 and 485 to close from the end of the blanking interval to the end of the corresponding "second interval" and to open at each "first interval" and blanking interval. Control signals en- / LSBLK and en-LSBLNK are binary signals that are logical inversions of each other and are generated by circuitry (not shown) in current sensing module 350. Switch 450 is turned on when power stage 300 is activated and is turned off otherwise.

[0094] Thus, in the second interval, voltages 458 and 459 cause transistors 420 and 421 to source and sink corresponding currents, respectively, based on the specific magnitudes of voltages 458, 459 and the input voltage of amplifier 450 (the voltage drop across LS switch 330). Thus, the output module effectively operates as a voltage-to-current converter. As a result, the difference current (represented by Ics) between the current sourced by transistor 420 and the current sunk by transistor 421 flows out of node 351. Since switch 360 is closed when power stage 300 is activated, the sensed current (Ics) flows through pin / pad CS 361 and is therefore available to phase controller 210.

[0095] Furthermore, capacitors 430 and 435 will charge / discharge according to the voltages on paths 458 and 459, respectively, and at the end of the second interval, the voltages across the capacitors will represent (or correspond to) the magnitude of the current Ics sensed at the end of the second period, respectively. In other words, capacitors 430 and 435 "hold" "information" (in these voltages across capacitors 430 and 435) representing the current sensed at the end of the second interval. In embodiments where the inductor current in the HS interval is simulated rather than sensed, this "valley hold" capability of circuit 40 can be advantageously used to estimate / simulate the inductor current in the first interval.

[0096] Amplifier 450 may be used to measure the voltage across HS switch 320 in the first interval and generate a sense current Ics accordingly in any known manner. For example, the differential input of amplifier 450 may be connected across high-side switch 320 (rather than low-side switch 330) in the first interval in a known manner, and Ics may be generated by operations similar to those described above to represent the inductor current in the first interval. In such an embodiment, switches 480 and 485 will also be closed during the first interval, and capacitors 430 and 435 will not be used.

[0097] When the power stage 300 is activated, the sense current Ics generated as described above is provided to the phase controller 210 via the switch 360 and the CS pin / pad ( 361 ).

[0098] However, when the power stage 300 is in an inactive state, the amplifier 450 remains in a "reset" state, but remains fully powered. One or more other portions of the current sensing module 350 may also remain powered. In the reset state of the amplifier 450, the switch 451 is closed and the differential input voltage of the amplifier 450 is zero. However, the voltage across the output nodes 480 and 485 may not be zero because a DC offset voltage may exist across the nodes 480 and 485, causing the sensed current Ics to be non-zero, at least when the amplifier 450 drives the output node 351. To prevent this non-zero current from being applied to the CS pin (361), the switch 360 remains open when the power stage is in an inactive state.

[0099] As described above, the current sensing module 350 can be implemented in the same manner as Figure 4 In some embodiments, a switch (eg, 360) is also used to disconnect the output of the corresponding amplifier driving output node 351 to prevent a non-zero offset voltage / current at the output of the amplifier from appearing at the CS pin when the power stage is inactive.

[0100] Although in the above example, switch 360 is implemented to prevent the output offset voltage of amplifier 450 from causing a non-zero sense current Ics to flow into the CS pin of power stage 300 when power stage 300 is in an inactive state, in general, switch 360 can also be used to similarly prevent a non-zero sense current Ics from flowing into the CS pin due to other reasons / causes (when the power stage is in an inactive state), for example, based on the specific design of the current sensing module of the power stage.

[0101] Throughout the specification, references to "one embodiment," "an embodiment," or similar language mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0102] Although in Figure 1 , 2A , 3A and 4, although the terminals / nodes are shown as being directly connected to (i.e., "connected to") various other terminals, it should be understood that there may be additional components in the path (as appropriate to the particular environment) and therefore, these connections may be considered to be "electrically coupled" to the same connection terminal.

[0103] It should be understood that the specific types of transistors described above (e.g., NMOS, PMOS, etc.) are for illustration only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art by reading the disclosure provided herein. For example, an NMOS transistor can be replaced with a PMOS (P-type MOS) transistor while also swapping the connections to the power supply terminal and the ground terminal.

[0104] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of the transistor (although they provide a current path when turned on and an open path when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as the control terminal.

[0105] Although various embodiments of the present application have been described above, it should be understood that they are presented by way of example only and not limitation. Therefore, the breadth and scope of the present application should not be limited by any of the above embodiments, but should only be defined according to the following claims and their equivalents.

Claims

1. A power stage of a multi-phase switching converter, characterized in that: The power stage comprises: a high-side switch and a low-side switch for periodically driving an inductor in a first interval and a second interval, respectively, based on a control signal, wherein the inductor is coupled to a junction of the high-side switch and the low-side switch; a current sensing module, configured to generate information at an output node of the power stage, the information being used to indicate a magnitude of an inductor current flowing through the inductor; and a switch coupled between the output node and an output pin of the power stage; Wherein, when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in a powered state, and the switch is turned off to disconnect the output node from the output pin.

2. The power stage according to claim 1, characterized in that Wherein the component of the current sensing module is an amplifier.

3. The power stage according to claim 2, characterized in that The information is electric current; When the power stage is in an inactive state, the amplifier has a non-zero output offset voltage such that the current is non-zero.

4. The power stage according to claim 3, characterized in that When the power stage is in an active state, the switch is closed; The high-side switch and the low-side switch drive the inductor in the first interval and the second interval, respectively, only when the power stage is in an active state.

5. The power stage according to claim 4, characterized in that The control signal indicates whether the power stage is in an active state or an inactive state.

6. The power stage according to claim 5, characterized in that A high impedance (Hi-Z) state of the control signal indicates that the power stage is in an inactive state.

7. The power stage according to claim 4, characterized in that The power stage further comprises a gate driver for receiving the control signal, the gate driver for generating a corresponding output signal based on a logic level of the control signal to control the high-side switch and the low-side switch to be opened or closed correspondingly; Wherein, if the state of the control signal is the high impedance (Hi-Z) state, the gate driver generates an output signal having a value that turns off the switch.

8. The power stage according to claim 7, characterized in that The current sensing module comprises: a fully differential amplifier coupled to the differential input terminal to receive the voltage across the low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch, and a third switch; wherein a first current terminal of the first transistor is coupled to a first constant reference potential, a second current terminal of the first transistor is coupled to the output node, a first current terminal of the second transistor is coupled to a second constant reference potential, and a second current terminal of the second transistor is coupled to the output node; The first capacitor is coupled between the control terminal of the first transistor and the first constant reference potential, and the second capacitor is coupled between the control terminal of the second transistor and the second constant reference potential; The first switch is coupled between a first differential output terminal of the differential output pair of the fully differential amplifier and the control terminal of the first transistor, the second switch is coupled between a second differential output terminal of the differential output pair and the control terminal of the second transistor, and the third switch is coupled between the differential input terminals, wherein the first switch is closed when the power stage is in an inactive state, and either of the first switch and the second switch may be closed in the first interval and the second interval except for a blanking interval between the first interval and the second interval.

9. A multi-phase switching converter, characterized in that: The multi-phase switching converter comprises: Multiple power stages that work together to produce a regulated supply voltage on a power rail; a phase controller for controlling each of the plurality of power stages to generate the regulated supply voltage; Wherein a first power stage among the plurality of power stages comprises: a high-side switch and a low-side switch for periodically driving an inductor in a first interval and a second interval, respectively, based on a control signal, wherein the inductor is coupled to a junction of the high-side switch and the low-side switch; a current sensing module, configured to generate information at an output node of the power stage, the information being used to indicate a magnitude of an inductor current flowing through the inductor; a switch coupled between the output node and an output pin of the power stage, wherein when the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in an energized state and the switch is opened to disconnect the output node from the output pin.

10. The multi-phase switching converter according to claim 9, characterized in that: Wherein the component of the current sensing module is an amplifier.

11. The multi-phase switching converter according to claim 10, characterized in that: The information is electric current; Wherein, when the power stage is in an inactive state, the amplifier also has a non-zero output offset voltage so that the current is non-zero.

12. The multi-phase switching converter according to claim 11, characterized in that: When the power stage is in an active state, the switch is closed; The high-side switch and the low-side switch are used to drive the inductor in the first interval and the second interval, respectively, only when the power stage is in an active state.

13. The multi-phase switching converter according to claim 12, characterized in that: The control signal indicates whether the power stage is in an active state or an inactive state.

14. The multi-phase switching converter according to claim 13, characterized in that: A high impedance (Hi-Z) state of the control signal indicates that the power stage is in an inactive state.

15. The multi-phase switching converter according to claim 12, characterized in that: The multi-phase switching converter further comprises a gate driver for receiving the control signal, wherein the gate driver is used to generate a corresponding output signal based on the logic level of the control signal to control the high-side switch and the low-side switch to be opened or closed respectively; Wherein, if the state of the control signal is the high impedance (Hi-Z) state, the gate driver generates an output signal having a value that turns off the switch.

16. The multi-phase switching converter according to claim 15, characterized in that: The current sensing module comprises: a fully differential amplifier coupled to the differential input terminal to receive the voltage across the low-side switch; a first capacitor, a second capacitor, a first transistor, a second transistor; and a first switch, a second switch, and a third switch; wherein a first current terminal of the first transistor is coupled to a first constant reference potential, a second current terminal of the first transistor is coupled to the output node, a first current terminal of the second transistor is coupled to a second constant reference potential, and a second current terminal of the second transistor is coupled to the output node; The first capacitor is coupled between the control terminal of the first transistor and the first constant reference potential, and the second capacitor is coupled between the control terminal of the second transistor and the second constant reference potential; The first switch is coupled between a first differential output terminal of the differential output pair of the fully differential amplifier and the control terminal of the first transistor, the second switch is coupled between a second differential output terminal of the differential output pair and the control terminal of the second transistor, and the third switch is coupled between the differential input terminals, wherein the first switch is closed when the power stage is in an inactive state, and either of the first switch and the second switch may be closed in the first interval and the second interval except for a blanking interval between the first interval and the second interval.

17. A power stage of a multi-phase switching converter, characterized in that: The power stage comprises: a high-side switch and a low-side switch for periodically driving an inductor in a first interval and a second interval, respectively, based on a control signal, wherein the inductor is coupled to a junction of the high-side switch and the low-side switch; A current sensing module is used to generate information at an output node of the power stage, the information being used to represent the magnitude of the inductor current flowing through the inductor, wherein when the power stage is in an inactive state, no current flows from the output node to a phase controller of the multi-phase switching converter.

18. The power stage according to claim 17, characterized in that When the power stage is in an inactive state, a component of the current sensing module for driving the output node remains in an energized state; The power stage further includes a switch coupled between the output node and an output pin of the power stage, wherein the output pin is coupled to the phase controller; When the power stage is in an inactive state, the switch is opened to disconnect the output node from the output pin.

Images