Sampling circuit, analog-to-digital converter and receiver

Abstract

The invention provides a sampling circuit, an analog-to-digital converter and a receiver. The sampling circuit includes: a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; a first capacitor connected between the linearization circuit and a first output terminal for outputting the first sampled signal; and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampled signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0090671 filed on July 12, 2023, and Korean Application No. 10-2023-0119280 filed on September 7, 2023, in the Korean Intellectual Property Office, the disclosures of each of which are incorporated herein by reference in their entirety. Technical Field

[0003] The device and apparatus according to the present disclosure relate to a sampling circuit, and more particularly, to a sampling circuit included in an analog-to-digital converter and an operating method of the sampling circuit. Background Art

[0004] Analog-to-digital converters may be used in various applications, and in particular, analog-to-digital converters used in high-speed communications, signal analyzers, etc. may have high sampling rates. However, as the sampling speed increases, the analog-to-digital converter becomes more susceptible to process, temperature, and voltage. Summary of the invention

[0005] One aspect is to provide a linearization circuit and method of operating the same for improving the linearity between the input and output of a sampling circuit.

[0006] According to an aspect of one or more embodiments, there is provided a sampling circuit, comprising:

[0007] a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampling signal; and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampling signal.

[0008] According to another aspect of one or more embodiments, an analog-to-digital converter is provided, comprising: a sampling circuit configured to receive an input signal as an analog signal and output a sampling signal at regular time intervals; a front-end circuit configured to receive the sampling signal, process the sampling signal, and output the processed signal; and a back-end circuit configured to receive the processed signal and convert the processed signal into an output signal as a digital signal, and output the digital signal. The input signal includes a first input signal and a second input signal. The sampling circuit includes: a linearization circuit connected to a first input terminal for receiving the first input signal and a second input terminal for receiving the second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; a first capacitor connected between the linearization circuit and a first output terminal for outputting the first sampling signal; and a second capacitor connected between the linearization circuit and a second output terminal for outputting the second sampling signal.

[0009] According to another aspect of one or more embodiments, there is provided a receiver including a sampling circuit, the sampling circuit being configured to receive an input signal as an analog signal and output a sampling signal at regular time intervals. The sampling circuit includes: a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampling signal; and a second capacitor connected between the linearization circuit and a second output terminal for outputting a second sampling signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of an analog-to-digital converter (ADC) according to an embodiment;

[0012] Figure 2 is a block diagram illustrating one ADC among a plurality of ADCs included in a time-interleaved ADC (TI-ADC) according to an embodiment;

[0013] Figure 3A is a diagram showing an equivalent circuit of a sampling circuit according to an embodiment;

[0014] Figure 3B An equivalent circuit of a first stage sampling circuit according to an embodiment is shown;

[0015] Figure 3C An equivalent circuit of a second stage sampling circuit according to an embodiment is shown;

[0016] Figure 4 is a block diagram showing a sampling circuit according to an embodiment;

[0017] Figure 5 is an equivalent circuit diagram of a sampling circuit including a linearization circuit according to an embodiment;

[0018] Fig. 6A An equivalent circuit of a first stage sampling circuit according to an embodiment is shown;

[0019] Figure 6B is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment;

[0020] Figure 6C is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment;

[0021] Fig.6D is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment;

[0022] Fig. 6E is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment;

[0023] Fig. 6F is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment;

[0024] Fig. 7A An equivalent circuit of a second stage sampling circuit according to an embodiment is shown;

[0025] Figure 7B is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment;

[0026] Figure 7C is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment;

[0027] Fig.7D An equivalent circuit of a second stage sampling circuit according to an embodiment is shown;

[0028] Fig. 7E is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment;

[0029] Figure 7Fis a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment;

[0030] Figure 8 is a block diagram of a communication device according to an embodiment. DETAILED DESCRIPTION

[0031] In order to achieve a high sampling rate in an analog-to-digital converter, a time-interleaved analog-to-digital converter (ADC) may include multiple analog-to-digital converters that receive an input together, and the multiple analog-to-digital converters may sample the input at different time points. However, the multiple ADCs in the time-interleaved ADC are affected by the input common mode voltage.

[0032] Figure 1 is a block diagram of an analog-to-digital converter (ADC) according to an embodiment.

[0033] Reference Figure 1 , the ADC may be implemented as a time interleaved analog-to-digital converter (TI-ADC) 10. However, the embodiment is not limited thereto, and in some embodiments, the analog-to-digital converter may be implemented as any device that converts an analog signal into a digital signal.

[0034] According to an embodiment, the TI-ADC 10 may generate an output signal OUT as a digital signal by converting an input signal IN as an analog signal. In other words, the TI-ADC 10 may receive an input signal IN requiring digital conversion and generate an output signal OUT by converting the input signal IN.

[0035] like Figure 1 As shown, the TI-ADC 10 may include a plurality of ADCs 100. The plurality of ADCs 100 may receive an input signal IN in common (or in a time-division manner), and may each output a digital signal corresponding to the magnitude of the input signal IN. Each of the plurality of ADCs 100 may be synchronized to a clock signal, and the plurality of clock signals supplied to the ADCs 100 may have different phases from each other. Therefore, the TI-ADC 10 may have a high sampling rate.

[0036] although Figure 1 A single input signal IN is shown, but the embodiment is not limited thereto. In some embodiments, the TI-ADC 10 may receive two input signals including a first input signal INP and a second input signal INN, wherein the first input signal INP and the second input signal INN may be in the form of a differential signal pair (see, for example, the following description). FIG. 3A to FIG. 7F ).

[0037] According to the TI-ADC 10, linearity degradation due to leakage current can be reduced by using a sampling circuit that performs sampling without being affected by leakage current. A detailed description thereof will be given later with reference to the accompanying drawings.

[0038] Figure 2 is a block diagram illustrating one ADC among a plurality of ADCs included in a TI-ADC according to an embodiment.

[0039] Reference Figure 2 , the operation of any one ADC 100 among a plurality of ADCs included in the TI-ADC 10 will be described.

[0040] Reference Figure 2 , the ADC 100 may include a sampling circuit 110 , a front-end circuit 120 , and a back-end circuit 130 .

[0041] The sampling circuit 110 may receive an input signal IN as an analog signal and output a sampling signal SAM_IN at regular time intervals. The sampling circuit 110 may provide the sampling signal SAM_IN to the front-end circuit 120 .

[0042] For example, the clock signal CK may be supplied to the sampling circuit 110, and the input signal IN may be sampled at the rising edge of the clock signal CK. The interval between the rising edges adjacent to each other (i.e., time t) may become the sampling period of the sampling circuit 110, and the sampling frequency may be 1 / t. According to some embodiments, the input signal may be sampled at the falling edge of the clock signal CK.

[0043] The front-end circuit 120 may receive the sampling signal SAM_IN, process the sampling signal SAM_IN, and output the processed signal PRO_IN. Here, the front-end circuit 120 may include a circuit for processing the sampling signal SAM_IN, such as an amplifier, a filter, or a mixer. The front-end circuit 120 may provide the processed signal PRO_IN to the back-end circuit 130.

[0044] The back-end circuit 130 may receive the processed signal PRO_IN and output an output signal OUT as a digital signal by converting the processed signal PRO_IN.

[0045] Figure 3A is a diagram showing an equivalent circuit of a sampling circuit according to the embodiment. Figure 3B An equivalent circuit of a first stage sampling circuit according to an embodiment is shown. Figure 3C An equivalent circuit of a second stage sampling circuit according to an embodiment is shown.

[0046] Reference Figure 3A , the sampling circuit 110 a according to the embodiment will be described first.

[0047] The sampling circuit 110 a according to the embodiment may receive input signals INP and INN as a differential signal pair as input values, and output sampling signals SAM_INP and SAM_INN as output values.

[0048] The sampling circuit 110 a according to an embodiment may include a plurality of switches (eg, a first switch S31 , a second switch S32 , a third switch S33 , and a fourth switch S34 ) and a plurality of capacitors (eg, a first capacitor C31 and a second capacitor C32 ).

[0049] Reference Figure 3A , the first switch S31 may be connected between the terminal for applying the first input signal INP and the first node N31. The second switch S32 may be connected between the terminal for applying the first input signal INP and the second node N32. The third switch S33 may be connected between the terminal for applying the second input signal INN and the first node N31. The fourth switch S34 may be connected between the terminal for applying the second input signal INN and the second node N32. The first capacitor C31 may be connected between the terminal for outputting the first sampling signal SAM_INP and the first node N31. The second capacitor C32 may be connected between the terminal for outputting the second sampling signal SAM_INN and the second node N32.

[0050] In some embodiments, the first switch S31 and the fourth switch S34 may be turned on or off at the same timing according to the clock signal. In some embodiments, the second switch S32 and the third switch S33 may be turned on or off at the same timing according to the clock signal.

[0051] In some embodiments, the first switch S31 and the fourth switch S34 may be turned on or off complementarily with respect to the second switch S32 and the third switch S33 based on the clock signal. For example, when the first switch S31 and the fourth switch S34 are turned on, the second switch S32 and the third switch S33 may be turned off. Conversely, when the first switch S31 and the fourth switch S34 are turned off, the second switch S32 and the third switch S33 may be turned on.

[0052] Hereinafter, for the convenience of description, the situation where the first switch S31 and the fourth switch S34 are turned on and the second switch S32 and the third switch S33 are turned off will be referred to as the first stage, and the situation where the first switch S31 and the fourth switch S34 are turned off and the second switch S32 and the third switch S33 are turned on will be referred to as the second stage.

[0053] The first switch S31 to the fourth switch S34 may have an on-resistance when turned on, and an off-resistance when turned off. For example, each switch may be implemented by a transistor, wherein the on-resistance refers to the resistance value between the drain terminal and the source terminal when the transistor is turned on, and the off-resistance refers to the resistance value between the drain terminal and the source terminal when the transistor is turned off.

[0054] A description will be given on the assumption that all of the first to fourth switches S31 to S34 have the same on-resistance RON and the same off-resistance ROFF.

[0055] Figure 3B is an equivalent circuit diagram of the sampling circuit 110 a showing the first stage using the on-resistance and off-resistance of the switch. Figure 3C is an equivalent circuit diagram of the sampling circuit 110 a showing the second stage using the on-resistance and off-resistance of the switch.

[0056] Reference Figure 3B , the voltage level applied to the first node N31 in the first stage is The voltage level applied to the second node N32 in the first stage is Here, INP represents the voltage level of the first input signal INP, and INN represents the voltage level of the second input signal INN.

[0057] Since ROFF is significantly greater than RON, a voltage level applied to the first node N31 of the first stage may be approximately INP-INN (V), and a voltage level applied to the second node N32 of the first stage may be approximately INN-INP (V).

[0058] The first capacitor C31 may output a first sampling signal SAM_INP of the first stage based on a voltage level INP-INN (V) applied to a first node N31 of the first stage. The second capacitor C32 may output a second sampling signal SAM_INN of the first stage based on a voltage level INN-INP (V) applied to a second node N32 of the first stage. The first sampling signal SAM_INP and the second sampling signal SAM_INN may be a differential signal pair.

[0059] Reference Figure 3C , the voltage level applied to the first node N31 in the second stage may be The voltage level applied to the second node N32 in the second stage may be Here, INP represents the voltage level of the first input signal INP, and INN represents the voltage level of the second input signal INN.

[0060] Since ROFF is significantly greater than RON, a voltage level applied to the first node N31 of the second stage may be approximately INN-INP (V), and a voltage level applied to the second node N32 of the second stage may be approximately INP-INN (V).

[0061] The first capacitor C31 may output a first sampling signal SAM_INP of the second stage based on a voltage level applied to the first node N31 of the second stage. The second capacitor C32 may output a second sampling signal SAM_INN of the second stage based on a voltage level applied to the second node N32 of the second stage. The first sampling signal SAM_INP and the second sampling signal SAM_INN may be a differential signal pair.

[0062] In other words, when ROFF is significantly greater than RON, the sampling circuit 110a may output sampling signals SAM_INP and SAM_INN based on the voltages (e.g., INP-INN (V) and INN-INP (V)) applied to the first node N31 and the second node N32, thereby maintaining linearity between the magnitude of the input signal and the magnitude of the output signal.

[0063] However, due to the need for high temperature environment or high speed implementation, the size of ROFF may be more significantly reduced compared to RON. In this case, that is, when ROFF is not significantly greater than RON, the sampling circuit 110a needs to be based on the voltage applied to the first node N31 and the second node N32 (e.g., and The sampling signals SAM_INP and SAM_INN are output, and thus linearity between the magnitude of an input signal and the magnitude of an output signal may be degraded.

[0064] Even when RON is reduced due to a high temperature environment or a need for high-speed design, the sampling circuit 110 according to the embodiment can use a linearization circuit ( Figure 4 The linearization circuit 200 of FIG. 200 maintains the linearity between the magnitude of the input signal and the magnitude of the output signal. Figure 4 The sampling circuit 110b of the linearization circuit 200).

[0065] Figure 4 is a block diagram showing a sampling circuit according to an embodiment.

[0066] The sampling circuit 110 b according to the embodiment may receive input signals INP and INN as a differential signal pair as input values, and output sampling signals SAM_INP and SAM_INN as output values.

[0067] The sampling circuit 110b according to the embodiment may further include a linearization circuit 200. In other words, the sampling circuit 110b according to the embodiment may include a plurality of switches (e.g., a first switch S41, a second switch S42, a third switch S43, and a fourth switch S44), a plurality of capacitors (e.g., a first capacitor C41 and a second capacitor C42), and a linearization circuit 200.

[0068] Reference Figure 4 , the first switch S41 may be connected between a terminal for applying a first input signal INP and the linearization circuit 200. The second switch S42 may be connected between a terminal for applying the first input signal INP and the linearization circuit 200. The third switch S43 may be connected between a terminal for applying a second input signal INN and the linearization circuit 200. The fourth switch S44 may be connected between a terminal for applying a second input signal INN and the linearization circuit 200. The linearization circuit 200 may be connected to a terminal for applying the first input signal INP and a terminal for applying the second input signal INN. The first capacitor C41 may be connected between a terminal for outputting a first sampling signal SAM_INP and the linearization circuit 200. The second capacitor C42 may be connected between a terminal for outputting a second sampling signal SAM_INN and the linearization circuit 200.

[0069] Since the linearization circuit 200 is connected to a terminal for applying the first input signal INP and a terminal for applying the second input signal INN, linearity degradation due to leakage current can be reduced. A detailed description thereof will be given later with reference to the following drawings.

[0070] Figure 5 is an equivalent circuit diagram of a sampling circuit including a linearization circuit according to an embodiment.

[0071] Figure 5 It shows that according to Figure 4 FIG. 1 is a diagram of a sampling circuit 110 b of an embodiment of a linearization circuit 200 , and includes an equivalent circuit of the linearization circuit 200 .

[0072] The sampling circuit 110b may include first to fourth switches S41 to S44, a first capacitor C41 and a second capacitor C42, and a linearization circuit 200. The linearization circuit 200 may include a fifth switch S51, a sixth switch S52, a seventh switch S53, an eighth switch S54, a ninth switch S55, a tenth switch S56, an eleventh switch S57, and a twelfth switch S58.

[0073] Reference Figure 5 , a terminal for inputting a first input signal INP may be connected to a seventh node N57. A terminal for inputting a second input signal INN may be connected to an eighth node N58.

[0074] The first switch S41 may be connected between the seventh node N57 and the fifth node N55. The second switch S42 may be connected between the seventh node N57 and the third node N53. The third switch S43 may be connected between the eighth node N58 and the fourth node N54. The fourth switch S44 may be connected between the eighth node N58 and the sixth node N56. The fifth switch S51 may be connected between the seventh node N57 and the fourth node N54. The sixth switch S52 may be connected between the seventh node N57 and the sixth node N56. The seventh switch S53 may be connected between the eighth node N58 and the fifth node N55. The eighth switch S54 may be connected between the eighth node N58 and the third node N53. The ninth switch S55 may be connected between the fifth node N55 and the first node N51. The tenth switch S56 may be connected between the third node N53 and the second node N52. The eleventh switch S57 may be connected between the fourth node N54 and the first node N51. The twelfth switch S58 may be connected between the sixth node N56 and the second node N52.

[0075] The first capacitor C41 may be connected between the first node N51 and a terminal for outputting the first sampling signal SAM_INP. The second capacitor C42 may be connected between the second node N52 and a terminal for outputting the second sampling signal SAM_INN.

[0076] In some embodiments, the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55 and the twelfth switch S58 can be turned on or off at the same timing according to the clock signal. In some embodiments, the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56 and the eleventh switch S57 can be turned on or off at the same timing according to the clock signal.

[0077] In some embodiments, the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55, and the twelfth switch S58 may be complementarily turned on or off relative to the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56, and the eleventh switch S57 based on the clock signal. For example, when the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55, and the twelfth switch S58 are turned on, the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56, and the eleventh switch S57 may be turned off. Conversely, when the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55 and the twelfth switch S58 are turned off, the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56 and the eleventh switch S57 may be turned on.

[0078] Hereinafter, the case where the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55 and the twelfth switch S58 are turned on and the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56 and the eleventh switch S57 are turned off will be referred to as the first stage, and the case where the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55 and the twelfth switch S58 are turned off and the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56 and the eleventh switch S57 are turned on will be referred to as the second stage. For example, Figure 5}}}}}}} may be an equivalent circuit diagram of the sampling circuit 110 b performing the first stage of the sampling operation.

[0079] In some embodiments, the first to fourth switches S41 to S44 and the fifth to twelfth switches S51 to S58 may have an on-resistance when turned on and an off-resistance when turned off. For example, each switch may be implemented with a transistor, wherein the on-resistance refers to the resistance value between the drain terminal and the source terminal when the transistor is turned on, and the off-resistance refers to the resistance value between the drain terminal and the source terminal when the transistor is turned off.

[0080] A description will be given on the assumption that the first to fourth switches S41 to S44 and the fifth to twelfth switches S51 to S58 all have the same on-resistance.

[0081] Fig. 6A An equivalent circuit of a first stage sampling circuit according to an embodiment is shown. Figure 6B is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment. Figure 6C is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment. Figure 6C An equivalent circuit of a first stage sampling circuit according to an embodiment is shown. Fig.6D is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment. Fig. 6E is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment. Fig. 6F is a diagram for describing an equivalent circuit of a first-stage sampling circuit according to an embodiment.

[0082] Fig. 6A 1 is an equivalent circuit diagram of a sampling circuit 110 b in the first stage using the on-resistance and off-resistance of a switch. In the first stage, the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55, and the twelfth switch S58 may be turned on, and the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56, and the eleventh switch S57 may be turned off.

[0083] The first to fourth switches S41 to S44 and the fifth to twelfth switches S51 to S58 may have the same on-resistance RON, the second switch S42 and the third switch S43 may have a first off-resistance ROFF1, the tenth switch S56 and the eleventh switch S57 may have a second off-resistance ROFF2, and the sixth switch S52 and the seventh switch S53 may have a third off-resistance ROFF3.

[0084] The first capacitor C41 may output a first sampling signal SAM_INP of the first phase based on a voltage level applied to the first node N51 of the first phase. The second capacitor C42 may output a second sampling signal SAM_INN of the first phase based on a voltage level applied to the second node N52 of the first phase.

[0085] According to some embodiments, in the first stage, by making the voltage level applied to the first node N51 and the voltage level applied to the fourth node N54 the same as each other, the linearity between the voltage magnitudes of the input signals INP and INN and the voltage magnitude of the first sampling signal SAM_INP as the output signal can be improved. According to some embodiments, in the first stage, by making the voltage level applied to the third node N53 and the voltage level applied to the second node N52 the same as each other, the linearity between the voltage magnitudes of the input signals INP and INN and the voltage magnitude of the second sampling signal SAM_INN as the output signal can be improved.

[0086] Will refer to Fig. 6A , Figure 6B and Figure 6C The first node N51 will be described in detail. Fig.6D , Fig. 6E and Fig. 6F The second node N52 is described in detail.

[0087] Reference Fig. 6A , the path related to the voltage level applied to the first node N51 and the voltage level applied to the fourth node N54 is the path ABC interconnecting the terminal for applying the first input signal INP, the seventh node N57, the fifth node N55, the first node N51, the fourth node N54, the eighth node N58 and the terminal for applying the second input signal INN, and the path D interconnecting the seventh node N57 and the fourth node N54.

[0088] First, refer to Figure 6B , will describe the path ABC.

[0089] Reference Figure 6B , path ABC may include a path A interconnecting a terminal for applying a first input signal INP, a seventh node N57, a first switch S41 having an on-resistance RON, a fifth node N55, a ninth switch S55 having an on-resistance RON, and a first node N51; a path B interconnecting the first node N51 and an eleventh switch S57 having a second off-resistance ROFF2; and a path C interconnecting the eleventh switch S57 having a second off-resistance ROFF2, a fourth node N54, a third switch S43 having a first off-resistance ROFF1, and a terminal for applying a second input signal INN.

[0090] When the path D is not considered, the voltage level applied to the first node N51 may be Here, INP represents the voltage level of the first input signal INP, INN represents the voltage level of the second input signal INN, ROFF2 represents the off resistance value of the eleventh switch S57, ROFF1 represents the off resistance value of the third switch S43, and RON represents the on resistance values ​​of the first switch S41 and the ninth switch S55.

[0091] In other words, the first capacitor C41 may be based on the voltage level applied to the first node N51 in the first stage. The first sampling signal SAM_INP of the first stage is output.

[0092] Reference Figure 6C , showing a path ABC and a path D. The path D may be a path interconnecting a terminal for applying the first input signal INP, a seventh node N57, a fifth switch S51 having an on-resistance RON, and a fourth node N54.

[0093] Since ROFF2 is significantly greater than RON, the fifth switch S51 having the on-resistance RON may be used as a short-circuit switch to equalize the voltage levels applied to both ends of the eleventh switch S57. In other words, as the voltage levels applied to both ends of the eleventh switch S57 become the same as each other, the second off-resistance ROFF2, which is the off-resistance of the eleventh switch S57, may become very large.

[0094] As the second off resistance ROFF2 of the eleventh switch S57 becomes very large, the voltage level applied to the first node N51 of the first stage

[0095] It can be approximated as INP-INN(V).

[0096] In other words, the path D is a new leakage path of the leakage current, and even when the on-resistance RON of the switch becomes small, the second off-resistance ROFF2 of the eleventh switch S57 can become very large due to the fifth switch S51 as a short-circuit switch.

[0097] Therefore, regardless of the on-resistance RON of the switch, the first capacitor C41 may output the first sampling signal SAM_INP of the first stage based on the voltage level INP-INN (V) applied to the first node N51 of the first stage.

[0098] Reference Fig.6D , the paths related to the voltage level applied to the second node N52 and the voltage level applied to the third node N53 are the path EFG interconnecting the eighth node N58, the sixth node N56, the second node N52, the third node N53 and the seventh node N57, and the path H interconnecting the eighth node N58 and the third node N53.

[0099] First, refer to Fig. 6E , the path EFG will be described.

[0100] Reference Fig. 6E , the path EFG may include a path E interconnecting a terminal for applying the second input signal INN, an eighth node N58, a fourth switch S44 having an on-resistance RON, a sixth node N56, a twelfth switch S58 having an on-resistance RON, and a second node N52, a path F interconnecting the second node N52 and a tenth switch S56 having a second off-resistance ROFF2, and a path G interconnecting the tenth switch S56 having a second off-resistance ROFF2, a third node N53, the second switch S42 having a first off-resistance ROFF1, and a terminal for applying the first input signal INP.

[0101] When the path H is not considered, the voltage level applied to the second node N52 may be

[0102] Here, INP represents the voltage level of the first input signal INP, INN represents the voltage level of the second input signal INN, ROFF2 represents the off resistance value of the tenth switch S56, ROFF1 represents the off resistance value of the second switch S42, and RON represents the on resistance values ​​of the fourth switch S44 and the twelfth switch S58.

[0103] The second capacitor C42 may be based on the voltage level applied to the second node N52 of the first stage. The second sampling signal SAM_INN of the first stage is output.

[0104] Reference Fig. 6F , showing a path EFG and a path H. The path H may interconnect a terminal for applying the second input signal INN, an eighth node N58, an eighth switch S54 having an on-resistance RON, and the third node N53.

[0105] Since ROFF2 is significantly greater than RON, the eighth switch S54 having the on-resistance RON can be used as a short-circuit switch to equalize the voltage levels applied to both ends of the tenth switch S56. In other words, as the voltage levels applied to both ends of the tenth switch S56 become the same as each other, the second off-resistance ROFF2 as the off-resistance of the tenth switch S56 can become very large.

[0106] As the second off resistance ROFF2 of the tenth switch S56 becomes very large, the voltage level applied to the second node N52 of the first stage

[0107] It can be approximated as INN-INP(V).

[0108] In other words, the path H is a new leakage path of the leakage current, and even when the on-resistance RON of the switch becomes small, the second off-resistance ROFF2 of the tenth switch S56 can become very large due to the eighth switch S54 as a short-circuit switch.

[0109] Therefore, regardless of the on-resistance RON of the switch, the second capacitor C42 may output the second sampling signal SAM_INN of the first stage based on the voltage level INN-INP (V) applied to the second node N52 of the first stage.

[0110] Therefore, in the first stage, even when the on-resistance RON of the switch has become smaller due to the high temperature environment or the need for high-speed design, the sampling circuit 110 according to the embodiment can also use the linearization circuit ( Figure 4 A linearization circuit 200) is used to maintain linearity.

[0111] Fig. 7AAn equivalent circuit of a second stage sampling circuit according to an embodiment is shown. Figure 7B is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment. Figure 7C is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment. Fig.7D An equivalent circuit of a second stage sampling circuit according to an embodiment is shown. Fig. 7E is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment. Figure 7F is a diagram for describing an equivalent circuit of a second-stage sampling circuit according to an embodiment.

[0112] Fig. 7A 1 is an equivalent circuit diagram of the sampling circuit 110 b in the second stage using the on-resistance and off-resistance of the switch. In the second stage, the first switch S41, the fourth switch S44, the fifth switch S51, the eighth switch S54, the ninth switch S55 and the twelfth switch S58 may be turned off, and the second switch S42, the third switch S43, the sixth switch S52, the seventh switch S53, the tenth switch S56 and the eleventh switch S57 may be turned on.

[0113] The switches S41 to S44 and S51 to S58 may have the same on-resistance RON, the first switch S41 and the fourth switch S44 may have a first off-resistance ROFF1, the ninth switch S55 and the twelfth switch S58 may have a second off-resistance ROFF2, and the fifth switch S51 and the eighth switch S54 may have a third off-resistance ROFF3.

[0114] In the second phase, the first capacitor C41 may output a first sampling signal SAM_INP based on a voltage level applied to the first node N51. In the second phase, the second capacitor C42 may output a second sampling signal SAM_INN of the second phase based on a voltage level applied to the second node N52.

[0115] According to some embodiments, in the second stage, by making the voltage level applied to the first node N51 and the voltage level applied to the fifth node N55 the same as each other, the linearity between the voltage magnitude of the input signals INP and INN and the voltage magnitude of the first sampling signal SAM_INP as the output signal can be improved. According to some embodiments, by making the voltage level applied to the second node N52 and the voltage level applied to the sixth node N56 the same as each other, the linearity between the voltage magnitude of the input signals INP and INN and the voltage magnitude of the second sampling signal SAM_INN as the output signal can be improved.

[0116] Will refer to Fig. 7A , Figure 7B and Figure 7C The first node N51 will be described in detail. Fig.7D , Fig. 7E and Figure 7F The second node N52 is described in detail.

[0117] Reference Fig. 7A , the path related to the voltage level applied to the first node N51 and the voltage level applied to the fifth node N55 is a path IJK interconnecting the terminal for applying the second input signal INN, the eighth node N58, the fourth node N54, the first node N51, the fifth node N55, the eighth node N58 and the terminal for applying the first input signal INP, and a path L interconnecting the eighth node N58 and the fifth node N55.

[0118] First, refer to Figure 7B , the path IJK will be described.

[0119] Reference Figure 7B , the path IJK may include a path I interconnecting a terminal for applying a second input signal INN, an eighth node N58, a third switch S43 having an on-resistance RON, a fourth node N54, an eleventh switch S57 having an on-resistance RON, and a first node N51, a path J interconnecting the first node N51 and a ninth switch S55 having a second off-resistance ROFF2, and a path K interconnecting the ninth switch S55 having a second off-resistance ROFF2, a fifth node N55, the first switch S41 having a first off-resistance ROFF1, and a terminal for applying a first input signal INP.

[0120] When the path L is not considered, the voltage level applied to the first node N51 may be

[0121] Here, INP represents the voltage level of the first input signal INP, INN represents the voltage level of the second input signal INN, ROFF2 represents the off resistance value of the ninth switch S55, ROFF1 represents the off resistance value of the first switch S41, and RON represents the on resistance values ​​of the third switch S43 and the eleventh switch S57.

[0122] In other words, the first capacitor C41 may be based on the voltage level applied to the first node N51 in the second stage. The first sampling signal SAM_INP of the second stage is output.

[0123] Reference Figure 7C , showing a path IJK and a path L. The path L may interconnect a terminal for applying the second input signal INN, an eighth node N58, a seventh switch S53 having an on-resistance RON, and a fifth node N55.

[0124] Since ROFF2 is significantly greater than RON, the seventh switch S53 having the on-resistance RON can be used as a short-circuit switch to equalize the voltage levels applied to both ends of the ninth switch S55. In other words, as the voltage levels applied to both ends of the ninth switch S55 become the same as each other, the second off-resistance ROFF2 as the off-resistance of the ninth switch S55 can become very large.

[0125] As the second off resistance ROFF2 of the ninth switch S55 becomes very large, the voltage level applied to the first node N51 in the second stage

[0126] It can be approximated as INN-INP(V).

[0127] In other words, the path L is a new leakage path of the leakage current, and even when the on-resistance RON of the switch becomes small, the second off-resistance ROFF2 of the ninth switch S55 can become very large due to the seventh switch S53 as a short-circuit switch.

[0128] Therefore, regardless of the on-resistance RON of the switch, the first capacitor C41 may output the first sampling signal SAM_INP of the second stage based on the voltage level INN-INP (V) applied to the first node N51 of the second stage.

[0129] Reference Fig.7D , the path related to the voltage level applied to the second node N52 and the voltage level applied to the sixth node N56 is the path MNO interconnecting the terminal for applying the first input signal INP, the seventh node N57, the third node N53, the second node N52, the sixth node N56 and the eighth node N58, and the path P interconnecting the seventh node N57 and the sixth node N56.

[0130] First, refer to Fig. 7E , the path MNO will be described.

[0131] Reference Fig. 7E , the path MNO may include a path M interconnecting a terminal for applying a first input signal INP, a seventh node N57, a second switch S42 having an on-resistance RON, a third node N53, and a tenth switch S56 having an on-resistance RON, a path N interconnecting the tenth switch S56 having an on-resistance RON and a second node N52, and a path O interconnecting the second node N52, a twelfth switch S58 having a second off-resistance ROFF2, a sixth node N56, a fourth switch S44 having a first off-resistance ROFF1, and a terminal for applying a second input signal INN.

[0132] When the path P is not considered, the voltage level applied to the second node N52 may be

[0133] Here, INP represents the voltage level of the first input signal INP, INN represents the voltage level of the second input signal INN, ROFF2 represents the off resistance value of the twelfth switch S58, ROFF1 represents the off resistance value of the fourth switch S44, and RON represents the on resistance value of the second switch S42 and the tenth switch S56.

[0134] The second capacitor C42 may be based on the voltage level applied to the second node N52 of the second stage. The second sampling signal SAM_INN of the second stage is outputted.

[0135] Reference Figure 7F , showing a path MNO and a path P. The path P may interconnect a terminal for applying the first input signal INP, a seventh node N57, a sixth switch S52 having an on-resistance RON, and a sixth node N56.

[0136] Since ROFF2 is significantly greater than RON, the sixth switch S52 having the on-resistance RON can be used as a short-circuit switch to equalize the voltage levels applied to both ends of the twelfth switch S58. In other words, as the voltage levels applied to both ends of the twelfth switch S58 become the same as each other, the second off-resistance ROFF2, which is the off-resistance of the twelfth switch S58, can become very large.

[0137] As the second off resistance ROFF2 of the twelfth switch S58 becomes very large, the voltage level applied to the second node N52 in the second stage It can be approximated as INP-INN(V).

[0138] In other words, the path P is a new leakage path of the leakage current, and even when the on-resistance RON of the switch becomes small, the second off-resistance ROFF2 of the twelfth switch S58 can become very large due to the sixth switch S52 as a short-circuit switch.

[0139] Therefore, regardless of the on-resistance RON of the switch, the second capacitor C42 may output the second sampling signal SAM_INN of the second stage based on the voltage level INP-INN (V) applied to the second node N52 of the second stage.

[0140] Therefore, in the second stage, even when the on-resistance RON of the switch has become smaller due to the high temperature environment or the need for high-speed design, the sampling circuit 110b according to the embodiment can use the linearization circuit ( Figure 4 A linearization circuit 200) is used to maintain linearity.

[0141] In the first stage of the sampling circuit 110 b according to the embodiment, the fifth switch S51 and the eighth switch S54 may be implemented as short switches, and in the second stage of the sampling circuit 110 b , the seventh switch S53 and the sixth switch S52 may be implemented as short switches.

[0142] Therefore, even when the on-resistance RON of the switch has become smaller due to a high temperature environment or the need for high-speed design, the linearity between the magnitude of the input signal and the magnitude of the output signal in the sampling circuit 110b can be maintained.

[0143] Figure 8 is a block diagram showing a communication device 1000 according to an embodiment.

[0144] According to some embodiments, the TI-ADC 10 may be used to process signals received by the communication device 1000 .

[0145] The communication device 1000 may refer to any device that communicates with another communication device through a communication channel CH. For example, in some embodiments, the communication device 1000 may be a portable device such as a laptop computer, a mobile phone, and a wearable device, or a component included in a portable device. In some embodiments, the communication device 1000 may be a fixed device such as a desktop computer, a server, and an information kiosk, or a component included in a fixed device. In some embodiments, the communication device 1000 may be used as a component of a transportation tool such as a car or a ship. According to some embodiments, the communication channel CH may include a wired channel, and the communication device 1000 may perform communication based on any wired communication (e.g., optical communication, Ethernet, peripheral component interconnect (PCI), high-speed PCI (PCIe), universal serial bus (USB), serial ATA (SATA), etc.). According to some embodiments, the communication channel CH may include a wireless channel, and the communication device 1000 may perform communication based on any wireless communication (e.g., wireless local area network (WLAN), Bluetooth, long-term evolution (LTE), fifth generation (5G), etc.).

[0146] like Figure 8 As shown, the communication device 1000 may include a transmitter 1220, a receiver 1240, and a processing circuit system 1260. When the communication channel CH includes a wireless channel, the communication device 1000 may further include at least one antenna. The at least one antenna may be connected to the transmitter 1220 and the receiver 1240. According to some embodiments, the transmitter 1220 and the receiver 1240 may be implemented as a single component and may be collectively referred to as a transceiver.

[0147] The transmitter 1220 may receive transmit data TXD from the processing circuit system 1260 and output a transmit signal TX to the communication channel CH based on the transmit data TXD. Figure 8As shown, the transmitter 1220 may include a transmission side front-end circuit 1220_1 and a digital-to-analog converter (DAC) 1220_2. The DAC 1220_2 may convert the transmission data TXD received from the processing circuit system 1260 into an analog signal, and the transmission side front-end circuit 1220_1 may generate a transmission signal TX by processing the analog signal. The transmission side front-end circuit 1220_1 may include a circuit for processing an analog signal, such as an amplifier, a filter, or a mixer.

[0148] The receiver 1240 may receive a receive signal RX from the communication channel CH and provide receive data RXD to the processing circuit system 1260 based on the receive signal RX. Figure 8 As shown, the receiver 1240 may include an ADC. The ADC may process the received signal RX and may include a circuit for processing the received signal RX, such as an amplifier, a filter, or a mixer.

[0149] The analog-to-digital converter may generate reception data RXD by converting a signal received from the sampling circuit described above. For high-speed communication, in some embodiments, the ADC may be a TI-ADC 10 including a plurality of sub-ADCs. According to some embodiments, the sampling circuit may include a switch implemented as a short-circuit switch, so that even when the on-resistance RON of the switch becomes small due to a high temperature environment or the need for high-speed design, the linearity between the magnitude of the output signal and the magnitude of the input signal may be maintained at the sampling circuit.

[0150] The processing circuit system 1260 may generate transmission data TXD based on information to be transmitted to another communication device through the communication channel CH in the transmission mode, and provide the transmission data TXD to the transmitter 1220. The processing circuit system 1260 may receive reception data RXD from the transmitter 1220 in the reception mode, and obtain information transmitted by another communication device through the communication channel CH by processing the reception data RXD. The processing circuit system 1260 may include programmable components, components providing fixed functions, and / or reconfigurable components.

[0151] Although various embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A sampling circuit, comprising: a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; a first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampling signal; as well as A second capacitor is connected between the linearization circuit and a second output terminal for outputting a second sampling signal.

2. The sampling circuit according to claim 1, in, The first switch is connected between the seventh node and the fifth node, The second switch is connected between the seventh node and the third node, The third switch is connected between the eighth node and the fourth node, The fourth switch is connected between the eighth node and the sixth node, the first input terminal is connected to the seventh node, the second input terminal is connected to the eighth node, The first capacitor is connected between the first node and the first output terminal, The second capacitor is connected between the second node and the second output terminal, and The linearization circuit comprises: a fifth switch connected between the seventh node and the fourth node; a sixth switch connected between the seventh node and the sixth node; a seventh switch connected between the eighth node and the fifth node; an eighth switch connected between the eighth node and the third node; a ninth switch connected between the fifth node and the first node; a tenth switch connected between the third node and the second node; an eleventh switch connected between the fourth node and the second node; and A twelfth switch is connected between the sixth node and the second node.

3. The sampling circuit according to claim 2, wherein: When the first switch, the fourth switch, the fifth switch, the eighth switch, the ninth switch, and the twelfth switch are turned on, the second switch, the third switch, the sixth switch, the seventh switch, the tenth switch, and the eleventh switch are configured to be turned off.

4. The sampling circuit according to claim 2, wherein: When the first switch, the fifth switch, and the ninth switch are turned on and the third switch and the eleventh switch are turned off, a voltage level at the first node and a voltage level at the fourth node are identical to each other.

5. The sampling circuit according to claim 2, wherein: When the fourth switch, the twelfth switch, and the eighth switch are turned on and the tenth switch and the second switch are turned off, a voltage level at the second node and a voltage level at the third node are identical to each other.

6. The sampling circuit according to claim 2, wherein: When the second switch, the third switch, the sixth switch, the seventh switch, the tenth switch, and the eleventh switch are turned on, the first switch, the fourth switch, the fifth switch, the eighth switch, the ninth switch, and the twelfth switch are configured to be turned off.

7. The sampling circuit according to claim 2, wherein: When the third switch, the seventh switch, and the eleventh switch are turned on and the first switch and the ninth switch are turned off, a voltage level at the first node and a voltage level at the fifth node are identical to each other.

8. The sampling circuit according to claim 2, wherein: When the second switch, the sixth switch, and the tenth switch are turned on and the twelfth switch and the fourth switch are turned off, a voltage level at the second node and a voltage level at the sixth node are identical to each other.

9. The sampling circuit according to claim 2, wherein: The first input signal and the second input signal form a differential signal pair.

10. An analog-to-digital converter, comprising: a sampling circuit configured to receive an input signal as an analog signal and output a sampling signal at regular time intervals; a front-end circuit configured to receive the sampled signal, process the sampled signal, and output a processed signal; as well as a back-end circuit configured to receive the processed signal and convert the processed signal into an output signal as a digital signal, and output the digital signal, The input signal includes a first input signal and a second input signal, and Wherein, the sampling circuit comprises: a linearization circuit connected to a first input terminal for receiving the first input signal and a second input terminal for receiving the second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; A first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampling signal; and A second capacitor is connected between the linearization circuit and a second output terminal for outputting a second sampling signal.

11. The analog-to-digital converter of claim 10, wherein: The first switch is connected between the seventh node and the fifth node, The second switch is connected between the seventh node and the third node, The third switch is connected between the eighth node and the fourth node, The fourth switch is connected between the eighth node and the sixth node, the first input terminal is connected to the seventh node, the second input terminal is connected to the eighth node, The first capacitor is connected between the first node and the first output terminal, The second capacitor is connected between the second node and the second output terminal, and The linearization circuit comprises: a fifth switch connected between the seventh node and the fourth node; a sixth switch connected between the seventh node and the sixth node; a seventh switch connected between the eighth node and the fifth node; an eighth switch connected between the eighth node and the third node; a ninth switch connected between the fifth node and the first node; a tenth switch connected between the third node and the second node; an eleventh switch connected between the fourth node and the second node; and A twelfth switch is connected between the sixth node and the second node.

12. The analog-to-digital converter according to claim 11, wherein: When the first switch, the fourth switch, the fifth switch, the eighth switch, the ninth switch, and the twelfth switch are turned on, the second switch, the third switch, the sixth switch, the seventh switch, the tenth switch, and the eleventh switch are configured to be turned off.

13. The analog-to-digital converter according to claim 11, wherein: When the first switch, the fifth switch, and the ninth switch are turned on and the third switch and the eleventh switch are turned off, a voltage level at the first node and a voltage level at the fourth node are identical to each other.

14. The analog-to-digital converter according to claim 11, wherein: When the fourth switch, the twelfth switch, and the eighth switch are turned on and the tenth switch and the second switch are turned off, a voltage level at the second node and a voltage level at the third node are identical to each other.

15. The analog-to-digital converter according to claim 11, wherein: When the second switch, the third switch, the sixth switch, the seventh switch, the tenth switch, and the eleventh switch are turned on, the first switch, the fourth switch, the fifth switch, the eighth switch, the ninth switch, and the twelfth switch are configured to be turned off.

16. The analog-to-digital converter according to claim 11, wherein: When the third switch, the seventh switch, and the eleventh switch are turned on and the first switch and the ninth switch are turned off, a voltage level at the first node and a voltage level at the fifth node are identical to each other.

17. The analog-to-digital converter according to claim 11, wherein: When the second switch, the sixth switch, and the tenth switch are turned on and the twelfth switch and the fourth switch are turned off, a voltage level at the second node and a voltage level at the sixth node are identical to each other.

18. The analog-to-digital converter according to claim 11, wherein: The first input signal and the second input signal form a differential signal pair.

19. A receiver comprising a sampling circuit configured to receive an input signal as an analog signal and output a sampling signal at regular time intervals, wherein: The sampling circuit comprises: a linearization circuit connected to a first input terminal for receiving a first input signal and a second input terminal for receiving a second input signal; a first switch connected between the first input terminal and the linearization circuit; a second switch connected between the first input terminal and the linearization circuit; a third switch connected between the second input terminal and the linearization circuit; a fourth switch connected between the second input terminal and the linearization circuit; A first capacitor connected between the linearization circuit and a first output terminal for outputting a first sampling signal; and A second capacitor is connected between the linearization circuit and a second output terminal for outputting a second sampling signal.

20. The receiver of claim 19, wherein: The first switch is connected between the seventh node and the fifth node, The second switch is connected between the seventh node and the third node, The third switch is connected between the eighth node and the fourth node, The fourth switch is connected between the eighth node and the sixth node, the first input terminal is connected to the seventh node, the second input terminal is connected to the eighth node, The first capacitor is connected between the first node and the first output terminal, The second capacitor is connected between the second node and the second output terminal, and The linearization circuit comprises: a fifth switch connected between the seventh node and the fourth node; a sixth switch connected between the seventh node and the sixth node; a seventh switch connected between the eighth node and the fifth node; an eighth switch connected between the eighth node and the third node; a ninth switch connected between the fifth node and the first node; a tenth switch connected between the third node and the second node; an eleventh switch connected between the fourth node and the second node; and A twelfth switch is connected between the sixth node and the second node.

Images