Analog-to-Digital Converter, Conversion Method, and Electronic Product

Abstract

The present invention provides an analog-to-digital converter, a conversion method and an electronic product, comprising: a differential analog-to-digital conversion module and a compensation module; the differential analog-to-digital conversion module eliminates sampling thermal noise based on a dual-sampling method and realizes analog-to-digital conversion of an input signal; the compensation module receives a compensation signal, and an output end thereof is connected to an input end of a preamplifier in the differential analog-to-digital conversion module, and compensates for a change in an input signal coupled to the input end of the preamplifier based on a differential method; wherein, the input signal and the compensation signal connected to the same input end of the preamplifier are differential signals. The analog-to-digital converter, the conversion method and the electronic product of the present invention adopt a sampling thermal noise elimination technology, and increase a signal bandwidth limited by an amplifier saturation problem by adopting a first-order approximation compensation module based on a differential circuit, and have the advantages of a small sampling capacitor, low noise and a large signal bandwidth.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an analog-to-digital converter, a conversion method and an electronic product. Background Art

[0002] Analog to Digital converter (ADC) plays a vital role in integrated circuits (IC). It is the key bridge between the analog world and the digital world. Common types of ADCs include: Successive Approximation Register (SAR ADC), Σ-Δ ADC, and Pipeline ADC. ADCs are increasingly required to achieve high precision. However, since the sampling thermal noise (kT / C noise) must meet the requirements of the signal-to-noise ratio (SNR), the sampling capacitor needs to be large enough in high-precision design, which also causes it to occupy most of the area and power consumption. At the same time, in the system design stage, an overly large sampling capacitor will also increase the power consumption and design complexity of the input signal driving circuit and the reference voltage driving circuit, which is no less difficult than ADC design.

[0003] In order to overcome the limitation of sampling thermal noise on sampling capacitors, the solution that has attracted much attention at present is to reduce the impact of sampling thermal noise on ADC performance through double sampling. This solution can effectively eliminate noise under low-frequency input signals. However, in the case of high-frequency input signals, the rapidly changing input signal will cause the amplifier output to saturate, which will greatly reduce the sampling thermal noise elimination effect and seriously reduce the linearity of the system.

[0004] Therefore, how to achieve high-quality sampling thermal noise elimination in both low-frequency input signals and high-frequency input signals has become one of the problems that technicians in this field need to solve urgently.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an analog-to-digital converter, a conversion method and an electronic product, which are used to solve the problems of poor sampling thermal noise elimination effect and impact on system linearity in the case of high-frequency input signals in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides an analog-to-digital converter, which at least includes:

[0008] A differential analog-to-digital conversion module and a compensation module;

[0009] The differential analog-to-digital conversion module eliminates sampling thermal noise based on the double-sampling method and realizes analog-to-digital conversion of the input signal;

[0010] The compensation module receives a compensation signal, and its output end is connected to the input end of the preamplifier in the differential analog-to-digital conversion module, and compensates for the change of the input signal coupled to the input end of the preamplifier based on the differential method;

[0011] Wherein, the input signal and the compensation signal connected to the same input end of the preamplifier are differential signals.

[0012] Optionally, the compensation module includes a first compensation unit and a second compensation unit, and both the first compensation unit and the second compensation unit include a differential circuit, a first switch, a second switch and a compensation capacitor;

[0013] The input end of the differential circuit receives the corresponding compensation signal, and the output end is connected to the lower plate of the compensation capacitor via the first switch; the upper plate of the compensation capacitor is connected to the corresponding input end of the preamplifier;

[0014] One end of the second switch is connected to the common-mode voltage, and the other end is connected to the lower plate of the compensation capacitor;

[0015] Wherein, the sampling timing of the first switch is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module, and the on-off state of the second switch is opposite to that of the first switch.

[0016] More optionally, the analog-to-digital converter satisfies:

[0017]

[0018] Wherein, Δt is the time difference of double sampling, R d is the value of the resistor in the differential circuit, C d is the value of the capacitor in the differential circuit, C R is the value of the compensation capacitor, C S is the value of the sampling capacitor.

[0019] More optionally, the differential analog-to-digital conversion module is of a SAR ADC structure.

[0020] More optionally, the differential analog-to-digital conversion module includes a third switch, a first switched-capacitor array, a fourth switch, a first noise cancellation capacitor, a fifth switch, a sixth switch, a second switched-capacitor array, a seventh switch, a second noise cancellation capacitor, an eighth switch, a preamplifier, a latch, and a SAR logic unit;

[0021] One end of the third switch is connected to the first input signal, and the other end is connected to the lower plates of the sampling capacitors in the first switched-capacitor array; the lower plates of the sampling capacitors in the first switched-capacitor array are also respectively connected to the positive-phase reference voltage and the negative-phase reference voltage through corresponding switches, and the upper plates are connected to the first input terminal of the preamplifier; one end of the fourth switch is connected to the common-mode voltage, and the other end is connected to the upper plates of the sampling capacitors in the first switched-capacitor array;

[0022] One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plates of the sampling capacitors in the second switched-capacitor array; the lower plates of the sampling capacitors in the second switched-capacitor array are also respectively connected to the positive-phase reference voltage and the negative-phase reference voltage through corresponding switches, and the upper plates are connected to the second input terminal of the preamplifier; one end of the seventh switch is connected to the common-mode voltage, and the other end is connected to the upper plates of the sampling capacitors in the second switched-capacitor array;

[0023] The first output terminal and the second output terminal of the preamplifier are respectively connected to the lower plates of the first noise cancellation capacitor and the second noise cancellation capacitor;

[0024] One end of the fifth switch is connected to the common-mode voltage, and the other end is connected to the upper plate of the first noise cancellation capacitor; one end of the eighth switch is connected to the common-mode voltage, and the other end is connected to the upper plate of the second noise cancellation capacitor;

[0025] The first input terminal and the second input terminal of the latch are respectively connected to the upper plates of the first noise cancellation capacitor and the second noise cancellation capacitor;

[0026] The SAR logic unit is connected to the output terminal of the latch and controls the first switched-capacitor array and each switch in the first switched-capacitor array to switch to the corresponding reference voltage based on the output signal of the latch.

[0027] More optionally, the differential analog-to-digital conversion module is a Pipe-SAR ADC structure.

[0028] More optionally, the differential analog-to-digital conversion module includes a third switch, a first switched-capacitor array, a fourth switch, a first noise cancellation capacitor, a fifth switch, a sixth switch, a second switched-capacitor array, a seventh switch, a second noise cancellation capacitor, an eighth switch, a first feedback capacitor, a second feedback capacitor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a preamplifier, a comparator, a SAR logic unit, a post-amplifier, and at least one stage of SAR ADC unit;

[0029] One end of the third switch is connected to the first input signal, and the other end is connected to the lower plates of the sampling capacitors in the first switched-capacitor array; the lower plates of the sampling capacitors in the first switched-capacitor array are also respectively connected to the positive-phase reference voltage and the negative-phase reference voltage through corresponding switches, and the upper plates are connected to the input end of the preamplifier; one end of the fourth switch is connected to the common-mode voltage, and the other end is connected to the upper plates of the sampling capacitors in the first switched-capacitor array;

[0030] One end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plates of the sampling capacitors in the second switched-capacitor array; the lower plates of the sampling capacitors in the second switched-capacitor array are also respectively connected to the positive-phase reference voltage and the negative-phase reference voltage through corresponding switches, and the upper plates are connected to the second input end of the preamplifier; one end of the seventh switch is connected to the common-mode voltage, and the other end is connected to the upper plates of the sampling capacitors in the second switched-capacitor array;

[0031] The first output end and the second output end of the preamplifier are respectively connected to the lower plates of the first noise cancellation capacitor and the second noise cancellation capacitor;

[0032] One end of the fifth switch is connected to the common-mode voltage, and the other end is connected to the upper plate of the first noise cancellation capacitor; one end of the eighth switch is connected to the common-mode voltage, and the other end is connected to the upper plate of the second noise cancellation capacitor;

[0033] The first input end and the second input end of the comparator are respectively connected to the upper plates of the first noise cancellation capacitor and the second noise cancellation capacitor;

[0034] The SAR logic unit is connected to the output end of the comparator, and controls the switches in the first switched-capacitor array and the second switched-capacitor array to switch to the corresponding reference voltages based on the output signal of the SAR logic unit;

[0035] The first input end and the second input end of the post-amplifier are respectively connected to the upper plates of the first noise cancellation capacitor and the second noise cancellation capacitor, and form a loop amplifier with the preamplifier;

[0036] The lower plate of the first feedback capacitor is connected to the common-mode voltage via the ninth switch and also connected to the first output terminal of the post-stage amplifier via the tenth switch; the upper plate of the first feedback capacitor is connected to the output terminal of the first switched-capacitor array; the lower plate of the second feedback capacitor is connected to the common-mode voltage via the eleventh switch and also connected to the second output terminal of the post-stage amplifier via the twelfth switch; the upper plate of the second feedback capacitor is connected to the output terminal of the second switched-capacitor array;

[0037] Each stage of the SAR ADC units is cascaded in sequence at the output terminal of the post-stage amplifier.

[0038] More specifically, the differential analog-to-digital conversion module further includes a thirteenth switch, a fourteenth switch, a first resistor, and a second resistor; the first resistor is connected between the fifth switch and the common-mode voltage, and the thirteenth switch is connected in parallel across the first resistor; the second resistor is connected between the eighth switch and the common-mode voltage, and the fourteenth switch is connected in parallel across the second resistor.

[0039] To achieve the above object and other related objects, the present invention further provides an analog-to-digital conversion method, which is implemented based on the above analog-to-digital converter, and the analog-to-digital conversion method at least includes:

[0040] At a first sampling moment, an input signal and sampling thermal noise are collected at the input terminal of a pre-amplifier; at the same time, a compensation voltage is obtained by differentiating a compensation signal, and the compensation voltage is loaded at the input terminal of the pre-amplifier to compensate for a voltage change of the input signal coupled to the input terminal of the pre-amplifier;

[0041] At a second sampling moment, the signal that has been compensated and pre-amplified in sequence is sampled and stored;

[0042] In a quantization stage, the sampling thermal noise stored at the output terminal of the pre-amplifier and the sampling thermal noise sampled at the input terminal of the pre-amplifier cancel each other out; based on successive approximation logic, the potential of the lower plate of the sampling capacitor is adjusted, thereby realizing analog-to-digital conversion.

[0043] To achieve the above object and other related objects, the present invention further provides an electronic product, which at least includes: the above analog-to-digital converter.

[0044] As described above, the analog-to-digital converter, conversion method, and electronic product of the present invention have the following beneficial effects:

[0045] 1. The analog-to-digital converter, conversion method, and electronic product of the present invention cancel the voltage change coupled by the input signal through the compensation module, thereby reducing the signal change amount at the input node of the preamplifier, avoiding the saturation of the preamplifier output, greatly improving the spurious-free dynamic range of the analog-to-digital converter, and further enhancing the stability and reliability of the analog-to-digital converter under high-frequency signals.

[0046] 2. The analog-to-digital converter, conversion method, and electronic product of the present invention achieve the elimination of sampling thermal noise based on the double-sampling technology, effectively reducing the equivalent input noise, and thereby reducing the area of the sampling capacitor; at the same time, the noise of the compensation module can also be eliminated, further reducing the area and power consumption of the compensation module.

[0047] 3. The analog-to-digital converter, conversion method, and electronic product of the present invention have significant advantages in improving the analog-to-digital conversion performance and broadening the signal bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It shows a schematic structural diagram of an analog-to-digital converter of the present invention.

[0049] Figure 2 It shows a schematic structural diagram of a compensation unit of the present invention.

[0050] Figure 3 It shows another schematic structural diagram of an analog-to-digital converter of the present invention.

[0051] Figure 4 It shows Figure 1 and Figure 3 a schematic working timing diagram of the analog-to-digital converter.

[0052] Figure 5 It shows still another schematic structural diagram of an analog-to-digital converter of the present invention.

[0053] Figure 6 It shows Figure 5 a schematic working timing diagram of the analog-to-digital converter.

[0054] Figure 7 It shows a schematic diagram of the principle of the output saturation of the preamplifier of the present invention at high-frequency signals.

[0055] Figure 8 It shows a schematic diagram of the principle of avoiding the output saturation of the preamplifier of the present invention at high-frequency signals.

[0056] Figure 9 It shows a schematic simulation diagram of the spurious-free dynamic range of the analog-to-digital converter of the present invention and the analog-to-digital converter without compensation at different input signal frequencies.

[0057] Figure 10It shows a schematic diagram of the simulation results of the equivalent input noises in the analog-to-digital converter of the present invention.

[0058] Description of Component Labels

[0059] 1 Analog-to-digital converter

[0060] 11 Differential analog-to-digital conversion module

[0061] 111a, 111b First and second switched-capacitor arrays

[0062] 112 Preamplifier

[0063] 113 Latch

[0064] 114 SAR logic unit

[0065] 115 Comparator

[0066] 116 Post-amplifier

[0067] 117 SAR ADC unit

[0068] 12a, 12b First and second compensation units

[0069] 121 Differential circuit

[0070] 121a Operational amplifier Detailed implementation manners

[0071] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] Please refer to Figures 1 to 10 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0073] Such as Figure 1 and Figure 8As shown, the present invention provides an analog-to-digital converter 1, which includes a differential analog-to-digital conversion module 11 and a compensation module. The differential analog-to-digital conversion module 11 eliminates sampling thermal noise based on a double-sampling method and realizes analog-to-digital conversion of an input signal; the compensation module receives a compensation signal, and its output end is connected to the input end of a preamplifier in the differential analog-to-digital conversion module 11, and compensates for the change of the input signal coupled to the input end of the preamplifier based on a differential method; wherein, the input signal and the compensation signal connected to the same input end of the preamplifier are differential signals. In this example, the first input signal is V ip , and its corresponding first compensation signal is V in ; the second input signal is V in , and its corresponding second compensation signal is V ip .

[0074] As Figure 2 shown, the compensation module includes a first compensation unit 12a and a second compensation unit 12b. In this embodiment, both the first compensation unit 12a and the second compensation unit 12b include a differential circuit 121, a first switch K1, a second switch K2, and a compensation capacitor C R .

[0075] Specifically, the input end of the differential circuit 121 receives the corresponding compensation signal, and its output end is connected to the lower plate of the compensation capacitor C R via the first switch K1. The upper plate of the compensation capacitor C R serves as the output end of the corresponding compensation unit (connected to the input end of the preamplifier); as Figure 4 shown, the first switch K1 is controlled by a first control signal . The sampling timing of the first switch K1 is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module 11. As Figure 2 shown, as an example, the differential circuit 121 includes an operational amplifier 121a, a capacitor C d (input capacitor) and a resistor R d (feedback resistor). The lower plate of the capacitor C d serves as the input end of the differential circuit 121, the upper plate of the capacitor C d is connected to the input end of the operational amplifier 121a, the output end of the operational amplifier 121a serves as the output end of the differential circuit 121, and the resistor R d is connected between the input end (the upper plate of the capacitor C d ) and the output end of the operational amplifier 121a; in actual use, any circuit structure that can achieve differentiation is applicable to the present invention and is not limited to this embodiment.

[0076] Specifically, one end of the second switch K2 is connected to the common-mode voltage V CM , and the other end is connected to the lower plate of the compensation capacitor C R . AsFigure 3 As shown, the second switch K2 is controlled by the inverse signal of the first control signal That is, the on / off state of the second switch K2 is opposite to that of the first switch K1 As an implementation of the present invention, the differential analog-to-digital conversion module 11 is of SAR ADC structure. As

[0077] shown, by way of example, the differential analog-to-digital conversion module 11 includes a third switch K3, a first switched-capacitor array 111a, a fourth switch K4, a preamplifier 112, a first noise cancellation capacitor C Figure 1 shown, by way of example, the differential analog-to-digital conversion module 11 includes a third switch K3, a first switched-capacitor array 111a, a fourth switch K4, a preamplifier 112, a first noise cancellation capacitor C NCa , a fifth switch K5, a sixth switch K6, a second switched-capacitor array 111b, a seventh switch K7, a second noise cancellation capacitor C NCb , an eighth switch K8, a latch 113 and a SAR logic unit 114

[0078] Specifically, one end of the third switch K3 is connected to the first input signal V ip , and the other end is connected to the lower plates of the sampling capacitors Cs in the first switched-capacitor array 111a; the third switch K3 is controlled by the second control signal The lower plates of the sampling capacitors Cs in the first switched-capacitor array 111a are also respectively connected to the positive-phase reference voltage V RP and the anti-phase reference voltage V RN through corresponding switches. The upper plates of the sampling capacitors Cs in the first switched-capacitor array 111a are connected to the first input terminal of the preamplifier 112. One end of the fourth switch K4 is connected to the common-mode voltage V CM , and the other end is connected to the upper plates of the sampling capacitors Cs in the first switched-capacitor array 111a; the fourth switch K4 is controlled by the first control signal The lower plate of the first noise cancellation capacitor C NCa is connected to the first output terminal of the preamplifier 112, and the upper plate is connected to the first input terminal of the latch 113. One end of the fifth switch K5 is connected to the common-mode voltage V CM , and the other end is connected to the upper plate of the first noise cancellation capacitor C NCa ; the fifth switch K5 is controlled by the second control signal The sixth switch K6, the second switched-capacitor array 111b, the seventh switch K7, the second noise cancellation capacitor C NCband the eighth switch K8 form another branch in the differential path, and the connection relationship will not be elaborated here one by one. The preamplifier 112 and the latch 113 form a comparator. In this embodiment, the preamplifier 112 is set as a high-bandwidth and low-noise amplifier. The SAR logic unit 114 is connected to the output end of the latch 113, and controls each switch in the first switched-capacitor array 111a and the second switched-capacitor array 111b to switch to the corresponding reference voltage (the positive-phase reference voltage V RP or the inverted-phase reference voltage V RN ) to achieve successive approximation analog-to-digital conversion.

[0079] Furthermore, as shown in Figure 3 , the differential analog-to-digital conversion module 11 further includes a thirteenth switch K13, a fourteenth switch K14, a first resistor R1, and a second resistor R2. The first resistor R1 is connected between the fifth switch K5 and the common-mode voltage V CM . The thirteenth switch K13 is connected in parallel across the first resistor R1. The thirteenth switch K13 is controlled by the fourth control signal and is used to adjust the potential of the upper plate of the first noise cancellation capacitor C NCa . After the sampling capacitor finishes sampling and before the noise cancellation capacitor samples, the potential of the upper plate of the first noise cancellation capacitor C NCa is raised from the common-mode voltage V CM to the sum of the common-mode voltage and the voltage drop across the first resistor. Similarly, the connection relationship and function of the second resistor R2 and the fourteenth switch K14 are similar and will not be elaborated here one by one.

[0080] The control timing of the differential analog-to-digital conversion module 11( Figure 1 and Figure 3 ) in this implementation is as shown in Figure 4 . Any SAR ADC structure that eliminates sampling thermal noise based on the dual-sampling method is applicable to the present invention and is not limited to this embodiment. The differential analog-to-digital conversion module 11 of the present invention based on the SAR ADC structure embeds a noise cancellation capacitor at the output end of the preamplifier 112, cooperates with the original sampling capacitor to achieve dual sampling, collects sampling thermal noise, and cancels this noise during the successive approximation quantization process. Therefore, this analog-to-digital converter can achieve a high signal-to-noise and distortion ratio (SNDR).

[0081] As another implementation of the present invention, in order to improve the quantization speed, the differential analog-to-digital conversion module 11 is set as a Pipe-SAR ADC structure. As shown in Figure 5 , by way of example, the differential analog-to-digital conversion module 11 includes a third switch K3, a first switched-capacitor array 111a, a fourth switch K4, a preamplifier 112, a first noise cancellation capacitor CNCa , the fifth switch K5, comparator 115, SAR logic unit 114, post - amplifier 116, first feedback capacitor C FBa , the sixth switch K6, second switched - capacitor array 111b, seventh switch K7, second noise - cancellation capacitor C NCbb , the eighth switch K8, second feedback capacitor C FBb , the ninth switch K9, tenth switch K10, eleventh switch K11, twelfth switch K12 and at least one - stage SAR ADC unit 117; wherein, the third switch K3, sixth switch K6, first switched - capacitor array 111a, second switched - capacitor array 111b, fourth switch K4, seventh switch K7, pre - amplifier 112, first noise - cancellation capacitor C NCa , second noise - cancellation capacitor C NCb , the fifth switch K5, eighth switch K8 and Figure 1 have the same corresponding connection relationship, which will not be elaborated one by one here. The first input terminal and the second input terminal of the post - amplifier 116 are respectively connected to the upper plates of the first noise - cancellation capacitor C NCa and the second noise - cancellation capacitor C NCb , and form a loop amplifier with the pre - amplifier 112 (the output is inverted with respect to the input, which can be achieved by adjusting the output phases of the pre - amplifier 112 and / or the post - amplifier 116). The first input terminal and the second input terminal of the comparator 115 are respectively connected to the upper plates of the first noise - cancellation capacitor C NCa and the second noise - cancellation capacitor C NCb , and input the comparison result into the SAR logic unit 114 to generate the switching control signals for the first switched - capacitor array 111a and the second switched - capacitor array 111b. The lower plate of the first feedback capacitor C FBa is connected to the common - mode voltage V CM via the ninth switch K9, and the ninth switch K9 is controlled by the second control signal The lower plate of the first feedback capacitor C FBa is also connected to the first output terminal of the post - amplifier 116 via the tenth switch K10, and the tenth switch K10 is controlled by the third control signal The upper plate of the first feedback capacitor C FBa is connected to the output terminal of the first switched - capacitor array 111a. The second feedback capacitor C FBb , eleventh switch K11 and twelfth switch K12 are connected between the second input terminal of the pre - amplifier 112 and the second output terminal of the post - amplifier 116 in a similar connection relationship, which will not be elaborated one by one here. Each stage of SAR ADC unit 117 is cascaded in sequence at the output terminal of the post - amplifier 116; in this example, only one - stage SAR ADC unit 117 is provided as the second - stage SAR ADC.

[0082] Similarly, further, the differential analog-to-digital conversion module 11 of this implementation manner may further include a thirteenth switch K13, a fourteenth switch K14, a first resistor R1, and a second resistor R2. The connection relationship and functions are the same as those of Figure 3 , and will not be elaborated here one by one.

[0083] The control timing of the differential analog-to-digital conversion module 11 of this implementation manner is as shown in Figure 6 . The differential analog-to-digital conversion module 11 of this example can achieve a high signal-to-noise distortion ratio and a high sampling rate.

[0084] As shown in Figures 1 to 6 , at the sampling moment t1, the control sampling capacitor Cs samples based on the lower plate. On this basis, an additional sampling moment t2 is added to control the noise cancellation capacitor to sample; there is a delay Δt between the sampling moment t1 and the sampling moment t2. The sampling thermal noise at the sampling moment t1 is regarded as dynamic offset, and self-zeroing is performed through the dual sampling of the sampling capacitor Cs and the noise cancellation capacitor to cancel the influence of the sampling thermal noise. For the sake of simplicity, taking the single side of the differential structure of Figure 5 as an example for illustration, as shown in Figure 7 , in the initial state, the third switch K3, the fourth switch K4, and the fifth switch K5 are all in the closed state under the control of the first control signal and the second control signal ; at the sampling moment t1, the first control signal controls the fourth switch K4 to open, and at this time the sampling thermal noise is fixed. For an analog-to-digital converter operating continuously, this noise can be regarded as the random noise of the system, but for the current sampling and quantization process, this noise can also be regarded as dynamic offset. In this example, in order to increase energy efficiency, the amplifier in the SAR ADC comparator is reused as a preamplifier. After Δt (sampling moment t2), the sampling thermal noise is regarded as the offset of the preamplifier, and the influence of this noise on the performance of the analog-to-digital conversion system is canceled by the output offset self-zeroing method, so as to be able to break through the limitation of the smaller sampling capacitor on the signal-to-noise distortion ratio (Signal to Noise and Distortion Ratio, SNDR).

[0085] During Δt, the first input signal V ip is also changing, and is coupled to the input terminal V T of the preamplifier 112 through the sampling capacitor Cs; the sampling thermal noise and the changing input signal coupled to the V T node are amplified together by the preamplifier 112. Briefly speaking, the output voltage of the preamplifier 112 satisfies at the sampling moment t2:

[0086] A 1out (t 2) = A 1 ·[V ip (t 2 ) - V ip (t 1 ) + v ns1 ) (1);

[0087] where A 1 is the amplification factor of the preamplifier 112, V ip (t 2 ) is the value of the input signal at the sampling time t2, V ip (t 1 ) is the value of the input signal at the sampling time t1, and v ns1 is the sampling thermal noise on the sampling capacitor Cs at the sampling time t1. It should be noted that the formula (1) does not include the influence of other non-ideal factors such as the offset and noise of the preamplifier 112; nor does it consider the gain coefficient brought by the parasitic capacitance and feedback capacitance at the input end of the preamplifier 112 to the output calculation of the preamplifier 112.

[0088] The noise introduced by the preamplifier 112 at the sampling time t2 is equivalent to the input end and satisfies the following relationship:

[0089]

[0090] where γ is the noise factor, k is the Boltzmann constant, T is the temperature, and C NC is the capacitance value of the noise cancellation capacitor.

[0091] For low-frequency input signals, since the change of the first input signal V ip itself is relatively slow, within the time period Δt, the change amount of the first input signal V ip is relatively small; however, when the first input signal V ip is a high-frequency signal, due to the relatively fast change, within the time period Δt, the change amount of the first input signal V ip is relatively large. As shown in Figure 7 , if the change amount of the input signal coupled through the sampling capacitor C S is amplified (A 1 ·[V ip (t 2 ) - V ip (t 1)]) Exceeding the output range of the preamplifier 112 will seriously degrade the performance of the analog-to-digital converter; the above problems can be alleviated by reducing the delay Δt or reducing the gain of the preamplifier 112. Considering equations (1) and (2) together, reducing the delay Δt requires increasing the bandwidth of the preamplifier 112 to better collect the sampling thermal noise on the noise cancellation capacitor; if the noise introduced by the preamplifier 112 at the sampling time t2 is to be kept unchanged, the power consumption of the preamplifier 112 needs to be increased, which may seriously reduce the overall energy efficiency of the system. On the other hand, reducing the gain of the preamplifier 112 can also alleviate the problem of amplifier saturation, but this will also cause the preamplifier 112 to introduce greater noise at the sampling time t2, reducing the overall signal-to-noise distortion ratio of the analog-to-digital converter. This limitation restricts the ability of the sampling thermal noise cancellation technology to increase the signal bandwidth.

[0092] The compensation module of the present invention compensates for the influence of the varying signal on the input node of the preamplifier 112 through a first-order approximation compensation path based on a differential circuit, effectively canceling the coupling of the input signal (satisfying ) at the input node of the preamplifier 112, so that the preamplifier 112 can operate within a smaller input range, ensuring both the elimination of sampling thermal noise and the improvement of the system linearity. The input signal (compensation signal) of the differential circuit 121 satisfies Ignoring the finite gain and finite bandwidth of the operational amplifier 121a in the differential circuit 121 for the time being, the output of the differential circuit 121 satisfies:

[0093] V ind =-R d ·C d ·dV in (3);

[0094] where dV in is the differential of the compensation signal Vin.

[0095] At the sampling time t1, the first switch K1 and the fourth switch K4 are turned off, the second switch K2 is turned on, the upper plates of the compensation capacitor C R and the sampling capacitor C S are disconnected from the common-mode voltage V CM , and the lower plate of the compensation capacitor C R is switched from the output of the differential circuit 121 to the common-mode voltage V CM . The compensation path compensates for the voltage change of the V T node through the compensation capacitor C R and satisfies:

[0096]

[0097] where C P is for V TThe parasitic capacitance of the node. Combining Equation (1) and Equation (4), it can be obtained that if the following conditions are met:

[0098]

[0099] That is Then the voltage of node V T can be compensated approximately to the first order, and the output voltage saturation of the preamplifier 112 can be avoided while reducing the sampling thermal noise. In addition, this compensation condition is independent of the input signal frequency.

[0100] It should be noted that the above principle is described based on the analog-to-digital converter with a Pipe-SAR ADC structure. The principle of the analog-to-digital converter with a SAR ADC structure is similar and will not be elaborated here one by one.

[0101] The present invention also provides an analog-to-digital conversion method, which is implemented based on the analog-to-digital converter of the present invention. The method includes:

[0102] 1) At the first sampling moment t1, the input signal and the sampling thermal noise are collected at the input end of the preamplifier 112; at the same time, the compensation voltage is obtained by differentiating the compensation signal, and the compensation voltage is loaded at the input end of the preamplifier 112 to compensate for the voltage change of the input signal coupled to the input end of the preamplifier 112.

[0103] Specifically, in this embodiment, taking the Figure 5 analog-to-digital converter with a Pipe-SAR ADC structure as an example, in the initial state, the first control signal and the second control signal are at high level, the third control signal is at low level, the first switch K1 in each compensation unit is closed, and the second switch K2 is open; in the differential analog-to-digital conversion module, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7, the eighth switch K8, the ninth switch K9, and the eleventh switch K11 are closed, the tenth switch K10 and the twelfth switch K12 are open, and the upper plates of the compensation capacitor C R and the sampling capacitor Cs are connected to the common-mode voltage V CM . At the first sampling moment t1, the first control signal jumps to low level, the first switch K1 in each compensation unit is open, and the second switch K2 is closed; in the differential analog-to-digital conversion module, the fourth switch K4 and the seventh switch K7 are open, the upper plates of the compensation capacitor C R and the sampling capacitor Cs are disconnected from the common-mode voltage V CM , and the lower plate of the compensation capacitor C R is switched to the common-mode voltage V CM, the sampling capacitor Cs completes sampling. At this time, the sampling thermal noise is collected on the upper plate of the sampling capacitor Cs. Before the second sampling moment t2 arrives, the change amount of the input signal is coupled to the upper plate (Vcs) of the sampling capacitor Cs and is canceled by the compensation voltage (V CR ), and the change amount of the input signal (V AIN ) of the preamplifier 112 becomes smaller, so that the output signal (Vo1) of the preamplifier 112 is within the output range, as shown in Figure 8 .

[0104] 2) At the second sampling moment t2, sample and store the signal that has been compensated and pre-amplified in sequence.

[0105] Specifically, at the second sampling moment t2, the second control signal jumps to a low level, the third switch K3, the fifth switch K5, the sixth switch K6, the eighth switch K8, the ninth switch K9 and the eleventh switch K11 are turned off, the upper plate of the noise cancellation capacitor is disconnected from the common-mode voltage V CM , and the input signal and the sampling thermal noise are sampled and stored on the noise cancellation capacitor. At this time, the noise cancellation capacitor completes sampling.

[0106] 3) In the quantization stage, make the sampling thermal noise stored at the output end of the preamplifier 112 cancel out the sampling thermal noise sampled at the input end of the preamplifier 112 through the preamplifier 112; adjust the potential of the lower plate of the sampling capacitor based on the successive approximation logic, thereby realizing analog-to-digital conversion.

[0107] Specifically, after the double sampling is completed, the third control signal jumps to a high level, the tenth switch K10 and the twelfth switch K12 are turned on to achieve inter-stage amplification; during this process, since the sampling thermal noise at the input end of the preamplifier 112 is out of phase with the sampling thermal noise on the noise cancellation capacitor, noise cancellation is realized on the noise cancellation capacitor.

[0108] The present invention also provides an electronic product, which includes the analog-to-digital converter 1 of the present invention, thereby realizing high-performance analog-to-digital conversion and meeting requirements such as accuracy, linearity, power consumption, conversion speed, etc. This electronic product is applicable to fields such as audio processing, video processing, medical equipment, industrial automation, consumer electronics, automotive electronics, energy management, etc., which will not be elaborated one by one here.

[0109] In order to verify the improvement of the analog-to-digital converter 1 of the present invention on the system performance, compare the analog-to-digital converter 1 with a compensation module set and the analog-to-digital converter without a compensation module. For a fair comparison, except for the compensation path, other circuits are kept the same (that is, the difference between the two is only whether there is a compensation module); among them, the sampling capacitor C Figure 5 ​S has a capacitance value of 2 pF, and the post-stage amplifier 116 uses a gain-boosting operational amplifier structure to implement a high-gain operational amplifier. Such a test design ensures the reliability and comparability of the test results. As Figure 9 shown, compared with the analog-to-digital converter without compensation, the analog-to-digital converter of the present invention can improve the spurious-free dynamic range (SFDR) performance by 10 dB to 30 dB in the case of input frequency signals from about 2 MHz to 10 MHz. This improvement will bring significant improvements to the performance and stability of the system, making the analog-to-digital converter perform more excellently under high-frequency signals.

[0110] The present invention eliminates the sampling thermal noise by collecting and canceling the sampling thermal noise regarded as the offset voltage through a pre-amplifier. The following further tests the effect of eliminating the sampling thermal noise of the present invention. Taking Figure 5 the analog-to-digital converter as an example, as Figure 10 shown, after adopting the sampling thermal noise elimination technology of the present invention, the equivalent input sampling thermal noise is reduced from the original 105 μV to 9.8 μV, and the total noise of the equivalent input sampling thermal noise, pre-amplifier, post-stage amplifier, and differential circuit (calculated by summing the squares of each item and then taking the square root) is reduced from 113 μV to 39.8 μV. Therefore, the sampling thermal noise elimination technology of the present invention can achieve a signal-to-noise distortion ratio of 92 dB when using a 2 pF sampling capacitor. In addition, from Figure 10 it can also be seen that the noise of the differential circuit can also be eliminated by this structure. Therefore, the area and power consumption required to implement the operational amplifier 121a are much lower than those of the pre-amplifier 112 and the post-stage amplifier 116. Thus, it can be seen that the analog-to-digital converter of the present invention has significant advantages in improving system performance and reducing power consumption.

[0111] In summary, the present invention provides an analog-to-digital converter, a conversion method, and an electronic product, including: a differential analog-to-digital conversion module and a compensation module; the differential analog-to-digital conversion module eliminates the sampling thermal noise based on a dual-sampling method and implements the analog-to-digital conversion of the input signal; the compensation module receives a compensation signal, and the output end is connected to the input end of the pre-amplifier in the differential analog-to-digital conversion module, and compensates for the change of the input signal coupled to the input end of the pre-amplifier based on a differential method; wherein, the input signal and the compensation signal connected to the same input end of the pre-amplifier are differential signals. The analog-to-digital converter, conversion method, and electronic product of the present invention adopt a sampling thermal noise elimination technology, and increase the signal bandwidth limited by the amplifier saturation problem by adopting a first-order approximation compensation module based on a differential circuit, and have the advantages of a small sampling capacitor, low noise, and a large signal bandwidth. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0112] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises at least: Differential analog-to-digital conversion module and compensation module; The differential analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of an input signal; the differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a preamplifier, a latch and a SAR logic unit; one end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to a positive reference voltage and a negative reference voltage through corresponding switches, and the upper plate is connected to the first input end of the preamplifier; one end of the fourth switch is connected to a common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array; one end of the sixth switch is connected to a second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; The lower plate of the sampling capacitor is also connected to the positive reference voltage and the negative reference voltage through corresponding switches, and the upper plate is connected to the second input terminal of the preamplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array; the first output terminal and the second output terminal of the preamplifier are respectively connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor; one end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; one end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor; the first input terminal and the second input terminal of the latch are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; the SAR logic unit is connected to the output terminal of the latch, and controls the first switch capacitor array and each switch in the first switch capacitor array to switch to the corresponding reference voltage based on the output signal of the latch; The compensation module receives a compensation signal, and its output end is connected to the input end of the preamplifier in the differential analog-to-digital conversion module, and compensates for the change of the input signal coupled to the input end of the preamplifier based on a differential method; the compensation module includes a first compensation unit and a second compensation unit, and the first compensation unit and the second compensation unit both include a differential circuit, a first switch, a second switch and a compensation capacitor; the input end of the differential circuit receives the corresponding compensation signal, and the output end is connected to the lower plate of the compensation capacitor via the first switch; the upper plate of the compensation capacitor is connected to the corresponding input end of the preamplifier; one end of the second switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor; wherein the sampling timing of the first switch is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module, and the on-off state of the second switch is opposite to that of the first switch; The input signal and the compensation signal connected to the same input terminal of the pre-amplifier are differential signals.

2. An analog-to-digital converter, characterized in that: The analog-to-digital converter comprises at least: Differential analog-to-digital conversion module and compensation module; The differential analog-to-digital conversion module eliminates sampling thermal noise based on a double sampling method and realizes analog-to-digital conversion of an input signal; the differential analog-to-digital conversion module includes a third switch, a first switch capacitor array, a fourth switch, a first noise elimination capacitor, a fifth switch, a sixth switch, a second switch capacitor array, a seventh switch, a second noise elimination capacitor, an eighth switch, a first feedback capacitor, a second feedback capacitor, a ninth switch, a tenth switch, an eleventh switch, a twelfth switch, a preamplifier, a comparator, a SAR logic unit, a post-amplifier and at least one SAR ADC unit; one end of the third switch is connected to the first input signal, and the other end is connected to the lower plate of each sampling capacitor in the first switch capacitor array; the lower plate of each sampling capacitor in the first switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through the corresponding switch, and the upper plate is connected to the first input end of the preamplifier; one end of the fourth switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the first switch capacitor array; one end of the sixth switch is connected to the second input signal, and the other end is connected to the lower plate of each sampling capacitor in the second switch capacitor array; the lower plate of each sampling capacitor in the second switch capacitor array is also connected to the positive reference voltage and the negative reference voltage through the corresponding switch, and the upper plate is connected to the second input end of the preamplifier; one end of the seventh switch is connected to the common mode voltage, and the other end is connected to the upper plate of each sampling capacitor in the second switch capacitor array; the first output end and the second output end of the preamplifier are respectively connected to the lower plates of the first noise elimination capacitor and the second noise elimination capacitor; one end of the fifth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the first noise elimination capacitor; One end of the eighth switch is connected to the common mode voltage, and the other end is connected to the upper plate of the second noise elimination capacitor; the first input end and the second input end of the comparator are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor; the SAR logic unit is connected to the output end of the comparator, and controls each switch in the first switch capacitor array and the second switch capacitor array to switch to the corresponding reference voltage based on the output signal of the comparator; the first input end and the second input end of the post-stage amplifier are respectively connected to the upper plates of the first noise elimination capacitor and the second noise elimination capacitor, and form a ring amplifier with the pre-amplifier; the lower plate of the first feedback capacitor is connected to the common mode voltage via the ninth switch, and is also connected to the first output end of the post-stage amplifier via the tenth switch; the upper plate of the first feedback capacitor is connected to the output end of the first switch capacitor array; the lower plate of the second feedback capacitor is connected to the common mode voltage via the eleventh switch, and is also connected to the second output end of the post-stage amplifier via the twelfth switch; the upper plate of the second feedback capacitor is connected to the output end of the second switch capacitor array; each level of SAR ADC unit is sequentially cascaded to the output end of the post-stage amplifier; The compensation module receives a compensation signal, and its output end is connected to the input end of the preamplifier in the differential analog-to-digital conversion module, and compensates for the change of the input signal coupled to the input end of the preamplifier based on a differential method; the compensation module includes a first compensation unit and a second compensation unit, and the first compensation unit and the second compensation unit both include a differential circuit, a first switch, a second switch and a compensation capacitor; the input end of the differential circuit receives the corresponding compensation signal, and the output end is connected to the lower plate of the compensation capacitor via the first switch; the upper plate of the compensation capacitor is connected to the corresponding input end of the preamplifier; one end of the second switch is connected to the common mode voltage, and the other end is connected to the lower plate of the compensation capacitor; wherein the sampling timing of the first switch is consistent with the sampling timing of the sampling capacitor in the differential analog-to-digital conversion module, and the on-off state of the second switch is opposite to that of the first switch; The input signal and the compensation signal connected to the same input terminal of the pre-amplifier are differential signals.

3. The analog-to-digital converter according to claim 1 or 2, characterized in that: The analog-to-digital converter satisfies: Among them, Δt is the time difference between the two samples, R d is the value of the resistor in the differential circuit, C d is the value of the capacitor in the differential circuit, C R is the value of the compensation capacitor, C S is the value of the sampling capacitor.

4. The analog-to-digital converter according to claim 1 or 2, characterized in that: The differential analog-to-digital conversion module also includes a thirteenth switch, a fourteenth switch, a first resistor and a second resistor; the first resistor is connected between the fifth switch and the common mode voltage, and the thirteenth switch is connected in parallel to both ends of the first resistor; the second resistor is connected between the eighth switch and the common mode voltage, and the fourteenth switch is connected in parallel to both ends of the second resistor.

5. An analog-to-digital conversion method, implemented based on the analog-to-digital converter according to any one of claims 1 to 4, characterized in that: The analog-to-digital conversion method at least comprises: At a first sampling moment, the input signal and the sampled thermal noise are collected to the input end of the preamplifier; at the same time, a compensation voltage is obtained by differentiating the compensation signal, and the compensation voltage is loaded to the input end of the preamplifier to compensate for the voltage change of the input signal coupled to the input end of the preamplifier; At the second sampling moment, sampling and storing the signals that have been compensated and pre-amplified in sequence; In the quantization stage, the sampling thermal noise stored at the output of the preamplifier and the sampling thermal noise sampled at the input of the preamplifier cancel each other out; the potential of the lower plate of the sampling capacitor is adjusted based on successive approximation logic, thereby achieving analog-to-digital conversion.

6. An electronic product, characterized in that: The electronic product at least comprises: an analog-to-digital converter as described in any one of claims 1-4.

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