Time synchronization method and time synchronization device

Abstract

The invention discloses a time synchronization method and a time synchronization device, and belongs to the technical field of communication, and the time synchronization method comprises the steps that an ith pulse signal sent by a second chip in a sending period is received, the second chip sends n pulse signals in the sending period, the ith pulse signal is a pulse signal in the n pulse signals, n is a positive integer, and n is a positive integer; the pulse widths of any two pulse signals in the sending period are different, the pulse widths of the pulse signals are used for representing the sending sequence numbers of the pulse signals in the sending period, the time interval between any two adjacent pulse signals in the sending period is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is smaller than or equal to n; and updating the time of the first chip according to the pulse width of the ith pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a time synchronization method and a time synchronization device. Background Art

[0002] In the related art, when multiple chips work together in an electronic device, it is usually necessary to keep the multiple chips at the same time reference. In order to achieve the same time reference for multiple chips, the master chip usually sends a pulse to other slave chips every other time period, and sends a master chip timestamp matching the current pulse to other slave chips to be synchronized.

[0003] However, using this time synchronization method, once any pulse signal or timestamp signal is lost or abnormal due to hardware interference or untimely processing by the receiving chip, it will cause errors in the time synchronization of the slave chip. It can be seen that the existing time synchronization method is prone to the problem of time synchronization errors from the chip. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a time synchronization method and a time synchronization device, which can solve the problem that the time synchronization process of the existing time synchronization method is prone to errors.

[0005] In a first aspect, an embodiment of the present application provides a time synchronization method, which is executed by a first chip, and the method includes:

[0006] Receive the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0007] The time of the first chip is updated according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

[0008] In a second aspect, an embodiment of the present application provides a time synchronization method, which is executed by a second chip, and the method includes:

[0009] During a sending cycle, a pulse signal is sent to the first chip every first time interval, wherein the second chip sends n pulse signals during the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

[0010] In a third aspect, an embodiment of the present application provides a time synchronization device, applied to a first chip, the device comprising:

[0011] A receiving module, used to receive the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0012] An updating module is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

[0013] In a fourth aspect, an embodiment of the present application provides a time synchronization device, which is applied to a second chip, and the device includes:

[0014] A sending module is used to send a pulse signal to a first chip at every first time interval within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

[0015] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect or the second aspect are implemented.

[0016] In a sixth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect or the second aspect are implemented.

[0017] In the seventh aspect, an embodiment of the present application provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the steps of the method described in the first aspect or the second aspect.

[0018] In an eighth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the method described in the first aspect or the second aspect.

[0019] In the embodiment of the present application, since the pulse width of each received pulse signal can characterize the sending sequence number of the current pulse signal in the sending cycle, and the time interval between any two adjacent pulse signals in the sending cycle is the first time interval, thus, according to the pulse width of the currently received i-th pulse signal and the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signal can be determined, so that even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined according to the timestamp corresponding to the previously received pulse signal and the relative time interval between the current i-th pulse signal and the previously received pulse signal. In addition, since the relative time interval between the current pulse signal and the previously received pulse signal can be determined according to the pulse width of the currently received pulse signal and the first time interval, that is, the pulse width of each pulse signal can be used as the relative time information of the pulse signal itself, so that when the pulse signal is lost during the transmission process, since the pulse signal itself carries the relative time information, when the pulse signal is received again, the current accurate timestamp can still be calculated according to the pulse width of the pulse signal received again, thereby solving the problem of error-prone time synchronization process in the existing time synchronization method. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is one of the flow charts of a time synchronization method provided in an embodiment of the present application;

[0021] Figure 2 is a waveform diagram of pulse transmission in an embodiment of the present application;

[0022] Figure 3 This is a second flow chart of a time synchronization method provided in an embodiment of the present application;

[0023] Figure 4 This is a flowchart of a time synchronization method provided in an embodiment of the present application;

[0024] Figure 5 This is a fourth flow chart of a time synchronization method provided in an embodiment of the present application;

[0025] Figure 6 This is one of the structural schematic diagrams of a time synchronization device provided in an embodiment of the present application;

[0026] Figure 7 This is a second structural diagram of a time synchronization device provided in an embodiment of the present application;

[0027] Figure 8 is a schematic diagram of the structure of an electronic device provided by some embodiments of the present application;

[0028] Fig. 9 One of the hardware structure diagrams of the electronic device provided in some embodiments of the present application;

[0029] Fig.10 The second schematic diagram of the hardware structure of the electronic device provided for some embodiments of the present application. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0031] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0032] In the following, in conjunction with the accompanying drawings, a time synchronization method and a time synchronization device provided by an embodiment of the present application are described in detail through specific embodiments and their application scenarios.

[0033] See also Figure 1 , Figure 1 A schematic flow chart of a time synchronization method provided in an embodiment of the present application, wherein the time synchronization method is executed by a first chip, and the time synchronization method comprises the following steps:

[0034] Step 101, receiving the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signals within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0035] Step 102: Update the time of the first chip according to the pulse width of the i-th pulse signal to synchronize the time of the first chip with the time of the second chip.

[0036] In the related art, in order to meet the needs of various differentiated performance enhancements, other external chips besides the main processor will be added to electronic devices such as mobile phones as processing for dedicated services. For example, dedicated chips such as camera image processing and display screen processing, and these chips need to maintain the same time reference as the main processor when processing data. Based on this, in some embodiments of the present application, the second chip may be the main processor in the electronic device, and the first chip may be various external chips in the electronic device. It is understandable that in an electronic device, a plurality of different first chips may be included, and the second chip may send pulse signals and timestamps to each first chip respectively according to the method provided in the embodiment of the present application, so as to achieve time synchronization between each first chip and the second chip.

[0037] It should be noted that in the embodiments of the present application, the above-mentioned time synchronization method can be applied not only to electronic devices such as mobile phones, but also to time synchronization scenarios involving multiple sensors and multiple processors in the fields of virtual reality (VR) / wearable devices / robots.

[0038] For example, in some embodiments of the present application, the time synchronization method can also be applied to time synchronization between multiple sensors. Since sensors usually include chips, when multiple sensors work together, the chip in one of the sensors can be used as the second chip in the embodiments of the present application. At the same time, the chips in other sensors can be used as the first chip. Based on the time synchronization method provided in the embodiments of the present application, time synchronization between multiple sensors can be achieved.

[0039] For example, in some other embodiments of the present application, the time synchronization method can also be applied to time synchronization between multiple processors. When multiple processors work together, one of the processors can be used as the second chip in the embodiment of the present application. At the same time, the other processors can be used as the first chip to achieve time synchronization between multiple processors based on the time synchronization method provided in the embodiment of the present application.

[0040] The above-mentioned sending cycle can be a period set artificially, and specifically n continuously sent pulse signals can be used as a sending cycle. For example, the sent pulse signals can be encoded, and n pulse signals encoded as 1 to n can be used as n pulse signals in the first sending cycle, and n pulse signals encoded as n+1 to 2n can be used as n pulse signals in the second sending cycle. And so on, the encoding of the pulse signals in each sending cycle can be determined. Among them, the encoding of the pulse signal can be used as the sending order of the pulse signal, and the smaller the encoding, the earlier the sending order. The above-mentioned n pulse signals can be sent with a first time interval as the pulse period, and the time interval between the rising edges of two adjacent pulse signals is the first time interval.

[0041] It is understandable that the first chip and the second chip can preselect and agree on the pulse widths of pulse signals sent at different times in a sending cycle. For example, the pulse width of the first pulse signal can be agreed to be the first pulse width, the pulse width of the second pulse signal can be agreed to be the second pulse width, ..., the pulse width of the ith pulse signal can be agreed to be the ith pulse width, ..., the pulse width of the nth pulse signal can be agreed to be the nth pulse width, etc. In this way, after receiving the ith pulse signal, the first chip can determine the sending sequence number of the ith pulse signal in the sending cycle according to the pulse signal of the ith pulse signal, and can determine the timestamp corresponding to the ith pulse signal based on this.

[0042] For example, in some embodiments of the present application, when the first chip has not received the timestamp corresponding to the i-th pulse signal, the sending sequence number of the i-th pulse signal is determined to be 5 according to the pulse width of the i-th pulse signal, and the first chip has previously received the timestamp corresponding to the pulse signal with a sending sequence number of 3, the timestamp corresponding to the i-th pulse signal can be obtained by adding twice the first time interval to the timestamp corresponding to the pulse signal with a sending sequence number of 3, and the timestamp of the first chip when receiving the i-th pulse signal can be updated to: the timestamp corresponding to the i-th pulse signal obtained, so as to realize the process of updating the time of the first chip according to the pulse width of the i-th pulse signal.

[0043] For another example, in some embodiments of the present application, when the first chip has not received the timestamp corresponding to the i-th pulse signal, the sending sequence number of the i-th pulse signal is determined to be 6 according to the pulse width of the i-th pulse signal, and the first chip has previously received the timestamp corresponding to the pulse signal with the sending sequence number 1, the timestamp corresponding to the i-th pulse signal can be obtained by adding five times the first time interval to the timestamp corresponding to the pulse signal with the sending sequence number 1, and the timestamp of the first chip when receiving the i-th pulse signal can be updated to: the timestamp corresponding to the i-th pulse signal obtained, so as to realize the process of updating the time of the first chip according to the pulse width of the i-th pulse signal.

[0044] In this implementation, since the pulse width of each received pulse signal can represent the sending sequence number of the current pulse signal in the sending cycle, and the time interval between any two adjacent pulse signals in the sending cycle is the first time interval, thus, according to the pulse width of the currently received i-th pulse signal and the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signal can be determined. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined according to the timestamp corresponding to the previously received pulse signal and the relative time interval between the current i-th pulse signal and the previously received pulse signal. In addition, since the relative time interval between the current pulse signal and the previously received pulse signal can be determined according to the pulse width of the currently received pulse signal and the first time interval, that is, the pulse width of each pulse signal can be used as the relative time information of the pulse signal itself. Thus, when the pulse signal is lost during the transmission process, since the pulse signal itself carries the relative time information, when the pulse signal is received again, the current accurate timestamp can still be calculated according to the pulse width of the pulse signal received again, thereby solving the problem of the time synchronization process being prone to error in the existing time synchronization method.

[0045] Optionally, the pulse width of the first pulse signal in the sending cycle is a first pulse width, and updating the time of the first chip according to the pulse width of the i-th pulse signal includes:

[0046] When the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the first chip is updated based on the first timestamp and the pulse width of the i-th pulse signal to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0047] The first timestamp may be the current timestamp of the second chip when the second chip starts to send the first pulse signal, and specifically may be the current timestamp of the clock in the second chip. That is, the first timestamp may be the timestamp of the rising edge of the first pulse signal, for example, see Figure 2 , when P1 is the first pulse signal, Figure 2 The t1 in is the first timestamp. It can be understood that, Figure 2 , the horizontal axis is the time axis, and the unit of the horizontal axis can be various time units, such as microseconds, etc. Figure 2 The Δt in may be the first time interval mentioned above.

[0048] It is understandable that the first chip will perform a time update each time it receives a pulse signal sent by the first chip, so that the time of the first chip is synchronized with the time of the second chip. For ease of understanding, the following takes the process of the first chip performing time update in one of the transmission cycles as an example to further explain the time synchronization method:

[0049] When the first chip receives the first pulse signal in the above-mentioned transmission cycle, it can receive the first timestamp corresponding to the first pulse signal sent by the second chip, wherein the first timestamp can be the timestamp sent by the second chip through the serial peripheral interface (SPI), or the first timestamp can also be the timestamp sent by the second chip through the I2C bus (Inter IC BUS), or the first timestamp can also be the timestamp sent by the second chip through the Universal Asynchronous Receiver / Transmitter (UART). The first timestamp is the timestamp corresponding to the rising edge of the first pulse signal. After receiving the first timestamp, the first chip can update the timestamp when the first chip starts to receive the first pulse signal to the first timestamp, or it can also be based on the timestamp when the first chip starts to receive the first pulse signal as the first timestamp to update the timestamp of the current time point.

[0050] After receiving other pulse signals in the above-mentioned transmission cycle, the first chip can subsequently determine the serial number of the currently received pulse signal according to the pulse width of the pulse signal. For example, when the current pulse signal is determined to be the second pulse signal in the transmission cycle based on the pulse width, since the time difference between the rising edge of the first pulse signal and the rising edge of the second pulse signal is the first time interval, and the timestamp of the first pulse signal is the first timestamp, it can be determined that the rising edge timestamp of the second pulse signal is the sum of the first timestamp and the first time interval. Then, the timestamp when the first chip starts to receive the second pulse signal can be updated to the determined rising edge timestamp of the second pulse signal, or the timestamp of the current time point can be updated based on the determined rising edge timestamp of the second pulse signal. Correspondingly, when the current pulse signal is determined to be the third pulse signal in the sending cycle based on the pulse width, since the time difference between the rising edge of the first pulse signal and the rising edge of the third pulse signal is twice the first time interval, and the timestamp of the first pulse signal is the first timestamp, it can be determined that the rising edge timestamp of the third pulse signal is the sum of twice the first time interval and the first timestamp, and based on this, the timestamp of the first chip is updated, and so on, the rising edge timestamp corresponding to each pulse signal in the above-mentioned sending cycle can be determined based on this method, and the timestamp of the first chip can be updated based on the determined rising edge timestamp of the pulse signal to achieve time synchronization between the first chip and the second chip.

[0051] It is understandable that, during the cooperation between the first chip and the second chip, the pulse signal sent may form a plurality of sending cycles, wherein time synchronization may be performed in each sending cycle according to the above-mentioned time synchronization method.

[0052] In this implementation, since the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the second chip can be updated based on the first timestamp and the pulse width of the i-th pulse signal, that is, the time of the second chip can be updated based on the first timestamp for other pulse signals except the first pulse signal in the same sending cycle. In this way, in the process of time synchronization, only one timestamp signal needs to be sent for n pulse signals in the same sending cycle. Compared with the related art, which requires sending a timestamp signal once for each pulse signal, this is beneficial to reducing the sending frequency of the timestamp signal, thereby reducing the probability of transmission errors during the transmission process, and further beneficial to reducing the probability of time synchronization errors of the first chip during the time synchronization process.

[0053] Optionally, the pulse width of the first pulse signal in the sending cycle is the first pulse width, and after receiving the i-th pulse signal sent by the second chip in the sending cycle, the method further includes:

[0054] When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when receiving the i-th pulse signal is updated to the first timestamp to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0055] Among them, the pulse width of the i-th pulse signal being equal to the first pulse width may mean that: the i-th pulse signal is the first pulse signal in the above-mentioned sending cycle.

[0056] The above-mentioned updating of the timestamp of the first chip when receiving the i-th pulse signal to the first timestamp may mean: updating the timestamp of the first chip starting to receive the first pulse signal to the first timestamp, or, it may be based on the timestamp of the first chip starting to receive the first pulse signal as the first timestamp to update the timestamp of the current time point.

[0057] In this implementation, when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when receiving the i-th pulse signal is updated to the first timestamp, thereby achieving time synchronization between the first chip and the second chip when the first pulse signal is received.

[0058] Optionally, the pulse width of the first pulse signal in the sending cycle is the first pulse width, and after receiving the i-th pulse signal sent by the second chip in the sending cycle, the method further includes:

[0059] When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is not received, determine a third timestamp based on the second timestamp, the first time interval and n, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous sending cycle;

[0060] The timestamp of the first chip when receiving the i-th pulse signal is updated to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

[0061] The failure to receive the first timestamp sent by the second chip may mean that the first chip fails to successfully receive the first timestamp sent by the second chip. For example, the failure may be due to hardware interference or untimely processing by the receiving chip.

[0062] The above-mentioned second timestamp can be the rising edge timestamp corresponding to the first pulse signal in the previous sending cycle of the current sending cycle. Since the rising edge of the first pulse signal in the current sending cycle and the rising edge of the first pulse signal in the previous sending cycle are separated by n first time intervals, and the rising edge timestamp of the first pulse signal in the previous sending cycle is the second timestamp, it can be determined that the rising edge timestamp of the first pulse signal in the current sending cycle is: the sum of the second timestamp and n times the first time interval, that is, the above-mentioned third timestamp is: the sum of the second timestamp and n times the first time interval.

[0063] The above-mentioned updating of the timestamp of the first chip when receiving the i-th pulse signal to the third timestamp may mean: updating the timestamp of the first chip starting to receive the i-th pulse signal to the third timestamp, or, it may be based on the timestamp of the first chip starting to receive the i-th pulse signal as the third timestamp to update the timestamp of the current time point.

[0064] The above-mentioned sending cycle may be a non-first sending cycle in the process of time synchronization between the first chip and the second chip, that is, the sending cycle has a previous sending cycle. In addition, for the first sending cycle in the process of time synchronization between the first chip and the second chip, if the first timestamp corresponding to the first pulse signal is not received, the first chip may request the second chip to send the timestamp again until the timestamp is received.

[0065] In this implementation, in a sending cycle, when the first timestamp corresponding to the first pulse signal is not successfully received, the time point corresponding to the first pulse signal in the current sending cycle can still be updated based on the second timestamp in the previous sending cycle, thereby helping to further improve the time synchronization effect between the first chip and the second chip.

[0066] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0067] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0068] The pulse widths of the above-mentioned n pulse signals gradually increase in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width. Specifically, it means that in the process where the second chip sends n pulse signals to the first chip in sequence with a pulse period of the first time interval, the pulse width of the current pulse signal increases by the first width compared with the pulse width of the pulse signal sent last time.

[0069] Correspondingly, the pulse widths of the above-mentioned n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width. Specifically, it means that in the process where the second chip sends n pulse signals to the first chip in sequence with a pulse period of the first time interval, the pulse width of the current pulse signal is reduced by the first width compared with the pulse width of the pulse signal sent last time.

[0070] See also Figure 3 , the following takes the pulse width of the n pulse signals, which gradually increases in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width as an example to further explain the time synchronization method, wherein the first width is recorded as Δw, the first time interval is recorded as Δt, the currently received pulse signal is recorded as Wi, and the first pulse width is recorded as W0. The first chip is a slave processor, and the second chip is a master processor, see Figure 2 , Figure 2 A pulse waveform diagram of the n pulse signals sent, wherein the first timestamp is t1, the pulse width of the first pulse signal P1 is W0, the pulse width of the second pulse signal P2 is W0+Δw, and the pulse width of the nth pulse signal Pn is W0+(n-1)*Δw. The first pulse signal in the next sending cycle is Pn+1, and the pulse width of Pn+1 is W0. The time synchronization method comprises the following steps:

[0071] Receive the i-th pulse signal;

[0072] Determine whether the i-th pulse signal Wi is equal to W0;

[0073] If Wi is equal to W0, it is determined whether the first timestamp is received, wherein Wi being equal to W0 indicates that the i-th pulse signal is the first pulse signal in the current transmission cycle, and the first timestamp is the timestamp when the transmitting end sends the i-th pulse signal;

[0074] If a first timestamp is received, updating the timestamp of the first chip when receiving the i-th pulse signal to the first timestamp;

[0075] If the first timestamp is not received, determining a third timestamp based on the second timestamp, the first time interval and n, and updating the timestamp of the first chip when receiving the i-th pulse signal to the third timestamp;

[0076] If Wi is not equal to W0, then based on the first timestamp and the pulse width of the i-th pulse signal, the time of the first chip is updated;

[0077] Determine whether time synchronization is completed. If so, end it. If not, receive the i+1th pulse signal.

[0078] In this embodiment, the pulse widths of the n pulse signals are gradually increased or decreased according to the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width. This is beneficial for subsequently determining the timestamps corresponding to each pulse signal, and updating the time of the first chip based on the timestamps corresponding to the determined pulse signals.

[0079] See also Figure 4 The embodiment of the present application further provides a time synchronization method, which is applied to a second chip, and the method comprises the following steps:

[0080] Step 401: During a sending cycle, a pulse signal is sent to the first chip every first time interval, wherein the second chip sends n pulse signals during the sending cycle, the pulse widths of any two pulse signals during the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal during the sending cycle, and n is an integer greater than 1.

[0081] Optionally, sending a pulse signal to the first chip at every first time interval during the sending period includes:

[0082] Obtaining a sending sequence number of a pulse signal to be sent within the sending cycle, wherein the pulse signal to be sent is any one of the n pulse signals;

[0083] When the sending sequence number of the pulse signal to be sent is an integer multiple of n plus 1, sending the pulse signal to be sent to the first chip, and sending a first timestamp to the first chip, where the first timestamp is the timestamp when the second chip sends the pulse signal to be sent;

[0084] When the sending sequence number of the pulse signal to be sent is not an integer multiple of n plus 1, the pulse signal to be sent is sent to the first chip.

[0085] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0086] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0087] This implementation is a time synchronization method on the second chip side corresponding to the time synchronization method on the first chip side provided in the above embodiment. Its specific implementation process corresponds to the above embodiment and has the same beneficial effects. To avoid repetition, it will not be described here.

[0088] For easier understanding, see Figure 2 and Figure 5 The time synchronization method is further explained below with a specific embodiment, and the time synchronization method includes the following steps:

[0089] The second chip sends a pulse signal P1 and a timestamp signal t1, wherein P1 is the first pulse signal in the sending cycle, and t1 is the timestamp when the second chip sends P1 to the first chip;

[0090] Determine whether there is an interval of Δt, that is, whether there is an interval of Δt from the last time a pulse signal is sent, where Δt is a first time interval. If not, continue to determine whether there is an interval of Δt;

[0091] If it is determined that the interval time has reached Δt, it is determined whether the code i of the pulse signal Pi to be sent is an integer multiple of n+1.

[0092] If i is an integer multiple of n+1, a pulse signal Pi is sent to the first chip, and then a timestamp signal ti corresponding to the pulse signal Pi is sent to the first chip, wherein i is an integer multiple of n+1 indicating that the pulse signal to be sent is the first pulse signal in a sending cycle;

[0093] End time synchronization and return to the above step "determine whether the interval is Δt";

[0094] If i is not an integer multiple of n + 1, a pulse signal Pi is sent to the first chip, wherein i is not an integer multiple of n + 1, indicating that the pulse signal to be sent is not the first pulse signal in a sending cycle. Therefore, only the pulse signal Pi needs to be sent without sending the corresponding timestamp, and the time synchronization is ended, and the above step of "determining whether there is an interval of Δt" is returned.

[0095] See also Figure 6 , Figure 6A schematic diagram of the structure of a time synchronization device 600 provided in an embodiment of the present application, wherein the time synchronization device 600 is applied to a first chip, and the device includes:

[0096] A receiving module 601 is used to receive the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0097] The updating module 602 is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

[0098] Optionally, the pulse width of the first pulse signal within the sending cycle is a first pulse width, and the update module 602 is specifically used to update the time of the first chip based on the first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0099] Optionally, the pulse width of the first pulse signal within the sending cycle is a first pulse width, and the update module 602 is specifically used to update the timestamp of the first chip when receiving the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0100] Optionally, the pulse width of the first pulse signal in the sending period is a first pulse width, and the device further includes:

[0101] a determination module, configured to determine a third timestamp based on a second timestamp, the first time interval, and n when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is not received, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous sending cycle;

[0102] The updating module 602 is further configured to update the timestamp of the first chip when receiving the i-th pulse signal to the third timestamp, so as to synchronize the time of the first chip with the time of the second chip.

[0103] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0104] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0105] In this implementation, since the pulse width of each received pulse signal can represent the sending sequence number of the current pulse signal in the sending cycle, and the time interval between any two adjacent pulse signals in the sending cycle is the first time interval, thus, according to the pulse width of the currently received i-th pulse signal and the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signal can be determined. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined according to the timestamp corresponding to the previously received pulse signal and the relative time interval between the current i-th pulse signal and the previously received pulse signal. In addition, since the relative time interval between the current pulse signal and the previously received pulse signal can be determined according to the pulse width of the currently received pulse signal and the first time interval, that is, the pulse width of each pulse signal can be used as the relative time information of the pulse signal itself. Thus, when the pulse signal is lost during the transmission process, since the pulse signal itself carries the relative time information, when the pulse signal is received again, the current accurate timestamp can still be calculated according to the pulse width of the pulse signal received again, thereby solving the problem of the time synchronization process being prone to error in the existing time synchronization method.

[0106] The time synchronization device 600 in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0107] The time synchronization device 600 in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0108] The time synchronization device 600 provided in the embodiment of the present application can achieve Figure 1 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0109] See also Figure 7 , Figure 7 A schematic diagram of the structure of a time synchronization device 700 provided in an embodiment of the present application, wherein the time synchronization device 700 is applied to a second chip, and the device includes:

[0110] The sending module 701 is used to send a pulse signal to the first chip at every first time interval within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

[0111] Optionally, the sending module 701 includes:

[0112] An acquisition submodule, used for acquiring a sending sequence number of a pulse signal to be sent within the sending cycle, wherein the pulse signal to be sent is any one of the n pulse signals;

[0113] a sending submodule, configured to send the pulse signal to be sent to the first chip when the sending sequence number of the pulse signal to be sent is an integer multiple of n plus 1, and to send a first timestamp to the first chip, wherein the first timestamp is a timestamp when the second chip sends the pulse signal to be sent;

[0114] The sending submodule is further configured to send the pulse signal to be sent to the first chip when the sending sequence number of the pulse signal to be sent is not an integer multiple of n plus 1.

[0115] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0116] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0117] In this implementation, since the pulse width of each received pulse signal can represent the sending sequence number of the current pulse signal in the sending cycle, and the time interval between any two adjacent pulse signals in the sending cycle is the first time interval, thus, according to the pulse width of the currently received i-th pulse signal and the first time interval, the relative time interval between the i-th pulse signal and the previously received pulse signal can be determined. Thus, even if the timestamp corresponding to the i-th pulse signal is not received, the timestamp corresponding to the i-th pulse signal can be determined according to the timestamp corresponding to the previously received pulse signal and the relative time interval between the current i-th pulse signal and the previously received pulse signal. In addition, since the relative time interval between the current pulse signal and the previously received pulse signal can be determined according to the pulse width of the currently received pulse signal and the first time interval, that is, the pulse width of each pulse signal can be used as the relative time information of the pulse signal itself. Thus, when the pulse signal is lost during the transmission process, since the pulse signal itself carries the relative time information, when the pulse signal is received again, the current accurate timestamp can still be calculated according to the pulse width of the pulse signal received again, thereby solving the problem of the time synchronization process being prone to error in the existing time synchronization method.

[0118] The time synchronization device 700 in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0119] The time synchronization device 700 in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0120] The time synchronization device 700 provided in the embodiment of the present application can realize Figure 4 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0121] Alternatively, if Figure 8 As shown, the embodiment of the present application further provides an electronic device 800, including a processor 801, a memory 802, a program or instruction stored in the memory 802 and executable on the processor 801, and the program or instruction is executed by the processor 801 to implement the above Figure 1 or Figure 4 The various processes of the time synchronization method embodiment in the illustrated embodiment can achieve the same technical effect, and will not be described again here to avoid repetition.

[0122] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0123] Fig. 9 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.

[0124] The electronic device 900 includes but is not limited to: a radio frequency unit 901, a network module 902, an audio output unit 903, an input unit 904, a sensor 905, a display unit 906, a user input unit 907, an interface unit 908, a memory 909, and a processor 910 and other components.

[0125] The radio frequency unit 901 is used to receive the i-th pulse signal sent by the second chip within a transmission cycle, wherein the second chip sends n pulse signals within the transmission cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the transmission cycle are different, and the pulse widths of the pulse signals are used to characterize the transmission sequence number of the pulse signal within the transmission cycle, the time interval between any two adjacent pulse signals within the transmission cycle is the first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n;

[0126] The processor 910 is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

[0127] Optionally, the processor 910 is also used to update the time of the first chip based on a first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0128] Optionally, the processor 910 is also used to update the timestamp of the first chip when receiving the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

[0129] Optionally, the processor 910 is further configured to determine a third timestamp based on the second timestamp, the first time interval and the n when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is not received, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous sending cycle;

[0130] The processor 910 is further configured to update the timestamp of the first chip when receiving the i-th pulse signal to the third timestamp, so as to synchronize the time of the first chip with the time of the second chip.

[0131] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0132] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0133] Those skilled in the art will appreciate that the electronic device 900 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 910 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig. 9 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0134] It should be understood that in the embodiment of the present application, the input unit 904 may include a graphics processor (Graphics Processing Unit, GPU) 9041 and a microphone 9042, and the graphics processor 9041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 906 may include a display panel 9061, and the display panel 9061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 907 includes a touch panel 9071 and other input devices 9072. The touch panel 9071 is also called a touch screen. The touch panel 9071 may include two parts: a touch detection device and a touch controller. Other input devices 9072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0135] The memory 909 can be used to store software programs and various data. The memory 909 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 909 may include a volatile memory or a non-volatile memory, or the memory 909 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 909 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0136] The processor 910 may include one or more processing units; optionally, the processor 910 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 910.

[0137] Fig.10 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.

[0138] The electronic device 1000 includes but is not limited to: a radio frequency unit 1001, a network module 1002, an audio output unit 1003, an input unit 1004, a sensor 1005, a display unit 1006, a user input unit 1007, an interface unit 1008, a memory 1009, and a processor 1010 and other components.

[0139] Among them, the radio frequency unit 1001 is used to send a pulse signal to the first chip every first time interval within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

[0140] Optionally, the processor 1010 is configured to obtain a sending sequence number of a pulse signal to be sent within the sending cycle, wherein the pulse signal to be sent is any one of the n pulse signals;

[0141] The radio frequency unit 1001 is configured to send the pulse signal to be sent to the first chip when the sending sequence number of the pulse signal to be sent is an integer multiple of n plus 1, and send a first timestamp to the first chip, where the first timestamp is a timestamp when the second chip sends the pulse signal to be sent;

[0142] The radio frequency unit 1001 is used to send the pulse signal to be sent to the first chip when the sending sequence number of the pulse signal to be sent is not an integer multiple of n plus 1.

[0143] Optionally, the pulse widths of the n pulse signals gradually increase in a sending order, and the difference between the pulse widths of any two adjacent pulse signals is the first width; or,

[0144] The pulse widths of the n pulse signals gradually decrease in the order of transmission, and the difference between the pulse widths of any two adjacent pulse signals is the first width.

[0145] Those skilled in the art will appreciate that the electronic device 1000 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1010 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.10 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0146] It should be understood that in the embodiment of the present application, the input unit 1004 may include a graphics processor (Graphics Processing Unit, GPU) 10041 and a microphone 10042, and the graphics processor 10041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1006 may include a display panel 10061, and the display panel 10061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1007 includes a touch panel 10071 and other input devices 10072. The touch panel 10071 is also called a touch screen. The touch panel 10071 may include two parts: a touch detection device and a touch controller. Other input devices 10072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0147] The memory 1009 can be used to store software programs and various data. The memory 1009 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1009 may include a volatile memory or a non-volatile memory, or the memory 1009 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1009 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0148] The processor 1010 may include one or more processing units; optionally, the processor 1010 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1010.

[0149] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned time synchronization method embodiment are implemented and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0150] The processor is a processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0151] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned time synchronization method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0152] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0153] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0154] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0155] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A time synchronization method, executed by a first chip, characterized in that: The method comprises: Receive the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n; The time of the first chip is updated according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

2. The method according to claim 1, characterized in that The pulse width of the first pulse signal in the sending cycle is a first pulse width, and the updating of the time of the first chip according to the pulse width of the i-th pulse signal includes: When the pulse width of the i-th pulse signal is not equal to the first pulse width, the time of the first chip is updated based on the first timestamp and the pulse width of the i-th pulse signal to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

3. The method according to claim 1, characterized in that The pulse width of the first pulse signal in the sending cycle is the first pulse width. After receiving the i-th pulse signal sent by the second chip in the sending cycle, the method further includes: When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, the timestamp of the first chip when receiving the i-th pulse signal is updated to the first timestamp to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

4. The method according to claim 1, characterized in that: The pulse width of the first pulse signal in the sending cycle is the first pulse width. After receiving the i-th pulse signal sent by the second chip in the sending cycle, the method further includes: When the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is not received, determine a third timestamp based on the second timestamp, the first time interval and n, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous sending cycle; The timestamp of the first chip when receiving the i-th pulse signal is updated to the third timestamp, so that the time of the first chip is synchronized with the time of the second chip.

5. A time synchronization method, executed by a second chip, characterized in that: The method comprises: During a sending cycle, a pulse signal is sent to the first chip every first time interval, wherein the second chip sends n pulse signals during the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

6. A time synchronization device, applied to a first chip, characterized in that: The device comprises: A receiving module, used to receive the i-th pulse signal sent by the second chip within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the i-th pulse signal is a pulse signal among the n pulse signals, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, the time interval between any two adjacent pulse signals within the sending cycle is a first time interval, i is an integer greater than 0, n is an integer greater than 1, and i is less than or equal to n; An updating module is used to update the time of the first chip according to the pulse width of the i-th pulse signal, so that the time of the first chip is synchronized with the time of the second chip.

7. The device according to claim 6, characterized in that The pulse width of the first pulse signal within the sending cycle is a first pulse width, and the update module is specifically used to update the time of the first chip based on the first timestamp and the pulse width of the i-th pulse signal when the pulse width of the i-th pulse signal is not equal to the first pulse width, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp sent by the second chip to the first chip, and the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

8. The device according to claim 6, characterized in that The pulse width of the first pulse signal within the sending cycle is the first pulse width. The update module is specifically used to update the timestamp of the first chip when receiving the i-th pulse signal to the first timestamp when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is received, so as to synchronize the time of the first chip with the time of the second chip, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle.

9. The device according to claim 6, characterized in that The pulse width of the first pulse signal in the sending period is a first pulse width, and the device further includes: a determination module, configured to determine a third timestamp based on a second timestamp, the first time interval, and n when the pulse width of the i-th pulse signal is equal to the first pulse width and the first timestamp sent by the second chip is not received, wherein the first timestamp is the timestamp when the second chip sends the first pulse signal to the first chip within the sending cycle, and the second timestamp is the timestamp corresponding to the first pulse signal in the previous sending cycle; The updating module is further used to update the timestamp of the first chip when receiving the i-th pulse signal to the third timestamp, so as to synchronize the time of the first chip with the time of the second chip.

10. A time synchronization device, applied to a second chip, characterized in that: The device comprises: A sending module is used to send a pulse signal to a first chip at every first time interval within a sending cycle, wherein the second chip sends n pulse signals within the sending cycle, the pulse widths of any two pulse signals within the sending cycle are different, and the pulse widths of the pulse signals are used to characterize the sending sequence number of the pulse signal within the sending cycle, and n is an integer greater than 1.

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