Two-step differential full parallel adc circuit, module for cis

Abstract

The present application relates to the technical field of CMOS image sensor design, and particularly relates to a two-step differential full-parallel ADC circuit and module for CIS.The present application provides a two-step differential full-parallel ADC circuit for CIS, which comprises a coarse quantization generating unit, a fine quantization generating unit, a comparator unit, a storage capacitor unit, a quantization switch unit, a logic control unit, a signal processing unit, a counter unit and an adder unit.The present application adopts two-step column-level differential full-parallel processing, divides the 11-bit quantization process into parallel 5-bit coarse quantization and 6-bit fine quantization, can effectively shorten the overall quantization time, and improve the data quantization rate of the ADC.The present application solves the problem of long quantization time, low conversion speed and limited CMOS image sensor frame frequency of the traditional SS ADC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of CMOS image sensor design, and more particularly, relates to: 1. A two-step differential full-parallel ADC circuit for CIS; 2. A two-step differential full-parallel ADC module for CIS. BACKGROUND

[0002] CMOS image sensors (CIS for short) are increasingly widely used in modern electronic devices, and their performance has a direct impact on the imaging effect of images, and a high-performance analog-to-digital converter (ADC for short) is a core part of a CMOS image sensor.

[0003] In general, the speed of a column-level ADC is better than that of a chip-level ADC, and the power consumption and area are better than those of a pixel-level ADC, and a good trade-off between speed, area, precision, and power consumption can be achieved, which is the mainstream architecture of ADCs in the readout circuit of a CMOS image sensor.

[0004] There are many types of commonly used column-level ADCs, mainly including SS ADC, SAR ADC, cyclic ADC, etc., each of which has different structural characteristics. Among them, SS ADC has a simple structure, low power consumption, small area, and can generate high-precision and high-linearity ramp signals, and is very suitable for application in column-level ADCs.

[0005] Today's CMOS image sensors are required to have high frame rates in a variety of practical application scenarios. However, the traditional SS ADC has low speed, and the time for a single quantization of an N-bit SS ADC is 2 N clock cycles, which results in a long quantization time and low conversion speed, thereby limiting the frame rate of the CMOS image sensor. SUMMARY

[0006] Therefore, it is necessary to provide a two-step differential full-parallel ADC circuit and module for CIS to solve the problem of long quantization time and low conversion speed of the traditional SS ADC, thereby limiting the frame rate of the CMOS image sensor.

[0007] The present application adopts the following technical solutions:

[0008] In a first aspect, the present application provides a two-step differential full-parallel ADC circuit for CIS, which is used for 11-bit quantization of a single-column pixel signal V IN .

[0009] The two-step differential full-parallel ADC circuit for CIS includes a coarse quantization generation unit DAC1, a fine quantization generation unit DAC2, a comparator unit, a storage capacitor unit, a quantization switch unit, a logic control unit Logic1, a signal processing unit Logic2, a counter unit, and an adder unit Adder.

[0010] The DAC1 is configured to provide a staircase ramp voltage signal RAMP_Coarse and serve as a coarse quantization ramp voltage.

[0011] The DAC2 is configured to provide a set of differential ramp voltage signals RAMP_Fine1-RAMP_Fine2 and serve as fine quantization ramp voltages.

[0012] The comparator unit is configured to compare V IN with RAMP_Coarse, RAMP_Fine1, and RAMP_Fine2. The comparator unit includes two comparators COMP1 and COMP2, whose inverting input terminals are connected to V IN , and whose non-inverting input terminals are connected to RAMP_Coarse, RAMP_Fine1, and RAMP_Fine2 through the storage capacitor unit and the quantization switch unit. REF The output terminal of COMP1 is configured to output a control signal CN1, and the output terminal of COMP2 is configured to output a control signal CN2.

[0013] The Logic1 is configured to control the quantization switch unit according to CN1.

[0014] The Logic2 is configured to generate control signals RB1, COUNT1, and COUNT2 according to CN1 and CN2.

[0015] The counter unit includes two counters Counter1 and Counter2. The Counter1 is configured to count 5-bit coarse quantization according to COUNT1, and the Counter2 is configured to count 6-bit fine quantization according to COUNT2.

[0016] The Adder is configured to process the count values of Counter1 and Counter2 according to a preset rule to obtain a final 11-bit quantization result according to RB1.

[0017] The two-step differential full-parallel ADC circuit for CIS is implemented according to the method or process of the embodiments of the present disclosure.

[0018] In a second aspect, the present disclosure discloses a two-step differential full-parallel ADC module for CIS, which adopts the layout of the two-step differential full-parallel ADC circuit for CIS disclosed in the first aspect.

[0019] This implementation of a two-step differential fully parallel ADC module for CIS is based on the method or process of an embodiment of this disclosure.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. This invention employs a two-step column-level differential fully parallel processing method, which decomposes the 11-bit quantization process into parallel 5-bit coarse quantization and 6-bit fine quantization, effectively shortening the overall quantization time and improving the data quantization rate of the ADC.

[0022] 2. This invention takes into account the possibility that the fine quantization reversal point may occur before the coarse quantization reversal point, and uses a differential ramp voltage signal for fine quantization to compensate for the missing quantization interval and ensure the accuracy of the quantization result.

[0023] 3. This invention also takes into account the errors caused by non-ideal factors such as the parasitic capacitance of the MOS transistor switch and the offset voltage of the comparator in the circuit. The counter for fine quantization is designed to be 7 bits, and a calibration rule based on redundant bits is used to eliminate errors and ensure the accuracy of the quantization results. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 The overall structure diagram of the two-step differential fully parallel ADC circuit for CIS provided by the present invention;

[0026] Figure 2 for Figure 1 Circuit diagram of DAC1;

[0027] Figure 3 for Figure 1 Circuit diagram of DAC2;

[0028] Figure 4 for Figure 1 Circuit diagram of Logic1;

[0029] Figure 5 for Figure 1 Circuit diagram of Logic2;

[0030] Figure 6 For the quantification process V IN, the signal waveform diagram of the coarse quantization slope voltage, the fine quantization slope voltage, CN1, and CN2;

[0031] Figure 7 the time diagram for 11-bit quantization without redundant calibration;

[0032] Figure 8 the time diagram for 11-bit quantization with redundant calibration;

[0033] Figure 9 the operation process diagram corresponding to the case that the fine quantization result of the upward slope is valid without redundant calibration;

[0034] Figure 10 the operation process diagram corresponding to the case that the fine quantization result of the downward slope is valid without redundant calibration;

[0035] Figure 11 the operation process diagram corresponding to the case that the fine quantization result of the upward slope is valid with redundant calibration;

[0036] Figure 12 the operation process diagram corresponding to the case that the fine quantization result of the downward slope is valid with redundant calibration. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0038] It should be noted that when a component is referred to as being "mounted on" another component, it can be directly on the other component or there can be a middle component. When a component is referred to as being "disposed on" another component, it can be directly disposed on the other component or there can be a middle component. When a component is referred to as being "fixed on" another component, it can be directly fixed on the other component or there can be a middle component.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Embodiment 1

[0041] Referring to Figure 1 , Figure 1 The overall structure of a two-step differential full-parallel ADC circuit for CIS is shown, which belongs to column-level ADC and is used for 11-bit quantization of single-column pixel signal V IN .

[0042] As Figure 1 shown, the two-step differential full-parallel ADC circuit for CIS includes a coarse quantization generation part DAC1, a fine quantization generation part DAC2, a comparator part, a storage capacitor part, a quantization switch part, a logic control part Logic1, a signal processing part Logic2, a counter part, and an adder part Adder.

[0043] The following are described one by one:

[0044] (1) DAC1 is used to provide a ladder ramp voltage signal RAMP_Coarse and serve as a coarse quantization ramp voltage.

[0045] DAC1 can adopt a design as Figure 2 :

[0046] DAC1 includes a counter Counter3, a decoder Decoder, an operational amplifier A0, a set of resistor string arrays, and a set of control switch arrays.

[0047] In general, Counter3 is a Gray code counter used to generate a 5-bit Gray code; Decoder converts the 5-bit Gray code into a binary code and controls the control switch arrays; the control switch arrays are placed between a high voltage VH and a low voltage VL, change the switch state under the control of Decoder, and cooperate with the resistor string arrays, pass through A0 connected in the form of unit negative feedback, and output RAMP_Coarse at the output end of A0.

[0048] The specific connection relationship is as follows:

[0049] The resistor string arrays include 32 resistors R_C1 to R_C 32 in series; the first end of R_C1 is connected to the high voltage VH; the second end of R_C 32 is connected to the low voltage VL; the first end of R_C x is connected to the second end of R_C x-1 , and the second end is connected to the first end of R_C x+1 ; x ∈ [2, 31].

[0050] The control switch arrays include 33 switches S_C1 to S_C 33 ; the first end of R_C y is connected to the high voltage VH through S_Cy Positive input of A0, second end through S_C y+1 Positive input of A0; y∈[1,32]

[0051] Output of Counter3 connects input of Decoder;

[0052] Decoder is used to generate control signals a1~a 33 ; wherein, a j is used to control opening or closing of S_C j ; j∈[1,33]

[0053] Output of A0 connects its negative input and outputs RAMP_Coarse.

[0054] Of course, DAC1 can also be other design, as long as it can generate RAMP_Coarse.

[0055] (II) DAC2 is used to provide a set of differential ramp voltage signals RAMP_Fine1~RAMP_Fine2, and as fine quantization ramp voltage.

[0056] DAC2 can adopt the design as follows: Figure 3

[0057] DAC2 includes: a set of current source array, a set of differential switch array, a load resistance sub-department, a segment decoder Segment_Decoder, an operational amplifier sub-department.

[0058] In general, the segment decoder generates control signals to control the differential switch array to realize the corresponding current source in the current source array output to the load resistance sub-department; the load resistance sub-department is divided into two branches, one of which is through the resistance R1 to complete the current to voltage conversion, and cooperates with the operational amplifier sub-department to generate the gradually rising ramp voltage signal RAMP_Fine1; the other branch passes through the load resistance R2, and cooperates with the operational amplifier sub-department to generate the gradually descending ramp voltage signal RAMP_Fine2.

[0059] The specific connection relationship is as follows:

[0060] The current source array includes: 18 current sources I0~I 17 ; wherein, I0 is a unit current source I, I1 is a 2 times current source 2I, I2 is a 4 times current source 4I, I3~I 17 are 8 times current sources 8I.

[0061] The differential switch array includes: 18 switches S_I0~S_I 17 ; S_I0~S_I 17 ​All are single-blade double-throw switches;

[0062] Wherein, I k The output end of S_I k Is connected to the fixed end of S_I k The moving end one is connected to RAMP_Fine1, and the moving end two is connected to RAMP_Fine2; k∈[0,7];

[0063] Segment_Decoder is used to generate control signals b0~b 17 ; Wherein, b k Is used to control the switching of S_I k ; It should be noted that b0~b2 are binary codes; b3~b 17 Are thermometer codes.

[0064] The load resistance sub-department includes: 2 resistors R1~R2; the first end of R1 is connected to RAMP_Fine1, and the first end of R2 is connected to RAMP_Fine2; the second end of R1 is connected to the second end of R2;

[0065] The operational amplifier sub-department includes: 1 operational amplifier A1, 1 capacitor C0, 1 NMOS tube N1; the positive input end of A1 is connected to the second end of R1, the first end of C0, and the drain level of N1; the negative input end of A1 is connected to the control voltage V0; the gate level of N1 is connected to the output end of A1, the drain is connected to the second end of C0, and the source level is grounded.

[0066] Of course, DAC1 can also be designed in other ways, as long as it can generate RAMP_Fine1 and RAMP_Fine2.

[0067] (Three) Comparator part is used to compare V IN With coarse quantization slope voltage and fine quantization slope voltage.

[0068] Referring to Figure 1 , the comparator part includes: 2 comparators COMP1~COMP2.

[0069] The inverting input end of COMP1, COMP2 is connected to V IN ;

[0070] The non-inverting input end of COMP1, COMP2 is connected to RAMP_Coarse, RAMP_Fine1, RAMP_Fine2, and reference voltage V REF Through the storage capacitor part and the quantization switch part.

[0071] Wherein, the quantization switch part includes: 6 switches S11, S22, S21, S22, S31, S32; the storage capacitor part includes: 2 storage capacitors C1~C2.

[0072] The first end of S11 and S12 is connected with RAMP_Coarse; the second end of S11 is connected with the in-phase input end of COMP1 and the first end of C1; the second end of S12 is connected with the in-phase input end of COMP2 and the first end of C2; the first end of S21 is connected with RAMP_Fine1, and the second end is connected with the second end of C1 and the first end of S31; the first end of S22 is connected with RAMP_Fine2, and the second end is connected with the second end of C2 and the first end of S32; the second end of S31 and S32 is connected with V REF .

[0073] It should be noted that the capacitance of C1 and C2 is the same, and is C.

[0074] The output end of COMP1 is used for outputting control signal CN1; the output end of COMP2 is used for outputting control signal CN2.

[0075] (Four) Logic1 is used for controlling the quantization switch part according to CN1.

[0076] Referring to Figure 4 , Logic1 comprises: 2 D flip-flops DFF5-DFF6, 2 inverters INV3-INV4, and 1 AND gate AND5.

[0077] Specifically, the clock input CLK end of DFF5 is connected with clock signal CK, the D end is connected with CN1, and the RB end is connected with reset signal RST; the clock input non-CLK end of DFF6 is connected with the Q end of DFF5, the D end is connected with digital power supply voltage VCC12, and the RB end is connected with reset signal RST; the input end of INV3 is connected with the Q end of DFF6; the input end one of AND5 is connected with the output end of INV3, the input end two is connected with switch total signal T0, and the output end outputs switch signal SC1; the input end of INV4 is connected with SC1, and the output end outputs switch signal SC2.

[0078] Among them, SC1 controls S11, S12, S31 and S32 to be disconnected or closed; SC2 controls S31 and S32 to be disconnected or closed.

[0079] (Five) Logic2 is used for generating control signals RB1, COUNT1 and COUNT2 according to CN1 and CN2.

[0080] Referring to Figure 5 , Logic2 comprises: 4 D flip-flops DFF1-DFF4, 3 AND gates AND1-AND3, and 1 OR gate OR.

[0081] Specifically, the RB end of DFF1 and DFF2 is connected with a reset signal RST; the clock input CLK end of DFF1 is connected with CN2, the D end and the Q non-end are connected; the input end one of AND1 is connected with the Q end of DFF1, and is recorded as a control signal CM2, the input end two is connected with CN1; the clock input CLK end of DFF2 is connected with the output end of AND1, the D end is connected with a digital power voltage VCC12, and the Q end outputs COUNT1; the clock input CLK non-end of DFF3 is connected with CN1, the D end is connected with VCC12, the RB end is connected with RB1, and the Q end outputs a control signal A1; the input end one of AND2 is connected with the Q non-end of DFF3, the input end two is connected with RST, and the output end outputs a control signal RB2; the clock input CLK non-end of DFF4 is connected with CM2, the D end is connected with VCC12, the RB end is connected with RB2, and the Q end outputs a control signal B1; the input end one of AND3 is connected with the Q non-end of DFF4, the input end two is connected with RST, and the output end outputs RB1; the input end one of OR is connected with A1, the input end two is connected with B1, and the output end outputs COUNT2.

[0082] (Six) The counter part includes two counters Counter1-Counter2. Counter1 is used for counting according to the 5-bit coarse quantization of COUNT1; and Counter2 is used for counting according to the 6-bit fine quantization of COUNT2.

[0083] As shown in Figure 1 , COUNT1 is connected with the control end of Counter1, and COUNT2 is connected with the control end of Counter2.

[0084] It should be noted that, since the 11-bit quantization process is decomposed into parallel 5-bit coarse quantization and 6-bit fine quantization; if no redundant calibration is needed, Counter1 can adopt a 5-bit counter, and Counter2 can adopt a 6-bit counter; if redundant calibration is needed, Counter1 can adopt a 5-bit counter, and Counter2 can adopt a 7-bit counter.

[0085] (Seven) Adder is used for data processing on the counting values of Counter1 and Counter2 according to a preset rule based on RB1, to obtain the final 11-bit quantization result (i.e. OUT<10:0>).

[0086] As shown in Figure 1 , the input end one of Adder is connected with the output end of Counter1, the input end two is connected with the output end of Counter2, and the control end is connected with RB1.

[0087] The two-step differential full-parallel ADC circuit for CIS based on the above structure works as follows:

[0088] First, T0 is kept high, SC1 is high and SC2 is low, S11, S12, S31 and S32 are closed, S21 and S22 are open, RAMP_Coarse, RAMP_Fine1 and RAMP_Fine2 start simultaneously, and Counter1 and Counter2 also start counting simultaneously.

[0089] The voltage at the first terminals of C1 and C2 rises with RAMP_Coarse, and this voltage is fed into the non-inverting input terminals of COMP1 and COMP2; the inverting input terminals of COMP1 and COMP2 are connected to V. IN ;

[0090] Initially, CN1 and CN2 are at low level;

[0091] When RAMP_Coarse is greater than V IN When CN1 and CN2 toggle and output a high level, Counter1 stops counting, and the 5-bit coarse quantization is complete; at this time, the voltage at the first terminal of C1 and C2 is V. REF +m*MSB; m represents the count value of Counter1 at this time, and MSB represents the most significant bit.

[0092] CN1 is processed by Logic1, which switches SC1 to low level and SC2 to high level, opens S11, S12, S31, and S32, and closes S21 and S22. RAMP_Fine1 connects to the second terminal of C1, and RAMP_Fine2 connects to the second terminal of C2. The voltage values ​​at the first terminals of C1 and C2 will follow the changes in the fine quantization ramp voltage based on the voltage value when coarse quantization is completed. Counter2 continues to count and continues to perform fine quantization.

[0093] Since RAMP_Fine1 and RAMP_Fine2 are a pair of differential ramps, the voltage at the non-inverting input of COMP1 is based on the voltage value when coarse quantization is completed, and the ramp decreases; the voltage at the non-inverting input of COMP2 is based on the voltage value when coarse quantization is completed, and the ramp increases.

[0094] It should be noted that, according to V IN Due to differences, the following four situations may occur during the quantization process, as illustrated in the quantization diagram and the corresponding output waveforms of CN1 and CN2, such as... Figure 6 As shown:

[0095] Case 1: V IN Located above MSB / 2 in a coarse quantization voltage range, and intersecting only with the fine quantization upslope, such as... Figure 6 As shown in (a).

[0096] Case 2: V IN MSB / 2, and has intersection with both fine quantization upward and downward slope, but the intersection of downward slope is earlier than that of upward slope, as shown in Figure 6 (b).

[0097] Case 3: V IN MSB / 2, and has intersection with both fine quantization upward and downward slope, but the intersection of upward slope is earlier than that of downward slope, as shown in Figure 6 (c).

[0098] Case 4: V IN MSB / 2, and has intersection with both fine quantization upward and downward slope, but the intersection of upward slope is earlier than that of downward slope, as shown in Figure 6 (d).

[0099] When CN1 flips from high level to low level, the fine quantization downward slope ends; when CN2 flips from low level to high level, the fine quantization upward slope ends; at this time, the charge amount stored by C1 and C2 is m*MSB*C; wherein the first end voltage value of C1 is V REF +m*MSB-n*LSB; the first end voltage value of C2 is V REF +(m-1)*MSB+n*LSB; n represents the count value of Counter2 at this time, and LSB represents the least significant bit.

[0100] In the fine quantization process, by detecting RB1, it is determined whether the upward or downward slope fine quantization result is valid, and then the count value of Counter1 and Counter2 is processed according to different cases, so as to obtain the final result of 11-bit quantization.

[0101] Specifically, RB1 reflects the falling edge flip time of CN1 and CM2, which can be used for judgment:

[0102] 1. If RB1 changes from high level to low level, i.e. CN1 falls first, it is determined that the upward slope fine quantization result is valid.

[0103] 2. If RB1 remains high level, i.e. CM2 signal falls first, it is determined that the downward slope fine quantization result is valid.

[0104] If the error caused by non-ideal factors such as parasitic capacitance of MOS switch in the circuit and offset voltage of comparator is not considered, there is no need to perform redundant calibration. Referring to Figure 7 In this case, the overall 11-bit quantization time is shortened to 2 6T; where T represents a clock cycle. In this case, Counterl is a 5-bit counter and Counter2 is a 6-bit counter, and the corresponding preset rule is designed as follows:

[0105] ① When the upward sloping fine quantization result is valid, the low bits of the count value of Counterl are padded with zeros to obtain code value P1, and the high bits of the count value of Counter2 are padded with zeros to obtain code value P2. Then, P1 and P2 are added to obtain code value P3.

[0106] P1 = d H10 d H9 d H8 d H7 d H6 000000; P2 = 00000d L5 d L4 d L3 d L2 d L1 d L0 ;

[0107] P3 = D 10 D9D8D7D6D5D4D3D2D1D0.

[0108] P1 = d H10 ~ d H6 represents the 5 bits of the count value of Counterl; d L5 d L4 d L3 d L2 d L1 d L0 represents the 6 bits of the count value of Counter2; D 10 ~ D0 represents the 11 bits of the final 11-bit quantization result.

[0109] For the convenience of understanding, the operation process of ① can be referred to Figure 9 .

[0110] ② When the downward sloping fine quantization result is valid, the low bits of the count value of Counterl are padded with zeros, and then 0000100000 is added to obtain code value P4. The high bits of the count value of Counter2 are padded with zeros, and then 00000000001 is added to obtain code value P5. Then, P5 is inverted first, and then added to P4 to obtain code value P6.

[0111] P4 = d H10 d H9 d H8 d H7 d H6 000000 + 00001000000;

[0112] P5 = 00000d L5 d L4 d L3 d L2 d L1 d L0 +000000000001;

[0113] P6=D 10 D9D8D7D6D5D4D3D2D1D0.

[0114] Where, d H10 ~d H6 The 5-digit representation of the Counter1 count value; d L5 d L4 d L3 d L2 d L1 d L0 The 6-bit representation of the Counter2 count value; D 10 ~D0 represents the 11 bits of the final 11-bit quantization result.

[0115] For easier understanding, please refer to the calculation process in step ②. Figure 10 .

[0116] Of course, to further ensure the accuracy of the 11-bit quantization result, errors caused by non-ideal factors such as the parasitic capacitance of the MOSFET switches and the offset voltage of the comparator must be considered, requiring redundant calibration; see [link to relevant documentation]. Figure 8 In this case, the overall quantization time for 11 bits is reduced to 2. 6 T+ΔT; where T represents the clock cycle; ΔT represents the redundancy calibration time. In this case, Counter1 uses a 5-bit counter and Counter2 uses a 7-bit counter, with the corresponding preset rules designed as follows:

[0117] ③ When the upward ramp refinement result is valid, first pad the low bits of Counter1's count value with zeros to obtain the code value Q1, and pad the high bits of Counter2's count value with zeros to obtain the code value Q2; then add Q1 and Q2 to obtain Q3.

[0118] Where Q1=d H10 d H9 d H8 d H7 d H6 000000; Q2 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 ;

[0119] Q3 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0.

[0120] wherein d H10 ~ d H6 represents the 5 bits of the count value of Counterl; d L6 d L5 d L4 d L3 d L2 d L1 d L0 represents the 7 bits of the count value of Counter2; D 10 ~ D0 represents the 11 bits of the final 11-bit quantization result.

[0121] For the convenience of understanding, the operation process of ③ can refer to Figure 11 .

[0122] ④ When the downward sloping fine quantization result is valid, the count value of Counterl is first zero-filled in the low bits and then added by 0000100000 to obtain the code value Q4, the count value of Counter2 is first zero-filled in the high bits and then added by 00000000001 to obtain the code value Q5, and then Q5 is first inverted and then added by Q4 to obtain the code value Q6.

[0123] wherein Q4 = d H10 d H9 d H8 d H7 d H6 000000 + 00001000000;

[0124] Q5 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 + 00000000001;

[0125] Q6 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0.

[0126] wherein d H10 ~ d H6 represents the 5 bits of the count value of Counterl; d L6 d L5 d L4 d L3 d L2 d L1 d L0 represents the 7 bits of the count value of Counter2; D10 ~D0 represents the 11th bit of the final 11-bit quantization result.

[0127] For the convenience of understanding, the operation process of ④ can refer to Figure 12 .

[0128] Embodiment 2

[0129] The embodiment 2 discloses a two-step differential full-parallel ADC module for CIS, which adopts the layout of the two-step differential full-parallel ADC circuit for CIS disclosed in the embodiment 1. The mode of packaging into a module is more conducive to the promotion and application of the above-mentioned circuit.

[0130] The two-step differential full-parallel ADC module for CIS includes a coarse quantization generation module (i.e. corresponding to DAC1), a fine quantization generation module (i.e. corresponding to DAC2), a comparator module (i.e. corresponding to the comparator part), a storage capacitor module (i.e. corresponding to the storage capacitor part), a quantization switch module (i.e. corresponding to the quantization switch part), a logic control module (i.e. corresponding to Logic1), a signal processing module (i.e. corresponding to Logic2), a counter module (i.e. corresponding to the counter part), and an adder module (i.e. corresponding to the Adder). For specific circuit distribution, please refer to the embodiment 1, which will not be repeated here.

[0131] The embodiment 2 also discloses a CMOS image sensor simultaneously, which adopts the above-mentioned two-step differential full-parallel ADC module for CIS.

[0132] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above-mentioned embodiments are not described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present disclosure.

[0133] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of variations and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A two-step differential full parallel ADC circuit for CIS for 11 bit quantization of single column pixel signal V IN The two-step differential full-parallel ADC circuit for CIS comprises: ​ a coarse quantization generation unit DAC1 for providing a ladder ramp voltage signal RAMP_Coarse as a coarse quantization ramp voltage; a fine quantization generation unit DAC2 for providing a group of differential ramp voltage signals RAMP_Fine1~RAMP_Fine2 as fine quantization ramp voltages; a storage capacitor unit; a quantization switch unit; a comparator section for comparing V IN with the coarse quantization ramp voltage, the fine quantization ramp voltage; the comparator section comprises: 2 comparators COMP1~COMP2; the inverting input terminals of COMP1, COMP2 are connected with V IN ; the non-inverting input terminals of COMP1, COMP2 are connected with RAMP_Coarse, RAMP_Fine1, RAMP_Fine2, reference voltage V REF through a storage capacitor section, a quantization switch section; the output terminal of COMP1 is used for outputting a control signal CN1; the output terminal of COMP2 is used for outputting a control signal CN2; a logic control unit Logic1 for controlling the quantization switch unit according to CN1; a signal processing unit Logic2 for generating control signals RB1, COUNT1, and COUNT2 according to CN1 and CN2; a counter unit comprising two counters Counter1~Counter2, Counter1 for counting 5-bit coarse quantization according to COUNT1, and Counter2 for counting 6-bit fine quantization according to COUNT2; and an adder unit Adder for performing data processing on the counting values of Counter1 and Counter2 according to RB1 in a preset rule to obtain a final 11-bit quantization result; wherein Logic2 comprises four D flip-flops DFF1~DFF4, three AND gates AND1~AND3, and one OR gate OR; the RB terminals of DFF1 and DFF2 are connected to a reset signal RST; the clock input CLK terminal of DFF1 is connected to CN2, and the D terminal and the Q nonterminal are connected; the input terminal one of AND1 is connected to the Q terminal of DFF1 and is denoted as a control signal CM2, and the input terminal two is connected to CN1; the clock input CLK terminal of DFF2 is connected to the output terminal of AND1, the D terminal is connected to a digital power supply voltage VCC12, and the Q terminal outputs COUNT1; the clock input CLK nonterminal of DFF3 is connected to CN1, the D terminal is connected to VCC12, the RB terminal is connected to RB1, and the Q terminal outputs a control signal A1; the input terminal one of AND2 is connected to the Q nonterminal of DFF3, the input terminal two is connected to RST, and the output terminal outputs a control signal RB2; the clock input CLK nonterminal of DFF4 is connected to CM2, the D terminal is connected to VCC12, the RB terminal is connected to RB2, and the Q terminal outputs a control signal B1; the input terminal one of AND3 is connected to the Q nonterminal of DFF4, the input terminal two is connected to RST, and the output terminal outputs RB1; the input terminal one of OR is connected to A1, the input terminal two is connected to B1, and the output terminal outputs COUNT2.

2. The two-step differential fully parallel ADC circuit for CIS according to claim 1, wherein, the quantization switch unit comprises six switches S11, S22, S21, S22, S31, and S32; the storage capacitor unit comprises two storage capacitors C1~C2; the first terminals of S11 and S12 are connected to RAMP_Coarse; the second terminal of S11 is connected to the noninverting input terminal of COMP1 and the first terminal of C1; the second terminal of S12 is connected to the noninverting input terminal of COMP2 and the first terminal of C2; the first terminal of S21 is connected to RAMP_Fine1, and the second terminal is connected to the second terminal of C1 and the first terminal of S31; The first end of S22 is connected with RAMP_Fine2, and the second end is connected with the second end of C2 and the first end of S32; The second end of S31, S32 is connected to V REF .

3. The two-step differential fully parallel ADC circuit for CIS according to claim 2, wherein, Logic1 comprises: 2 D flip-flops DFF5~DFF6, 2 inverters INV3~INV4, and 1 AND gate AND5; The clock input CLK end of DFF5 is connected with the clock signal CK, the D end is connected with CN1, and the RB end is connected with the reset signal RST; The clock input non-CLK end of DFF6 is connected with the Q end of DFF5, the D end is connected with the digital power supply voltage VCC12, and the RB end is connected with the reset signal RST; The input end of INV3 is connected with the Q end of DFF6; The input end one of AND5 is connected with the output end of INV3, the input end two is connected with the switch total signal T0, and the output end outputs the switch signal SC1; The input end of INV4 is connected with SC1, and the output end outputs the switch signal SC2; SC1 controls S11, S12, S31 and S32 to be disconnected or closed; SC2 controls S31 and S32 to be disconnected or closed.

4. The two-step differential fully parallel ADC circuit for CIS according to claim 1, wherein, If RB1 changes from high level to low level, it is judged that the upward slope fine quantization result is valid; If RB1 keeps high level, it is judged that the downward slope fine quantization result is valid.

5. The two-step differential fully parallel ADC circuit for CIS according to claim 4, wherein, If Counter1 is a 5-bit counter and Counter2 is a 6-bit counter, the preset rule is as follows: When the upward slope fine quantization result is valid, the low bits of the count value of Counter1 are zero-padded to obtain code value P1, and the high bits of the count value of Counter2 are zero-padded to obtain code value P2; then P1 and P2 are added to obtain code value P3; wherein P1 = d H10 d H9 d H8 d H7 d H6 000000; P2 = 00000d L5 d L4 d L3 d L2 d L1 d L0 ; P3 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0; When the downward slope fine quantization result is valid, the low bits of the count value of Counter1 are zero-padded, and then 0000100000 is added to obtain code value P4, the high bits of the count value of Counter2 are zero-padded, and then 00000000001 is added to obtain code value P5; then P5 is inverted first, and then added to P4 to obtain code value P6; P4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000; P5=00000d L5 d L4 d L3 d L2 d L1 d L0 +00000000001; P6 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0; wherein d H10 ~d H6 d represents 5 bits of the count value of Counterl; d L5 d L4 d L3 d L2 d L1 d L0 D represents 6 bits of the count value of Counter2; D 10 ~D0 represents 11 bits of the final 11-bit quantization result.

6. The two-step differential fully parallel ADC circuit for CIS according to claim 4, wherein, If Counter1 is a 5-bit counter and Counter2 is a 7-bit counter, the preset rule is as follows: When the upward slope fine quantization result is valid, the low bits of the count value of Counter1 are zero-padded to obtain code value Q1, and the high bits of the count value of Counter2 are zero-padded to obtain code value Q2; then Q1 and Q2 are added to obtain Q3; wherein Q1 = d H10 d H9 d H8 d H7 d H6 000000; Q2 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 ; Q3 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0; When the downward slope fine quantization result is valid, the low bits of the count value of Counter1 are zero-padded, and then 0000100000 is added to obtain code value Q4, the high bits of the count value of Counter2 are zero-padded, and then 00000000001 is added to obtain code value Q5; then Q5 is inverted first, and then added to Q4 to obtain code value Q6; wherein Q4 = d H10 d H9 d H8 d H7 d H6 000000+00001000000; Q5 = 0000d L6 d L5 d L4 d L3 d L2 d L1 d L0 +00000000001; Q6 = D 10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0; wherein d H10 d H6 d L6 d L5 d L4 d L3 d L2 d L1 d L0 d 10 ~D0 represents 11 bits of the final 11-bit quantization result.

7. The two-step differential fully parallel ADC circuit for CIS according to claim 1, wherein, DAC1 comprises: 1 counter Counter3, 1 decoder Decoder, 1 operational amplifier A0, 1 set of resistance string arrays, and 1 set of control switch arrays; The resistance string array includes 32 resistances R_C1~R_C 32 in series; wherein the first end of R_C1 is connected to a high level VH; the second end of R_C 32 is connected to a low level VL; the first end of R_C x is connected to the second end of R_C x-1 , and the second end of R_C x+1 is connected to the first end of R_C x∈[2,31] The control switch array includes 33 switches S_C1~S_C 33 ; where R_C y The first end is through S_C y Connect the positive input terminal of A0, and the second terminal is connected through S_C. y+1 Connect the positive input terminal of A0; y∈[1,32]; The output end of Counter3 is connected with the input end of Decoder; Decoder is used to generate control signal a1~a 33 ; wherein a j is used to control the opening or closing of S_C j ; j∈[1,33] The output end of A0 is connected with its negative input end, and outputs RAMP_Coarse.

8. The two-step differential fully parallel ADC circuit for CIS according to claim 1, wherein, The DAC2 comprises: a set of current source arrays, a set of differential switch arrays, a load resistor subunit, a segment decoder, and an operational amplifier subunit; The current source array comprises: 18 current sources I0~I 17 ; wherein I0 is a unit current source I, I1 is a 2 times current source 2I, I2 is a 4 times current source 4I, I3~I 17 are all 8 times current sources 8I; The differential switch array comprises 18 switches S_I0~S_I 17 ; S_I0~S_I 17 , all of which are single-pole double-throw switches. where I k the output of S_I k is connected to the non-moving end of S_I k ; the moving end one of S_I k is connected to RAMP_Fine1, and the moving end two is connected to RAMP_Fine2; k ∈ [0, 7] Segment_Decoder is used to generate control signals b0~b 17 ; wherein b k is used to control the switching of S_I k ; The load resistor subunit comprises: two resistors R1 and R2; a first end of the R1 is connected to the RAMP_Fine1, and a first end of the R2 is connected to the RAMP_Fine2; a second end of the R1 is connected to a second end of the R2; The operational amplifier subunit comprises: an operational amplifier A1, a capacitor C0, and an NMOS transistor N1; a positive input end of the A1 is connected to the second end of the R1, a first end of the C0, and a drain of the N1; a negative input end of the A1 is connected to a control voltage V0; a gate of the N1 is connected to an output end of the A1, a drain is connected to a second end of the C0, and a source is grounded.

9. A two-step differential full parallel ADC module for CIS, characterized in that, The layout of the two-step differential full-parallel ADC circuit for CIS is adopted, and the layout is as claimed in any one of claims 1-8.

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