Storage unit, memory and preparation method thereof

Abstract

The present disclosure relates to a memory cell, a memory, and a method for preparing the same. In the memory cell, the semiconductor layer is in the form of a closed ring; the region within the ring of the semiconductor layer includes a first region and a second region that are insulated and isolated in a first direction. The semiconductor layer includes: a first semiconductor portion surrounding a portion of the boundary of the first region, and a second semiconductor portion surrounding a portion of the boundary of the second region. The first gate is located within the first region. The two second gates are located on two sides of the first semiconductor portion that are opposite to the first gate and in a second direction; the second direction intersects the first direction. The contact electrode conformally covers the inner sidewall of the second semiconductor portion. The first electrode is located within the second region and is insulated from the contact electrode. The second electrode is located on the outside of the second semiconductor portion that is away from the first electrode along the first and second directions and is insulated from the second semiconductor portion. The present disclosure is conducive to improving the storage density, storage capacity, and electrical performance and reliability of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of a number of memory cells arranged in an array. The memory cell may adopt a 1T1C architecture, for example, comprising a transistor and a capacitor.

[0003] Currently, with the increasing demand for memory capacity, memory cells are being arranged in three dimensions. However, the scalability issues and complex manufacturing processes of 1T1C architecture memory cells can easily degrade the electrical performance of memory cells when the size is further reduced, making it difficult to further reduce the size of memory cells while maintaining their electrical performance. Summary of the Invention

[0004] Based on this, the embodiments of the present disclosure provide a memory cell, a memory and a method for manufacturing the same, so as to improve the storage density, storage capacity, electrical performance and reliability of the memory.

[0005] On the one hand, an embodiment of the present disclosure provides a memory cell comprising: a semiconductor layer, a first gate, two second gates, a contact electrode, a first dielectric layer, a first electrode, a second dielectric layer, and a second electrode. The semiconductor layer is in the shape of a closed ring; the region within the ring of the semiconductor layer comprises a first region and a second region that are insulated and isolated in a first direction. The semiconductor layer comprises: a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region. The first gate is located within the first region. The two second gates are located on opposite sides of the first semiconductor portion, facing away from the first gate and in a second direction; the second direction intersects the first direction. The contact electrode conformally covers the inner sidewalls of the second semiconductor portion. The first electrode is located within the second region. The first dielectric layer covers the sidewalls of the first electrode and conformally covers the inner sidewalls of the contact electrode. The second electrode is located on the outer side of the second semiconductor portion, facing away from the first electrode along the first and second directions. The second dielectric layer is located between the second semiconductor portion and the second electrode and conformally covers a portion of the outer sidewalls of the second semiconductor portion. The second electrode conformally covers the outer sidewalls of the second dielectric layer.

[0006] According to some embodiments, the second gate includes a first sub-gate and a second sub-gate stacked in the second direction away from the first semiconductor portion and made of different materials.

[0007] According to some embodiments, the first sub-gate is a polysilicon gate, and the second sub-gate and the first gate are metal gates.

[0008] According to some embodiments, the second electrode includes: a first sub-electrode and two second sub-electrodes. The first sub-electrode conformally covers an outer sidewall of the second dielectric layer. The two second sub-electrodes respectively cover outer sidewalls of the first sub-electrode that face away from the second dielectric layer and are opposite in the second direction.

[0009] According to some embodiments, the first sub-electrode is a polysilicon electrode, the second sub-electrode is a metal electrode, and the first electrode and the second sub-electrode are electrically connected.

[0010] According to some embodiments, the memory cell further includes: a first isolation structure and two second isolation structures. The first isolation structure is located between the first region and the second region. The two second isolation structures are respectively located between the corresponding second gate and the second electrode. The first isolation structure and the second isolation structure are staggered in the first direction.

[0011] In another aspect, embodiments of the present disclosure further provide a memory device comprising: at least one memory cell as described in any of the preceding embodiments, at least one bit line, and at least one word line. The bit line extends along a second direction and is electrically connected to an outer sidewall of a first semiconductor portion of the memory cell that faces away from the first gate and extends along the second direction. The word line is electrically connected to the first gate and two second gates of the memory cell.

[0012] According to some embodiments, there are a plurality of memory cells, and the memory cells are arranged in a row along a third direction, the third direction intersecting the first direction and the second direction in pairs, wherein the memory cells in a row share the same word line.

[0013] On the other hand, an embodiment of the present disclosure further provides a method for preparing a memory, comprising the following steps.

[0014] A stacked structure is formed, wherein the stacked structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers that are alternately stacked.

[0015] The stack structure is etched along a stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0016] A semiconductor layer is formed on the inner sidewall of the second sacrificial layer within the first receiving hole. The semiconductor layer is in a closed ring shape, and the region within the ring includes a first region and a second region insulated and isolated from each other in a first direction. The semiconductor layer includes a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region.

[0017] A first gate is formed in the first region.

[0018] Second gates are formed on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in a second direction. The second direction intersects the first direction.

[0019] A contact electrode is formed in the second region to conformally cover the inner sidewall of the second semiconductor portion.

[0020] A first dielectric layer in a closed ring shape is formed in the second region to conformally cover the inner sidewall of the contact electrode.

[0021] A first electrode is formed in the inner ring area of ​​the first dielectric layer.

[0022] A second dielectric layer is formed on an outer sidewall of the second semiconductor portion away from the first electrode along the first direction and the second direction.

[0023] A second electrode is formed on an outer sidewall of the second dielectric layer away from the second semiconductor portion.

[0024] According to some embodiments, the second gate and the second electrode are formed simultaneously.

[0025] According to some embodiments, the second gate includes: a first sub-gate and a second sub-gate stacked in a second direction away from the first semiconductor portion and made of different materials. The second electrode includes: a first sub-electrode conformally covering an outer sidewall of the second semiconductor portion, and a second sub-electrode respectively covering outer sidewalls of the first sub-electrode facing away from the second semiconductor portion and opposite in the second direction.

[0026] The etching of the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form the first accommodating hole includes: etching the stacked structure to form two first accommodating areas extending along the first direction and spaced apart in the second direction; forming a third sacrificial layer in the first accommodating area; etching the stacked structure between the two first accommodating areas to form the first accommodating hole.

[0027] The method for preparing the memory further includes: etching the stack structure to form a first isolation trench, so as to separate the stack structure into a first section located on a side of the first semiconductor portion away from the first gate and a second section located on a side of the second semiconductor portion away from the first electrode through the first isolation trench.

[0028] Correspondingly, the second gates are formed on both sides of the first semiconductor portion that are away from the first gate and opposite to each other in the second direction, including: removing at least a portion of the third sacrificial layer near the first semiconductor portion in the first sub-portion to form a second accommodating hole, while making the second sacrificial layer retained in the first sub-portion between the first semiconductor portion and the second accommodating hole constitute a first sub-gate; forming a second sub-gate and a word line connected to the second sub-gate in the second accommodating hole.

[0029] The second electrode is formed on the outer wall of the second dielectric layer away from the second semiconductor part, including: removing at least a portion of the third sacrificial layer in the second section close to the second semiconductor part along the second direction to form a third accommodating hole, and at the same time making the second sacrificial layer in the second section conformally covering the outer wall of the second semiconductor part constitute a first sub-electrode; forming a second sub-electrode in the third accommodating hole.

[0030] According to some embodiments, the method for preparing the memory further includes the following steps.

[0031] While etching the stack structure to form the first isolation trench, a second isolation trench is formed to separate a third section located on the side of the first section away from the second section in the stack structure through the second isolation trench; the second sacrificial layer in the third section is connected to the outer side wall of the first semiconductor section away from the first gate and extending along the second direction.

[0032] The second sacrificial layer in the third section is removed to form a bit line accommodating groove.

[0033] A bit line is formed in the bit line receiving groove.

[0034] According to some embodiments, forming a semiconductor layer on an inner sidewall of a second sacrificial layer in a first receiving hole includes the following steps.

[0035] A dielectric material layer is formed to conformally cover the wall of the first receiving hole.

[0036] A fourth sacrificial layer is formed to cover the inner sidewall of the dielectric material layer and fill the first receiving hole.

[0037] A portion of the fourth sacrificial layer and a portion of the dielectric material layer close to the first end of the first accommodating hole in the first direction are removed to expose a portion of the hole wall of the first accommodating hole.

[0038] The remaining fourth sacrificial layer is removed.

[0039] A semiconductor material layer is formed to conformally cover the inner sidewall of the remaining dielectric material layer and the exposed hole wall of the first receiving hole.

[0040] The outer sidewall of the first sacrificial layer extending along the second direction is etched until the semiconductor material layer is exposed.

[0041] The semiconductor material layer is etched based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0042] The outer sidewall of the first sacrificial layer extending along the first direction is etched until the initial semiconductor layer is exposed.

[0043] The initial semiconductor layer is etched based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

[0044] According to some embodiments, before etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the method for manufacturing the memory further includes the following steps.

[0045] A fifth sacrificial layer is formed to cover the inner sidewall of the semiconductor material layer and fill the first receiving hole.

[0046] A first portion of the fifth sacrificial layer close to the first end of the first receiving hole is removed to expose the first region, so as to form a first gate in the first region.

[0047] After forming the first gate, a second portion of the fifth sacrificial layer near the second end of the first receiving hole in the first direction is removed to expose the second region. The first end and the second end are two opposite ends of the fifth sacrificial layer in the first direction.

[0048] A contact electrode material layer is formed in the second region to conformally cover the inner sidewall of the semiconductor material layer and the remaining sidewall of the fifth sacrificial layer, and a sixth sacrificial layer is formed to cover the inner sidewall of the contact electrode material layer and fill the second region.

[0049] The remaining fifth sacrificial layer is removed.

[0050] The contact electrode material layer is etched based on the removed area of ​​the fifth sacrificial layer, so that the contact electrode material layer conformally covering the inner sidewall of the second semiconductor portion forms a contact electrode.

[0051] A first isolation structure is formed in the removed area of ​​the fifth sacrificial layer and the contact electrode material layer.

[0052] According to some embodiments, forming a first dielectric layer in a closed ring shape in the second region that conformally covers the inner sidewall of the contact electrode and forming a first electrode in the region inside the ring of the first dielectric layer includes the following steps.

[0053] The sixth sacrificial layer is removed.

[0054] A first dielectric layer is formed conformally covering the inner sidewall of the contact electrode and the sidewall of the first isolation structure close to the contact electrode.

[0055] A first electrode is formed to cover the inner sidewall of the first dielectric layer and fill the sixth sacrificial layer removed area.

[0056] The embodiments of the present disclosure may or may have at least the following advantages:

[0057] In an embodiment of the present disclosure, the semiconductor layer of the transistor is arranged in a closed ring shape, and the area within the ring of the semiconductor layer is divided into a first area and a second area that are insulated and isolated in the first direction. In this way, a first gate can be arranged in the first area, and a second gate can be arranged on both sides of the first gate along the second direction outside the semiconductor layer, so as to increase the turn-on current of the transistor and reduce the leakage current. In addition, a contact electrode and a first electrode of the capacitor can be arranged in the second area, and a second electrode can be arranged on the side of the contact electrode facing away from the first electrode outside the semiconductor layer, so as to increase the storage capacity of the capacitor. Therefore, the memory cell in the embodiment of the present disclosure adopts the above-mentioned structure, which not only helps to improve the space utilization of the memory cell to effectively reduce the planar area of ​​a single memory cell, but also increases the thickness of the semiconductor layer to help increase the turn-on current of the transistor and reduce the leakage current, and helps to increase the storage capacity of the capacitor. This helps to improve the storage density and storage capacity of the memory, and ensures that the memory cell has better electrical performance and reliability, so as to improve the electrical performance and reliability of the memory.

[0058] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 A schematic diagram of a three-dimensional structure of a storage unit provided in some embodiments;

[0061] Figure 2 is a schematic top view of a storage unit provided in some embodiments;

[0062] Figure 3 A schematic diagram of the structure of a memory provided in some embodiments;

[0063] Figure 4 A schematic flow chart of a method for preparing a memory provided in some embodiments;

[0064] Figure 5 A schematic structural diagram of a structure obtained after forming a stacked structure provided in some embodiments;

[0065] Figure 6A schematic structural diagram of a structure obtained after forming a first accommodating area provided in some embodiments;

[0066] Figure 7 is a schematic structural diagram of a structure obtained after forming a third sacrificial layer provided in some embodiments;

[0067] Figure 8 A schematic structural diagram of a structure obtained after forming a first receiving hole provided in some embodiments;

[0068] Figure 9 is a schematic structural diagram of a structure obtained after forming a first dielectric material layer provided in some embodiments;

[0069] Figure 10 is a schematic structural diagram of a structure obtained after forming a fourth sacrificial layer provided in some embodiments;

[0070] Figure 11 A schematic structural diagram of a structure obtained after a portion of the fourth sacrificial layer is removed, provided in some embodiments;

[0071] Figure 12 A schematic structural diagram of a structure obtained after forming a semiconductor material layer provided in some embodiments;

[0072] Figure 13 is a schematic structural diagram of a structure obtained after forming a fifth sacrificial layer provided in some embodiments;

[0073] Figure 14 A schematic structural diagram of a structure obtained after forming a first region provided in some embodiments;

[0074] Figure 15 A schematic structural diagram of a structure obtained after forming a first gate dielectric layer provided in some embodiments;

[0075] Figure 16 A schematic structural diagram of a structure obtained after forming a first gate provided in some embodiments;

[0076] Figure 17 A schematic structural diagram of a structure obtained after forming a second region provided in some embodiments;

[0077] Figure 18 A schematic structural diagram of a structure obtained after forming a contact electrode material layer provided in some embodiments;

[0078] Figure 19 is a schematic structural diagram of a structure obtained after forming a sixth sacrificial layer provided in some embodiments;

[0079] Figure 20is a schematic structural diagram of a structure obtained after removing the remaining fifth sacrificial layer provided in some embodiments;

[0080] Figure 21 A schematic structural diagram of a structure obtained after forming a first isolation structure provided in some embodiments;

[0081] Figure 22 A schematic structural diagram of a structure obtained after etching the outer sidewall of the first sacrificial layer extending along the second direction, provided in some embodiments;

[0082] Figure 23 A schematic structural diagram of a structure obtained after forming an initial semiconductor layer provided in some embodiments;

[0083] Figure 24 A schematic structural diagram of a structure obtained after backfilling the etched regions of the first sacrificial layer and the semiconductor material layer with insulating material provided in some embodiments;

[0084] Figure 25 is a schematic structural diagram of a structure obtained after removing the third sacrificial layer provided in some embodiments;

[0085] Figure 26 A schematic structural diagram of a structure obtained after etching the outer sidewall of the first sacrificial layer extending along the first direction, provided in some embodiments;

[0086] Figure 27 A schematic structural diagram of a structure obtained after forming a semiconductor layer and a contact electrode provided in some embodiments;

[0087] Figure 28 A schematic structural diagram of a structure obtained after re-forming a third sacrificial layer provided in some embodiments;

[0088] Figure 29 A schematic structural diagram of a structure obtained after forming a first isolation trench and a second isolation trench provided in some embodiments;

[0089] Figure 30 A schematic structural diagram of a structure obtained after forming a second isolation structure and a third isolation structure provided in some embodiments;

[0090] Figure 31 A schematic structural diagram of a structure obtained after forming a second accommodating hole and a third accommodating hole provided in some embodiments;

[0091] Figure 32 A schematic structural diagram of a structure obtained after forming a second sub-gate, a second word line, and a second sub-electrode provided in some embodiments;

[0092] Figure 33 is a schematic structural diagram of a structure obtained after removing the sixth sacrificial layer provided in some embodiments;

[0093] Figure 34 A schematic structural diagram of a structure obtained after forming a first dielectric layer and a first electrode provided in some embodiments;

[0094] Figure 35 A schematic structural diagram of a structure obtained after forming a bit line accommodating groove provided in some embodiments;

[0095] Figure 36 FIG. 1 is a schematic structural diagram of a structure obtained after forming a bit line provided in some embodiments.

[0096] Description of reference numerals:

[0097] 01-substrate, 1-transistor, 11-semiconductor layer, 111-first semiconductor portion, 111A-first part, 111B-second part, 112-second semiconductor portion, 12-first gate, 13-second gate, 131-first sub-gate, 132-second sub-gate, 14-first gate dielectric layer, 15-second gate dielectric layer, 2-capacitor, 21-contact electrode, 22-first dielectric layer, 23-first electrode, 24-second dielectric layer, 25-second electrode, 251-first sub-electrode, 252-second sub-electrode, 31-first isolation structure, 32-second isolation structure, 33-third isolation structure, 34-fourth isolation structure, 41-conductive pillar, 42-insulating layer, 43-conductive line, WL-word line, BL-bit line, R1-first region, R2-second region;

[0098] N-stack structure, N1-first division, N2-second division, N3-third division, L1-first sacrificial layer, L2-second sacrificial layer, L3 and L3'-third sacrificial layer, L4-fourth sacrificial layer, L5-fifth sacrificial layer, L6-sixth sacrificial layer, Y1-protective layer, 220-dielectric material layer, 110-semiconducting hole, H2-second accommodating hole, H3-second accommodating hole, G1-first isolation groove, G2-second isolation groove, G3-bit line accommodating groove. DETAILED DESCRIPTION

[0099] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0100] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0101] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "electrically connected to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.

[0102] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0103] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present disclosure should not be limited to the specific shapes of the regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Accordingly, the regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present disclosure.

[0104] In the current DRAM manufacturing process, the memory cell 6F is mostly used. 2A manufacturing method for arranged and buried wordlines. Because further reducing the size of memory cells becomes very difficult with this method, as the demand for memory storage capacity continues to increase, memory cells have begun to be arranged in three dimensions. However, due to the scalability issues of memory cells in DRAM and the complexity of their process, further reducing the size of memory cells can easily degrade their electrical performance, making it difficult to further reduce the size of memory cells while ensuring their electrical performance.

[0105] Based on this, the embodiments of the present disclosure provide a storage unit and a memory, which are beneficial to reducing the planar occupied area of ​​the storage unit to improve the storage density and storage capacity of the memory, and are also beneficial to ensuring that the storage unit has better electrical performance and reliability to improve the electrical performance and reliability of the memory.

[0106] See also Figure 1 and Figure 2 The present disclosure provides a memory cell that can be used in a memory, particularly a DRAM. The memory cell adopts a 1T1C architecture, that is, includes a transistor 1 and a capacitor 2.

[0107] By way of example, the memory cell includes: a semiconductor layer 11, a first gate 12, two second gates 13, a contact electrode 21, a first dielectric layer 22, a first electrode 23, a second dielectric layer 24, and a second electrode 25. Specifically, the transistor 1 includes: a semiconductor layer 11, a first gate 12, and two second gates 13. The capacitor 2 includes: a contact electrode 21, a first dielectric layer 22, a first electrode 23, a second dielectric layer 24, and a second electrode 25.

[0108] For example, Figure 1 and Figure 2 As shown in FIG, the semiconductor layer 11 is in the form of a closed ring, including but not limited to a rectangular ring structure or a square ring structure. The region within the ring of the semiconductor layer 11 includes a first region R1 and a second region R2 that are insulated and isolated in a first direction (e.g., the X direction). The semiconductor layer 11 includes a first semiconductor portion 111 surrounding a portion of the first region R1 and a second semiconductor portion 112 surrounding a portion of the second region R2.

[0109] In some examples, the semiconductor layer 11 is a rectangular ring structure, with a first direction (e.g., the X direction) being the length direction of the rectangular ring structure, and a second direction (e.g., the Y direction) being the width direction of the rectangular ring structure. The first region R1 and the second region R2 may be arranged side by side in the first direction (e.g., the X direction). The memory cell further includes a first isolation structure 31 located between the first region R1 and the second region R2 to insulate the first region R1 from the second region R2. Thus, the dividing line between the first semiconductor portion 111 and the second semiconductor portion 112 in the semiconductor layer 11 may be located within the region corresponding to the sidewall of the first isolation structure 31.

[0110] It is understood that the semiconductor layer 11 is in a closed ring shape, with the first semiconductor portion 111 and the second semiconductor portion 112 being an integral structure. In the disclosed embodiment, the portions of the semiconductor layer 11 located in different regions are divided into the first semiconductor portion 111 and the second semiconductor portion 112 merely to clearly describe the relative positional relationship between the semiconductor layer 11 and other structures; that is, there is no physical structural boundary between the first semiconductor portion 111 and the second semiconductor portion 112.

[0111] For example, Figure 1 and Figure 2 As shown in FIG, the first gate 12 is located in the first region R1. The two second gates 13 are located on opposite sides of the first semiconductor portion 111 away from the first gate 12 and in a second direction (eg, Y direction). The second direction intersects with the first direction, eg, is orthogonal.

[0112] In some examples, the second gate 13 includes a first sub-gate 131 and a second sub-gate 132 that are stacked in a second direction (eg, the Y direction) away from the first semiconductor portion 111 and made of different materials.

[0113] For example, the first sub-gate 131 is a polysilicon gate, and the second sub-gate 132 and the first gate 12 are metal gates.

[0114] For example, the metal gate includes, but is not limited to, a single structure of tungsten or copper having excellent conductivity, and may also include a stacked structure of metal and metal, or metal and metal compound. For example, the metal gate includes a stacked structure of titanium nitride and tungsten.

[0115] In some examples, the memory cell further includes a first gate dielectric layer 14 and a second gate dielectric layer 15. The first gate dielectric layer 14 is located between the first gate 12 and the first semiconductor portion 111 of the semiconductor layer 11. The first gate dielectric layer 14 may surround and cover the entire sidewall of the first gate 12, and cover the inner sidewall of the first semiconductor portion 111 exposed to the first region R1 and the sidewall of the first isolation structure 31 exposed to the first region R1. The second gate dielectric layer 15 is located between the second gate 13 and the sidewall of the first semiconductor portion 111 facing away from the first gate 12 in the second direction (e.g., the Y direction).

[0116] For example, the second gate dielectric layer 15 is disposed parallel to the second gate 13, and the second gate dielectric layer 15 and the second gate 13 may have the same length in a first direction (e.g., the X direction). For further example, the orthographic projection of the second gate dielectric layer 15 along the second direction (e.g., the Y direction) substantially coincides with the orthographic projection of the first sub-gate 131 in the second gate 13 in the second direction (e.g., the Y direction).

[0117] For example, the materials of the first gate dielectric layer 14 and the second gate dielectric layer 15 may be the same or different.

[0118] In some examples, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof. K represents a dielectric constant, and the dielectric constant of the high-K dielectric material is, for example, greater than or equal to 3.9, and may be, for example, 20.

[0119] In some examples, the high-K dielectric material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0120] For example, the material of the first gate dielectric layer 14 and / or the second gate dielectric layer 15 may be silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ) or hafnium oxide (HfO 2 ).

[0121] For example, please see Figure 1 and Figure 2 The contact electrode 21 conformally covers the inner sidewalls of the second semiconductor portion 112. The first electrode 23 is located within the second region R2. The first dielectric layer 22 covers the sidewalls of the first electrode 23 and conformally covers the inner sidewalls of the contact electrode 21. The second electrode 25 is located on the outer side of the second semiconductor portion 112, away from the first electrode 23, along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0122] The second dielectric layer 24 is located between the second semiconductor portion 112 and the second electrode 25 and conformally covers a portion of the outer wall of the second semiconductor portion 112 .

[0123] The second electrode 25 conformally covers the outer sidewall of the second dielectric layer 24 .

[0124] Here, the contact electrode 21 conformally covers the inner sidewalls of the second semiconductor portion 112 and can be directly electrically connected to the semiconductor layer 11 of the transistor 1. Furthermore, the contact electrode 21 is a conformal thin film and can have the same shape as the inner sidewalls of the second semiconductor portion 112. In the example where the first isolation structure 31 is provided between the first region R1 and the second region R2, the end surface of the contact electrode 21 facing the first isolation structure 31 contacts the sidewalls of the first isolation structure 31. The first electrode 23 and the second electrode 25 are located on the inner and outer sides of the contact electrode 21, respectively, so as to oppose the contact electrode 21 and constitute the electrodes of the capacitor 2.

[0125] In the embodiment of the present disclosure, the semiconductor layer 11 of the transistor 1 is configured as a closed ring, and the area within the ring of the semiconductor layer 11 is divided into a first region R1 and a second region R2 that are insulated and isolated in a first direction (e.g., the X direction). In this way, a first gate 12 can be provided in the first region R1, and a second gate 13 can be provided on both sides of the first gate 12 along a second direction (e.g., the Y direction) outside the semiconductor layer 11, so as to increase the turn-on current of the transistor 1 and reduce the leakage current. Furthermore, the contact electrode 21 and the first electrode 23 of the capacitor 2 can be provided in the second region R2, and a second electrode 25 can be provided on the side of the contact electrode 21 facing away from the first electrode 23 outside the semiconductor layer 11, so as to increase the storage capacity of the capacitor 2. Therefore, the memory cell in the embodiment of the present disclosure adopts the above-mentioned structure, which not only helps to improve the space utilization of the memory cell to effectively reduce the planar area of ​​a single memory cell, but also increases the thickness of the semiconductor layer 11, so as to increase the turn-on current of the transistor 1 and reduce the leakage current, and helps to increase the storage capacity of the capacitor 2. This helps to improve the storage density and storage capacity of the memory, and ensures that the storage unit has better electrical performance and reliability, thereby improving the electrical performance and reliability of the memory.

[0126] In some embodiments, the semiconductor layer 11 includes, but is not limited to, an indium gallium zinc oxide film layer (i.e., an IGZO film layer). Based on the excellent leakage resistance, low cost, and simple manufacturing process of the IGZO film layer, the leakage resistance of the transistor 1 can be improved accordingly, thereby reducing the production cost of the memory cell and simplifying the manufacturing process of the memory cell to improve production efficiency.

[0127] It can be understood that the contact electrode 21 is in contact with the second semiconductor portion 112 in the semiconductor layer 11. In the example where the semiconductor layer 11 is an IGZO film layer, the second semiconductor portion 112 and the contact electrode 21 can also be equivalent to one electrode of the capacitor 2.

[0128] In some embodiments, the first electrode 23 and the second electrode 25 are electrically connected.

[0129] In some embodiments, the second electrode 25 includes a first sub-electrode 251 and two second sub-electrodes 252. The first sub-electrode 251 conformally covers the outer sidewalls of the second dielectric layer 24. The two second sub-electrodes 252 respectively cover the outer sidewalls of the first sub-electrode 251 facing away from the second dielectric layer 24 and opposite to each other in the second direction (e.g., the Y direction).

[0130] In some embodiments, the first sub-electrode 251 is a polysilicon electrode, the second sub-electrode 252 is a metal electrode, and the first electrode 23 and the second sub-electrode 252 are electrically connected.

[0131] For example, the first electrode 23 and the second sub-electrode 252 are both formed of metal materials, which include but are not limited to single structures with excellent conductivity such as tungsten or copper, and can also include a stacked structure of metal and metal, or metal and metal compound.

[0132] For example, the first electrode 23 and the second sub-electrode 252 are a stacked structure of titanium nitride and tungsten.

[0133] Illustratively, the contact electrode 21 and the first electrode 23 are made of the same material, including but not limited to titanium nitride.

[0134] For example, the first dielectric layer 22 and the second dielectric layer 24 are made of the same or different materials, for example, silicon oxide, silicon nitride, high-K dielectric materials or a combination thereof.

[0135] In some embodiments, the memory cell further includes two second isolation structures 32 . The two second isolation structures 32 are respectively located between the corresponding second gate 13 and the second electrode 25 .

[0136] For example, the first isolation structure 31 and the second isolation structure 32 may be staggered in a first direction (eg, X direction).

[0137] For example, the first gate 12 and the second gate 13 are staggered in a first direction (e.g., the X direction). In the disclosed embodiment, the two second gates 13 are located on either side of the first gate 12 and are staggered relative to the first gate 12 in the first direction (e.g., the X direction), which helps to further increase the turn-on current of the transistor 1 and reduce the leakage current of the transistor 1, thereby further improving the electrical performance and reliability of the memory cell.

[0138] For example, the size of the second gate 13 in the first direction (e.g., X direction) is larger than the size of the first gate 12 in the first direction (e.g., X direction). In addition, the sidewall of the second gate 13 facing away from the second electrode 25 in the first direction (e.g., X direction) may be flush with the sidewall of the first gate 12 facing away from the first isolation structure 31 in the first direction (e.g., X direction).

[0139] In some embodiments, please refer to Figure 1 and Figure 2 The outer sidewall of the first semiconductor portion 111 , which is away from the first gate 12 and extends along the second direction (eg, the Y direction), is connected to the bit line BL.

[0140] For example, the dimension of the outer side wall of the first semiconductor portion 111 connected to the bit line BL in the second direction (for example, the Y direction) is a first dimension D1; the distance between the outer side walls of the first semiconductor portion 111 on opposite sides in the second direction (for example, the Y direction) is a second dimension D2; wherein, the first dimension D1 is greater than the second dimension D2.

[0141] In the embodiment of the present disclosure, the outer side wall of the first semiconductor portion 111 connected to the bit line BL has a larger dimension in the second direction (for example, the Y direction), which is beneficial to ensure that the first semiconductor portion 111 can have a larger contact area with the bit line BL along the extension direction of the bit line BL, so as to further reduce the contact resistance between the transistor 1 (for example, the first semiconductor portion 111) and the bit line BL.

[0142] In some embodiments, the bit line BL is formed of a conductive material, including but not limited to silicon-based materials, metal-based materials, or combinations thereof. For example, the bit line BL may be made of polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit line BL may be a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0143] For example, the first semiconductor portion 111 includes: a first portion 111A connected to the bit line BL, and a second portion 111B integrally connected to the first portion 111A and located between the first gate 12 and the second gate 13; wherein the size of the first portion 111A in a first direction (for example, the X direction) is larger than the size of the second portion 111B in a second direction (for example, the Y direction).

[0144] For example, the size of the second semiconductor portion 112 in the first direction (eg, X direction) and the size of the second semiconductor portion 112 in the second direction (eg, Y direction) are both the same as the size of the second portion 111B in the second direction (eg, Y direction).

[0145] In some embodiments, please refer to Figure 1 and Figure 2 The memory cell further includes a third isolation structure 33 and a fourth isolation structure 34. The third isolation structure 33 is located between the second gate 13 and the bit line BL. The fourth isolation structure 34 is located between the third isolation structure 33 and the second isolation structure 32 and covers the sidewall of the second gate 13 facing away from the first gate 12.

[0146] In the embodiment of the present disclosure, the first isolation structure 31 , the second isolation structure 32 , the third isolation structure 33 and the fourth isolation structure 34 adopt the aforementioned configuration, which is also beneficial for eliminating the GIDL effect of the transistor 1 , thereby improving the electrical performance and reliability of the transistor 1 .

[0147] It should be noted that the first isolation structure 31, the second isolation structure 32, the third isolation structure 33, and the fourth isolation structure 34 are formed of insulating materials and may be single-layer structures or stacked-layer structures. Furthermore, the insulating materials used for the first isolation structure 31, the second isolation structure 32, the third isolation structure 33, and the fourth isolation structure 34 may be the same or different. For example, the insulating materials may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0148] In some examples, the materials of the first isolation structure 31 , the second isolation structure 32 , and the third isolation structure 33 are all silicon nitride, and the material of the fourth isolation structure 34 is silicon oxide.

[0149] It should be supplemented that, in some embodiments, the first gate 12 and the two second gates 13 are connected to the same word line WL.

[0150] In some other embodiments, the first gate 12 and the two second gates 13 are respectively connected to different word lines WL to achieve independent control of the first gate 12 and the second gate 13 .

[0151] The present disclosure also provides a memory. Figure 3 The memory includes: at least one memory cell as described in any of the above embodiments, at least one bit line BL, and at least one word line WL. The bit line BL extends along a second direction (e.g., the Y direction) and is electrically connected to an outer sidewall of the first semiconductor portion 111 of the memory cell that faces away from the first gate 12 and extends along the second direction (e.g., the Y direction). The word line WL is electrically connected to the first gate 12 and the two second gates 13 of the memory cell.

[0152] Here, the word line WL is electrically connected to the first gate 12 and the two second gates 13 in a corresponding manner. This can be expressed as: one word line WL is electrically connected to the first gate 12 and the two second gates 13 of the same memory cell at the same time; or, the word line WL is electrically connected to the first gate 12 and the two second gates 13 in a one-to-one correspondence. That is, the embodiments of the present disclosure do not limit the corresponding relationship between the electrical connections between the word line WL and the first gate 12 and the second gate 13.

[0153] In some embodiments, there are multiple memory cells, and the memory cells are arranged in a row along a third direction (e.g., the Z direction). The third direction (e.g., the Z direction) intersects with the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) in pairs, for example, they are orthogonal to each other. The memory cells in a row share the same word line WL.

[0154] In some embodiments, a plurality of memory cells are distributed in different layers in a third direction (e.g., Z direction). The third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., Y direction). In which, a plurality of memory cells having the same orthographic projection position in the third direction (e.g., Z direction) and located in different layers are connected to a plurality of bit lines BL in different layers, and the orthographic projection positions of the plurality of bit lines BL in the third direction (e.g., Z direction) are the same. The memory further includes: a plurality of conductive pillars 41 arranged at intervals along the second direction (e.g., Y direction). Each conductive pillar 41 extends respectively along the third direction (e.g., Z direction) and is connected to the bit line BL of the target layer, and is insulated from the bit lines BL outside the target layer.

[0155] For example, the conductive pillar 41 penetrates each bit line BL above the target layer along a third direction (e.g., the Z direction), and the bottom surface of the conductive pillar 41 is in contact with the bit line BL of the target layer. The side wall of the conductive pillar 41 is covered with an insulating layer 42 to insulate the conductive pillar 41 from each bit line BL above the target layer.

[0156] In some embodiments, please refer to Figure 3 Multiple memory cells are arranged in a row along a third direction (e.g., the Z direction). The second sub-electrodes 252 of a row of memory cells can be integrally structured. Furthermore, the first electrode 23 of a memory cell can be electrically connected to the second sub-electrode 252 in the same memory cell via a conductive line 43.

[0157] Some embodiments of the present disclosure also provide a memory manufacturing method for manufacturing the memory described in some of the aforementioned embodiments. This manufacturing method also possesses the technical advantages of the aforementioned memories. Furthermore, the memory manufacturing method provided by the embodiments of the present disclosure reduces the difficulty of the process, is easy to implement, and also helps improve the production efficiency and yield of the memory.

[0158] See also Figure 4 , the preparation method of the memory includes the following steps.

[0159] S10 , forming a stacked structure, where the stacked structure includes a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked.

[0160] S20 , etching the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole.

[0161] S30: Form a semiconductor layer on the inner sidewall of the second sacrificial layer within the first receiving hole. The semiconductor layer is in a closed ring shape, and the region within the ring includes a first region and a second region insulated and isolated from each other in a first direction. The semiconductor layer includes a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region.

[0162] S40 , forming a first gate in the first region.

[0163] S50 , forming second gates on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in a second direction, where the second direction intersects the first direction.

[0164] S60 , forming a contact electrode in the second region to conformally cover the inner sidewall of the second semiconductor portion.

[0165] S70 , forming a first dielectric layer in the second region that conformally covers the inner sidewall of the contact electrode and is in a closed ring shape.

[0166] S80 , forming a first electrode in the inner ring region of the first dielectric layer.

[0167] S90 , forming a second dielectric layer on an outer sidewall of the second semiconductor portion away from the first electrode along the first direction and the second direction.

[0168] S100 , forming a second electrode on an outer sidewall of the second dielectric layer away from the second semiconductor portion.

[0169] It should be understood that although the above Figure 4 The steps in the flowchart are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0170] The following examples are for Figure 4 At least some of the steps shown in the figure, as well as other supplementary steps of the memory manufacturing method, are provided as examples of possible implementations, but are not limited thereto. Furthermore, the step numbers before each step below do not limit the order in which the steps are executed. That is, the steps can be executed in a different order to meet the requirements.

[0171] In some embodiments, the second gate and the second electrode are formed simultaneously to simplify the manufacturing process.

[0172] In some embodiments, the second gate includes: a first sub-gate and a second sub-gate stacked in a second direction away from the first semiconductor portion and made of different materials. The second electrode includes: a first sub-electrode conformally covering an outer sidewall of the second semiconductor portion, and a second sub-electrode covering opposite outer sidewalls of the first sub-electrode facing away from the second semiconductor portion in the second direction.

[0173] Step S20 of etching the stacked structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole may include steps S201 to S203 .

[0174] S201 , etching the stack structure to form two first accommodating areas extending along a first direction and spaced apart in a second direction.

[0175] S202 , forming a third sacrificial layer in the first accommodating area.

[0176] S203 , etching the stacked structure between the two first accommodating areas to form a first accommodating hole.

[0177] Correspondingly, the method for preparing the memory further includes: step S310.

[0178] S310 , etching the stack structure to form a first isolation trench, so as to separate the stack structure into a first subsection located on a side of the first semiconductor portion away from the first gate and a second subsection located on a side of the second semiconductor portion away from the first electrode through the first isolation trench.

[0179] Accordingly, step S50 of forming the second gates on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in the second direction may include steps S501 and S502 .

[0180] S501 , removing at least a portion of the third sacrificial layer in the first sub-section to form a second receiving hole, while making the second sacrificial layer remaining between the first semiconductor portion and the second receiving hole in the first sub-section constitute a first sub-gate.

[0181] S502 , forming a second sub-gate and a word line connected to the second sub-gate in the second receiving hole.

[0182] Correspondingly, step S100 forms a second electrode on the outer wall of the second dielectric layer away from the second semiconductor part, including: removing at least part of the third sacrificial layer in the second section close to the second semiconductor part along the second direction to form a third accommodating hole, and at the same time making the second sacrificial layer in the second section conformally covering the outer wall of the second semiconductor part to form a first sub-electrode; forming a second sub-electrode in the third accommodating hole.

[0183] In some embodiments, the method for preparing the memory further includes the following steps.

[0184] S110, while etching the stack structure to form the first isolation trench, a second isolation trench is formed to separate a third section located on the side of the first section away from the second section in the stack structure through the second isolation trench; the second sacrificial layer in the third section is connected to the outer side wall of the first semiconductor section away from the first gate and extending along the second direction.

[0185] S120 , removing the second sacrificial layer in the third section to form a bit line accommodating groove.

[0186] S130 , forming a bit line in the bit line receiving groove.

[0187] In some embodiments, step S30 of forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole may include steps S301 to S309 .

[0188] S301 , forming a dielectric material layer conformally covering the wall of the first receiving hole.

[0189] S302 , forming a fourth sacrificial layer covering the inner sidewall of the dielectric material layer and filling the first receiving hole.

[0190] S303 , removing a portion of the fourth sacrificial layer and a portion of the dielectric material layer near the first end of the first receiving hole in the first direction, exposing a portion of the hole wall of the first receiving hole.

[0191] S304 , removing the remaining fourth sacrificial layer.

[0192] S305 , forming a semiconductor material layer that conformally covers the inner sidewalls of the remaining dielectric material layer and the exposed hole walls of the first receiving hole.

[0193] S306 , etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed.

[0194] S307 , etching the semiconductor material layer based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer.

[0195] S308 , etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed.

[0196] S309 , etching the initial semiconductor layer based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers, forming semiconductor layers respectively located on inner sidewalls of each second sacrificial layer.

[0197] In some embodiments, before performing step S306 to etch the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed, the memory manufacturing method further includes the following steps S401 to S402 and steps S601 to S605.

[0198] S401 , forming a fifth sacrificial layer covering the inner sidewall of the semiconductor material layer and filling the first receiving hole.

[0199] S402 , removing a first portion of the fifth sacrificial layer close to the first end of the first receiving hole to expose the first region, so as to form a first gate in the first region.

[0200] S601, after forming the first gate, remove a second portion of the fifth sacrificial layer near the second end of the first receiving hole in the first direction (e.g., the X direction) to expose a second region. The first end and the second end are opposite ends of the fifth sacrificial layer in the first direction.

[0201] S602 , forming a contact electrode material layer in the second region conformally covering the inner sidewalls of the semiconductor material layer and the remaining sidewalls of the fifth sacrificial layer, and a sixth sacrificial layer covering the inner sidewalls of the contact electrode material layer and filling the second region.

[0202] S603 , removing the remaining fifth sacrificial layer.

[0203] S604 , etching the contact electrode material layer based on the removed area of ​​the fifth sacrificial layer, so that the contact electrode material layer conformally covers the inner sidewall of the second semiconductor portion to form a contact electrode.

[0204] S605 , forming a first isolation structure in the removed area of ​​the fifth sacrificial layer and the contact electrode material layer.

[0205] In some embodiments, step S70 of forming a first dielectric layer in a closed ring shape in the second region conformally covering the inner sidewall of the contact electrode includes steps S701 and S702 , and step S80 of forming a first electrode in the region inside the ring of the first dielectric layer includes step S801 .

[0206] S701, removing the sixth sacrificial layer.

[0207] S702 , forming a first dielectric layer conformally covering the inner sidewalls of the contact electrode and the sidewalls of the first isolation structure close to the contact electrode.

[0208] S801 , forming a first electrode covering the inner sidewall of the first dielectric layer and filling the sixth sacrificial layer removed area.

[0209] In order to more clearly illustrate the preparation method of the memory in some of the above embodiments, the following Figures 5 to 36 Understand some embodiments of the present disclosure.

[0210] In step S10, refer to Figure 5 , forming a stacked structure N, which includes a plurality of first sacrificial layers L1 and a plurality of second sacrificial layers L2 that are alternately stacked.

[0211] Here, the number of stacked layers of the first sacrificial layer L1 and the second sacrificial layer L2 in the stacked structure N can be set to match the storage requirement of the memory unit in the third direction (eg, Z direction).

[0212] For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 in the stack structure N may start with the first sacrificial layer L1 and end with the second sacrificial layer L2. However, this is not limited to the above. For example, the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the second sacrificial layer L2 and end with the first sacrificial layer L1; or the alternating stacking of the first sacrificial layer L1 and the second sacrificial layer L2 may start with the second sacrificial layer L1 and end with the first sacrificial layer L1, etc., all of which are permitted.

[0213] In some examples, the first sacrificial layer L1 includes, but is not limited to, a silicon oxide layer.

[0214] In some examples, the second sacrificial layer L2 includes, but is not limited to, a polysilicon layer.

[0215] As a further example, the second sacrificial layer L2 is a heavily doped polysilicon layer. The doping concentration of the doping element in the second sacrificial layer L2 can be 1E21 / cm 3 ~1E22 / cm 3 .

[0216] Here, the second sacrificial layer L2 is a heavily doped polysilicon layer, which is beneficial for increasing the threshold voltage of the transistor 1 after the first sub-gate 131 of the second gate 13 is subsequently formed based on the second sacrificial layer L2.

[0217] In some examples, taking the first sacrificial layer L1 as the starting layer and the second sacrificial layer L2 as the ending layer in the stacked structure N as an example, the stacked structure N may further include a protective layer Y1 covering the top second sacrificial layer L2. The protective layer Y1 may be, for example, a hard mask layer, including but not limited to a silicon nitride layer.

[0218] In step S20, refer to Figures 6 to 8The stack structure N is etched along the stacking direction of the first sacrificial layer L1 and the second sacrificial layer L2 (ie, the third direction, such as the Z direction) to form a first receiving hole H1.

[0219] In some embodiments, step S20 may include steps S201 to S203.

[0220] In step S201, refer to Figure 6 , the stacked structure N is etched to form two first accommodating areas A1 extending along a first direction (eg, X direction) and spaced apart in a second direction (eg, Y direction).

[0221] Here, it is understandable that Figure 6 Only two first accommodating areas A1 are used as an example. When forming the first accommodating areas A1, multiple first accommodating areas A1 can be formed in the stacking structure N, spaced apart in the second direction (e.g., the Y direction). Based on two adjacent first accommodating areas A1 in the second direction (e.g., the Y direction) and the stacking structure N therebetween, a corresponding memory cell is prepared.

[0222] In step S202, refer to Figure 7 , a third sacrificial layer L3 is formed in the first accommodating area A1.

[0223] Here, the third sacrificial layer L3 can be formed by a deposition process and a grinding process. The top surface of the third sacrificial layer L3 is flush with the top surface of the stacked structure N.

[0224] Illustratively, the third sacrificial layer L3 and the first sacrificial layer L1 are made of the same material.

[0225] Illustratively, the third sacrificial layer L3 includes but is not limited to a silicon oxide layer.

[0226] In step S203, refer to Figure 8 , etching the stack structure N between the two first accommodating areas A1 to form a first accommodating hole H1.

[0227] Here, the first receiving hole H1 penetrates the stacked structure N and can expose the surface of the substrate 01. The first receiving hole H1 is used to define the formation position of the semiconductor layer 11 in the aforementioned transistor 1. The shape and size of the first receiving hole H1 can be set according to requirements.

[0228] For example, the cross-sectional shape of the first accommodating hole H1 includes but is not limited to a rectangle. The cross-sectional shape of the first accommodating hole H1 refers to a cross-sectional shape of the first accommodating hole H1 parallel to the XY plane.

[0229] In step S30, refer to Figures 9 to 27A semiconductor layer 11 is formed on the inner sidewall of the second sacrificial layer L2 within the first receiving hole H1. The semiconductor layer 11 is in a closed ring shape. The area within the ring of the semiconductor layer 11 includes a first region R1 and a second region R2 that are insulated and isolated from each other in a first direction (e.g., the X direction). The semiconductor layer 11 includes a first semiconductor portion 111 surrounding a portion of the first region R1 and a second semiconductor portion 112 surrounding a portion of the second region R2.

[0230] In some embodiments, step S30 may include steps S301 to S309. Furthermore, step S40, forming the first gate 12 in the first region R1, and step S60, forming the contact electrode 21 conformally covering the inner sidewall of the second semiconductor portion 112 in the second region R2, may be performed between steps S305 and S306. Step S40 may include steps S401 to S402. Step S60 may include steps S601 to S605.

[0231] In step S301, please refer to Figure 9 , forming a dielectric material layer 220 that conformally covers the wall of the first receiving hole H1.

[0232] Illustratively, the dielectric material layer 220 includes, but is not limited to, a high-K dielectric material layer.

[0233] In some examples, the dielectric material layer 220 may be formed of materials such as aluminum oxide (Al 2 O 3 ), zinc oxide (ZnO), zirconium oxide (ZrO 2 ), or hafnium oxide (HfO 2 ).

[0234] For example, the dielectric material layer 220 may be formed by a deposition process, including but not limited to an atomic layer deposition process.

[0235] For example, the top surface of the dielectric material layer 220 is flush with the top surface of the stacked structure N, and the top surface of the dielectric material layer 220 may be polished by a grinding process.

[0236] In step S302, refer to Figure 10 , forming a fourth sacrificial layer L4 covering the inner sidewall of the dielectric material layer 220 and filling the first receiving hole H1.

[0237] Illustratively, the material of the fourth sacrificial layer L4 is the same as that of the first sacrificial layer L1 .

[0238] Illustratively, the material of the fourth sacrificial layer L4 includes but is not limited to silicon oxide.

[0239] In step S303, refer to Figure 11 , remove part of the fourth sacrificial layer L4 and part of the dielectric material layer 220 near the first end (eg, left end) of the first accommodating hole H1 in the first direction (eg, X direction), exposing part of the hole wall of the first accommodating hole H1.

[0240] In step S304, refer to Figure 12 , remove the remaining fourth sacrificial layer L4.

[0241] In step S305, please continue to refer to Figure 12 , forming a semiconductor material layer 110 that conformally covers the inner sidewalls of the remaining dielectric material layer 220 and the exposed hole wall of the first receiving hole H1 .

[0242] By way of example, the semiconductor material layer 110 includes, but is not limited to, an IGZO layer.

[0243] For example, the top surface of the semiconductor material layer 110 is flush with the top surface of the stacked structure N, and the top surface of the semiconductor material layer 110 may be polished by a grinding process.

[0244] In step S401, refer to Figure 13 , forming a fifth sacrificial layer L5 covering the inner sidewall of the semiconductor material layer 110 and filling the first receiving hole H1.

[0245] Illustratively, the material of the fifth sacrificial layer L5 is the same as that of the first sacrificial layer L1 .

[0246] Illustratively, the material of the fifth sacrificial layer L5 includes but is not limited to silicon oxide.

[0247] For example, the top surface of the fifth sacrificial layer L5 is flush with the top surface of the stacked structure N, and the top surface of the fifth sacrificial layer L5 can be polished by a grinding process.

[0248] In step S402, refer to Figures 14 to 16 , a first portion of the fifth sacrificial layer L5 close to the first end (eg, the left end) of the first receiving hole H1 is removed to expose the first region R1 , so as to form the first gate 12 in the first region R1 .

[0249] It is understandable that Figure 15 As shown in , after the first region R1 is exposed, the first gate dielectric layer 14 may be conformally formed on the inner sidewall of the first region R1 before forming the first gate 12. Figure 16 As shown in FIG, a first gate 12 is formed to cover the inner sidewall of the first gate dielectric layer 14 and fill the first region.

[0250] For example, the first gate dielectric layer 14 is formed by a deposition process, which includes but is not limited to an atomic layer deposition process.

[0251] For example, the material of the first gate dielectric layer 14 includes, but is not limited to, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-K dielectric material, ferroelectric material, antiferroelectric material, or a combination thereof.

[0252] For example, the top surfaces of the first gate dielectric layer 14 and the first gate electrode 12 are flush with the top surface of the stacked structure N, and the top surfaces of the first gate dielectric layer 14 and the first gate electrode 12 can be polished by a grinding process.

[0253] In step S601, refer to Figure 17 After forming the first gate 12, a second portion of the fifth sacrificial layer L5 near the second end (e.g., the right end) of the first receiving hole H1 in the first direction (e.g., the X direction) is removed to expose the second region R2. The first end and the second end are opposite ends of the fifth sacrificial layer L5 in the first direction (e.g., the X direction).

[0254] In step S602, refer to Figure 18 , a contact electrode material layer 210 is formed in the second region R2 to conformally cover the inner sidewalls of the semiconductor material layer 110 and the sidewalls of the remaining fifth sacrificial layer L5. Figure 19 , forming a sixth sacrificial layer L6 covering the inner sidewall of the contact electrode material layer 210 and filling the second region R2.

[0255] Illustratively, the material of the sixth sacrificial layer L6 is the same as that of the first sacrificial layer L1 .

[0256] Illustratively, the material of the sixth sacrificial layer L6 includes, but is not limited to, silicon oxide.

[0257] For example, the top surfaces of the contact electrode material layer 210 and the sixth sacrificial layer L6 are flush with the top surface of the stacked structure N, and the top surfaces of the contact electrode material layer 210 and the sixth sacrificial layer L6 can be polished by a grinding process.

[0258] In step S603, refer to Figure 20 , remove the remaining fifth sacrificial layer L5.

[0259] In step S604, please continue to refer to Figure 20 The contact electrode material layer 210 is etched based on the removed area of ​​the fifth sacrificial layer L5 , so that the contact electrode material layer 210 conformally covers the inner sidewall of the second semiconductor portion 112 to form the contact electrode 21 .

[0260] Here, it can be understood that in step S604, the semiconductor material layer 110 has not yet been etched and separated to form the semiconductor layer 11. Accordingly, Figure 20 After etching the sidewalls of the contact electrode material layer 210 to expose the sixth sacrificial layer L6, the remaining contact electrode material layer forms the initial contact electrode 21A. The initial contact electrode 21A can be separated by subsequent etching to form the contact electrode 21.

[0261] Illustratively, the contact electrode material layer 210 includes, but is not limited to, a titanium nitride layer.

[0262] In step S605, refer to Figure 21 A first isolation structure 31 is formed in the removed area of ​​the fifth sacrificial layer L5 and the contact electrode material layer 210 .

[0263] Illustratively, the material of the first isolation structure 31 is different from the material of the sixth sacrificial layer L6 .

[0264] By way of example, the material of the first isolation structure 31 includes, but is not limited to, silicon nitride.

[0265] In step S306, refer to Figure 22 , the outer sidewall of the first sacrificial layer L1 extending along the second direction (eg, the Y direction) is etched until the semiconductor material layer 110 is exposed.

[0266] In step S307, refer to Figure 23 The semiconductor material layer 110 is etched based on the removal area extending along the second direction (for example, the Y direction) of the first sacrificial layer L1 to remove the semiconductor material layer 110 extending along the second direction (for example, the Y direction) between adjacent second sacrificial layers L2 to form an initial semiconductor layer 11A.

[0267] Here, the first gate dielectric layer 14 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 can serve as an etch stop layer for the semiconductor material layer 110. Furthermore, it is understood that the initial contact electrode 21 extending along the second direction (e.g., the Y direction) between adjacent second sacrificial layers L2 can also be etched and removed.

[0268] In addition, please refer to Figure 24 After forming the initial semiconductor layer 11A, the removed regions of the first sacrificial layer L1 and the semiconductor material layer 110 (including the initial contact electrode 21A) may be filled with an insulating material 5 .

[0269] Illustratively, the insulating material 5 is different from the material of the first sacrificial layer L1 .

[0270] By way of example, the material of the insulating material 5 includes, but is not limited to, silicon nitride.

[0271] In step S308, please refer to Figure 25 and Figure 26 , the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, the X direction) is etched until the initial semiconductor layer 11A is exposed.

[0272] For example, Figure 25 As shown in , the third sacrificial layer L3 is removed, exposing the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, X direction). Figure 26 As shown in FIG, the outer sidewall of the first sacrificial layer L1 extending along the first direction (eg, the X direction) is etched until the initial semiconductor layer 11A and the dielectric material layer 220 are exposed.

[0273] Here, after step S308 is performed, each first sacrificial layer L1 in the stacked structure N has been effectively removed without any residue.

[0274] In step S309, refer to Figure 27 The initial semiconductor layer 11A is etched based on the removal area extending along the first direction (for example, the X direction) of the first sacrificial layer L1 to remove the initial semiconductor layer 11A extending along the first direction (for example, the X direction) between adjacent second sacrificial layers L2, thereby forming semiconductor layers 11 respectively located on the inner side walls of each second sacrificial layer L2.

[0275] Here, the first gate dielectric layer 14 extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2 can serve as an etch stop for the initial semiconductor layer 11A. Furthermore, the initial contact electrodes 21A extending along the first direction (e.g., the X direction) between adjacent second sacrificial layers L2 can be removed by etching to form contact electrodes 21 located on the inner sidewalls of the semiconductor layer 11 corresponding to each second sacrificial layer L2.

[0276] At this point, the semiconductor layer 11 of the memory cell in the embodiment of the present disclosure has been prepared. The relevant structure of the semiconductor layer 11 can be found in the relevant descriptions in some of the aforementioned embodiments and will not be described in detail here.

[0277] In addition, please refer to Figure 28 After forming the semiconductor layer 11 and the contact electrode 21 , the sacrificial material may be backfilled in the removed areas of the original third sacrificial layer L3 , the first sacrificial layer L1 and the semiconductor material layer 110 (including the initial contact electrode 21A) to re-form the third sacrificial layer L3 ′.

[0278] In step S310, please combine Figure 2 and Figure 29 It is understood that after etching to form the third sacrificial layer L3', the stacked structure N forms a first isolation groove G1, so as to separate the stacked structure N into a first section N1 located on the side of the first semiconductor portion 111 away from the first gate 12, and a second section N2 located on the side of the second semiconductor portion 112 away from the first electrode 23 through the first isolation groove G1.

[0279] In step S110, please refer to Figure 29While etching the stack structure N to form the first isolation trench G1, a second isolation trench G2 is formed to separate a third section N3 located on the side of the first section N1 away from the second section N2 in the stack structure N through the second isolation trench G2; the second sacrificial layer L2 in the third section N3 is connected to the outer side wall of the first semiconductor portion 111 away from the first gate 12 and extending along the second direction (for example, the Y direction).

[0280] Accordingly, see Figure 30 , a second isolation structure 32 is formed in the first isolation trench G1 , and a third isolation structure 33 is formed in the second isolation trench G2 .

[0281] For example, the material of the second isolation structure 32 and the third isolation structure 33 is the same as the material of the first isolation structure 31 , and is different from the material of the third sacrificial layer L3 ′.

[0282] By way of example, the materials of the second isolation structure 32 and the third isolation structure 33 include, but are not limited to, silicon nitride.

[0283] It should be noted that in the above-described embodiment of forming the second isolation structure 32 and the third isolation structure 33, the dielectric material layer 220 retained within the first sub-portion N1 can constitute the second gate dielectric layer 15, and the dielectric material layer 220 retained within the second sub-portion N2 can constitute the second dielectric layer 24. That is, step S90 can be simultaneously implemented to form the second dielectric layer 24 on the outer sidewalls of the second semiconductor portion 112 along the first direction (e.g., the X direction) and the second direction (e.g., the Y direction) away from the first electrode 23. Furthermore, the second sacrificial layer L2 retained within the first sub-portion N1 can substantially constitute the first sub-gate 131 of the second gate 13, and the second sacrificial layer L2 retained within the second sub-portion N2 can substantially constitute the first sub-electrode 251 of the second electrode 25.

[0284] Based on this, in step S50, please combine Figure 2 and Figure 31 、 Figure 32 It is understood that the second gates 13 are formed on two sides of the first semiconductor portion 111 that are away from the first gate 12 and opposite to each other in the second direction (eg, the Y direction).

[0285] For example, step S50 may include steps S501 and S502.

[0286] In step S501, refer to Figure 31 At least a portion of the third sacrificial layer L3 ′ near the first semiconductor portion 111 in the first sub-portion N1 is removed to form a second accommodating hole H2 . At the same time, the second sacrificial layer L2 retained in the first sub-portion N1 between the first semiconductor portion 111 and the second accommodating hole H2 constitutes the first sub-gate 131 .

[0287] Here, the second receiving hole H2 exposes the sidewall of the second gate dielectric layer 15 facing away from the first semiconductor portion 111 .

[0288] In step S502, refer to Figure 32 , a second sub-gate 132 and a word line WL connected to the second sub-gate 132 are formed in the second receiving hole H2.

[0289] For example, the second sub-gate 132 and the word line WL are formed of a metal material, such as tungsten or copper, and are an integrated structure.

[0290] For example, the second sub-gate 132 and the word line WL may also be a stacked structure of metal and metal, or metal and metal compound. For example, the second sub-gate 132 and the word line WL adopt a stacked structure of titanium nitride and tungsten.

[0291] In step S100, please continue to combine Figure 2 and Figure 31 、 Figure 32 It is understood that the second electrode 25 is formed on the outer sidewall of the second dielectric layer 24 away from the second semiconductor portion 112 .

[0292] For example, Figure 31 As shown, at least a portion of the third sacrificial layer L3' in the second sub-portion N2 along the second direction (e.g., the Y direction) close to the second semiconductor portion 112 is removed to form a third receiving hole H3, while the second sacrificial layer L2 in the second sub-portion N2 conformally covering the outer wall of the second semiconductor portion 112 forms the first sub-electrode 251. Figure 32 As shown, the second sub-electrode 252 is formed in the third receiving hole H3.

[0293] In some examples, the second sub-gate 132 and the second sub-electrode 252 may be simultaneously formed with the same material and the same process.

[0294] In addition, it can be understood that after forming the second accommodating hole H2 and the third accommodating hole H3 , the third sacrificial layer L3 ′ remaining outside the second sub-gate 132 and the second sub-electrode 252 can constitute the fourth isolation structure 34 .

[0295] In step S70, please combine Figure 2 and Figure 33 、 Figure 34 It is understood that a first dielectric layer 22 conformally covering the inner sidewall of the contact electrode 21 and having a closed ring shape is formed in the second region R2 .

[0296] For example, step S70 may include steps S701 to S702.

[0297] In step S701, refer to Figure 33, the sixth sacrificial layer L6 is removed to expose the inner sidewall of the contact electrode 21 and the sidewall of the first isolation structure 31 close to the contact electrode 21 .

[0298] In step S702, refer to Figure 34 , forming a first dielectric layer 22 conformally covering the inner sidewall of the contact electrode 21 and the sidewall of the first isolation structure 31 close to the contact electrode 21 .

[0299] In step S80 (ie S801), please continue to refer to Figure 34 A first electrode 23 is formed in the inner region of the first dielectric layer 22. The first electrode 23 covers the inner sidewall of the first dielectric layer 22 and fills the removed region of the sixth sacrificial layer L6.

[0300] In step S120, refer to Figure 35 , the second sacrificial layer L2 in the third sub-section N3 is removed to form a bit line accommodating groove G3.

[0301] Here, after removing the second sacrificial layer L2 in the third sub-portion N3 , the bit line receiving groove G3 may expose the outer sidewall of the first semiconductor portion 111 in the semiconductor layer 11 extending along the second direction (eg, the Y direction).

[0302] In step S130, refer to Figure 36 The bit line BL is formed in the bit line receiving groove G3 . The bit line BL may be in contact with and connected to an outer sidewall of the first semiconductor portion 111 in the semiconductor layer 11 extending along the second direction (eg, the Y direction).

[0303] For example, the materials forming the bit lines BL include, but are not limited to, silicon-based materials, metal-based materials, or combinations thereof. For example, the material of the bit lines BL includes polysilicon, metal, metal nitride, metal silicide, or combinations thereof. For example, the bit lines BL may have a single-layer structure of tungsten, titanium nitride, or polysilicon, or a stacked-layer structure of titanium nitride, tungsten, or the like.

[0304] For example, the bit line BL is formed by filling the bit line receiving groove G4 with a metal material, such as tungsten or copper.

[0305] It is worth mentioning that in some embodiments, see Figure 3 The plurality of memory cells are arranged in a row along a third direction (e.g., the Z direction). Furthermore, the plurality of memory cells are distributed in different layers in the third direction (e.g., the Z direction). Furthermore, the plurality of memory cells located in different layers and having the same orthographic projection position in the third direction (e.g., the Z direction) are connected to a plurality of bit lines BL in different layers, and the orthographic projection positions of the plurality of bit lines BL in the third direction (e.g., the Z direction) are the same.

[0306] Based on this, the method for preparing the memory may further include the following steps.

[0307] S140, forming a through hole that passes through each layer of bit lines BL above the target layer bit line BL, and conformally forming an insulating layer 42 covering the through hole wall in the through hole, and a conductive column 41 covering the insulating layer 42 and filling the through hole, so that the bottom surface of the conductive column 41 is in contact with the target layer bit line BL, and the side wall of the conductive column 41 is insulated from the each layer of bit lines BL above the target layer.

[0308] In some embodiments, please refer to Figure 3 Multiple memory cells are arranged in a row along a third direction (e.g., the Z direction). The second sub-electrodes 252 of a row of memory cells can be integrally structured. Furthermore, the first electrode 23 of a memory cell can be electrically connected to the second sub-electrode 252 in the same memory cell via a conductive line 43.

[0309] Based on this, the method for preparing the memory may further include the following steps.

[0310] S150 , forming a conductive line 43 to electrically connect the first electrode 23 and the second sub-electrode 252 in the same memory cell through the conductive line 43 .

[0311] For example, the conductive pillars 41 and the conductive wires 43 can be formed of metal materials, such as tungsten or copper.

[0312] In the description of this specification, the terms "removing" and "etching" can be implemented by using at least one etching process of wet etching and / or dry etching as needed.

[0313] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0314] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0315] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the scope of the present disclosure, and all such variations and improvements fall within the scope of protection of the present disclosure.

Claims

1. A storage unit, characterized in that: include: Semiconductor layer, in the shape of a closed ring; The inner region of the semiconductor layer includes a first region and a second region insulated and isolated from each other in a first direction; The semiconductor layer includes: a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region; a first gate located in the first region; two second gates, respectively located on two sides of the first semiconductor portion facing away from the first gate and opposite to each other in a second direction; the second direction intersects the first direction; a contact electrode conformally covering an inner sidewall of the second semiconductor portion; a first electrode located in the second region; a first dielectric layer, covering each sidewall of the first electrode and conformally covering the inner sidewall of the contact electrode; a second electrode located on an outer side of the second semiconductor portion away from the first electrode along the first direction and the second direction; The second dielectric layer is located between the second semiconductor portion and the second electrode and conformally covers a portion of the outer wall of the second semiconductor portion; the second electrode conformally covers the outer wall of the second dielectric layer.

2. The storage unit according to claim 1, wherein The second gate includes a first sub-gate and a second sub-gate stacked in the second direction away from the first semiconductor portion and made of different materials.

3. The storage unit according to claim 2, wherein: The first sub-gate is a polysilicon gate; The second sub-gate and the first gate are metal gates respectively.

4. The storage unit according to claim 1, wherein: The second electrode comprises: a first sub-electrode conformally covering an outer sidewall of the second dielectric layer; The two second sub-electrodes respectively cover outer side walls of the first sub-electrode that are away from the second dielectric layer and opposite to each other in the second direction.

5. The storage unit according to claim 4, wherein: The first sub-electrode is a polysilicon electrode; The second sub-electrode is a metal electrode; the first electrode and the second sub-electrode are electrically connected.

6. The storage unit according to any one of claims 1 to 5, wherein: Also includes: a first isolation structure, located between the first region and the second region; two second isolation structures, respectively located between corresponding second gates and second electrodes; The first isolation structure and the second isolation structure are staggered in the first direction.

7. A memory, characterized in that: include: At least one storage unit according to any one of claims 1 to 6; at least one bit line; The bit line extends along the second direction and is electrically connected to an outer sidewall of the first semiconductor portion of the memory cell that is away from the first gate and extends along the second direction; at least one word line; The word line is electrically connected to the first gate and the two second gates in the memory cell respectively.

8. The memory according to claim 7, wherein: There are multiple storage units, and the multiple storage units are arranged along a third direction; the third direction intersects with the first direction and the second direction in pairs; Wherein, a column of memory cells shares the same word line.

9. A method for preparing a memory, characterized in that: include: forming a stacked structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately stacked; Etching the stack structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form a first receiving hole; forming a semiconductor layer on an inner sidewall of the second sacrificial layer in the first receiving hole; The semiconductor layer is in a closed ring shape, and the region within the ring of the semiconductor layer includes a first region and a second region insulated and isolated from each other in a first direction; the semiconductor layer includes: a first semiconductor portion surrounding a portion of the first region, and a second semiconductor portion surrounding a portion of the second region; forming a first gate in the first region; forming second gates on two sides of the first semiconductor portion that are away from the first gate and opposite to each other in a second direction; the second direction intersects the first direction; forming a contact electrode in the second region conformally covering an inner sidewall of the second semiconductor portion; forming a first dielectric layer in the second region in a closed ring shape that conformally covers the inner sidewall of the contact electrode; forming a first electrode in the inner region of the ring of the first dielectric layer; forming a second dielectric layer on an outer sidewall of the second semiconductor portion away from the first electrode along the first direction and the second direction; A second electrode is formed on an outer sidewall of the second dielectric layer away from the second semiconductor portion.

10. The method for preparing a memory according to claim 9, wherein: The second gate and the second electrode are formed simultaneously.

11. The method for preparing a memory according to claim 9, wherein: The second gate includes: a first sub-gate and a second sub-gate stacked in the second direction away from the first semiconductor portion and made of different materials; the second electrode includes: a first sub-electrode conformally covering an outer sidewall of the second semiconductor portion, and a second sub-electrode respectively covering outer sidewalls of the first sub-electrode facing away from the second semiconductor portion and opposite in the second direction; The etching of the stack structure along the stacking direction of the first sacrificial layer and the second sacrificial layer to form the first accommodating hole includes: etching the stack structure to form two first accommodating areas extending along the first direction and spaced apart in the second direction; forming a third sacrificial layer in the first accommodating areas; and etching the stack structure between the two first accommodating areas to form the first accommodating hole. The manufacturing method of the memory further includes: etching the stack structure to form a first isolation trench, so as to separate the stack structure into a first sub-portion located on a side of the first semiconductor portion facing away from the first gate and a second sub-portion located on a side of the second semiconductor portion facing away from the first electrode through the first isolation trench; The second gates are formed on two sides of the first semiconductor portion facing away from the first gate and opposite to each other in the second direction, comprising: removing at least a portion of the third sacrificial layer in the first sub-portion near the first semiconductor portion to form a second receiving hole, while allowing the second sacrificial layer remaining in the first sub-portion between the first semiconductor portion and the second receiving hole to constitute the first sub-gate; and forming the second sub-gate and a word line connected to the second sub-gate in the second receiving hole. The second electrode is formed on the outer wall of the second dielectric layer away from the second semiconductor part, including: removing at least a portion of the third sacrificial layer in the second section close to the second semiconductor part along the second direction to form a third accommodating hole, and at the same time making the second sacrificial layer in the second section conformally covering the outer wall of the second semiconductor part constitute the first sub-electrode; forming the second sub-electrode in the third accommodating hole.

12. The method for preparing a memory according to claim 11, wherein: Also includes: While etching the stack structure to form the first isolation trench, a second isolation trench is formed to separate a third subsection located on a side of the first subsection away from the second subsection in the stack structure through the second isolation trench; the second sacrificial layer in the third subsection is connected to an outer sidewall of the first semiconductor portion that is away from the first gate and extends along the second direction; removing the second sacrificial layer in the third sub-section to form a bit line accommodating groove; The bit line is formed in the bit line receiving groove.

13. The method for preparing a memory according to any one of claims 9 to 12, wherein: The step of forming a semiconductor layer on the inner sidewall of the second sacrificial layer in the first receiving hole includes: forming a dielectric material layer conformally covering the wall of the first accommodating hole; forming a fourth sacrificial layer covering the inner sidewall of the dielectric material layer and filling the first receiving hole; removing a portion of the fourth sacrificial layer and a portion of the dielectric material layer near a first end of the first accommodating hole in the first direction, exposing a portion of a hole wall of the first accommodating hole; removing the remaining fourth sacrificial layer; forming a semiconductor material layer conformally covering the remaining inner sidewalls of the dielectric material layer and the exposed hole walls of the first receiving hole; Etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed; etching the semiconductor material layer based on the removal area of ​​the first sacrificial layer extending along the second direction to remove the semiconductor material layer extending along the second direction between adjacent second sacrificial layers to form an initial semiconductor layer; Etching the outer sidewall of the first sacrificial layer extending along the first direction until the initial semiconductor layer is exposed; The initial semiconductor layer is etched based on the removal area of ​​the first sacrificial layer extending along the first direction to remove the initial semiconductor layer extending along the first direction between adjacent second sacrificial layers to form the semiconductor layers respectively located on the inner sidewalls of each second sacrificial layer.

14. The method for preparing a memory according to claim 13, wherein: The method further includes etching the outer sidewall of the first sacrificial layer extending along the second direction until the semiconductor material layer is exposed: forming a fifth sacrificial layer covering the inner sidewall of the semiconductor material layer and filling the first receiving hole; removing a first portion of the fifth sacrificial layer near the first end of the first receiving hole to expose the first region, thereby forming the first gate in the first region; After forming the first gate, removing a second portion of the fifth sacrificial layer near the second end of the first receiving hole in the first direction to expose the second region; the first end and the second end are respectively two opposite ends of the fifth sacrificial layer in the first direction; forming a contact electrode material layer in the second region that conformally covers the inner sidewalls of the semiconductor material layer and the remaining sidewalls of the fifth sacrificial layer, and forming a sixth sacrificial layer that covers the inner sidewalls of the contact electrode material layer and fills the second region; removing the remaining fifth sacrificial layer; etching the contact electrode material layer based on the removed area of ​​the fifth sacrificial layer so that the contact electrode material layer conformally covering the inner sidewall of the second semiconductor portion constitutes the contact electrode; A first isolation structure is formed in the removed areas of the fifth sacrificial layer and the contact electrode material layer.

15. The method for preparing a memory according to claim 14, wherein: The method comprises forming a first dielectric layer in the second region that conformally covers the inner sidewall of the contact electrode and is in a closed ring shape, and forming a first electrode in the inner region of the ring of the first dielectric layer, comprising: removing the sixth sacrificial layer; forming the first dielectric layer conformally covering the inner sidewall of the contact electrode and the first isolation structure close to the sidewall of the contact electrode; The first electrode is formed to cover the inner sidewall of the first dielectric layer and fill the sixth sacrificial layer removed area.

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