Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention discloses a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes: providing a substrate; forming a target film, a first mask film, a second mask film, and an upper mask pattern on the substrate; forming a first spacer pattern including a first line portion, a second line portion, and a folded portion connecting the first line portion and the second line portion; forming a slit mask pattern partially covering the first spacer pattern; forming a first mask pattern by patterning the second mask film using the slit mask pattern and the first spacer pattern as an etching mask; forming a second spacer pattern; forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask; and forming a plurality of target patterns by patterning the target film using the second mask pattern as an etching mask.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0090902 filed in the Korean Intellectual Property Office on July 13, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of the present disclosure relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a line pattern and a method of manufacturing the same. Background Art

[0003] As semiconductor devices become more and more integrated, individual circuit patterns are becoming finer to implement more semiconductor devices within the same area. However, the miniaturization of individual circuit patterns increases the complexity of the manufacturing process and may cause defects. Summary of the invention

[0004] Embodiments of the present disclosure provide a method of manufacturing a semiconductor device with improved process margin.

[0005] Embodiments of the present disclosure also provide a semiconductor device with improved integration.

[0006] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate including a first region and a second region; sequentially forming a target film, a first mask film, a second mask film and an upper mask pattern on the substrate; forming a first spacer pattern extending along a side surface of the upper mask pattern, wherein the first spacer pattern comprises a first line portion, a second line portion and a folded portion, the first line portion and the second line portion extending in parallel across the first region and the second region, the folded portion bending from the first line portion and the second line portion on the second region and connecting the first line portion and the second line portion; forming a slit mask pattern covering the first spacer pattern on the second region; forming the first mask pattern by patterning the second mask film using the slit mask pattern and the first spacer pattern as an etching mask; forming a second spacer pattern extending along an inner side surface and an outer side surface of the first mask pattern; forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask; and forming a plurality of target patterns by patterning the target film using the second mask pattern as an etching mask.

[0007] According to one embodiment, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate; sequentially forming a target film, a first mask film, a second mask film, and an upper mask pattern on the substrate; forming a first spacer pattern extending along a side surface of the upper mask pattern; forming a first mask pattern by patterning the second mask film using the first spacer pattern as an etching mask; forming a second spacer pattern, the second spacer pattern including an inner spacer pattern extending along an inner side surface of the first mask pattern and an outer spacer pattern extending along an outer side surface of the first mask pattern; forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask; and forming a plurality of line patterns by patterning the target film using the second mask pattern as an etching mask. The inner spacer pattern includes a first inner line portion, a second inner line portion, a first inner folded portion, and a second inner folded portion, the first inner line portion and the second inner line portion extending in parallel, the first inner folded portion connecting a first end of the first inner line portion and a first end of the second inner line portion, and the second inner folded portion connecting a second end of the first inner line portion and a second end of the second inner line portion. The outer spacer pattern extends along an outer circumference of the first inner line portion, an outer circumference of the second inner line portion, and an outer circumference of the second inner folding portion, and does not extend along an outer circumference of the first inner folding portion.

[0008] According to one embodiment, a semiconductor device is provided, comprising: a substrate; a first conductive pattern disposed on the substrate, wherein the first conductive pattern includes a first line pattern, a second line pattern, and a first folding pattern, the first line pattern and the second line pattern extend in parallel in a first direction, and the first folding pattern connects a first end of the first line pattern and a first end of the second line pattern; and a second conductive pattern disposed on the substrate, wherein the second conductive pattern includes a third line pattern, a fourth line pattern, and a second folding pattern, the third line pattern and the fourth line pattern extend in parallel in the first direction, and the second folding pattern connects a first end of the third line pattern and a first end of the fourth line pattern. The second folding pattern protrudes beyond the first folding pattern in the first direction, and the first conductive pattern and the second conductive pattern are alternately and repeatedly arranged in a second direction intersecting the first direction.

[0009] It should be noted that the effects of the present disclosure are not limited to the effects described above, and other effects of the present disclosure will be clear from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a layout of a semiconductor device according to some embodiments.

[0011] Figure 2 yes Figure 1 An enlarged layout of region R.

[0012] Figure 3 It is along Figure 2 A cross-sectional view taken along line I1-I1.

[0013] Figure 4 It is along Figure 2 A cross-sectional view taken along line I2-I2.

[0014] Figure 5 and Figure 6 is a semiconductor device according to some embodiments ( Figure 1 ) is an enlarged layout of area R.

[0015] Figures 7 to 32 Intermediate steps of a method of manufacturing a semiconductor device according to some embodiments are shown.

[0016] Fig.33 is a layout diagram illustrating intermediate steps of a method of fabricating a semiconductor device according to some embodiments.

[0017] Figure 34 to Figure 39 Intermediate steps of a method of manufacturing a semiconductor device according to some embodiments are shown.

[0018] Figures 40 to 49 Intermediate steps of a method of manufacturing a semiconductor device according to some embodiments are shown.

[0019] Figure 50 to Figure 53 Intermediate steps of a method of manufacturing a semiconductor device according to some embodiments are shown. DETAILED DESCRIPTION

[0020] In this specification, dynamic random access memory (DRAM) will be mainly described as an exemplary semiconductor device, but it is only illustrative. Those skilled in the art to which the present disclosure belongs will understand that the embodiments of the inventive concept can be applied to various other semiconductor devices including circuit patterns formed by patterning. For example, the embodiments of the inventive concept can be applied to different semiconductor devices (such as system large-scale integrated circuits (LSI), flash memory, static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RERAM), complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), micro-electromechanical system (MEM), active components, passive components, etc.).

[0021] Will refer to below Figures 1 to 6 Semiconductor devices according to some exemplary embodiments are described.

[0022] Figure 1 is a layout of a semiconductor device according to some embodiments. Figure 2 yes Figure 1 An enlarged layout of region R. Figure 3 It is along Figure 2 A cross-sectional view taken along line I1-I1. Figure 4 It is along Figure 2 A cross-sectional view taken along line I2-I2.

[0023] Reference Figure 1 and Figure 2 , a semiconductor device according to some embodiments includes a cell region CR, boundary regions ER1 and ER2 , and a peripheral region PR.

[0024] The memory cells are arranged in the cell region CR. The peripheral region PR is a core / peripheral region formed near the cell region CR. In the peripheral region PR, some control components and dummy components that control the functions of the memory cells formed in the cell region CR are formed. The peripheral region PR is shown as surrounding the cell region CR, but the embodiments of the present disclosure are not necessarily limited thereto. For example, in other embodiments, the cell region CR and the peripheral region PR are arranged in various other configurations. In this specification, the cell region CR may also be referred to as a first region.

[0025] In some embodiments, the peripheral region PR includes first and second peripheral regions PR1 and PR2, and the first and second peripheral regions PR1 and PR2 are arranged near the cell region CR in the first direction X. The cell region CR is interposed in the first direction X between the first and second peripheral regions PR1 and PR2.

[0026] The boundary regions ER1 and ER2 are disposed between the cell region CR and the peripheral region PR. For example, the boundary regions ER1 and ER2 include a first boundary region ER1 and a second boundary region ER2. The first boundary region ER1 is disposed between the cell region CR and the first peripheral region PR1, and the second boundary region ER2 is located between the cell region CR and the second peripheral region PR2. In this specification, the first boundary region ER1 may also be referred to as a second region.

[0027] Reference Figures 1 to 4 According to some embodiments, the semiconductor device includes a substrate 100, a device isolation pattern 110, a base insulating layer 120, a conductive pattern 130, a first capping pattern 137, a gate electrode 160, a gate dielectric layer 162, a second capping pattern 168, a direct contact DC, a spacer structure 140, a buried contact BC, a landing pad (or "pad") LP, a capacitor structure 190 and a contact plug CP.

[0028] The substrate 100 is a semiconductor substrate (such as a silicon wafer). The substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but the embodiments of the present disclosure are not necessarily limited thereto. The substrate 100 is one of a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, and a semiconductor on insulator (SOI) substrate. For illustrative purposes, the substrate 100 will be described as a silicon substrate hereinafter.

[0029] The substrate 100 includes an active region AR. The active region AR is defined in the substrate 100 by a device isolation pattern 110. As the design rule of the semiconductor device decreases, the active region AR is formed into a strip shape extending obliquely. Figure 2 As shown in , the active region AR is a strip extending in a direction different from the first direction X and the second direction Y on a plane including the first direction X and the second direction Y.

[0030] The active region AR includes a plurality of strip-shaped regions extending parallel to each other. In some embodiments, the center of one of the active regions AR is adjacent to an end of another active region (AR).

[0031] The active regions AR serve as source / drain regions and contain impurities. For example, a first portion (such as a central portion) of each active region AR is connected to the conductive pattern 130 via a direct contact DC, and a second portion (such as two end portions) of the corresponding active region AR is connected to the capacitor structure 190 via a buried contact BC and / or a bonding pad LP.

[0032] The base insulating layer 120 is formed on the substrate 100 and the device isolation pattern 110. The base insulating layer 120 is interposed between the substrate 100 and the conductive pattern 130 or between the device isolation pattern 110 and the conductive pattern 130.

[0033] In one embodiment, the base insulating layer 120 is a single layer. In another embodiment, Figure 3 and Figure 4 As shown in , the base insulating layer 120 has a multi-layer structure. For example, the base insulating layer 120 includes a first insulating layer 122, a second insulating layer 124, and a third insulating layer 126 sequentially stacked on the substrate 100 and the device isolation pattern 110. For example, the first insulating layer 122 includes a silicon oxide layer, the second insulating layer 124 includes a silicon nitride layer, and the third insulating layer 126 includes a silicon oxide layer.

[0034] The conductive pattern 130 is formed on the substrate 100, the device isolation pattern 110, and the base insulating layer 120. The conductive pattern 130 intersects the active region AR and the gate electrode 160. For example, the conductive pattern 130 extends longitudinally (or "lengthwise") in a first direction X, crosses the active region AR obliquely, and intersects the gate electrode 160 perpendicularly. A plurality of conductive patterns 130 are arranged along a second direction Y intersecting the first direction X. The conductive pattern 130 may be a bit line.

[0035] The conductive pattern 130 has a “U” shape from a planar perspective. For example, the conductive pattern 130 includes a plurality of line patterns 130a1, 130b1, 130a2, and 130b2 extending in parallel and a plurality of folding patterns 130c1 and 130c2 connecting the line patterns 130a1, 130b1, 130a2, and 130b2.

[0036] The line patterns 130a1, 130b1, 130a2, and 130b2 extend longitudinally in the first direction X across the cell region CR. For example, the line patterns 130a1, 130b1, 130a2, and 130b2 extend in the first direction X across the first boundary region ER1, the cell region CR, and the second boundary region ER2.

[0037] The folding patterns 130c1 and 130c2 may connect the line patterns 130a1, 130b1, 130a2, and 130b2 outside the cell region CR. For example, the folding patterns 130c1 and 130c2 are disposed in the first boundary region ER1.

[0038] For example, each conductive pattern 130 includes a first conductive pattern 1301 and a second conductive pattern 1302 arranged along the second direction Y.

[0039] The first conductive pattern 1301 includes a first line pattern 130a1, a second line pattern 130b1, and a first folding pattern 130c1. The first line pattern 130a1 and the second line pattern 130b1 extend longitudinally in the first direction X and are arranged along the second direction Y. The first folding pattern 130c1 connects a first end of the first line pattern 130a1 and a first end of the second line pattern 130b1 in the first boundary region ER1. In some embodiments, the second end of the first line pattern 130a1 and the second end of the second line pattern 130b1 are spaced apart from each other in the second direction Y. For example, the first line pattern 130a1 and the second line pattern 130b1 are not connected in the second boundary region ER2.

[0040] The second conductive pattern 1302 includes a third line pattern 130a2, a fourth line pattern 130b2, and a second folding pattern 130c2. The third line pattern 130a2 and the fourth line pattern 130b2 extend longitudinally in the first direction X and are arranged along the second direction Y. The second folding pattern 130c2 connects a first end of the third line pattern 130a2 and a first end of the fourth line pattern 130b2 in the first boundary region ER1. In some embodiments, a second end of the third line pattern 130a2 and a second end of the fourth line pattern 130b2 are spaced apart from each other in the second direction Y. For example, the third line pattern 130a2 and the fourth line pattern 130b2 are not connected in the second boundary region ER2.

[0041] In some embodiments, the folding patterns 130c1 and 130c2 are arranged in a row in the second direction Y. For example, the first folding pattern 130c1 and the second folding pattern 130c2 are located on a straight line extending in the second direction Y.

[0042] In some embodiments, the second ends of the line patterns 130a1, 130b1, 130a2, and 130b2 are aligned in a row along the second direction Y. For example, the second end of the first line pattern 130a1, the second end of the second line pattern 130b1, the second end of the third line pattern 130a2, and the second end of the fourth line pattern 130b2 are all located on a straight line extending in the second direction Y.

[0043] In some embodiments, the line patterns 130a1, 130b1, 130a2, and 130b2 extend longitudinally in the first direction X and are connected to a plurality of active regions AR arranged along the first direction X. For example, each of the line patterns 130a1, 130b1, 130a2, 130b2 is connected to a first portion (such as a central portion) of the active region AR through a plurality of direct contacts DC arranged along the first direction X.

[0044] In some embodiments, the pitches P1 and P2 between the line patterns 130a1, 130b1, 130a2, and 130b2 are the same. Here, the term "same" includes not only being completely the same, but also being slightly different due to process margins and other factors. For example, Figure 2 As shown in FIG. 1 , a pitch P1 between the first line pattern 130a1 and the second line pattern 130b1 or between the third line pattern 130a2 and the fourth line pattern 130b2 is the same as a pitch P2 between the first line pattern 130a1 and the fourth line pattern 130b2.

[0045] In some embodiments, the pitches P1, P2 are about 10 nm or less. For example, the pitches P1, P2 are in the range of about 4 nm to about 10 nm. The line patterns 130a1, 130b1, 130a2, and 130b2 are set by using, for example, a multiple patterning technique (MPT). In some embodiments, the line patterns 130a1, 130b1, 130a2, and 130b2 are set by using a quadruple patterning technique (QPT).

[0046] In some embodiments, the conductive pattern 130 has a single layer. In other embodiments, such as Figure 3 and Figure 4 As shown in , the conductive pattern 130 includes a plurality of layers. For example, the conductive pattern 130 includes a first sub-conductive layer 132, a second sub-conductive layer 134, and a third sub-conductive layer 136 sequentially stacked on the substrate 100. The first sub-conductive layer 132, the second sub-conductive layer 134, and the third sub-conductive layer 136 each include a conductive material (such as, at least one of polysilicon, TiN, TiSiN, tungsten (W), and tungsten silicide, or a combination thereof). For example, the first sub-conductive layer 132 includes polysilicon, the second sub-conductive layer 134 includes TiSiN, and the third sub-conductive layer 136 includes W.

[0047] The first capping pattern 137 is formed on the conductive pattern 130. The first capping pattern 137 extends along the top surface of the conductive pattern 130. In some embodiments, the first capping pattern 137 has a single layer. In other embodiments, Figure 3 and Figure 4 As shown in , the first capping pattern 137 includes a plurality of layers. For example, the first capping pattern 137 includes a first sub-capping pattern 138 and a second sub-capping pattern 139 sequentially stacked on the conductive pattern 130. The first sub-capping pattern 138 and the second sub-capping pattern 139 each include an insulating material (such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, or a combination thereof). For example, the first sub-capping pattern 138 and the second sub-capping pattern 139 each include silicon nitride.

[0048] The gate electrode 160 is formed on the substrate 100 and the device isolation pattern 110. The gate electrode 160 intersects both the active region AR and the conductive pattern 130. For example, the gate electrode 160 extends longitudinally in the second direction Y, intersects the active region AR obliquely, and also intersects the conductive pattern 130 vertically. In addition, the gate electrode 160 passes through a portion between a first portion (such as a central portion) and a second portion (such as two end portions) of the active region AR. For example, the gate electrode 160 passes through the active region AR between the direct contact DC and the buried contact BC. A plurality of gate electrodes 160 are arranged along the first direction X. The gate electrode 160 may be a word line.

[0049] In some embodiments, the gate electrode 160 has a single layer. In other embodiments, such as Figure 4 As shown in , the gate electrode 160 includes a plurality of layers. For example, the gate electrode 160 includes a fourth sub-conductive layer 164 and a fifth sub-conductive layer 166 sequentially stacked on the substrate 100. The fourth sub-conductive layer 164 and the fifth sub-conductive layer 166 each include a material such as a metal, polysilicon, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the fourth sub-conductive layer 164 includes TiN, and the fifth sub-conductive layer 166 includes n-type doped polysilicon.

[0050] The gate dielectric layer 162 is disposed between the gate electrode 160 and the substrate 100 (or the active region AR). The gate dielectric layer 162 includes at least one of silicon oxide, silicon oxynitride, silicon nitride, and a material having a dielectric constant greater than that of silicon oxide, but the embodiments of the present disclosure are not necessarily limited thereto.

[0051] The second capping pattern 168 is formed on the gate electrode 160. The second capping pattern 168 extends along the top surface of the gate electrode 160. The second capping pattern 168 includes an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto. The second capping pattern 168 may be a single layer or multiple layers including various combinations of insulating materials.

[0052] In some embodiments, the gate electrode 160 is buried in the substrate 100. For example, the substrate 100 includes a gate trench WT extending in the second direction Y. The gate dielectric layer 162 extends along the outline of the gate trench WT. The gate electrode 160 fills a portion of the gate trench WT on the gate dielectric layer 162. The second capping pattern 168 fills the other portion of the gate trench WT on the gate electrode 160. For example, the top surface of the gate electrode 160 is lower than the surface (e.g., the top surface) of the substrate 100.

[0053] A direct contact DC is formed on the substrate 100 and the device isolation pattern 110. The direct contact DC connects the active region AR of the substrate 100 with the conductive pattern 130. For example, the substrate 100 includes a first contact trench CT1 that penetrates the base insulating layer 120 and exposes a first portion (such as a central portion) of the active region AR. The direct contact DC is formed in the first contact trench CT1 to connect the active region AR of the substrate 100 with the conductive pattern 130.

[0054] In some embodiments, the first contact trench CT1 exposes a central portion of the active region AR. For example, the direct contact DC is connected to the central portion of the active region AR.

[0055] The direct contact DC includes a conductive material (such as at least one of polysilicon, TiN, TiSiN, W, and tungsten silicide, or a combination thereof), but the embodiments of the present disclosure are not necessarily limited thereto. For example, the direct contact DC includes polysilicon. The conductive pattern 130 is electrically connected to the active region AR of the substrate 100 through the direct contact DC.

[0056] The spacer structure 140 is formed on the side of the conductive pattern 130. The spacer structure 140 extends along the side of the conductive pattern 130 and the side of the first capping pattern 137. In some embodiments, the height of the spacer structure 140 (e.g., the level of the uppermost end of the spacer structure 140) is the same as or lower than the height of the top surface of the first capping pattern 137.

[0057] The spacer structure 140 includes an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto.

[0058] In some embodiments, the spacer structure 140 has multiple layers including various combinations of insulating materials. For example, the spacer structure 140 includes a base spacer 141 , a first lower spacer 142 , a second lower spacer 143 , a first side spacer 144 , and a second side spacer 145 .

[0059] The base spacer 141 is formed on the side of the conductive pattern 130. For example, the base spacer 141 conformally extends along at least a portion of the contour of the side of the conductive pattern 130 and the side of the first capping pattern 137. In some embodiments, the base spacer 141 is the innermost spacer of the spacer structure 140 that contacts the conductive pattern 130 and the direct contact DC.

[0060] The first lower spacer 142 is formed on the base spacer 141 within the first contact trench CT1. For example, the first lower spacer 142 conformally extends along the contour of the base spacer 141 within the first contact trench CT1.

[0061] The second lower spacer 143 is formed on the first lower spacer 142 within the first contact trench CT1. For example, the second lower spacer 143 fills a region of the first contact trench CT1 that remains after the base spacer 141 and the first lower spacer 142 have been formed.

[0062] The first side spacer 144 is formed on the outer side of the base spacer 141. In addition, the first side spacer 144 is also formed on the first lower spacer 142 and the second lower spacer 143. For example, the first side spacer 144 conformally extends along a portion of the side of the first capping pattern 137 and the contour of the conductive pattern 130.

[0063] The second side spacer 145 is formed on the outer side of the first side spacer 144. In addition, the second side spacer 145 is also formed on the second lower spacer 143. For example, the second side spacer 145 conformally extends along a portion of the side of the first capping pattern 137 and the contour of the conductive pattern 130. In some embodiments, the second side spacer 145 is an outermost spacer that contacts the buried contact BC.

[0064] The base spacer 141, the first lower spacer 142, the second lower spacer 143, the first side spacer 144 and the second side spacer 145 each include an insulating material (such as, at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide or a combination thereof), but the embodiments of the present disclosure are not necessarily limited thereto.

[0065] The buried contact BC is formed on the substrate 100 and the device isolation pattern 110. The buried contact BC connects the active region AR of the substrate 100 with the bonding pad LP. For example, the substrate 100 includes a second contact trench CT2 that penetrates the base insulating layer 120 and exposes a second portion of the active region AR. The buried contact BC is formed in the second contact trench CT2 and connects the active region AR of the substrate 100 with the bonding pad LP.

[0066] In some embodiments, the second contact trench CT2 exposes both end portions of the active region AR. For example, the buried contact BC is connected to both end portions of the active region AR.

[0067] The buried contact BC is formed on the side surface of the conductive pattern 130. In addition, the buried contact BC is spaced apart from the conductive pattern 130 by the spacer structure 140. For example, Figure 3 , the buried contact BC extends along a portion of the outer side surface of the spacer structure 140. The plurality of buried contacts BC arranged along the first direction X are spaced apart from each other by the conductive pattern 130 and the spacer structure 140 extending longitudinally in the first direction X. In some embodiments, a top surface of the buried contact BC is lower than a top surface of the first capping pattern 137.

[0068] The buried contacts BC form a plurality of isolation regions spaced apart from each other. For example, the buried contacts BC are interposed between the conductive patterns 130 and between the gate electrodes 160. In some embodiments, the buried contacts BC are arranged in a lattice structure.

[0069] The buried contact BC includes a conductive material such as at least one of polysilicon, TiN, TiSiN, W, and tungsten silicide, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the buried contact BC includes polysilicon.

[0070] The bonding pad LP is formed on the buried contact BC. The bonding pad LP is electrically connected to the buried contact BC. In some embodiments, the bonding pad LP at least partially overlaps the buried contact BC. For example, Figure 3 As shown in FIG. 1 , some portions of the bonding pad LP overlap the buried contact BC, and other portions of the bonding pad LP overlap some portions of the spacer structure 140 and some portions of the first capping pattern 137 .

[0071] The bonding pad LP includes a conductive material such as at least one of polysilicon, TiN, TiSiN, W, and tungsten silicide, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the bonding pad LP includes W. The capacitor structure 190 is electrically connected to the active region AR of the substrate 100 through the buried contact BC and the bonding pad LP.

[0072] The bonding pads LP form a plurality of isolation regions spaced apart from each other. For example, a pad groove PT is formed to define the bonding pads LP. The pad groove PT extends downward from the top surface of the bonding pad LP, and the bottom surface of the pad groove PT is lower than the top surface of the spacer structure 140. In addition, at least some portions of the pad groove PT overlap with at least some portions of the spacer structure 140. For example, the pad groove PT overlaps with some portions of the spacer structure 140 and some portions of the first cover pattern 137. For example, the bonding pads LP are separated from each other by the pad groove PT.

[0073] In some embodiments, an isolation pattern 180 is formed to fill the pad trench PT. The isolation pattern 180 includes an insulating material such as, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a material having a dielectric constant lower than that of silicon oxide, but the embodiments of the present disclosure are not necessarily limited thereto. The bonding pads LP are electrically separated from each other by the isolation pattern 180.

[0074] In some embodiments, the bonding pads LP have a honeycomb structure. The bonding pads LP arranged in the honeycomb structure can improve the integration of the semiconductor device.

[0075] The capacitor structure 190 is formed on the isolation pattern 180 and the bonding pad LP. The capacitor structure 190 is connected to the top surface of the bonding pad LP. For example, the isolation pattern 180 exposes at least some portions of the top surface of the bonding pad LP. The capacitor structure 190 is connected to at least some portions of the top surface of the bonding pad LP exposed by the isolation pattern 180. For example, the capacitor structure 190 is electrically connected to the active region AR of the substrate 100 through the buried contact BC and the bonding pad LP.

[0076] The capacitor structure 190 stores data and is controlled by the conductive pattern 130 and the gate electrode 160. In some embodiments, the capacitor structure 190 includes a sub-electrode 192, a capacitor dielectric layer 194, and an upper electrode 196 sequentially stacked on the bonding pad LP. The capacitor structure 190 stores charges in the capacitor dielectric layer 194 using a potential difference generated between the sub-electrode 192 and the upper electrode 196.

[0077] The sub-electrode 192 and the upper electrode 196 include, for example, at least one of doped polysilicon, metal, and metal nitride, but are not necessarily limited thereto. In addition, the capacitor dielectric layer 194 includes, for example, at least one of silicon oxide and a high-k material, but the embodiments of the present disclosure are not necessarily limited thereto.

[0078] The contact plug CP is electrically connected to the conductive pattern 130. For example, the contact plug CP is connected to the first line pattern 130a1 of the first conductive pattern 1301 of the conductive pattern 130 and the third line pattern 130a2 of the second conductive pattern 1302 of the conductive pattern 130. According to some embodiments, some control elements in the peripheral region PR are connected to the conductive pattern 130 through the contact plug CP and control the semiconductor device. For example, a sense amplifier in the second peripheral region PR2 is connected to the conductive pattern 130 through the contact plug CP.

[0079] In some embodiments, each conductive pattern 130 is commonly connected to a corresponding pair of active regions AR adjacent in the second direction Y. For example, one active region AR of two active regions AR adjacent in the second direction Y is connected to one line pattern of the corresponding conductive pattern 130 (e.g., the first line pattern 130a1 of the first conductive pattern 1301), and the other active region AR is connected to the other line pattern of the corresponding conductive pattern 130 (e.g., the second line pattern 130b1 of the first conductive pattern 1301). In addition, in some embodiments, two adjacent active regions AR share one gate electrode 160 extending in the second direction Y. For example, a semiconductor memory device having an improved unit memory cell storage capacity (such as capacitance) can be provided.

[0080] Figure 5 and Figure 6 is a semiconductor device according to some embodiments ( Figure 1 For convenience, the above reference will be summarized or omitted. Figures 1 to 4 Description of the component described.

[0081] Reference Figure 5 In some embodiments, the folding patterns 130c1 and 130c2 have a width greater than that of the line patterns 130a1, 130b1, 130a2, and 130b2.

[0082] For example, the width Wc of the first folding pattern 130c1 in the first direction X is greater than the width Wa of the first line pattern 130a1 in the second direction Y, and the width Wc of the first folding pattern 130c1 in the first direction X is greater than the width Wb of the second line pattern 130b1 in the second direction Y. The width Wa of the first line pattern 130a1 is the same as the width Wb of the second line pattern 130b1.

[0083] Reference Figure 6 In some embodiments, the conductive patterns 130 protrude in the first direction X alternately.

[0084] For example, the second folding pattern 130c2 of the second conductive pattern 1302 protrudes from the first folding pattern 130c1 of the first conductive pattern 1301 toward the first peripheral region PR1 by a distance D1 in the first direction X. The first conductive patterns 1301 and the second conductive patterns 1302 are alternately and repeatedly arranged in the second direction Y.

[0085] In some embodiments, the width Wc1 of the first folding pattern 130c1 and the width Wc2 of the second folding pattern 130c2 are each greater than the widths of the line patterns 130a1, 130b1, 130a2, and 130b2. The widths Wc1 and Wc2 are shown to be the same, but embodiments of the present disclosure are not necessarily limited thereto. In other embodiments, the widths Wc1 and Wc2 are different.

[0086] Will refer to below Figures 1 to 53 A method of fabricating a semiconductor device according to some embodiments is described.

[0087] Figures 7 to 32 1 shows intermediate steps of a method of manufacturing a semiconductor device according to some embodiments. For example, Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 , Fig. 27 , Fig.30 and Fig.32 Along the Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig.21 , Fig.23 , Fig.26 , Fig.29 and Fig.31For convenience, the above reference will be summarized or omitted. Figures 1 to 4 Description of the component described.

[0088] Reference Figure 7 and Figure 8 In one embodiment, a target film 130L, first mask films 210L and 215L, second mask films 220L and 225L, and upper mask patterns 230 and 235 are formed on a substrate 100 .

[0089] The target film 130L includes various materials that can be patterned by a patterning process that forms a pattern of a semiconductor device. For example, the target film 130L includes one or more of a conductive film, an insulating film, and a semiconductor film stacked on the substrate 100. For example, the target film 130L is a part of the substrate 100. The target film 130L can be a single film or include a plurality of films, and the plurality of films include a stack of a plurality of material films. The target film 130L is described below as, for example, a conductive film stacked on the substrate 100, but the embodiments of the present disclosure are not necessarily limited thereto.

[0090] In some embodiments, the target film 130L includes a conductive film for forming a bit line. For example, a device isolation pattern 110 defining a plurality of active regions AR in a substrate 100 is formed in a substrate. Thereafter, a base insulating layer 120 is formed on the substrate 100. Thereafter, a direct contact DC connecting the target film 130L with the active region AR is formed. Thereafter, a cap film 137L including an insulating material is formed on the target film 130L.

[0091] The target film 130L includes at least one of polysilicon, TiN, TiSiN, W, and tungsten silicide, or a combination thereof, but the embodiments of the present disclosure are not necessarily limited thereto. For example, the target film 130L includes a polysilicon film, a TiSiN film, and a W film sequentially stacked on the substrate 100 .

[0092] In some embodiments, the target film 130L is formed across the first boundary region ER1 , the cell region CR, and the second boundary region ER2 .

[0093] The first mask films 210L and 215L and the second mask films 220L and 225L are sequentially stacked on the target film 130L and / or the cap film 137L. The first mask films 210L and 215L and the second mask films 220L and 225L are different types of mask films according to the materials included in the target film 130L and / or the cap film 137L. The first mask films 210L and 215L contain a material having an etching selectivity with respect to the target film 130L and / or the cap film (137L). The second mask films 220L and 225L contain a material having an etching selectivity with respect to the first mask films 210L and 215L.

[0094] The first mask films 210L and 215L and the second mask films 220L and 225L include, for example, at least one of a silicon-containing material (such as silicon oxide, silicon oxynitride, silicon nitride, or polycrystalline silicon), a carbon-containing material (such as an amorphous carbon layer (ACL) or a spin-on hard mask (SOH)), a bottom anti-reflective coating (BARC), a metal, and an organic material, but the embodiments of the present disclosure are not necessarily limited thereto.

[0095] In some embodiments, the first mask films 210L and 215L include a first hard mask film 210L and a first anti-reflection film 215L sequentially stacked on the target film 130L and / or the cap film 137L. For example, the first hard mask film 210L includes an ACL film, and the first anti-reflection film 215L includes a SiON film.

[0096] In some embodiments, the second mask films 220L and 225L include a second hard mask film 220L and a second anti-reflection film 225L sequentially stacked on the first mask films 210L and 215L. For example, the second hard mask film 220L includes an ACL film, and the second anti-reflection film 225L includes a SiON film.

[0097] The upper mask patterns 230 and 235 are formed on the second mask films 220L and 225L. The upper mask patterns 230 and 235 include a material having an etching selectivity with respect to the second mask films 220L and 225L. For example, the upper mask patterns 230 and 235 include, for example, at least one of a silicon-containing material such as silicon oxide, silicon oxynitride, silicon nitride, or polysilicon, a carbon-containing material such as ACL or SOH, BARC, a metal, and an organic material, but the embodiments of the present disclosure are not necessarily limited thereto.

[0098] In some embodiments, the upper mask patterns 230 and 235 include an upper hard mask pattern 230 and an upper anti-reflective pattern 235 sequentially stacked on the second mask films 220L and 225L. For example, the upper hard mask pattern 230 includes a SOH film, and the upper anti-reflective pattern 235 includes a SiON film.

[0099] The upper mask patterns 230 and 235 include a plurality of upper mask lines 230a and 230b extending parallel to the first direction X. For example, the upper mask lines 230a and 230b extend longitudinally in the first direction X and include first and second upper mask lines 230a and 230b arranged along the second direction Y.

[0100] The upper mask lines 230a and 230b extend longitudinally in the first direction X and pass through the cell region CR. For example, the upper mask lines 230a and 230b extend along the first direction X and pass through the first boundary region ER1, the cell region CR, the second boundary region ER2, and the second peripheral region PR2.

[0101] In some embodiments, the upper mask patterns 230 and 235 further include an upper mask base 230c. The upper mask base 230c covers the first peripheral region PR1 and a portion of the first boundary region ER1. The upper mask lines 230a and 230b extend from the upper mask base 230c along the first direction X. The upper mask lines 230a and 230b and the upper mask base 230c define a plurality of upper mask openings 230o extending parallel to the first direction X within the upper mask patterns 230 and 235. For example, the first upper mask line 230a and the second upper mask line 230b define side surfaces of the upper mask openings 230o intersecting the second direction Y, and the upper mask base 230c defines side surfaces of the upper mask openings 230o intersecting the first direction X.

[0102] Reference Fig. 9 and Fig.10 In one embodiment, Figure 7 and Figure 8 A first spacer film 240L is formed on the structure depicted in FIG.

[0103] The first spacer film 240L covers the second mask films 220L and 225L and the upper mask patterns 230 and 235. For example, the first spacer film 240L conformally extends along top surfaces of the second mask films 220L and 225L and side and top surfaces of the upper mask patterns 230 and 235.

[0104] The first spacer film 240L includes a material having an etching selectivity with respect to the second mask films 220L and 225L and the upper mask patterns 230 and 235. For example, the first spacer film 240L includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the first spacer film 240L includes a silicon oxide film.

[0105] Reference Fig.11 and Fig.12 In one embodiment, the first spacer pattern 240 is formed by performing an etching process on the first spacer film 240L.

[0106] As a result of the etching process on the first spacer film 240L, a portion of the first spacer film 240L covering the top surfaces of the second mask films 220L and 225L and the top surfaces of the upper mask patterns 230 and 235 is removed. For example, the first spacer pattern 240 extending along the side surfaces of the upper mask patterns (230 and 235) is formed.

[0107] The first spacer pattern 240 includes a first line portion 240a, a second line portion 240b, a first folding portion 240c, and a second folding portion 240d. The first line portion 240a extends in the first direction X along the side surface of the first upper mask line 230a. The second line portion 240b extends in the first direction X along the side surface of the second upper mask line 230b. The first folding portion 240c connects the first line portion 240a and the second line portion 240b in the first boundary region ER1. For example, the first folding portion 240c is bent from the first end of the first line portion 240a and the first end of the second line portion 240b and extends in the second direction Y. The second folding portion 240d connects the first line portion 240a and the second line portion 240b on the opposite side of the first folding portion 240c. For example, the second folding portion 240d is bent from the second end of the first line portion 240a and the second end of the second line portion 240b and extends in the second direction Y. In some embodiments, the first line portion 240 a , the second line portion 240 b , the first folded portion 240 c , and the second folded portion 240 d extend along side surfaces of the upper mask opening 230 o .

[0108] In some embodiments, the first folded portion 240 c overlaps the target film 130L in the third direction Z. For example, the first folded portion 240 c is disposed in the first boundary region ER1 .

[0109] In some embodiments, the second folded portion 240 d does not overlap the target film 130L in the third direction Z. For example, the second folded portion 240 d is disposed in the second peripheral region PR2 .

[0110] In some embodiments, the upper anti-reflective pattern 235 is removed by an etching process on the first spacer film 240L. For example, the etching process on the first spacer film 240L continues until the upper hard mask pattern 230 is exposed. In some embodiments, the second anti-reflective film 225L serves as an etching stop film during the etching process on the first spacer film 240L. A portion of the second anti-reflective film 225L is removed by the etching process on the first spacer film 240L.

[0111] Reference Fig.13 and Fig.14 , in one embodiment, the upper mask patterns 230 and 235 are removed.

[0112] The upper mask patterns 230 and 235 are selectively removed with respect to the second mask films 220L and 225L and the first spacer patterns 240. For example, portions of the upper hard mask pattern 230 exposed between the first spacer patterns 240 are removed. The upper hard mask pattern 230 may be removed by, for example, an ashing process and / or a stripping process, but embodiments of the present disclosure are not necessarily limited thereto.

[0113] Reference Fig.15 and Fig.16 In one embodiment, a slit mask pattern 310 is formed to cover at least a portion of the first boundary region ER1.

[0114] The slit mask pattern 310 is formed on the second mask films 220L and 225L and the first spacer pattern 240. The slit mask pattern 310 covers the first folded portion 240c disposed in the first boundary region ER1. For example, the slit mask pattern 310 covers the first folded portion 240c, a portion of the first line portion 240a adjacent to the first folded portion 240c, and a portion of the second line portion 240b adjacent to the first folded portion 240c.

[0115] The slit mask pattern 310 includes a material having an etch selectivity with respect to the second mask films 220L and 225L. In some embodiments, the slit mask pattern 310 includes a photoresist.

[0116] Reference Fig.17 and Fig.18 In one embodiment, the first mask patterns 220 and 225 are formed by patterning the second mask films 220L and 225L using the first spacer patterns 240 and the slit mask patterns 310 as etching masks.

[0117] For example, an etching process of the second mask films 220L and 225L is performed using the first spacer pattern 240 and the slit mask pattern 310 as an etching mask. For example, the first mask patterns 220 and 225 are formed to have shapes transferred from the first spacer pattern 240 and the slit mask pattern 310. In some embodiments, the first mask patterns 220 and 225 include a first hard mask pattern 220 and a first anti-reflective pattern 225. The first hard mask pattern 220 is formed from the second hard mask film 220L, and the first anti-reflective pattern 225 is formed from the second anti-reflective film 225L.

[0118] In some embodiments, the slit mask pattern 310 is removed during the formation of the first mask patterns 220 and 225 .

[0119] Reference Fig.19 Fig. 20 In one embodiment, Fig.17 and Fig.18A second spacer film 250L is formed on the structure depicted in FIG.

[0120] The second spacer film 250L covers the first mask films 210L and 215L and the first mask patterns 220 and 225. For example, the second spacer film 250L conformally extends along top surfaces of the first mask films 210L and 215L and side and top surfaces of the first mask patterns 220 and 225.

[0121] The second spacer film 250L includes a material having an etching selectivity with respect to the first mask films 210L and 215L and the first mask patterns 220 and 225. For example, the second spacer film 250L includes at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the second spacer film 250L includes a silicon oxide film.

[0122] Reference Fig.21 and Fig. 22 In one embodiment, the second spacer pattern 250 is formed by performing an etching process on the second spacer film 250L.

[0123] As a result of the etching process on the second spacer film 250L, a portion of the second spacer film 250L covering the top surfaces of the first mask films 210L and 215L and the top surfaces of the first mask patterns 220 and 225 is removed. For example, the second spacer pattern 250 extending along the side surfaces of the first mask patterns 220 and 225 is formed.

[0124] The second spacer pattern 250 includes an inner spacer pattern 252 and an outer spacer pattern 254. The inner spacer pattern 252 extends along the inner side surface of the first mask patterns 220 and 225. The outer spacer pattern 254 extends along the outer side surface of the first mask patterns 220 and 225. The first mask patterns 220 and 225 are interposed between the inner spacer pattern 252 and the outer spacer pattern 254.

[0125] The inner spacer pattern 252 includes a first inner line portion 252a, a second inner line portion 252b, a first inner folding portion 252c, and a second inner folding portion 252d. The first inner line portion 252a extends in the first direction X. The second inner line portion 252b is opposite to the first inner line portion 252a and extends in the first direction X. The first inner folding portion 252c connects the first inner line portion 252a and the second inner line portion 252b in the first boundary region ER1. For example, the first inner folding portion 252c is bent from the first end of the first inner line portion 252a and the first end of the second inner line portion 252b, and extends in the second direction Y. The second inner folding portion 252d connects the first inner line portion 252a and the second inner line portion 252b on the opposite side of the first inner folding portion 252c. For example, the second inner folding portion 252d is bent from the second end of the first inner line portion 252a and the second end of the second inner line portion 252b, and extends in the second direction Y.

[0126] The outer spacer pattern 254 includes a first outer line portion 254a, a second outer line portion 254b, a first outer folding portion 254c, and a second outer folding portion 254d. The first outer line portion 254a and the second outer line portion 254b extend in the first direction X. The first outer line portion 254a and the second outer line portion 254b extend along the outer periphery of the first inner line portion 252a and the outer periphery of the second inner line portion 252b. For example, the first outer line portion 254a is opposite to the first inner line portion 252a, and the first mask patterns 220 and 225 are placed between the first outer line portion 254a and the first inner line portion 252a, the second outer line portion 254b is opposite to the second inner line portion 252b, and the first mask patterns 220 and 225 are placed between the second outer line portion 254b and the second inner line portion 252b. The first outer folding portion 254c connects the corresponding pairs of adjacent first outer line portions 254a and second outer line portions 254b in the first boundary region ER1. The first outer folding portion 254c does not extend along the periphery of the first inner folding portion 252c. For example, the first outer folding portion 254c is bent from the first ends of the corresponding pairs of adjacent first outer line portions 254a and second outer line portions 254b and extends in the second direction Y. The second outer folding portion 254d connects the first outer line portion 254a and the second outer line portion 254b on the opposite side of the first outer folding portion 254c. The second outer folding portion 254d extends along the periphery of the second inner folding portion 252d. For example, the second outer folding portion 254d is bent from the second end of the first outer line portion 254a and the second end of the second outer line portion 254b and extends in the second direction Y.

[0127] In some embodiments, the first inner folded portion 252c and the first outer folded portion 254c overlap the target film 130L in the third direction Z. For example, the first inner folded portion 252c and the first outer folded portion 254c are disposed in the first boundary region ER1.

[0128] In some embodiments, the second inner folded portion 252 d and the second outer folded portion 254 d do not overlap the target film 130L in the third direction Z. For example, the second inner folded portion 252 d and the second outer folded portion 254 d are disposed in the second peripheral region PR2 .

[0129] In some embodiments, the first inner folded portion 252c and the first outer folded portion 254c are arranged in a row along the second direction Y. For example, the first inner folded portion 252c and the first outer folded portion 254c are aligned along a straight line extending in the second direction Y.

[0130] Reference Fig.23 and Fig.24 ,exist Fig.21 and Fig. 22 A gap-fill film 260 is formed on the structure depicted in FIG.

[0131] The gap filling film 260 fills the empty space on the first mask films 210L and 215L. For example, the gap filling film 260 fills the space on the inner side of the inner spacer pattern 252 and the outer side of the outer spacer pattern 254. The gap filling film 260 includes a material such as SOH, but the embodiments of the present disclosure are not necessarily limited thereto.

[0132] Reference Fig.25 In one embodiment, Fig.23 and Fig.24 The structure depicted in FIG. 1 is subjected to a planarization process.

[0133] The etch-back process is performed as a planarization process, but the embodiments of the present disclosure are not necessarily limited thereto. As a result of the planarization process, the top surfaces of the first mask patterns 220 and 225, the second spacer pattern 250, and the gap filling film 260 become planar. For example, a uniform second spacer pattern 250 is obtained.

[0134] In some embodiments, the first anti-reflective pattern 225 is removed during the planarization process.

[0135] Reference Fig.26 and Fig. 27 In one embodiment, the first mask patterns 220 and 225 and the gap-fill film 260 are removed.

[0136] The first mask patterns 220 and 225 and the gap-filling film 260 are selectively removed from between the second spacer patterns 250. For example, portions of the first hard mask pattern 220 and the gap-filling film 260 exposed between the second spacer patterns 250 are removed. The removal of the first hard mask pattern 220 and the gap-filling film 260 may be performed, for example, by an ashing process and / or a stripping process, but embodiments of the present disclosure are not necessarily limited thereto.

[0137] Reference Fig.28 , in one embodiment, a cell opening mask pattern 320 is formed.

[0138] The cell opening mask pattern 320 exposes the cell region CR, the first boundary region ER1 and the second boundary region ER2. For example, the cell opening mask pattern 320 covers the first peripheral region PR1 and the second peripheral region PR2. In some embodiments, the cell opening mask pattern 320 covers the second inner folding portion 252d and the second outer folding portion 254d.

[0139] The cell opening mask pattern 320 includes a material having an etch selectivity with respect to the first mask films 210L and 215L. In some embodiments, the cell opening mask pattern 320 includes a photoresist.

[0140] Reference Fig.29 and Fig.30 In one embodiment, the second mask patterns 210 and 215 are formed by patterning the first mask films 210L and 215L using the second spacer patterns 250 and the cell opening mask patterns 320 as etching masks.

[0141] For example, an etching process of the first mask films 210L and 215L is performed using the second spacer pattern 250 and the cell opening mask pattern 320 as an etching mask. For example, the second mask patterns 210 and 215 are formed to have shapes transferred from the second spacer pattern 250 and the cell opening mask pattern 320. In some embodiments, the second mask patterns 210 and 215 include a second hard mask pattern 210 and a second anti-reflective pattern 215. The second hard mask pattern 210 is formed from the first hard mask film 210L, and the second anti-reflective pattern 215 is formed from the first anti-reflective film 215L.

[0142] In some embodiments, the cell opening mask pattern 320 is removed during the formation of the second mask pattern ( 210 and 215 ).

[0143] Reference Fig.31 and Fig.32 In one embodiment, a target pattern, such as the conductive pattern 130 , is formed by patterning the target film 130L using the second mask patterns 210 and 215 as an etching mask.

[0144] For example, an etching process is performed on the target film 130L and the capping film 137L using the second mask patterns 210 and 215 as etching masks. As a result of the etching process on the target film 130L and the capping film 137L, a target pattern (such as the conductive pattern 130) is formed from an overlapping region of the target film 130L with the second mask patterns 210 and 215. In some embodiments, the target film 130L includes a conductive film. In this manner, a Figure 2 The conductive pattern 130 is formed.

[0145] The conductive pattern 130 has a "U" shape from a planar perspective. For example, the conductive pattern 130 includes a plurality of line patterns 130a1, 130b1, 130a2, and 130b2 extending in parallel and a plurality of folding patterns 130c1 and 130c2 connecting the line patterns 130a1, 130b1, 130a2, and 130b2. The first conductive pattern 1301 (including the first line pattern 130a1, the second line pattern 130b1, and the first folding pattern 130c1) of the conductive pattern 130 is formed to have a shape transferred from the outer spacer pattern 254 by the outer spacer pattern 254, and the second conductive pattern 1302 (including the third line pattern 130a2, the fourth line pattern 130b2, and the second folding pattern 130c2) of the conductive pattern 130 is formed to have a shape transferred from the inner spacer pattern 252 by the inner spacer pattern 252.

[0146] As semiconductor devices become highly integrated, a circuit pattern having a folded region (such as a "U" shaped pattern) may be required. For example, in a semiconductor memory device, a folded bit line may be used to increase the storage capacity of a unit memory cell. Such a circuit pattern may be provided by an MPT (such as a QPT). The circuit pattern obtained from the QPT includes an inner pattern having a "U" shape on the inside of a mask pattern and an outer pattern having a "U" shape on the outside of the mask pattern. However, due to the resolution limit of photolithography, an environmental difference may occur between the inner pattern and the outer pattern, resulting in defects in the circuit pattern.

[0147] In contrast, the method of manufacturing a semiconductor device according to some embodiments uses a slit mask pattern 310 covering the folding region to eliminate the environmental difference between the inner pattern and the outer pattern. Fig.15 As described above, the slit mask pattern 310 covers the first folded portion 240c located in the first boundary region ER1. Fig.21As described above, in subsequent steps, the environmental difference between the folded portion of the inner spacer pattern 252 (such as the first inner folded portion 252c) and the folded portion of the outer spacer pattern 254 (such as the first outer folded portion 254c) can be eliminated. In addition, the second conductive pattern 1302 formed by the inner spacer pattern 252 and the first conductive pattern 1301 formed by the outer spacer pattern 254 can be provided in a more uniform shape. In this way, a semiconductor device with improved integration and a method of manufacturing a semiconductor device with improved process margin can be provided.

[0148] Fig.33 is a layout diagram showing intermediate steps of a method of manufacturing a semiconductor device according to some embodiments. For example, Fig.33 Shown in Fig.28 For convenience, the above references will be summarized or omitted. Figures 1 to 32 Description of the component described.

[0149] Reference Fig.28 and Fig.33 In one embodiment, the second mask patterns 210 and 215 are formed by patterning the first mask films 210L and 215L. The second mask patterns 210 and 215 are formed in the same manner as described above with reference to FIG. Fig.29 and Fig.30 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0150] During the formation of the second mask patterns 210 and 215, a residue 210R may be formed on the folded portions of the second mask patterns 210 and 215. The residue 210R includes an organic material left from patterning the first mask patterns 220 and 225. The residue 210R may be used as an etching mask during patterning of the target film 130L. In this manner, a Figure 5 The conductive pattern 130 is formed.

[0151] Figure 34 to Figure 39 1 shows intermediate steps of a method of manufacturing a semiconductor device according to some embodiments. For example, Fig.34 Shown in Fig. 9 The intermediate steps are performed after the steps depicted in , and Fig.35 , Fig.37 and Fig.39 Along the Fig.34 , Fig.36 and Fig.38 For convenience, the above reference will be summarized or omitted. Figures 1 to 33 Description of the component described.

[0152] Reference Fig. 9, Fig.10 , Fig.34 and Fig.35 In one embodiment, the first spacer pattern 240 is formed by performing an etching process on the first spacer film 240L. The first spacer pattern 240 may be formed in the same manner as described above with reference to Fig.11 and Fig.12 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0153] A portion of the second anti-reflection film 225L is removed by an etching process on the first spacer pattern 240. For example, referring to Fig.35 The second thickness TH2 of the portion of the second anti-reflective film 225L exposed by the upper hard mask pattern 230 and the first spacer pattern 240 is smaller than the first thickness TH1 of the portion of the second anti-reflective film 225L protected by the upper hard mask pattern 230 and the first spacer pattern 240 .

[0154] Reference Fig.36 and Fig.37 In one embodiment, the upper mask patterns 230 and 235 are removed, and the slit mask pattern 310 is formed. The removal of the upper mask patterns 230 and 235 and the formation of the slit mask pattern 310 may be performed in the same manner as described above with reference to FIG. Figures 13 to 16 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0155] Reference Fig.38 and Fig.39 In one embodiment, the first mask patterns 220 and 225 are formed by patterning the second mask films 220L and 225L. The first mask patterns 220 and 225 may be formed in the same manner as described above with reference to FIG. Fig.17 and Fig.18 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0156] The first mask patterns 220 and 225 include first side surfaces 220S1 and second side surfaces 220S2 that alternately protrude in the first direction X. For example, due to the environmental difference between the region of the second mask films 220L and 225L where the first side surfaces 220S1 are formed and the region of the second mask films 220L and 225L where the second side surfaces 220S2 are formed, the first side surfaces 220S1 of the first mask patterns 220 and 225 protrude toward the second peripheral region PR2 by a distance D2 beyond the second side surfaces 220S2 of the first mask patterns 220 and 225. For example, the first side surfaces 220S1 are patterned from the second hard mask film 220L at the second anti-reflective film 225L having a relatively large thickness (such as, Fig.37The second side surface 220S2 is patterned from the second hard mask film 220L on the second anti-reflective film 225L having a relatively small thickness (such as, Fig.37 For example, due to the thinness of the second anti-reflection film 225L, the second side surface 220S2 is etched more by a distance D2 than the first side surface 220S1 in the first direction X.

[0157] After that, execute the above reference Figures 19 to 32 In this way, we can obtain Figure 6 The conductive pattern 130 is formed.

[0158] Figures 40 to 49 1 shows intermediate steps of a method of manufacturing a semiconductor device according to some embodiments. For example, Fig.40 Shown in Fig. 9 The intermediate steps are performed after the steps depicted in , and Fig.41 , Fig.43 , Fig.47 and Fig.49 Along the Fig.40 , Fig.42 , Fig.46 and Fig.48 For convenience, the above reference will be summarized or omitted. Figures 1 to 33 Description of the component described.

[0159] Reference Fig.40 and Fig.41 In one embodiment, a slit mask pattern 310 is formed to cover at least a portion of the first boundary region ER1.

[0160] A slit mask pattern 310 is formed on the second mask films 220L and 225L and the upper mask patterns 230 and 235. The slit mask pattern 310 covers a portion of the first spacer film 240L in the first boundary region ER1. For example, the slit mask pattern 310 covers a portion of the first spacer film 240L adjacent to the upper mask base 230c.

[0161] The slit mask pattern 310 includes a material having an etch selectivity with respect to the second mask films 220L and 225L. In some embodiments, the slit mask pattern 310 includes a photoresist.

[0162] Reference Fig.42 and Fig.43 In one embodiment, the first spacer pattern 240 is formed by performing an etching process on the first spacer film 240L. The first spacer pattern 240 is formed in the same manner as described above with reference to Fig.11 and Fig.12 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0163] During the formation of the first spacer pattern 240, portions of the first spacer film 240L under the slit mask pattern 310 are not etched. For example, at least some portions of the first spacer pattern 240 in the first boundary region ER1 conformally extend along top surfaces of the second mask films 220L and 225L and side and top surfaces of the upper mask patterns 230 and 235.

[0164] Reference Fig.44 In one embodiment, the portions of the upper mask patterns 230 and 235 exposed between the first spacer patterns 240 are removed. The removal of the upper mask patterns 230 and 235 is similar to the above reference. Fig.13 and Fig.14 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0165] Portions of the upper mask patterns 230 and 235 protected by the first spacer pattern 240 are not removed. For example, at least some portions of the upper mask patterns 230 and 235 in the first boundary region ER1 are not removed but remain.

[0166] In some embodiments, the slit mask pattern 310 is removed during the removal of the upper mask patterns ( 230 and 235 ).

[0167] Reference Fig.45 In one embodiment, an etching process is performed on the first spacer pattern 240 .

[0168] As a result of the etching process on the first spacer pattern 240 , portions of the first spacer pattern 240 covering top surfaces of the second mask films 220L and 225L and top surfaces of the upper mask patterns 230 and 235 are removed.

[0169] In some embodiments, the second anti-reflective film 225L is patterned through an etching process of the first spacer pattern 240 , and thus the first anti-reflective pattern 225 is formed.

[0170] In some embodiments, at least some portions of the first anti-reflective pattern 225 in the first boundary region ER1 are not completely patterned. For example, at least some portions of the first anti-reflective pattern 225 in the first boundary region ER1 cover the top surface of the second hard mask film 220L.

[0171] Reference Fig.46 and Fig.47In one embodiment, the first mask patterns 220 and 225 are formed by patterning the second mask films 220L and 225L using the first spacer patterns 240 as an etching mask.

[0172] For example, an etching process of the second hard mask film 220L is performed using the first spacer pattern 240 and the first anti-reflective pattern 225 as an etching mask. In this manner, the first mask patterns 220 and 225 are formed to have shapes transferred from the first spacer pattern 240 and the slit mask pattern 310 .

[0173] Reference Fig.48 and Fig.49 In one embodiment, Fig.46 and Fig.47 The second spacer film 250L is formed on the structure depicted in FIG. The second spacer film 250L is formed in the same manner as described above with reference to FIG. Fig.19 and Fig. 20 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0174] After that, you can execute the above reference Figures 21 to 32 In this way, we can obtain Figure 2 The conductive pattern 130 is formed.

[0175] Figure 50 to Figure 53 1 shows intermediate steps of a method of manufacturing a semiconductor device according to some embodiments. For example, Fig.50 Shown in Fig.40 The intermediate steps are performed after the steps depicted in , and Fig.51 and Fig.53 Along the Fig.50 and Fig.52 For convenience, the above reference will be summarized or omitted. Figures 1 to 49 Description of the component described.

[0176] Reference Fig.40 , Fig.41 , Fig.50 and Fig.51 In one embodiment, the first spacer pattern 240 is formed by performing an etching process on the first spacer film 240L. The first spacer pattern 240 is formed in the same manner as described above with reference to Fig.42 and Fig.43 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0177] A portion of the second anti-reflection film 225L is removed by an etching process on the first spacer film 240L. Fig.51As shown in FIG. 1 , a fourth thickness TH4 of a portion of the second anti-reflective film 225L exposed by the slit mask pattern 310 and the upper hard mask pattern 230 is smaller than a third thickness TH3 of a portion of the second anti-reflective film 225L protected by the slit mask pattern 310 and the upper hard mask pattern 230 .

[0178] Reference Fig.52 and Fig.53 In one embodiment, the first mask patterns 220 and 225 are formed by patterning the second mask films 220L and 225L. The first mask patterns 220 and 225 are formed in the same manner as described above with reference to FIG. Figures 44 to 47 The method described is performed in the same manner, and therefore, a detailed description thereof will be omitted.

[0179] The first mask patterns 220 and 225 include third side surfaces 220S3 and fourth side surfaces 220S4 that alternately protrude in the first direction X. For example, due to the environmental difference between the region of the second mask films 220L and 225L where the third side surfaces 220S3 are formed and the region of the second mask films 220L and 225L where the fourth side surfaces 220S4 are formed, the third side surfaces 220S3 of the first mask patterns 220 and 225 protrude toward the second peripheral region PR2 beyond the fourth side surfaces 220S4 of the first mask patterns 220 and 225 by a distance D3. For example, the third side surfaces 220S3 are patterned from the second hard mask film 220L on the second anti-reflective film 225L having a relatively large thickness (such as, Fig.51 The fourth side surface 220S4 is patterned from the second hard mask film 220L on the second anti-reflective film 225L having a relatively small thickness (such as, Fig.51 For example, due to the thinness of the second anti-reflection film 225L, the fourth side surface 220S4 is etched more by a distance D3 than the third side surface 220S3 in the first direction X.

[0180] After that, execute the above reference Fig.48 , Fig.49 as well as Figures 21 to 32 In this way, we can obtain Figure 6 The conductive pattern 130 is formed.

[0181] Although the embodiments of the present invention have been specifically shown and described with reference to the accompanying drawings of the present invention, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the embodiments of the present invention as defined by the appended claims. It is therefore desired that the described embodiments be considered in all respects as illustrative and not restrictive, with reference to the appended claims rather than the foregoing description to indicate the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a substrate including a first region and a second region; sequentially forming a target film, a first mask film, a second mask film, and an upper mask pattern on a substrate; forming a first spacer pattern extending along a side surface of the upper mask pattern, wherein the first spacer pattern includes a first line portion, a second line portion, and a folded portion, the first line portion and the second line portion extending in parallel across the first region and the second region, the folded portion bending from the first line portion and the second line portion on the second region and connecting the first line portion and the second line portion; forming a slit mask pattern, the slit mask pattern covering the first spacer pattern on the second region; forming a first mask pattern by patterning a second mask film using the slit mask pattern and the first spacer pattern as an etching mask; forming a second spacer pattern extending along inner and outer side surfaces of the first mask pattern; forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask; and A plurality of target patterns are formed by patterning the target film using the second mask pattern as an etching mask.

2. The method according to claim 1, wherein: The target film includes a conductive film.

3. The method according to claim 1, wherein: Each of the plurality of target patterns includes a first line pattern, a second line pattern extending in parallel across the first region and the second region, and a folding pattern bent from and connecting the first line pattern and the second line pattern.

4. The method according to claim 3, wherein: The width of the folding pattern is greater than the width of the first line pattern and the width of the second line pattern.

5. The method according to claim 3, wherein: A pitch between the first line pattern and the second line pattern is 4 nm to 10 nm.

6. The method according to claim 1, further comprising: The upper mask pattern is removed before forming the slit mask pattern.

7. The method according to claim 1, wherein: Forming the slit mask pattern is before forming the first spacer pattern, and wherein the method further comprises: The upper mask pattern is removed after the slit mask pattern is formed.

8. The method according to claim 1, wherein: The slit mask pattern includes photoresist.

9. The method according to any one of claims 1 to 8, wherein: the second spacer pattern includes an inner spacer pattern extending along an inner side surface of the first mask pattern and an outer spacer pattern extending along an outer side surface of the first mask pattern, The inner spacer pattern includes a first inner line portion, a second inner line portion, a first inner folded portion, and a second inner folded portion, the first inner line portion and the second inner line portion extending in parallel, the first inner folded portion connecting a first end of the first inner line portion and a first end of the second inner line portion, the second inner folded portion connecting a second end of the first inner line portion and a second end of the second inner line portion, and The outer spacer pattern extends along an outer circumference of the first inner line portion, an outer circumference of the second inner line portion, and an outer circumference of the second inner folding portion, and does not extend along an outer circumference of the first inner folding portion.

10. The method according to any one of claims 1 to 8, further comprising: forming a plurality of active regions in a substrate, wherein the plurality of active regions correspond to the plurality of target patterns; forming a plurality of direct contacts, each of the plurality of direct contacts connecting a corresponding target pattern of the plurality of target patterns with a first portion of a corresponding active region of the plurality of active regions; forming a plurality of capacitor structures on the substrate, wherein each of the plurality of capacitor structures is connected to a second portion of a corresponding active region of the plurality of active regions; and A plurality of gate electrodes are formed on the substrate, wherein each of the plurality of gate electrodes passes between a first portion and a second portion of a corresponding active region among the plurality of active regions.

11. A method for manufacturing a semiconductor device, comprising: Setting the base; sequentially forming a target film, a first mask film, a second mask film, and an upper mask pattern on a substrate; forming a first spacer pattern extending along a side surface of the upper mask pattern; forming a first mask pattern by patterning a second mask film using the first spacer pattern as an etching mask; forming a second spacer pattern including an inner spacer pattern extending along an inner side surface of the first mask pattern and an outer spacer pattern extending along an outer side surface of the first mask pattern; forming a second mask pattern by patterning the first mask film using the second spacer pattern as an etching mask; as well as forming a plurality of line patterns by patterning the target film using the second mask pattern as an etching mask, wherein the inner spacer pattern comprises a first inner line portion, a second inner line portion, a first inner folded portion, and a second inner folded portion, the first inner line portion and the second inner line portion extend in parallel, the first inner folded portion connects a first end of the first inner line portion and a first end of the second inner line portion, the second folded portion connects a second end of the first inner line portion and a second end of the second inner line portion, and The outer spacer pattern extends along an outer circumference of the first inner line portion, an outer circumference of the second inner line portion, and an outer circumference of the second inner folding portion, and does not extend along an outer circumference of the first inner folding portion.

12. The method according to claim 11, wherein: The target film includes a conductive film.

13. The method according to claim 11, wherein: The target film overlaps the first inner folded portion and does not overlap the second inner folded portion.

14. The method according to claim 11, wherein: The step of patterning the target film using the second mask pattern as an etching mask includes forming a plurality of folding patterns connecting corresponding pairs of adjacent line patterns among the plurality of line patterns.

15. The method according to any one of claims 11 to 14, wherein: The first inner folded portion protrudes beyond the outer spacer pattern.

16. A semiconductor device comprising: substrate; a first conductive pattern disposed on the substrate, wherein the first conductive pattern comprises a first line pattern, a second line pattern and a first folding pattern, the first line pattern and the second line pattern extending in parallel in a first direction, and the first folding pattern connecting a first end of the first line pattern and a first end of the second line pattern; and a second conductive pattern disposed on the substrate, wherein the second conductive pattern includes a third line pattern, a fourth line pattern, and a second folding pattern, the third line pattern and the fourth line pattern extend in parallel in a first direction, and the second folding pattern connects a first end of the third line pattern and a first end of the fourth line pattern, wherein the second folding pattern protrudes beyond the first folding pattern in the first direction, and The first conductive patterns and the second conductive patterns are alternately and repeatedly arranged in a second direction intersecting the first direction.

17. The semiconductor device according to claim 16, wherein: The width of the first folding pattern is greater than the width of the first line pattern and the width of the second line pattern.

18. The semiconductor device according to claim 16, wherein: The second end of the first line pattern, the second end of the second line pattern, the second end of the third line pattern, and the second end of the fourth line pattern are arranged in a row along the second direction.

19. The semiconductor device according to any one of claims 16 to 18, further comprising: a plurality of active regions in the substrate, wherein the plurality of active regions correspond to the first line pattern to the fourth line pattern; a plurality of direct contacts, each of the plurality of direct contacts connecting a corresponding line pattern of the first to fourth line patterns with a first portion of a corresponding active region of the plurality of active regions; a plurality of capacitor structures disposed on the substrate, wherein each of the plurality of capacitor structures is connected to a second portion of a corresponding active region of the plurality of active regions; and A plurality of gate electrodes are disposed on the substrate, wherein each of the plurality of gate electrodes extends in the second direction and passes between a first portion and a second portion of a corresponding active region among the plurality of active regions.

20. The semiconductor device according to claim 19, further comprising: A contact plug is connected to the first line pattern and the third line pattern.

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