Storage structures and their formation methods, memory circuits and their operating methods

Abstract

A memory structure and its formation method, a memory circuit and its operation method, wherein the structure includes: a memory cell structure including a first select gate, a second select gate, an erase gate located between the first select gate and the second select gate, a first floating gate located between the erase gate and the first select gate, a second floating gate located between the erase gate and the second select gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate; a first channel region is formed in the substrate at the bottom of the first select gate, and a second channel region is formed in the substrate at the bottom of the second select gate; the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region; a source doped region is formed in the substrate at the bottom of the erase gate; drain doped regions are formed in the substrates on both sides of the memory cell structure; and a word line electrical connection structure is provided to electrically connect the first select gate and the second select gate of adjacent memory cell structures, thereby improving storage density while shortening write time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory structure and its formation method, a memory circuit and its operation method. Background Technology

[0002] Flash memory is a type of non-volatile memory that can retain data for a long time without a current supply, meaning that data is not lost when power is off. Floating-gate flash memory is widely used in various embedded electronic products such as financial IC cards and automotive electronics because it saves chip area and increases storage integration density.

[0003] Existing floating-gate flash memory structures typically include an erase gate, a control gate, and a floating gate. The control gate is located above the floating gate and is isolated by a dielectric layer. The erase gate is located between two pairs of control gates and the floating gate, serving as a common erase gate. The two word lines are located on either side of the two pairs of control gates and the floating gate, respectively, and are also isolated by dielectric layers. The oxide layer between the erase gate and the floating gate is a tunneling dielectric layer.

[0004] Typically, a single storage cell can only store one bit, that is, a binary number "0" or "1". For 8-bit flash memory, one byte of data requires three storage cells to store 0-7. Therefore, the storage density of existing flash memory structures is relatively low. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a memory structure and its formation method, a memory circuit and its operation method, so as to improve the performance of the formed memory structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a memory structure, comprising: a substrate; a plurality of memory cell structures located on the substrate, the memory cell structure including a first select gate, a second select gate, an erase gate located between the first select gate and the second select gate, a first floating gate located between the erase gate and the first select gate, a second floating gate located between the erase gate and the second select gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, wherein a first channel region is provided in the substrate at the bottom of the first select gate, and a second channel region is provided in the substrate at the bottom of the second select gate, the turn-on voltage of the first channel region being different from the turn-on voltage of the second channel region; a source doped region located in the substrate at the bottom of the erase gate; drain doped regions located in the substrate on both sides of the memory cell structure; and a word line electrical connection structure for electrically connecting the first select gate and the second select gate of adjacent memory cell structures.

[0007] Optionally, the substrate has a well region, and both the source doped region and the drain doped region are located within the well region; the dopant ion concentrations in the well regions under the first and second selected gates are different; the dopant ions include conductive ions, and the conductive ions include one or both of N-type and P-type conductive ions.

[0008] Optionally, it further includes: a first tunnel oxide layer located between the first select gate and the substrate; a second tunnel oxide layer located between the second select gate and the substrate; wherein the thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different or both.

[0009] Optionally, the widths of the first selection gate and the second selection gate are different.

[0010] Optionally, a plurality of the memory cell structures are arranged in an array along a first direction; the memory structure further includes: a plurality of word lines arranged along the first direction, one of the word lines being electrically connected to a word line electrical connection structure located in the same column of the memory structure; a plurality of source lines arranged along the first direction, one of the source lines being electrically connected to a source doped region located in the same column of the memory structure; and a plurality of bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to a drain doped region located in the same row of the memory structure.

[0011] Accordingly, the technical solution of the present invention also provides a method for forming a memory structure, comprising: providing a substrate; forming a plurality of memory cell structures on the substrate, the memory cell structure including a first select gate, a second select gate, an erase gate located between the first select gate and the second select gate, a first floating gate located between the erase gate and the first select gate, a second floating gate located between the erase gate and the second select gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, wherein a first channel region is provided in the substrate at the bottom of the first select gate, and a second channel region is provided in the substrate at the bottom of the second select gate, the turn-on voltage of the first channel region being different from the turn-on voltage of the second channel region; forming a source doped region in the substrate at the bottom of the erase gate; forming drain doped regions in the substrates on both sides of the memory cell structure respectively; and forming a word line electrical connection structure on the substrate, the word line electrical connection structure electrically connecting the first select gate and the second select gate of adjacent memory cell structures respectively.

[0012] Optionally, the substrate has a well region, and both the source doped region and the drain doped region are located within the well region; the dopant ion concentrations in the well regions under the first and second selected gates are different; the method for forming the well region includes: forming an initial well region in the substrate; implanting dopant ions into a portion of the initial well region to form well regions with different dopant concentration distributions, wherein the dopant ions include conductive ions, and the conductive ions include one or both of N-type and P-type conductive ions.

[0013] Optionally, it further includes: forming a first tunnel oxide layer between the substrate and the first select gate; forming a second tunnel oxide layer between the second select gate and the substrate; wherein the thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different, or both are different.

[0014] Optionally, the widths of the first selection gate and the second selection gate are different.

[0015] Optionally, a plurality of the memory cell structures are arranged in an array along a first direction; after forming the word line electrical connection structure, the method further includes: forming a plurality of word lines arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure located in the same column of the memory structure; forming a plurality of source lines arranged along the first direction, one of the source lines being electrically connected to the source doped region located in the same column of the memory structure; and forming a plurality of bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doped region located in the same row of the memory structure.

[0016] Accordingly, the technical solution of the present invention also provides a memory circuit, comprising: a plurality of memory cells arranged in an array, each memory cell including a first multi-gate transistor, a second multi-gate transistor, an erase gate, a source, a first drain, and a second drain; the first multi-gate transistor including a first floating gate, a first control gate coupled to the first floating gate, and a first select gate for controlling the first multi-gate transistor to turn on; the second multi-gate transistor including a second floating gate, a second control gate coupled to the second floating gate, and a second select gate for controlling the second multi-gate transistor to turn on; and the threshold voltage of the second multi-gate transistor being greater than the threshold voltage of the first multi-gate transistor; the erase gate being coupled to the first floating gate and the second floating gate; the source being a common end of the first multi-gate transistor and the second multi-gate transistor; the first drain being the other end of the first multi-gate transistor; and the second drain being the other end of the second multi-gate transistor; a plurality of word line nodes, each word line node being electrically connected to the first select gate and the second select gate of an adjacent memory cell in the same row; word lines being electrically connected to word line nodes in the same column; bit lines being electrically connected to the first drain and the second drain of memory cells in the same row; and source lines being electrically connected to the source of memory cells in the same column.

[0017] Optionally, it also includes: a write unit for applying a write voltage to a word line node to write logic 1 to one or both of the first floating gate and the second floating gate corresponding to the word line node.

[0018] Optionally, it also includes: a signal reading unit connected to the bit line, used to read the storage state in the first floating gate and the second floating gate.

[0019] Accordingly, the technical solution of the present invention also provides a method for forming the operation of the memory circuit described above, comprising: performing a write operation on two adjacent memory cells to be operated on, applying a write voltage to the word line node between the two adjacent memory cells; when the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the threshold voltage of the second multi-gate transistor, and the channel is opened through the first control gate and closed through the second control gate, writing logic 1 on the first floating gate; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened through the first control gate, writing logic 1 on the first floating gate; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened through the second control gate, writing logic 1 on the second floating gate.

[0020] Optionally, after performing a write operation on two adjacent memory cells to be operated on, a read operation is performed on the two adjacent memory cells; the read operation includes: applying an enable voltage to the word line node between the two adjacent memory cells, the enable voltage being greater than the threshold voltage of the second multi-gate transistor, and applying a first read voltage to the first control gate and the second control gate respectively, grounding the source line, applying a second read voltage to the bit line, obtaining the read current of the bit line corresponding to the two adjacent memory cells, and obtaining the storage state of the two adjacent memory cells according to the magnitude of the read current.

[0021] Optionally, the method includes: acquiring several reference current values ​​before the read operation; the method for acquiring the storage state of the two adjacent memory cells includes: comparing the read current with each reference current value, acquiring the grading result of the read current, and acquiring the overall storage state of the first floating gate and the second floating gate in the two adjacent memory cells based on the grading result.

[0022] Optionally, it further includes: providing a reference voltage, the reference voltage being greater than the threshold voltage of the second multi-gate transistor; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a first write operation, the first write operation including: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate; after the first write operation, performing the read operation to obtain a first read current; when the write voltage is greater than the reference voltage, performing a second write operation, the second write operation including: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate; after the second write operation, performing the read operation to obtain a second ... first write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a first write operation to obtain a second read current; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a second write operation to obtain a second read current; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a second write operation to obtain a second write current; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a second write operation to obtain a second write current; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a second write operation to obtain a second write current; when the If the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a third write operation is performed. The third write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charge in the second floating gate, and not storing charge in the first floating gate. After the third write operation, the read operation is performed to obtain a third read current. If the write voltage is greater than the reference voltage, a fourth write operation is performed. The fourth write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charge in the second floating gate, and not storing charge in the second floating gate. After the fourth write operation, the read operation is performed to obtain a fourth read current. The classification results of the first read current, the second read current, the third read current, and the fourth read current are different.

[0023] Optionally, it further includes: when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a fifth write operation, the fifth write operation including: opening a channel through the first control gate and opening a channel through the second control gate, storing charges in the first floating gate and the second floating gate respectively; after the fifth write operation, performing the read operation to obtain a fifth read current; when the write voltage is greater than the reference voltage, performing a sixth write operation, the sixth write operation including: opening a channel through the first control gate and opening a channel through the second control gate, storing charges in the first floating gate and the second floating gate respectively; after the sixth write operation, performing the read operation to obtain a sixth read current; when the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the second multi-gate transistor... A seventh write operation is performed on the threshold voltage of the transistor. The seventh write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate. After the seventh write operation, the read operation is performed to obtain the seventh read current. When the write voltage is less than the threshold voltage of the first multi-gate transistor, an eighth write operation is performed. The eighth write operation includes: not storing charge in either the first or second floating gate. After the eighth write operation, the read operation is performed to obtain the eighth read current. The classification results of the first read current, the second read current, the third read current, the fourth read current, the fifth read current, the sixth read current, the seventh read current, and the eighth read current are all different.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0025] In a storage structure provided by this invention, the first select gate and the second select gate of adjacent storage cell structures are electrically connected via word line electrical connections. Since the first channel region and the second channel region have different turn-on voltages, by controlling the magnitude of the voltage applied to the word line electrical connection structure, different conduction states of the first channel region and the second channel region can be simultaneously controlled. Furthermore, the first channel region also needs to be controlled to turn on via the first control gate, and the second channel region also needs to be controlled to turn on via the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region, realizing the writing of logic 1 to the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region, realizing the writing of logic 1 to the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate, and the second control gate, different combinations of write states of the first and second floating gates can be achieved. The write states can include eight states; therefore, two adjacent storage cells can store one byte of data. In addition, the first and second selection gates of the adjacent memory cell structure are electrically connected, allowing two adjacent memory cells to be written simultaneously. Therefore, while increasing storage density, the write time is shortened. The first select gate and the second select gate of the adjacent memory cell structure are electrically connected via word line electrical connections. Since the first channel region and the second channel region have different turn-on voltages, by controlling the magnitude of the voltage applied to the word line electrical connection structure, different conduction states of the first channel region and the second channel region can be controlled simultaneously. In addition, the first channel region also needs to be controlled to turn on via the first control gate, and the second channel region also needs to be controlled to turn on via the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region to realize the writing of logic 1 to the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region to realize the writing of logic 1 to the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate, and the second control gate, different combinations of write states of the first floating gate and the second floating gate can be realized. The write states can include eight states. Therefore, two adjacent memory cells can store one byte of data. In addition, the first and second selection gates of the adjacent memory cell structure are electrically connected, allowing two adjacent memory cells to be written simultaneously. Therefore, while increasing storage density, the write time is shortened.

[0026] In a method for forming a memory structure provided by the present invention, the first selection gate and the second selection gate of adjacent memory cell structures are electrically connected through word line electrical connections. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical connection structure, different conduction states of the first channel region and the second channel region can be controlled simultaneously. In addition, the first channel region also needs to be controlled to turn on through the first control gate, and the second channel region also needs to be controlled to turn on through the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region to realize the writing of logic 1 to the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region to realize the writing of logic 1 to the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate, and the second control gate, different combinations of write states of the first floating gate and the second floating gate can be realized. The write states can include eight states. Therefore, two adjacent memory cells can store one byte of data. In addition, the first and second selection gates of the adjacent memory cell structure are electrically connected, allowing two adjacent memory cells to be written simultaneously. Therefore, while increasing storage density, the write time is shortened.

[0027] In a memory circuit provided by this invention, the first multi-gate transistor includes a first floating gate, a first control gate coupled to the first floating gate, and a first select gate for controlling the first multi-gate transistor to turn on. The second multi-gate transistor includes a second floating gate, a second control gate coupled to the second floating gate, and a second select gate for controlling the second multi-gate transistor to turn on. The threshold voltage of the second multi-gate transistor is greater than the threshold voltage of the first multi-gate transistor. Several word line nodes are included, each electrically connected to the first select gate and the second select gate of an adjacent memory cell in the same row. When performing a write operation on two adjacent memory cells, the write voltage applied to the word line nodes between the two adjacent memory cells is controlled, and the on / off state of the first control gate and the second control gate relative to the channel is controlled, to achieve different combinations of write states for the first floating gate and the second floating gate. The write states can include eight states. Furthermore, since the bit line is electrically connected to the first drain and the second drain of the memory cell in the same row, during a read operation, the read current is obtained from the bit line, which can acquire the total storage information of the first floating gate and the second floating gate of the two adjacent memory cells. Therefore, two adjacent memory cells can store one byte of data. Furthermore, since two adjacent storage cells are written simultaneously, the write time is shortened while increasing storage density. Attached Figure Description

[0028] Figure 1This is a schematic diagram of the storage structure in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the memory circuit in an embodiment of the present invention. Detailed Implementation

[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0031] As described in the background section, existing flash memory architectures have low storage density, and their performance urgently needs to be improved.

[0032] To address the aforementioned problems, this invention provides a storage structure and its formation method, as well as a memory circuit and its operating method. When performing a write operation on two adjacent memory cells, the write voltage applied to the word line node between the two adjacent memory cells is controlled, along with the on / off state of the first and second control gates relative to the channel. This allows for different combinations of write states for the first and second floating gates, including eight possible states. Furthermore, since the bit line is electrically connected to the first and second drains of the adjacent memory cells, a read current is obtained from the bit line during a read operation, enabling the acquisition of the total stored information from the first and second floating gates of the two adjacent memory cells. Therefore, two adjacent memory cells can store one byte of data. Moreover, because the two adjacent memory cells are written to simultaneously, the write time is shortened while increasing storage density.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figure 1 This is a schematic diagram of the storage structure in an embodiment of the present invention.

[0035] Please refer to Figure 1The storage structure includes: a substrate 100; and a plurality of storage cell structures located on the substrate 100, the storage cell structures including a first select gate 101, a second select gate 102, an erase gate 103 located between the first select gate 101 and the second select gate 102, a first floating gate 104 located between the erase gate 103 and the first select gate 101, a second floating gate 105 located between the erase gate 103 and the second select gate 102, a first control gate 106 located on the first floating gate 104, and a second control gate 107 located on the second floating gate 105. The substrate 100 at the bottom of the first selection gate 101 has a first channel region (not shown in the figure), and the substrate 100 at the bottom of the second selection gate 102 has a second channel region (not shown in the figure). The turn-on voltage of the first channel region is different from that of the second channel region. A source doped region 108 is located in the substrate 100 at the bottom of the erase gate 103. Drain doped regions 109 are located in the substrates 100 on both sides of the memory cell structure. A word line electrical connection structure 110 electrically connects the first selection gate 101 and the second selection gate 102 of adjacent memory cell structures.

[0036] In the above storage structure, the first selection gate 101 and the second selection gate 102 of adjacent storage cell structures are electrically connected through the word line connection structure 110. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line connection structure 110, different conduction states of the first channel region and the second channel region can be simultaneously controlled. Furthermore, the first channel region also needs to be controlled to turn on through the first control gate 106, and the second channel region also needs to be controlled to turn on through the second control gate 107. When the first channel region is turned on, electrons are drawn from the first... When the second channel region enters the first floating gate 104, logic 1 is written into the first floating gate 104. When the second channel region is opened, electrons enter the second floating gate 105 from the second channel region, realizing the writing of logic 1 into the second floating gate 105. Therefore, by applying different voltages to the word line electrical connection structure 110, the first control gate 106, and the second control gate 107, different combinations of write states for the first floating gate 104 and the second floating gate 105 can be achieved. The write states can include eight states, thus two adjacent memory cells can store one byte of data. In addition, the first selection gate 101 and the second selection gate 102 of the adjacent memory cell structure are electrically connected, allowing two adjacent memory cells to be written simultaneously. Therefore, while increasing storage density, the write time is shortened.

[0037] In this embodiment, the substrate 100 has a well region (not shown in the figure), and the source doped region 108 and the drain doped region 109 are both located in the well region.

[0038] In this embodiment, the dopant ion concentrations in the well regions under the first selection gate 101 and the second selection gate 102 are different; the dopant ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

[0039] In this embodiment, the storage structure further includes: a first tunnel oxide layer 111 located between the first select gate 101 and the substrate 100; and a second tunnel oxide layer 112 located between the second select gate 102 and the substrate 100.

[0040] In this embodiment, the turn-on voltage of the first channel region differs from that of the second channel region by using well regions with different doped ion concentrations under the first selection gate 101 and the second selection gate 102. In another embodiment, one or both of the thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different; that is, first tunnel oxide layers and second tunnel oxide layers with different properties are selected to make the turn-on voltage of the first channel region different from that of the second channel region. In other embodiments, first selection gates and second selection gates with different widths can also be selected to make the turn-on voltage of the first channel region different from that of the second channel region.

[0041] In this embodiment, several of the storage cell structures are arranged in an array along a first direction (not shown in the figure).

[0042] In this embodiment, the memory structure further includes: a plurality of word lines (not shown in the figure) arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure 110 located in the same column of the memory structure; a plurality of source lines (not shown in the figure) arranged along the first direction, one of the source lines being electrically connected to the source doped region 108 located in the same column of the memory structure; and a plurality of bit lines (not shown in the figure) arranged along a second direction (not shown in the figure), the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doped region 109 located in the same row of the memory structure.

[0043] Accordingly, embodiments of the present invention also provide a method for forming the above-described storage structure; please refer to further details. Figure 1The method for forming the memory structure includes: providing a substrate 100; forming a plurality of memory cell structures on the substrate 100, the memory cell structures including a first selection gate 101, a second selection gate 102, an erase gate 103 located between the first selection gate 101 and the second selection gate 102, a first floating gate 104 located between the erase gate 103 and the first selection gate 101, a second floating gate 105 located between the erase gate 103 and the second selection gate 102, a first control gate 106 located on the first floating gate 104, and a second control gate 107 located on the second floating gate 105. The substrate 100 at the bottom of gate 101 has a first channel region (not shown in the figure), and the substrate 100 at the bottom of the second select gate 102 has a second channel region (not shown in the figure). The turn-on voltage of the first channel region is different from that of the second channel region. A source doped region 108 is formed in the substrate 100 at the bottom of the erase gate 103. Drain doped regions 109 are formed in the substrates 100 on both sides of the memory cell structure. A word line electrical connection structure 110 is formed on the substrate 100, and the word line electrical connection structure 110 electrically connects the first select gate 101 and the second select gate 102 of adjacent memory cell structures.

[0044] In the memory structure formed by the above method, the first selection gate 101 and the second selection gate 102 of adjacent memory cell structures are electrically connected through the word line connection structure 110. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line connection structure 110, the first channel region and the second channel region can be simultaneously controlled to achieve different conduction states. In addition, the first channel region also needs to be controlled to turn on through the first control gate 106, and the second channel region also needs to be controlled to turn on through the second control gate 107. When the first channel region is turned on, electrons are automatically... When the first channel region enters the first floating gate 104, logic 1 is written to the first floating gate 104. When the second channel region is opened, electrons enter the second floating gate 105 from the second channel region, realizing the writing of logic 1 to the second floating gate 105. Therefore, by applying different voltages to the word line electrical connection structure 110, the first control gate 106, and the second control gate 107, different combinations of write states for the first floating gate 104 and the second floating gate 105 can be achieved. The write states can include eight states, thus two adjacent memory cells can store one byte of data. In addition, the first selection gate 101 and the second selection gate 102 of the adjacent memory cell structure are electrically connected, allowing two adjacent memory cells to be written simultaneously. Therefore, while increasing storage density, the write time is shortened.

[0045] In this embodiment, the substrate 100 has a well region (not shown in the figure), and the source doped region 108 and the drain doped region 109 are both located in the well region.

[0046] In this embodiment, the dopant ion concentrations in the well regions under the first selection gate 101 and the second selection gate 102 are different.

[0047] In this embodiment, the method for forming the well region includes: forming an initial well region (not shown in the figure) within the substrate 100; implanting dopant ions into a portion of the initial well region to form a well region with different doping concentration distributions, wherein the dopant ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

[0048] In this embodiment, a first tunnel oxide layer 111 is formed between the substrate 100 and the first selection gate 101; and a second tunnel oxide layer 112 is formed between the second selection gate 102 and the substrate 100.

[0049] In this embodiment, the turn-on voltage of the first channel region differs from that of the second channel region by using well regions with different doped ion concentrations under the first selection gate 101 and the second selection gate 102. In another embodiment, one or both of the thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different; that is, first tunnel oxide layers and second tunnel oxide layers with different properties are selected to make the turn-on voltage of the first channel region different from that of the second channel region. In other embodiments, first selection gates and second selection gates with different widths can also be selected to make the turn-on voltage of the first channel region different from that of the second channel region.

[0050] In this embodiment, several of the storage cell structures are arranged in an array along a first direction (not shown in the figure).

[0051] In this embodiment, after forming the word line electrical connection structure 110, the method further includes: forming a plurality of word lines (not shown in the figure) arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure 110 located in the same column of the memory structure; forming a plurality of source lines (not shown in the figure) arranged along the first direction, one of the source lines being electrically connected to the source doped region 108 located in the same column of the memory structure; and forming a plurality of bit lines (not shown in the figure) arranged along a second direction (not shown in the figure), the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doped region 109 located in the same row of the memory structure.

[0052] Accordingly, embodiments of the present invention also provide a memory circuit, please refer to... Figure 2The memory circuit includes: a plurality of memory cells arranged in an array, each memory cell (as shown by the dashed line) including a first multi-gate transistor T1, a second multi-gate transistor T2, an erase gate EG, a source S, a first drain D1, and a second drain D2. The first multi-gate transistor T1 includes a first floating gate FG1, a first control gate CG1 coupled to the first floating gate FG1, and a first selection gate PG1 for controlling the first multi-gate transistor T1 to turn on. The second multi-gate transistor T2 includes a second floating gate FG2, a second control gate CG2 coupled to the second floating gate FG2, and a second selection gate PG2 for controlling the second multi-gate transistor T2 to turn on, and the threshold voltage of the second multi-gate transistor T2 is greater than 1. The threshold voltage of the first multi-gate transistor T1, the erase gate EG is coupled to the first floating gate FG1 and the second floating gate FG2, the source S is a common terminal of the first multi-gate transistor T1 and the second multi-gate transistor T2, the first drain D1 is the other terminal of the first multi-gate transistor T1, and the second drain D2 is the other terminal of the second multi-gate transistor T2; a plurality of word line nodes N, each word line node N is electrically connected to the first select gate PG1 and the second select gate PG2 of the adjacent memory cell in the same row; word line WL is electrically connected to the word line node N in the same column; bit line BL is electrically connected to the first drain D1 and the second drain D2 of the memory cell in the same row; source line SL is electrically connected to the source S of the memory cell in the same column.

[0053] In the aforementioned storage circuit, each word line node N is electrically connected to the first select gate PG1 and the second select gate PG2 of adjacent storage cells in the same row. The word line WL is electrically connected to the word line node N in the same column. By controlling the write voltage applied to the word line node N between the two adjacent storage cells, and controlling the channel-on state of the first control gate CG1 and the second control gate CG2, different combinations of write states for the first floating gate FG1 and the second floating gate FG2 can be achieved. These write states can include eight states. Furthermore, since the bit line BL is electrically connected to the first drain D1 and the second drain D2 of the storage cells in the same row, during a read operation, the read current is obtained from the bit line BL, allowing the acquisition of the total storage information of the first floating gate FG1 and the second floating gate FG2 of the two adjacent storage cells. Therefore, two adjacent storage cells can store one byte of data. Moreover, since two adjacent storage cells are written to simultaneously, the write time is shortened while increasing storage density.

[0054] In this embodiment, the storage circuit further includes a write unit (not shown in the figure), used to apply a write voltage to the word line node N and write logic 1 to one or both of the first floating gate FG1 and the second floating gate FG2 corresponding to the word line node N.

[0055] In this embodiment, the storage circuit further includes a signal reading unit (not shown in the figure), which is connected to the bit line BL and is used to read the storage state in the first floating gate FG1 and the second floating gate FG2.

[0056] Accordingly, this embodiment of the invention also provides a method for operating the above-described memory circuit; please refer to further details. Figure 2 The operation method of the memory circuit includes:

[0057] To perform a write operation on two adjacent memory cells, a write voltage is applied to the word line node N between the two adjacent memory cells.

[0058] When the write voltage is greater than the threshold voltage Vt1 of the first multi-gate transistor T1 and less than the threshold voltage Vt2 of the second multi-gate transistor T2, and the channel is opened through the first control gate CG1 and closed through the second control gate CG2, logic 1 is written to the first floating gate FG1.

[0059] When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2, and the channel is opened through the first control gate CG1, logic 1 is written to the first floating gate FG1.

[0060] When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2, and the channel is opened through the second control gate CG2, logic 1 is written to the second floating gate FG2.

[0061] In the above-described method, when performing a write operation on two adjacent memory cells, the write voltage applied to the word line node N between the two adjacent memory cells is controlled, and the channel-opening state of the first control gate CG1 and the second control gate CG2 is controlled to achieve different combinations of write states for the first floating gate FG1 and the second floating gate FG2. These write states can include eight states. Furthermore, since the bit line BL is electrically connected to the first drain D1 and the second drain D2 of the adjacent memory cells, during a read operation, the read current is obtained from the bit line BL, allowing the acquisition of the total stored information of the first floating gate FG1 and the second floating gate FG2 of the two adjacent memory cells. Therefore, two adjacent memory cells can store one byte of data. Moreover, since the two adjacent memory cells are written to simultaneously, the write time is shortened while increasing storage density.

[0062] In the write operation, the write voltage is applied to the first select gate PG1 and the second select gate PG2 of the two adjacent memory cells, respectively. By controlling the magnitude of the write voltage, and further by controlling the magnitude of the voltage applied to the first control gate CG1 and the second control gate CG2, the opening of the channels of the first multi-gate transistor T1 and the second multi-gate transistor T2 is controlled, respectively. When the channel of the first multi-gate transistor T1 is opened, electrons enter the first floating gate FG1 and write logic 1 to the first floating gate FG1. When the channel of the second multi-gate transistor T2 is opened, electrons enter the second floating gate FG2 and write logic 1 to the second floating gate FG2.

[0063] In this embodiment, after a write operation is performed on two adjacent memory cells to be operated on, a read operation is performed on the two adjacent memory cells.

[0064] In this embodiment, the read operation includes: applying a turn-on voltage to the word line node N between the two adjacent memory cells, the turn-on voltage being greater than the threshold voltage Vt2 of the second multi-gate transistor T2; applying a first read voltage to the first control gate CG1 and the second control gate CG2 respectively; grounding the source line SL; applying a second read voltage to the bit line BL; obtaining the read current of the bit line BL corresponding to the two adjacent memory cells; and obtaining the storage state of the two adjacent memory cells based on the magnitude of the read current. The read current of the bit line BL corresponding to the two adjacent memory cells is related to the total number of electrons stored in the first floating gate FG1 and the second floating gate FG2.

[0065] The reading operation further includes: acquiring several reference current values ​​before the reading operation. These reference current values ​​are used as reference values ​​for categorizing the reading current.

[0066] In this embodiment, the method for obtaining the storage state of the two adjacent storage cells includes: comparing the read current with each reference current value, obtaining the grading result of the read current, and obtaining the overall storage state of the first floating gate FG1 and the second floating gate FG2 in the two adjacent storage cells based on the grading result.

[0067] In this embodiment, during the write operation, different write voltages are applied to the word line node N between the two adjacent memory cells to store different numbers of electrons in the first floating gate FG1 (the second floating gate FG2) to represent different storage states.

[0068] Table 1 shows the various states during the read and write operations of the memory circuit, which will be described in detail below.

[0069] Write voltage T1 FG1 T2 FG2 Iread State 1 In <Vt1 closure 0 closure 0 "0” State 2 Vt1 <V<Vt2 Open 1 closure 0 "1” State 3 Vt2<V<Vc Open 1 closure 0 "2” State 4 Vt2<V<Vc closure 0 Open 1 "3” State 5 Vt2<V<Vc Open 1 Open 1 "4” State 6 V>Vc closure 0 Open 1 "5” Status 7 V>Vc Open 1 closure 0 "6” State 8 V>Vc Open 1 Open 1 "7”

[0070] Table 1 is a state table of read and write operations of the memory circuit in the embodiments of the present invention.

[0071] In this embodiment, the operation method of the memory circuit further includes: providing a reference voltage Vc, wherein the reference voltage is greater than the threshold voltage of the second multi-gate transistor T2.

[0072] Please continue referring to "State 3" in Table 1. When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and lower than the reference voltage Vc, a first write operation is performed. The first write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2; storing charge in the first floating gate FG1 and not storing charge in the second floating gate FG2; after the first write operation, the read operation is performed to obtain the first read current I1. In this embodiment, the obtained first read current I1 is in the third current range, and the two adjacent memory cells store logic "2".

[0073] Please continue referring to "State 7" in Table 1. When the write voltage is greater than the reference voltage, a second write operation is performed. The second write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2; storing charge in the first floating gate FG1, and not storing charge in the second floating gate FG2; after the second write operation, the read operation is performed to obtain the second read current I2. In this embodiment, the obtained second read current I2 is at the seventh current level, and the two adjacent memory cells store logic "6".

[0074] Please continue referring to "State 4" in Table 1. When the write voltage V is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and lower than the reference voltage Vc, a third write operation is performed. The third write operation includes: opening the channel through the second control gate CG2 and closing the channel through the first control gate CG1; storing charge in the second floating gate FG2; and not storing charge in the first floating gate FG1. After the third write operation, the read operation is performed to obtain the third read current. In this embodiment, the obtained third read current I3 is in the fourth current level, and the two adjacent memory cells store logic "3".

[0075] Please continue referring to "State 6" in Table 1. When the write voltage V is greater than the reference voltage Vc, a fourth write operation is performed. The fourth write operation includes: opening the channel through the second control gate CG2 and closing the channel through the first control gate CG1; storing charge in the second floating gate FG2, but not storing charge in the second floating gate FG2; after the fourth write operation, the read operation is performed to obtain the fourth read current I4. In this embodiment, the obtained fourth read current I4 is at the fifth current level, and the two adjacent memory cells store logic "5".

[0076] The classification results of the first reading current I1, the second reading current I2, the third reading current I3, and the fourth reading current I4 are different.

[0077] Please continue referring to "State 5" in Table 1. When the write voltage V is greater than the threshold voltage of the second multi-gate transistor T2 and lower than the reference voltage Vc, a fifth write operation is performed. The fifth write operation includes: opening the channel through the first control gate CG1 and the second control gate CG2, and storing charge in the first floating gate FG1 and the second floating gate FG2 respectively. After the fifth write operation, the read operation is performed to obtain the fifth read current I5. In this embodiment, the obtained fifth read current I5 is at the fifth current level, and the two adjacent memory cells store logic "4".

[0078] Please continue referring to "State 8" in Figure 1. When the write voltage V is greater than the reference voltage Vc, a sixth write operation is performed. The sixth write operation includes: opening the channel through the first control gate CG1 and the second control gate CG2, and storing charge in the first floating gate FG1 and the second floating gate FG2 respectively; after the sixth write operation, the read operation is performed to obtain the sixth read current I6. In this embodiment, the obtained sixth read current I6 is at the sixth current level, and the two adjacent memory cells store logic "7".

[0079] Please continue referring to "State 2" in Figure 1. When the write voltage is greater than the threshold voltage Vt1 of the first multi-gate transistor T1 and less than the threshold voltage Vt2 of the second multi-gate transistor T2, a seventh write operation is performed. The seventh write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2; storing charge in the first floating gate FG1; and not storing charge in the second floating gate FG2. After the seventh write operation, the read operation is performed to obtain the seventh read current I7. In this embodiment, the obtained seventh read current I7 is at the seventh current level, and the two adjacent memory cells store logic "1".

[0080] Please continue referring to "State 1" in Figure 1. When the write voltage is less than the threshold voltage Vt1 of the first multi-gate transistor T1, an eighth write operation is performed. The eighth write operation includes: no charge is stored in either the first floating gate FG1 or the second floating gate FG2; after the eighth write operation, the read operation is performed to obtain the eighth read current. In this embodiment, the obtained eighth read current I8 is 0, and the two adjacent memory cells store logic "0".

[0081] In this embodiment, the classification results of the first reading current I1, the second reading current I2, the third reading current I3, the fourth reading current I4, the fifth reading current I5, the sixth reading current I6, the seventh reading current I7, and the eighth reading current I8 are all different.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A storage structure, characterized in that, include: Substrate; A plurality of memory cell structures located on the substrate, the memory cell structures including a first select gate, a second select gate, an erase gate located between the first select gate and the second select gate, a first floating gate located between the erase gate and the first select gate, a second floating gate located between the erase gate and the second select gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, wherein a first channel region is provided in the substrate at the bottom of the first select gate, and a second channel region is provided in the substrate at the bottom of the second select gate, wherein the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region; The source doped region located within the substrate at the bottom of the erase gate; Drain doped regions located in the substrate on both sides of the memory cell structure; The word line electrical connection structure electrically connects the first selection gate and the second selection gate of adjacent memory cell structures, respectively.

2. The storage structure as described in claim 1, characterized in that, The substrate has a well region, and both the source doped region and the drain doped region are located within the well region; the dopant ion concentrations in the well regions under the first selected gate and the second selected gate are different; the dopant ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

3. The storage structure as described in claim 1, characterized in that, Also includes: A first tunnel oxide layer is located between the first selection gate and the substrate; A second tunnel oxide layer is located between the second selection gate and the substrate; The thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different, or both are different.

4. The storage structure as described in claim 1, characterized in that, The widths of the first selection gate and the second selection gate are different.

5. The storage structure as described in claim 1, characterized in that, A plurality of the memory cell structures are arranged in an array along a first direction; the memory structure further includes: a plurality of word lines arranged along the first direction, one of the word lines being electrically connected to a word line electrical connection structure located in the same column of the memory structure; a plurality of source lines arranged along the first direction, one of the source lines being electrically connected to a source doped region located in the same column of the memory structure; and a plurality of bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to a drain doped region located in the same row of the memory structure.

6. A method for forming a storage structure, characterized in that, include: Provide substrate; A plurality of memory cell structures are formed on the substrate. The memory cell structure includes a first select gate, a second select gate, an erase gate located between the first select gate and the second select gate, a first floating gate located between the erase gate and the first select gate, a second floating gate located between the erase gate and the second select gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate. A first channel region is formed in the substrate at the bottom of the first select gate, and a second channel region is formed in the substrate at the bottom of the second select gate. The turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region. A source doped region is formed within the substrate at the bottom of the erase gate; Drain doped regions are formed in the substrates on both sides of the memory cell structure; A word line electrical connection structure is formed on the substrate, which electrically connects the first selection gate and the second selection gate of adjacent memory cell structures, respectively.

7. The method for forming the storage structure as described in claim 6, characterized in that, The substrate has a well region, and both the source doped region and the drain doped region are located within the well region; The dopant ion concentrations are different in the well regions under the first and second selective gates; The method for forming the well region includes: forming an initial well region within the substrate; Dopant ions are injected into a portion of the initial well region to form well regions with different doping concentration distributions. The dopant ions include conductive ions, which include one or both of N-type and P-type conductive ions.

8. The method for forming the storage structure as described in claim 6, characterized in that, Also includes: A first tunnel oxide layer is formed between the substrate and the first selection gate; A second tunnel oxide layer is formed between the second selection gate and the substrate; The thickness and dielectric constant of the first tunnel oxide layer and the second tunnel oxide layer are different, or both are different.

9. The method for forming the storage structure as described in claim 6, characterized in that, The widths of the first selection gate and the second selection gate are different.

10. The method for forming the storage structure as described in claim 6, characterized in that, The plurality of memory cell structures are arranged in an array along a first direction; after forming the word line electrical connection structure, the method further includes: forming a plurality of word lines arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure located in the same column of the memory structure; forming a plurality of source lines arranged along the first direction, one of the source lines being electrically connected to the source doped region located in the same column of the memory structure; and forming a plurality of bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doped region located in the same row of the memory structure.

11. A memory circuit, characterized in that, include: A plurality of memory cells are arranged in an array. Each memory cell includes a first multi-gate transistor, a second multi-gate transistor, an erase gate, a source, a first drain, and a second drain. The first multi-gate transistor includes a first floating gate, a first control gate coupled to the first floating gate, and a first select gate for controlling the first multi-gate transistor to turn on. The second multi-gate transistor includes a second floating gate, a second control gate coupled to the second floating gate, and a second select gate for controlling the second multi-gate transistor to turn on. The threshold voltage of the second multi-gate transistor is greater than the threshold voltage of the first multi-gate transistor. The erase gate is coupled to the first floating gate and the second floating gate. The source is a common terminal of the first multi-gate transistor and the second multi-gate transistor. The first drain is the other terminal of the first multi-gate transistor, and the second drain is the other terminal of the second multi-gate transistor. Several word line nodes, each word line node being electrically connected to the first and second select gates of adjacent memory cells in the same row; Word lines are electrically connected to word line nodes in the same column; Bit lines are electrically connected to the first and second drains of the memory cells in the same row; The source line is electrically connected to the source of the memory cell in the same column.

12. The memory circuit as described in claim 11, characterized in that, Also includes: A write unit is used to apply a write voltage to a word line node to write logic 1 to one or both of the first floating gate and the second floating gate corresponding to the word line node.

13. The memory circuit as described in claim 11, characterized in that, Also includes: A signal reading unit, connected to the bit line, is used to read the storage states within the first floating gate and the second floating gate.

14. A method of operating a memory circuit as described in any one of claims 11 to 13, characterized in that, include: To perform a write operation on two adjacent memory cells, a write voltage is applied to the word line node between the two adjacent memory cells. When the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the threshold voltage of the second multi-gate transistor, and the channel is opened through the first control gate and closed through the second control gate, logic 1 is written to the first floating gate; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened through the first control gate, logic 1 is written to the first floating gate; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened through the second control gate, logic 1 is written to the second floating gate.

15. The method of operating the memory circuit as described in claim 14, characterized in that, After performing a write operation on two adjacent memory cells to be operated on, a read operation is performed on the two adjacent memory cells. The read operation includes: applying an enable voltage to the word line node between the two adjacent memory cells, the enable voltage being greater than the threshold voltage of the second multi-gate transistor, and applying a first read voltage to the first control gate and the second control gate respectively, grounding the source line, applying a second read voltage to the bit line, obtaining the read current of the bit line corresponding to the two adjacent memory cells, and obtaining the storage state of the two adjacent memory cells based on the magnitude of the read current.

16. The method of operating the memory circuit as described in claim 15, characterized in that, include: Prior to the read operation, several reference current values ​​are acquired; The method for obtaining the storage state of the two adjacent memory cells includes: comparing the read current with each reference current value, obtaining the grading result of the read current, and obtaining the overall storage state of the first floating gate and the second floating gate in the two adjacent memory cells based on the grading result.

17. The method of operating the memory circuit as described in claim 16, characterized in that, Also includes: A reference voltage is provided, which is greater than the threshold voltage of the second multi-gate transistor; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a first write operation is performed. The first write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate. After the first write operation, the read operation is performed to obtain a first read current. When the write voltage is greater than the reference voltage, a second write operation is performed. The second write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate. After the second write operation, the read operation is performed to obtain a second read current. When the write voltage is greater than the threshold voltage of the second multi-gate transistor... If the voltage is lower than the reference voltage, a third write operation is performed. The third write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charge in the second floating gate, and not storing charge in the first floating gate. After the third write operation, the read operation is performed to obtain a third read current. If the write voltage is greater than the reference voltage, a fourth write operation is performed. The fourth write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charge in the second floating gate, and not storing charge in the second floating gate. After the fourth write operation, the read operation is performed to obtain a fourth read current. The classification results of the first read current, the second read current, the third read current, and the fourth read current are different.

18. The method of operating the memory circuit as described in claim 17, characterized in that, Also includes: When the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a fifth write operation is performed. The fifth write operation includes: opening a channel through the first control gate and opening a channel through the second control gate, and storing charges in the first floating gate and the second floating gate, respectively. After the fifth write operation, the read operation is performed to obtain a fifth read current. When the write voltage is greater than the reference voltage, a sixth write operation is performed. The sixth write operation includes: opening a channel through the first control gate and opening a channel through the second control gate, and storing charges in the first floating gate and the second floating gate, respectively. After the sixth write operation, the read operation is performed to obtain a sixth read current. When the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the threshold voltage of the second multi-gate transistor... A threshold voltage is used to perform a seventh write operation, which includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charge in the first floating gate, and not storing charge in the second floating gate; after the seventh write operation, the read operation is performed to obtain a seventh read current; when the write voltage is less than the threshold voltage of the first multi-gate transistor, an eighth write operation is performed, which includes: not storing charge in either the first or second floating gate; after the eighth write operation, the read operation is performed to obtain an eighth read current; the classification results of the first read current, the second read current, the third read current, the fourth read current, the fifth read current, the sixth read current, the seventh read current, and the eighth read current are all different.

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