Semiconductor device and method of manufacturing the same

Abstract

The invention relates to a bipolar transistor semiconductor device, comprising: a substrate layer; a collector epitaxial layer supported by the substrate layer; a base region supported by a portion of the collector epitaxial layer; and an emitter region supported by a portion of the base region, where the emitter region comprises a polysilicon material.

Description

[0001] This application is a divisional application of a patent application with application number 2019112416152, application date December 6, 2019, and invention name “Semiconductor device and manufacturing method thereof”. Technical Field

[0002] The present disclosure relates to semiconductor devices, methods of manufacturing semiconductor devices, and electronic devices including semiconductor devices. More specifically, the present disclosure relates to bipolar junction transistor (BJT) semiconductor devices, also known as bipolar transistors. Background Art

[0003] Bipolar transistors are commonly used for current amplification in analog and digital circuits. In its simplest form, as shown in FIG. 1 , a discrete NPN bipolar transistor 100 includes an emitter region 101 electrically coupled to an emitter terminal 101a, a collector region 103 electrically coupled to a collector terminal 103a, and a base region 102 electrically coupled to a base terminal 102a. When configured in a common emitter mode, such a bipolar transistor 100 can operate as a current amplifier such that an input base current I B Small changes in the output collector / emitter current I C big changes.

[0004] The current amplification characteristics of a bipolar transistor are controlled by the current gain or amplification factor hFE (also called β). The amplified output collector / emitter current I C The size of the bipolar transistor is usually determined by hFE and the base current I B is defined by the product of .

[0005] Typically, a high current gain hFE characteristic is preferred so that a bipolar transistor driven by only a small base current can go into device saturation at high collector currents. Conventional BJTs typically have hFE values ​​ranging from about 10 to 500.

[0006] The conventional discrete bipolar transistor device structure includes a diffused emitter and base formed within the collector epitaxial layer. The emitter and base contact terminals are located on the device wafer front 104 and the collector terminal is located on the wafer back 105 .

[0007] In order to achieve a bipolar transistor with a high hFE, the device must achieve a high emitter Gummel number. The emitter Gummel number is a parameter used to measure the emitter efficiency of a transistor and is related to the effective doping of the emitter, which is limited by the narrowing of the bandgap and the carrier lifetime. Although technicians will be aware that this parameter can be used to evaluate and assist in the process of bipolar transistor design, a detailed discussion of the application of the Gummel number in transistor design is beyond the scope of this disclosure. In addition, for bipolar transistors, a low base Gummel number is also required. This value is related to the total base doping and is limited by the breakdown voltage BVCBO. BVCBO is the collector-base breakdown voltage when the emitter is floating. The limitation is that the base must contain the total critical doping to contain the depletion region of BVCBO, otherwise punch-through will occur.

[0008] Therefore, in order to achieve a high hFE for a bipolar transistor, the emitter must be highly doped and the base must be low doped and / or as narrow as possible.

[0009] To achieve bipolar transistors with hFE values ​​of 700 or more, conventional processes are limited by the maximum effective emitter dopant achievable and the process scaling (i.e., the variation in properties / characteristics between and within devices) associated with producing a low doping and narrow base. In fact, with a narrow base, the base width can become very difficult to control. Due to the higher doping, the emitter of the transistor diffuses faster than the base. Thus, for a very narrow base, the slightest doping variation will result in a non-uniform distribution of the base region. As the base becomes narrower, the non-uniform distribution of the base will worsen over a given time in the furnace.

[0010] Using known processes, discrete bipolar transistors with hFE of 1000 or more can be manufactured, but at the expense of device performance, such as having to accept large process extensions (i.e., due to having low doping and a narrow base), resulting in considerable yield loss, or having to use a Darlington transistor arrangement, which makes it impossible for the transistor to enter saturation (because it prevents VBC from changing polarity), which limits the maximum current that the transistor can conduct, thereby limiting the rating of the device.

[0011] It is well known that polysilicon emitter based transistors can be used in integrated chip ICs for high frequency applications. Typically, such transistors employed in ICs have their emitter, base, and collector contacts on one side of the wafer (i.e., the front side of the wafer). However, in the field of discrete high current transistors such as bipolar transistors, polysilicon emitter based transistors have not been employed, which have collector contacts on the side of the wafer opposite to the base and emitter contacts (i.e., the back side of the wafer), thereby providing the transistor with high collector current capability for a given die size. C The process requirement is that, for a given die size, the current flows laterally in the collector region of the transistor and then back to the front of the wafer for the contacts. Because the emitter area can be reduced, this causes the current gain curve to drop to a lower collector current, I C , and since the current needs to flow laterally to the collector contact on the front side, the resistance of the collector area is further increased.

[0012]

[0066] With the foregoing in mind, various aspects and embodiments of the present invention have been devised. Summary of the invention

[0013] According to one aspect of the present invention, a bipolar transistor semiconductor device is provided, comprising: a substrate layer; a collector epitaxial layer supported by the substrate layer; a base region supported by a portion of the collector epitaxial layer; and an emitter region supported by a portion of the base region, wherein the emitter region comprises polysilicon material.

[0014] Alternatively, the substrate layer may include silicon (Si) doped with at least one of antimony (Sb), arsenic (As), and phosphorus (P).

[0015] Alternatively, the collector epitaxial layer may include silicon (Si) doped with at least one of arsenic (As) and phosphorus (P).

[0016] Alternatively, the base region may include silicon (Si) doped with boron (B).

[0017] Alternatively, the emitter region may include silicon (Si) or polysilicon doped with arsenic (As).

[0018] Alternatively, the emitter region may include silicon (Si) or polysilicon doped with phosphorus (P).

[0019] Optionally, the device may further include a titanium (Ti) layer and / or an aluminum (Al) layer, the titanium layer and / or the aluminum layer being supported by the collector epitaxial layer, the base region, and the emitter region.

[0020] Optionally, the titanium layer and / or the aluminum layer may also include AlSi and / or AlSiCu.

[0021] Optionally, the device may further include an AlSi layer supported by the collector epitaxial layer, the base region and the emitter region.

[0022] Optionally, the device may further include an AlSiCu layer supported by the collector epitaxial layer, the base region and the emitter region.

[0023] Optionally, the device may include a backside metal stack for assembly.

[0024] According to another aspect of the present invention, a method for manufacturing a bipolar transistor semiconductor device is provided, which includes a substrate layer, a collector epitaxial layer, an emitter region and a base region, the method including: forming a collector epitaxial layer on the surface of the substrate layer; forming a base region on a portion of the collector epitaxial layer; and forming an emitter region on a portion of the base region, and wherein the emitter includes polycrystalline silicon material.

[0025] Optionally, forming the collector epitaxial layer on the surface of the substrate layer may include: depositing a low-doped N epitaxial layer on a high-doped N substrate.

[0026] Optionally, forming the base region on a portion of the collector epitaxial layer may include: forming an opening on a portion of the base region of the collector epitaxial layer; and forming a plasma oxide layer on the opening of the collector epitaxial layer to form the base region.

[0027] Optionally, forming the emitter region in a portion of the base region may include: removing a region in a portion of the base region; depositing a layer of polysilicon material in the region;

[0028] And implanting the region with a high dose of dopants to form the emitter region. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] For a more complete understanding of the present disclosure, reference is now made to the following description taken in conjunction with the accompanying drawings which are provided by way of non-limiting examples only, in which:

[0030] FIG1 shows a discrete bipolar transistor including an emitter region electrically coupled to an emitter terminal, a collector region electrically coupled to a collector terminal, and a base region electrically coupled to a base terminal;

[0031] Figure 2a to Figure 2l Process steps for fabricating an NPN bipolar junction transistor semiconductor device according to one or more embodiments of the present invention are shown. DETAILED DESCRIPTION

[0032] Now refer to Figures 2a to 2l, by way of example only, a step-by-step description of a manufacturing process for a bipolar transistor according to one or more embodiments is provided. In this example, the bipolar device is an NPN device. An equivalent PNP device can be realized by simply exchanging dopants N and P.

[0033] Figure 2a An initial substrate 201 for fabricating a semiconductor device according to an embodiment is shown. At this stage, a collector epitaxial layer 201a is deposited on the top surface of the substrate 201, so that the semiconductor device may include a low-doped N collector epitaxial layer deposited on a high-doped N substrate 201. For a substrate resistivity in the range of about 1 mΩcm to 10 mΩcm, the N doping in the substrate 201 is substantially higher than the N doping in the collector epitaxial layer, for example 10,000 times. In this example, the substrate 201 needs to be highly doped to achieve a low saturation voltage drop V sat . For N-type, the relationship between substrate resistivity and substrate doping is given. A first oxide layer 202 is formed on top of the low-doped N collector epitaxial layer. The first oxide layer 202 can be deposited on the top surface of the low-doped N collector epitaxial layer by any suitable technique or method. For example, the first oxide layer 202 can be thermally grown on the collector epitaxial layer. Other methods of forming the first oxide layer 202, such as chemical oxidation and electrically induced oxidation, can also be used. The first oxide layer 202 can be formed of an electrically insulating material such as silicon oxide. However, the oxide layer formed of silicon oxide is only an example and can be formed of another electrically insulating material.

[0034] Figure 2b It shows that Figure 2a Two channel implants 203a are formed at the periphery or a portion of the first oxide layer 202 of the semiconductor wafer 200 shown. First, two channels 203 are formed at the edge of the first oxide layer 202. The channel 203 can be formed by removing the end of the first oxide layer 202 or opening the end of the first oxide layer 202, for example, using dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE) or any other suitable etching process. A thin scattering oxide layer 203b is grown on the base of each channel 203. Highly doped N implants are performed through the thin scattering oxide layer 203b by an ion or plasma implantation process to form two channel implants 203a. Channel implants can be used to prevent any crosstalk between chips on the wafer and to prevent leakage current from flowing laterally from the collector of the device to the base. The channel implant 203a can be optionally formed at different locations on the first oxide layer 202, depending on the physical layout of the semiconductor wafer 200a.

[0035] In the next stage, refer to Figure 2c, etching away a portion of the first oxide layer 202 by, for example, using dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE) or any other suitable etching process, Figure 2b An opening 204 for base implantation is formed on the semiconductor wafer 200 shown in FIG. Figure 2c As shown, an opening 204 for base implant is formed between channel implants 203a of semiconductor wafer 200. A thin scattering oxide layer 204b is grown on the opening 204 for base implant. Then, a base implant 204a comprising a low doped P implant is formed by ion or plasma implantation through the thin scattering oxide layer 204b. The distance from the base edge to the channel diffusion should be selected so that it is large enough to prevent lateral breakdown between the base and collector of the device.

[0036] Figure 2d It shows that the formation Figure 2c The second oxide layer 205 on the top surface of the semiconductor wafer 200 is shown. At this stage, the second oxide layer 205 is formed on the semiconductor device so that the oxide layer covers the top surface of the semiconductor device and is densified. Plasma enhanced chemical vapor deposition (PECVD) can be used to form the oxide to maintain a low thermal budget, that is, to achieve shallow junctions. The second oxide layer 205 can be a plasma oxide layer. Any known process, such as chemical oxidation and electrically induced oxidation, can be used to grow and densify the plasma oxide layer.

[0037] Figure 2e Shown in Figure 2d Another opening 206 for the emitter region 207 is formed on the surface of the base region 208 of the semiconductor wafer 200. The opening 206 is formed by etching away a portion of the second oxide layer 205 by, for example, dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE) or any other suitable etching process. The purpose of the opening 206 is to accommodate the body of the emitter region 207, which will be described in the following paragraphs. The emitter opening can be a single area as shown by the opening 206, or a single area as a grid of oxide pillars (not shown) within the emitter region, where the base contact can be formed.

[0038] Figure 2f Shows the formation of Figure 2e The polysilicon layer 211 is formed on the top surface of the semiconductor wafer 200. Figure 2f As shown, the polysilicon layer 211 includes two layers, an upper layer 209 and a lower layer 210. In an optional embodiment, the polysilicon layer 211 may include any number of polysilicon layers. In this example, the lower layer 210 of the polysilicon layer 211 is an undoped polysilicon layer. Figure 2e The lower layer 210 is deposited on the top surface of the semiconductor wafer 200. Then, the upper layer 209 of the polysilicon layer 211 is deposited, and a high dose of N dopant is implanted therein to form an N doped layer. Then, the polysilicon layer 211 is driven in so that the N dopant in the upper layer 209 diffuses into the lower layer 210.

[0039] In the next stage, you can Figure 2f The semiconductor wafer 200 in the embodiment of the present invention removes the unnecessary polysilicon formed in the previous stage, that is, the polysilicon portion that is not part of the emitter. At this stage, the polysilicon layer 211 can be structured so that only the polysilicon layer 211 is retained. Figure 2g The polysilicon layer 211 shown is formed at a portion of the emitter region 207 of the semiconductor wafer 200, ie, a polysilicon emitter layer. The polysilicon layer 211 may be formed using any suitable technique or method.

[0040] In the next stage, if Figure 2h As shown, in Figure 2g A third oxide layer 213 is formed on the exposed top surface of the semiconductor wafer 200. The oxide layer is a plasma oxide layer formed by plasma oxidation. Other methods of forming an oxide layer, such as chemical oxidation and electrically induced oxidation, may also be used.

[0041] Figure 2i Shown in Figure 2h An opening 214 for base contact diffusion is formed in the base region 208 of the semiconductor wafer 200 in FIG. For example, the opening 214 is etched into the base region 208 by dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE) or any other suitable etching process. The purpose of the opening 214 is to receive a base contact diffusion implant with a higher doping than the P dopant of the base region.

[0042] In the next stage, refer to Figure 2j , base contact diffusion implant 214a is implanted into opening 214 using ion or plasma implantation. At this stage, as Figure 2i All dopants in the semiconductor wafer 200 are shown diffused into various regions of the semiconductor wafer 200. The polysilicon is protected from P implants by oxide. The diffusion can be performed in a single step or in multiple steps. The diffusion process results in the emitter polysilicon layer 212 being fully doped 215.

[0043] In the next stage, refer to Figure 2k ,exist Figure 2jAn opening 216 is formed on the top surface of the emitter region 207 of the semiconductor wafer 200 shown. The opening 216 is formed by etching (e.g., dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE) or any other suitable etching process). The opening 216 is formed to accommodate a metal alloy to contact the fully doped emitter polysilicon layer 215. The metal alloy includes conductive materials such as titanium (Ti), aluminum (Al) and combinations thereof. Other suitable conductive materials may also be used. At this stage, the base contact opening is made by a short acid dip to remove any unwanted oxide formed on the semiconductor device. The acid includes dilute hydrofluoric acid (HF) or any suitable acid. Since the oxide in the base contact is thinner than the oxide on the polysilicon, only the opening for the emitter contact is formed on the polysilicon. Otherwise, the base contact will be severely over-etched. The short acid dip at this stage ensures that the base contact opening is free of oxide in preparation for the next process step.

[0044] In the final stage, refer to Figure 2l , in such Figure 2k Conductive material 217 is deposited on the top surface of the semiconductor wafer 200 as shown. Figure 2l As shown, the conductive material 217 is deposited and structured by sputtering. The sputtering deposition used can be, for example, ion beam deposition, ion assisted deposition, reactive or gas flow sputtering, high target utilization rate sputtering (HiTUS) or high power pulsed magnetron sputtering (HiPIMS). The conductive material 217 may include titanium Ti and aluminum Al. Other suitable conductive materials may also be used. Then Figure 2k A passivation is deposited on the top surface of the semiconductor wafer 200 in the embodiment and structured. Then, according to an embodiment, a suitable backside metal stack for assembly is applied to the top layer of the semiconductor wafer 200 to form Figure 2l A bipolar transistor semiconductor device 200 is provided.

[0045] According to the present disclosure, a polysilicon emitter is applied to a discrete bipolar transistor device having a collector on the backside of the wafer of the device, i.e., where the collector is located on the same side (backside of the wafer) as the base and emitter of the device. As described above, this can be achieved by implanting a shallow base into the collector epitaxial layer, depositing polysilicon onto the emitter region, implanting the polysilicon region, and diffusing smoothly from the polysilicon into the silicon in the emitter in one step.

[0046] According to the present disclosure, a polysilicon emitter is applied to a bipolar transistor semiconductor device having a collector on the back side of a wafer of the device. The bipolar transistor semiconductor device includes a substrate layer supporting a collector epitaxial layer. The device also includes a base region supported by a portion of the collector epitaxial layer. The base region of the device supports an emitter region composed of polysilicon material. Terminals including Ti and Al extend from each of the collector epitaxial layer, the base region, and the emitter region.

[0047] As a result, the thermal budget of a bipolar transistor with this device structure can be reduced by about one-third or one-half of that of a conventional bipolar transistor with similar ratings, allowing hFE to be greater than or equal to 1000 without being limited by the process range. B When driven, bipolar transistors can also enter a high collector current I C High hFE is achieved by high emitter doping of the emitter (i.e., emitter with high emitter Gemming factor) and a well controlled narrow and low doped base (i.e., base with low base Gemming factor). Since a very low device thermal budget is achieved, the process margin is kept to a minimum even for an extremely narrow base.

[0048] The operation of the proposed semiconductor device is similar to that of a standard BJT. However, as a result of the structural design, the hFE of the semiconductor device is increased (i.e., approximately twice the hFE of an equivalent conventional bipolar transistor), and a base current of approximately half the base current of an equivalent conventional bipolar transistor may be sufficient to bring the semiconductor device into a given collector current I C Since the base current needs to flow through 0.7VV BE , so for power transistors, the power loss of the device can be considerable. For example, consider a 15A rated bipolar transistor, which has a C =15A requires a 1A base current to keep the transistor in saturation mode. This will result in a power loss on the BE diode (base-emitter diode) (I*V=1A*0.7V=700mW). In this example, by providing a bipolar transistor with double hFE, the IV power loss on the BE diode can be halved, i.e., to 0.5A*0.7V=350mW.

[0049] In at least one embodiment, according to the embodiment Figure 2l The bipolar transistor semiconductor device 200 is suitable for high power applications requiring high current amplification and device energy efficiency but with limited packaging space. That is, the BJT device is capable of handling high load currents and is compact in size, i.e., has a small device footprint in a thermally efficient package.

[0050] In the automotive industry, BJTs can be used in various in-vehicle electronic systems, for example, as load switches in airbag deployment, as pre-drivers to drive high current trench MOSFETs commonly used in fuel pumps, for overvoltage protection, low dropout regulation, LED backlight switching, and Royer converters for LCD backlighting in instrument clusters. Figure 2l The bipolar transistor semiconductor device 200 may be suitable for deployment in any of the above applications and is capable of handling high load current applications, but at the same time is energy efficient and compact, thereby occupying a very small packaging space in a vehicle.

[0051] Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0052] The term "comprising" does not exclude other elements or steps and the term "a" or "an" does not exclude a plurality. Reference signs in the claims should not be construed as limiting the scope of the claims.

[0053] In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.

[0054] The scope of the present disclosure includes any novel feature or combination of features disclosed therein, whether explicitly or implicitly, or any generalization thereof, whether or not it relates to the claimed invention or mitigates any or all of the problems solved by the invention. The applicants hereby give notice that new claims may be formulated to such features during the prosecution of the present application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with features of the independent claims, and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations recited in the claims.

Claims

1. A bipolar transistor semiconductor device, comprising: substrate layer; a collector epitaxial layer supported directly on the substrate layer; a base region supported by a portion of the collector epitaxial layer, the base region being formed in the collector epitaxial layer; an emitter region supported by a portion of the base region, wherein the emitter region comprises polysilicon material; and A titanium (Ti) layer and / or an aluminum (Al) layer, wherein the titanium layer and / or the aluminum layer are supported by the collector epitaxial layer, the base region and the emitter region, and wherein the titanium layer and / or the aluminum layer also includes AlSi and / or AlSiCu.

2. The bipolar transistor semiconductor device according to claim 1, wherein: The substrate layer further includes silicon (Si) doped with at least one element selected from the group consisting of antimony (Sb), arsenic (As), and phosphorus (P).

3. The bipolar transistor semiconductor device according to claim 1, wherein: The substrate layer and the collector epitaxial layer further include silicon (Si) doped with at least one element of the group consisting of arsenic (As) and phosphorus (P).

4. The bipolar transistor semiconductor device according to claim 1, wherein: The base region also includes silicon (Si) doped with boron (B).

5. The bipolar transistor semiconductor device according to claim 1, wherein: The emitter region also includes silicon (Si) or polysilicon doped with arsenic (As).

6. The bipolar transistor semiconductor device according to claim 1, wherein: The emitter region also includes silicon (Si) or polysilicon doped with phosphorus (P).

7. The bipolar transistor semiconductor device according to claim 1, further comprising an AlSi layer, wherein: The AlSi layer is supported by the collector epitaxial layer, the base region and the emitter region.

8. The bipolar transistor semiconductor device according to claim 1, further comprising an AlSiCu layer, wherein: The AlSiCu layer is supported by the collector epitaxial layer, the base region and the emitter region.

9. The bipolar transistor semiconductor device of claim 1, further comprising a backside metal stack for assembly.

10. A method for manufacturing a bipolar transistor semiconductor device, the bipolar transistor semiconductor device comprising a doped substrate layer, a collector epitaxial layer, an emitter region and a base region, the method comprising the following steps: forming the collector epitaxial layer directly on the surface of the substrate layer so that the collector epitaxial layer has a higher doping concentration of the same type as the doped substrate layer; forming the base region on a portion of the collector epitaxial layer such that the base region is formed in the collector epitaxial layer; and forming the emitter region on a portion of the base region, the emitter region comprising a polysilicon material; as well as A titanium (Ti) layer and / or an aluminum (Al) layer is formed, wherein the titanium (Ti) layer and / or the aluminum (Al) layer is supported by the collector epitaxial layer, the base region and the emitter region, and wherein the titanium layer and / or the aluminum layer also includes AlSi and / or AlSiCu.

11. The method of claim 10, wherein: The step of forming the collector epitaxial layer on the surface of the substrate layer further comprises: depositing a low-doped N epitaxial layer on the high-doped N substrate.

12. The method of claim 10, wherein: Forming the base region on a portion of the collector epitaxial layer further comprises the following steps: forming an opening on a portion of the collector epitaxial layer for the base region; and A plasma oxide layer is formed on the opening of the collector epitaxial layer to form the base region.

13. The method of claim 10, wherein: Forming the emitter region in a portion of the base region further comprises the following steps: removing a region in a portion of the base region; depositing a layer of polysilicon material in the region; and The region is implanted with a high dose of dopants to form the emitter region.

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