Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a device and equipment. The method comprises the following steps: providing a substrate; performing ion implantation on a lateral diffusion region of the substrate to form a P-type well region and an N-type drift region; etching the P-type well region and a core region of the substrate to form a fin-shaped structure and a planar block structure; the planar block structure is formed based on the unetched N-type drift region in the lateral diffusion region; a first transistor is formed based on the first fin-shaped structure; the substrate is inverted and removed; a second transistor is formed based on the second fin-shaped structure; a first fin-cut processing is performed on the first fin-shaped structure to form a first fin-cut groove, and / or a second fin-cut processing is performed on the second fin-shaped structure to form a second fin-cut groove; the etching depth of the first fin-cut groove is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure; and the etching depth of the second fin-cut groove is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, and in particular to a preparation method of a semiconductor structure, the semiconductor structure, a device and an apparatus. BACKGROUND

[0002] With the performance of fin field-effect transistor (FinFET) approaching the limit, a laterally-diffused metal-oxide semiconductor (LDMOS) process based on a new structure needs to be developed, which helps further miniaturization of transistors. Transistor stacking is considered as a promising miniaturization method. At present, how to realize process compatibility with stacked transistors for FinFET LDMOS as a component of a supporting circuit module is still a problem to be solved. SUMMARY

[0003] The present application provides a preparation method of a semiconductor structure, the semiconductor structure, a device and an apparatus to realize process compatibility between a lateral diffusion device and a stacked transistor.

[0004] In a first aspect, an embodiment of the present application provides a preparation method of a semiconductor structure, the semiconductor structure including a lateral diffusion device and a core device, the core device including a first transistor and a second transistor stacked along a first direction; the lateral diffusion device is arranged side by side with the first transistor or arranged side by side with the second transistor; the method includes: providing a substrate; the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are arranged adjacent to each other in a second direction; the second direction is perpendicular to the first direction; performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region; etching the P-type well region and the core region to form a fin-shaped structure and a planar block-shaped structure; the fin-shaped structure includes a first fin-shaped structure and a second fin-shaped structure stacked along the first direction; the planar block-shaped structure is formed based on the N-type drift region in the lateral diffusion region which is not etched; the planar block-shaped structure includes a first planar block-shaped structure and a second planar block-shaped structure stacked along the first direction; forming the first transistor based on the first fin-shaped structure; reversing and removing the substrate; forming the second transistor based on the second fin-shaped structure; wherein the method further includes: performing a first fin-cut processing on the first fin-shaped structure to form a first fin-cut trench, and / or performing a second fin-cut processing on the second fin-shaped structure to form a second fin-cut trench; the first fin-cut trench is perpendicular to the extension direction of the first fin-shaped structure, and the etching depth of the first fin-cut trench is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure; the second fin-cut trench is perpendicular to the extension direction of the second fin-shaped structure, and the etching depth of the second fin-cut trench is half of the height of the fin-shaped structure or equal to the height of the fin-shaped structure.

[0005] In some possible implementation manners, the etching the P-type well region and the core region to form the fin-shaped structure and the planar block structure comprises: coating photoresist on the N-type drift region to form a photoresist layer; etching the P-type well region and the core region under the mask of the photoresist layer to form the fin-shaped structure located in the P-type well region and the core region, and the planar block structure located in the N-type drift region.

[0006] In some possible implementation manners, before the first transistor is formed based on the first fin-shaped structure, the method further comprises: depositing oxide on the substrate and the fin-shaped structure to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the fin-shaped structure; and a first portion of the first shallow trench isolation structure is removed to expose the first fin-shaped structure.

[0007] In some possible implementation manners, in the case that the first fin-shaped structure is subjected to the first fin-cut processing; the depositing oxide on the substrate and the fin-shaped structure to form the first shallow trench isolation structure comprises: depositing oxide on the substrate and the fin-shaped structure, and depositing oxide in the first fin-cut groove to form the first shallow trench isolation structure; and the first shallow trench isolation structure fills the first fin-cut groove.

[0008] In some possible implementation manners, in the case that the second fin-shaped structure is subjected to the second fin-cut processing; before the second transistor is formed based on the second fin-shaped structure, the method further comprises: depositing oxide in the second fin-cut groove to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin-cut groove; a second portion of the first shallow trench isolation structure and a third portion of the second shallow trench isolation structure are removed to expose the second fin-shaped structure; and the height of the second portion is the same as the height of the third portion.

[0009] In some possible implementation manners, in the case that the lateral diffusion device is arranged side by side with the first transistor, while the first transistor is formed based on the first fin-shaped structure, the method further comprises: forming the lateral diffusion device based on the first fin-shaped structure and the first planar block structure located in the lateral diffusion region; while the second transistor is formed based on the second fin-shaped structure, the method further comprises: forming the isolation device based on the second fin-shaped structure and the second planar block structure located in the lateral diffusion region; and the isolation device and the lateral diffusion device are arranged in a stack along a first direction.

[0010] In some possible implementation manners, in the case that the lateral diffusion device is arranged side by side with the second transistor, when the first transistor is formed based on the first fin structure, the method further comprises: forming the isolation device based on the first fin structure and the first planar block structure located in the lateral diffusion region; when the second transistor is formed based on the second fin structure, the method further comprises: forming the lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and the isolation device and the lateral diffusion device are arranged in a stack along the first direction.

[0011] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is prepared by the method in the first aspect, and the semiconductor structure comprises: a core device; the core device comprises a first transistor and a second transistor arranged in a stack along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or the second transistor; an isolation device; the isolation device is arranged in a stack with the lateral diffusion device along the first direction, and the isolation device is arranged side by side with the second transistor or the first transistor; the lateral diffusion device comprises a fin structure and a planar block structure, the fin structure is formed by etching a P-type well region in the lateral diffusion device, and the planar block structure is an N-type drift region in the lateral diffusion device.

[0012] In a third aspect, an embodiment of the present application provides a semiconductor device, which comprises the semiconductor structure in the above embodiment.

[0013] In a fourth aspect, an embodiment of the present application provides an electronic device, which comprises a circuit board and the semiconductor device in the above embodiment, and the semiconductor device is arranged on the circuit board.

[0014] In the present application, by forming the fin structure and the planar block structure in the lateral diffusion region, the lateral diffusion device formed can withstand higher voltage and is fully compatible with the process of preparing the stacked transistors, thereby optimizing the preparation process of the semiconductor structure.

[0015] Further, the lateral diffusion device can be arranged side by side with the first transistor or the second transistor, and the etching depth of the first fin cutting process and the second fin cutting process can be selected as full-width depth or half-width depth according to actual requirements, so that the layout of the internal devices of the semiconductor structure is more flexible.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0018] Figure 1 An implementation flowchart of a method for preparing a semiconductor structure in embodiments of the application;

[0019] Figure 2 A design layout of a semiconductor structure in embodiments of the application;

[0020] Figure 3 A structure diagram of a semiconductor structure in embodiments of the application;

[0021] Figures 4A to 4D A diagram of a first preparation process of a semiconductor structure in embodiments of the application;

[0022] Figure 5 A diagram of a fourth preparation process of a semiconductor structure in embodiments of the application;

[0023] Figure 6 A diagram of a fifth preparation process of a semiconductor structure in embodiments of the application;

[0024] The above figures:

[0025] 10, semiconductor structure; 11, first transistor; 111, first spacer; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate dielectric layer; 115, first gate structure; 116, first source-drain metal; 12, lateral diffused device; 121, second spacer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate dielectric layer; 125, second gate structure; 126, second source-drain metal; 13, second transistor; 131, third spacer; 132, third source-drain structure; 133, third interlayer dielectric layer; 134, third gate dielectric layer; 135, third gate structure; 136, third source-drain metal; 14, isolation device; 143, fourth interlayer dielectric layer; 15, first insulating layer; 16, carrier wafer; 21, substrate; 22, fin structure; 221, first fin structure; 222, second fin structure; 231, first fin cut trench; 232, second fin cut trench; 24, photoresist layer; 25, planar block structure; 261, first gate oxide layer; 262, second gate oxide layer; 271, first contact layer; 272, second contact layer; 311, first dummy gate structure; 312, second dummy gate structure; 313, third dummy gate structure; 40, shallow trench isolation layer; 41, first shallow trench isolation structure. DETAILED DESCRIPTION

[0026] The exemplary embodiments will be described in detail below with reference to the accompanying drawings. The following description is only exemplary and is not intended to limit the scope, applicability or configuration of the application. Rather, the scope of the application is only limited by the claims.

[0027] In some embodiments, the LDMOS structure pursues higher breakdown voltage and lower on-resistance. In order to increase the breakdown voltage, there is a drift region between the source region and the drain region, and the impurity concentration of the drift region is low, which presents a high resistance state, and thus can withstand higher voltage. The LDMOS drift region uses STI (shallow trench isolation) / field oxide technology, so that the current path is blocked and becomes longer, thereby further improving the voltage withstand capability. In order to further shrink the size, the LDMOS based on the FinFET (fin field-effect transistor) process has attracted widespread attention. Taking nLDMOS as an example, P-well and N-type drift region are implanted on a p-type substrate, wherein the source region is located in the P-well, and the drain region and STI are located in the N-type drift region, and the gate covers the channel region, part of the N-type drift region and part of the STI region.

[0028] With the performance of FinFET approaching the limit, LDMOS processes based on new structures need to be developed, which helps to further shrink the size of the transistor. Transistor stacking is considered to be a very promising way of micro-shrinking, for example, CFET (complementary field effect transistor) technology. However, there are also some problems, such as: (1) the thermal stability of the bottom layer device when making the upper layer device; (2) the performance of the top layer device under low thermal budget; (3) the metal interconnection of the transistors between layers.

[0029] At present, as a part of the supporting circuit module, how to realize the process compatibility with the stacked transistors is still a problem to be solved.

[0030] In order to solve the above technical problems, the embodiments of the present application provide a preparation method of a semiconductor structure to realize the process compatibility between the lateral diffused device and the stacked transistors.

[0031] In the embodiments of the present application, the above semiconductor structure can be applied to semiconductor devices such as memories, processors and the like.

[0032] In some possible implementations, the semiconductor structure includes: a core device; the core device includes a first transistor and a second transistor stacked along a first direction; a lateral diffusion device; the lateral diffusion device is arranged side-by-side with the first transistor or with the second transistor; an isolation device; the isolation device is stacked with the lateral diffusion device in the first direction, and the isolation device is arranged side-by-side with the second transistor or with the first transistor; wherein the lateral diffusion device includes a fin structure and a planar block structure, the fin structure in the lateral diffusion device is formed by etching a P-type well region in the lateral diffusion device, and the planar block structure is an N-type drift region in the lateral diffusion device.

[0033] It is understood that the semiconductor structure mentioned in the embodiments of this application includes a lateral diffusion device (i.e., LDMOS) and a core device. The lateral diffusion device and the core device can be arranged adjacently, spaced apart, or in other arrangements; this application does not specifically limit this arrangement. It should be noted that a semiconductor structure can include multiple lateral diffusion devices and multiple core devices. The lateral diffusion devices and core devices in the same semiconductor structure are fabricated based on the same substrate (i.e., wafer). For ease of explanation, this application embodiment uses a semiconductor structure including one lateral diffusion device and one core device as an example.

[0034] In some embodiments, the lateral diffusion device in the semiconductor structure is disposed only on the front or back side of the semiconductor structure, that is, the lateral diffusion device is disposed side by side with the first transistor or side by side with the second transistor. The isolation device and the lateral diffusion device are stacked in a first direction. When the lateral diffusion device is disposed side by side with the first transistor, the isolation device is disposed side by side with the second transistor; when the lateral diffusion device is disposed side by side with the second transistor, the isolation device is disposed side by side with the first transistor.

[0035] In this embodiment, the core device includes a first transistor and a second transistor stacked back-to-back to form a stacked transistor. The first transistor and the second transistor can be the same type of transistor, such as a fin field-effect transistor.

[0036] Figure 2 It is a semiconductor structure composed of fin field-effect transistors and lateral diffusion devices. See [link / reference] Figure 2 As shown, the semiconductor structure includes a lateral diffusion device and a core device. The core device includes a first transistor and a second transistor stacked along a first direction. The semiconductor structure also includes a lateral diffusion device, which is arranged side-by-side with the first transistor or side-by-side with the second transistor. The following description, in conjunction with... Figure 2 The semiconductor structure shown illustrates the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0037] Figure 1 For an embodiment flowchart of the method for manufacturing the semiconductor structure in the present application, refer to FIG. 1. Figure 1 As shown in FIG. 1, the method for manufacturing the semiconductor structure can include the following steps.

[0038] S101, providing a substrate; wherein the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are adjacently arranged in a second direction; the second direction is perpendicular to a first direction.

[0039] It can be understood that the substrate includes the lateral diffusion region for forming the lateral diffusion device and the isolation device, and the core region for forming the core device. The lateral diffusion region and the core region can be adjacently arranged.

[0040] In some embodiments, the semiconductor structure is a stacked transistor, and accordingly, the lateral diffusion device and the isolation device are stacked; the first transistor and the second transistor in the core device are stacked.

[0041] In some embodiments, the substrate can be made of a silicon (Si) material, that is, a Si substrate, or other forms of substrates according to actual needs, such as a silicon on insulator (SOI) substrate.

[0042] S102, performing ion implantation in the lateral diffusion region to form a P-type well region and an N-type drift region.

[0043] It can be understood that, by using a mask plate process, ion implantation can be performed twice in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region, respectively. In the process of ion implantation, the P-type well region can be formed first, and then the N-type drift region can be formed. Alternatively, the N-type drift region can be formed first, and then the P-type well region can be formed. It should be noted that the implantation mode of the N-type drift region can be selected according to actual needs, such as full implantation or partial implantation, which is not limited in the embodiments of the present application; a PN junction in the horizontal direction (i.e., the second direction) can be formed between the N-type drift region and the P-type well region.

[0044] S103, etching the P-type well region and the core region to form a fin structure and a planar block structure; wherein the fin structure includes a first fin structure and a second fin structure stacked along the first direction; the planar block structure is formed based on the unetched N-type drift region in the lateral diffusion region; the planar block structure includes a first planar block structure and a second planar block structure stacked along the first direction.

[0045] It can be understood that, by etching the substrate, a fin structure and a planar block structure can be formed. The fin structure in the core region is used to form a core device; the fin structure and the planar block structure in the lateral diffusion region, the fin structure in the lateral diffusion region is formed by etching the P-type well region, and the planar block structure is formed by the unetched N-type drift region. In the lateral diffusion region, along the extension direction of the fin structure, the lateral diffusion region can be divided into a fin-type diffusion region and a planar diffusion region, wherein the fin-type diffusion region is a region in the lateral diffusion region where the fin structure is located, and the planar diffusion region is a region in the lateral diffusion region where the planar block structure is located. The fin structure and the planar block structure in the lateral diffusion region are used to form a lateral diffusion device and an isolation device. The fin structure can be divided into an upper half and a lower half, the upper half is a first fin structure, and the lower half is a second fin structure. Among them, the first fin structure located in the lateral diffusion region is used to form a lateral diffusion device or an isolation device, and the second fin structure located in the lateral diffusion region is used to form an isolation device or a lateral diffusion device; the first fin structure located in the core region is used to form a first transistor, and the second fin structure located in the core region is used to form a second transistor.

[0046] In some embodiments, a larger etching depth can be used when etching the substrate. The height of the fin structure should be greater than a preset height threshold, for example, the height of the fin structure can be greater than 100 nm, it should be noted that the height of the fin structure can be designed according to actual needs, and the embodiments of the present application do not make specific limitations.

[0047] S104, forming a first transistor based on the first fin structure.

[0048] It can be understood that, after the first fin structure is formed, the first transistor can be formed according to the standard process of preparing a transistor.

[0049] S105, film reversal and removal of the substrate.

[0050] It can be understood that, after the first transistor is formed, in order to prepare a second transistor, the first transistor can be subjected to film reversal treatment and the substrate is removed, so that the second fin structure is placed upward.

[0051] In some possible implementations, before the above S105, the method for preparing the semiconductor structure can further include: depositing an insulating material on the upper surface of the first transistor to form an insulating layer; and bonding the insulating layer with a film wafer.

[0052] In the embodiments of the present application, the bonded film wafer can provide physical support for the flipped first transistor after film reversal, effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0053] S106, forming a second transistor based on the second fin structure.

[0054] It can be understood that after the film is developed, the second transistor can be formed according to a standard process of preparing a transistor.

[0055] In some possible embodiments, the method for preparing the semiconductor structure further can include: performing a first fin cut process on the first fin structure to form a first fin cut groove, and / or performing a second fin cut process on the second fin structure to form a second fin cut groove; the first fin cut groove is perpendicular to an extension direction of the first fin structure, and an etching depth of the first fin cut groove is half of a height of the fin structure or equal to the height of the fin structure; the second fin cut groove is perpendicular to an extension direction of the second fin structure, and an etching depth of the second fin cut groove is half of a height of the fin structure or equal to the height of the fin structure.

[0056] It can be understood that, in the process of preparing the semiconductor structure, the first fin cut process and / or the second fin cut process can be selected according to actual needs. For example, the first fin cut process can be performed on the first fin structure, and the second fin cut process can be performed on the second fin structure; only the first fin cut process can be performed on the first fin structure; or only the second fin cut process can be performed on the second fin structure.

[0057] In some embodiments, in the case that the first fin cut process is performed on the first fin structure, an etching depth of the first fin cut process can be a half depth, that is, the etching depth is half of a height of the fin structure; or the etching depth of the first fin cut process can be a full depth, that is, the etching depth is equal to the height of the fin structure. The etching depth of the first fin cut process can be designed according to actual needs, which is not limited in the embodiments of the present application.

[0058] In some embodiments, in the case that the second fin cut process is performed on the second fin structure, an etching depth of the second fin cut process can be a half depth, that is, the etching depth is half of a height of the fin structure; or the etching depth of the second fin cut process can be a full depth, that is, the etching depth is equal to the height of the fin structure. The etching depth of the second fin cut process can be designed according to actual needs, which is not limited in the embodiments of the present application.

[0059] In some possible embodiments, S103 can include: coating photoresist on the N-type drift region to form a photoresist layer; etching the P-type well region and the core region under the mask effect of the photoresist layer to form the fin structure located in the P-type well region and the core region, and the planar block structure located in the N-type drift region.

[0060] It can be understood that, since the fin-shaped structure in the lateral diffusion region is formed by etching the P-type well region, in order to avoid etching to the N-type drift region, photoresist can be coated on the N-type drift region before etching, and the photoresist layer formed can protect the N-type drift region from being etched. At the same time, the P-type well region and the core region are etched, and the fin-shaped structure of the lateral diffusion region and the fin-shaped structure of the core region can be formed. The N-type drift region not etched forms a planar block structure.

[0061] In some possible implementation manners, before S104, the method for manufacturing the semiconductor structure can further include: depositing oxide on the substrate and the fin-shaped structure to form a first shallow trench isolation structure; the first shallow trench isolation structure wraps the fin-shaped structure; and a first portion of the first shallow trench isolation structure is removed to expose the first fin-shaped structure.

[0062] It can be understood that, the oxide is deposited on the substrate and the fin-shaped structure to form a first shallow trench isolation structure (STI). The first shallow trench isolation structure wraps the fin-shaped structure and covers the substrate. The portion (first portion) of the first shallow trench isolation structure wrapping the first fin-shaped structure is removed to expose the first fin-shaped structure, so as to facilitate subsequent manufacturing of the first transistor.

[0063] In some possible implementation manners, in the case that the first fin-shaped structure is subjected to the first fin cutting process, the depositing oxide on the substrate and the fin-shaped structure to form the first shallow trench isolation structure can include: depositing oxide on the substrate and the fin-shaped structure, and depositing oxide in the first fin cutting groove to form the first shallow trench isolation structure; and the first shallow trench isolation structure fills the first fin cutting groove.

[0064] It can be understood that, after the first fin-shaped structure is formed and the first fin-shaped structure is subjected to the first fin cutting process, the first fin cutting groove is formed, and the oxide is used to fill the first fin cutting groove in the process of forming the first shallow trench isolation structure.

[0065] In some possible implementation manners, in the case that the second fin-shaped structure is subjected to the second fin cutting process, before S106, the method for manufacturing the semiconductor structure can further include: depositing oxide in the second fin cutting groove to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin cutting groove; a second portion of the first shallow trench isolation structure and a third portion of the second shallow trench isolation structure are removed to expose the second fin-shaped structure; and the height of the second portion is the same as the height of the third portion.

[0066] It can be understood that after the second fin cut groove is formed and the oxide is filled in the second fin cut groove to form the second shallow trench isolation structure, at this time, the second fin structure is wrapped by the second shallow trench isolation structure and the first shallow trench isolation structure at the same time. Then, the part (i.e., the third part) of the second shallow trench isolation structure wrapping the second fin structure and the part (i.e., the second part) of the first shallow trench isolation structure wrapping the second fin structure are removed to expose the second fin structure, facilitating subsequent preparation of the second transistor.

[0067] In some possible implementation manners, in the case where the lateral diffusion device is arranged side by side with the first transistor, the method for manufacturing the semiconductor structure can further include, at the same time as S104, forming the lateral diffusion device based on the first fin structure and the first planar block structure located in the lateral diffusion region. At the same time as S106, the method for manufacturing the semiconductor structure can further include forming the isolation device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and the isolation device and the lateral diffusion device are arranged in a stacked manner along the first direction.

[0068] It can be understood that in the case where the lateral diffusion device is arranged side by side with the first transistor, the lateral diffusion device is manufactured at the same time as the first transistor is manufactured; and the isolation device is manufactured at the same time as the second transistor is manufactured.

[0069] In some possible implementation manners, in the case where the lateral diffusion device is arranged side by side with the second transistor, the method for manufacturing the semiconductor structure can further include, at the same time as S104, forming the isolation device based on the first fin structure and the first planar block structure located in the lateral diffusion region. At the same time as S106, the method for manufacturing the semiconductor structure can further include forming the lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; and the isolation device and the lateral diffusion device are arranged in a stacked manner along the first direction.

[0070] It can be understood that in the case where the lateral diffusion device is arranged side by side with the second transistor, the isolation device is manufactured at the same time as the first transistor is manufactured; and the lateral diffusion device is manufactured at the same time as the second transistor is manufactured.

[0071] In some embodiments, in the case that the lateral diffusion device is arranged side by side with the first transistor, the above-mentioned steps of forming the first transistor and the lateral diffusion device can comprise: based on the first fin structure, forming a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device; etching a part of the first fin structure to form a first source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the first source-drain recess and the second source-drain recess to form a first source-drain structure in the first transistor and a second source-drain structure in the lateral diffusion device; removing the first dummy gate structure and the second dummy gate structure, and forming a first gate structure in the first transistor and a second gate structure in the lateral diffusion device; forming a first source-drain metal in the first transistor and a second source-drain metal in the lateral diffusion device on the first source-drain structure and the second source-drain structure; and performing a back-end-of-line process on the first gate structure, the second gate structure, the first source-drain metal and the second source-drain metal to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0072] It should be noted that the same devices in the first transistor and the lateral diffusion device are formed in the same process, for example, the first dummy gate structure and the second dummy gate structure are formed in the same process, and the first source-drain structure and the second source-drain structure are formed in the same process.

[0073] In an example, after forming the first shallow trench isolation structure, a first portion of the first shallow trench isolation structure is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on a surface of the first fin structure to form a first gate oxide layer covering the surface of the first fin structure. Then, a gate recess is opened on the first gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a first dummy gate structure in the first transistor and a second dummy gate structure in the lateral diffusion device. A dielectric material is deposited on sidewalls of the first dummy gate structure to form a first spacer in the first transistor, and a dielectric material is deposited on sidewalls of the second dummy gate structure to form a second spacer in the lateral diffusion device. A portion of the first fin structure is etched to form a first source / drain recess and a second source / drain recess. Source / drain epitaxial growth is performed in the first source / drain recess to form a first source / drain structure in the first transistor, and source / drain epitaxial growth is performed in the second source / drain recess to form a second source / drain structure in the lateral diffusion device. A dielectric material is deposited on the first source / drain structure, the second source / drain structure, and the etched first shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the first interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the first dummy gate structure and the second dummy gate structure. Then, the first dummy gate structure and the second dummy gate structure are removed to expose the gate recess, and a metal material is deposited in the gate recess to form a first gate structure in the first transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the first interlayer dielectric layer and the second interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer, the first interlayer dielectric layer, and the second interlayer dielectric layer are etched to form a first via hole on an upper surface of the first source / drain structure and a second via hole on an upper surface of the second source / drain structure. A metal material is deposited in the first via hole and the second via hole to form a first source / drain metal and a second source / drain metal. Finally, a back-end-of-line process is performed on the first contact layer to form a first metal interconnection layer in the first transistor and a second metal interconnection layer in the lateral diffusion device.

[0074] In some embodiments, in the case where the lateral diffusion device is arranged side by side with the first transistor, the above-mentioned steps of forming the second transistor and the isolation device can include: based on the second fin structure, forming a third dummy gate structure in the second transistor; etching a portion of the second fin structure to form a third source / drain recess; performing source / drain epitaxial growth in the third source / drain recess to form a third source / drain structure in the second transistor; removing the third dummy gate structure and forming a third gate structure in the second transistor; forming a third source / drain metal in the second transistor on the third source / drain structure; performing a back-end-of-line process on the third gate structure and the third source / drain metal to form a third metal interconnection layer in the second transistor and a back surface dielectric layer in the isolation device; and the lateral diffusion device and the isolation device are arranged in a stack along a first direction.

[0075] It can be understood that the gate structure, the source-drain structure and the source-drain metal are not formed in the isolation device.

[0076] In an example, the second part of the first shallow trench isolation structure and the third part of the second shallow trench isolation structure are etched so that the second fin structure is exposed, and the remaining (i.e., not etched) first shallow trench isolation structure is used as a shallow trench isolation layer. An oxide of a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer, which covers the surface of the second fin structure. Then, a gate recess is opened on the second gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a third dummy gate structure in the second transistor; a dielectric material is deposited on the sidewall of the third dummy gate structure to form a third spacer in the second transistor. A part of the second fin structure is etched to form a third source-drain recess; source-drain epitaxial growth is performed in the third source-drain recess to form a third source-drain structure in the second transistor. A dielectric material is deposited on the third source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a fourth interlayer dielectric layer in the isolation device. It should be noted that the height of the third interlayer dielectric layer and the fourth interlayer dielectric layer is the same as the height of the third dummy gate structure. Then, the third dummy gate structure is removed to expose the gate recess, and a metal material is deposited in the gate recess to form a third gate structure in the second transistor. An insulating material is deposited on the third interlayer dielectric layer and the fourth interlayer dielectric layer to form a second contact layer. By photolithography, the second contact layer and the third interlayer dielectric layer are etched to form a third via hole located on the upper surface of the third source-drain structure. A metal material is deposited in the third via hole to form a third source-drain metal. Finally, a backside dielectric layer in the isolation device and a third metal interconnection layer in the second transistor are formed by performing a back-end-of-line process on the second contact layer.

[0077] It should be noted that, in the case where the lateral diffuser device is arranged side by side with the first transistor, since the gate structure and the source-drain structure are not formed in the isolation device, only a dielectric layer (i.e., a backside dielectric layer) needs to be formed in the process of the back-end-of-line process, and metal interconnection does not need to be performed in the backside dielectric layer.

[0078] In some embodiments, the metal material for forming the first gate structure, the second gate structure and the third gate structure can include, but is not limited to, tantalum nitride (TaN), titanium nitride (TiN), aluminum nitride (AlN), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), and the material of the first gate structure, the second gate structure and the third gate structure can be selected according to actual conditions, and is not limited to the metal materials listed above.

[0079] It should be noted that, for the convenience of description, the first source-drain structure mentioned in the embodiments of the present application is a short name, and specifically refers to the first source structure and / or the first drain structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, and the like are similar to the first source-drain structure, and "source-drain" in them is a short name for "source and / or drain".

[0080] In some embodiments, the oxide forming the first shallow trench isolation structure and the second shallow trench isolation structure can be any one of the following: silicon dioxide (SiO2) or silicon carbon oxide (SiCO), and the like.

[0081] In some embodiments, in the case where the lateral diffusion device is arranged side by side with the second transistor, the above-mentioned step of forming the first transistor and the isolation device can include: based on the first fin structure, forming a first dummy gate structure in the first transistor; etching a part of the first fin structure to form a first source-drain recess; performing source-drain epitaxial growth in the first source-drain recess to form a first source-drain structure in the first transistor; removing the first dummy gate structure and forming a first gate structure in the first transistor; forming a first source-drain metal in the first transistor on the first source-drain structure; performing a back-end-of-line process on the first gate structure and the first source-drain metal to form a first metal interconnection layer in the first transistor and a front surface dielectric layer in the isolation device; and the isolation device and the lateral diffusion device are arranged in a stack along the first direction.

[0082] In an example, a first portion of the first shallow trench isolation structure is etched so that the first fin structure is exposed. An oxide of a preset height is deposited on a surface of the first fin structure to form a first gate oxide layer covering the surface of the first fin structure. A gate recess is then opened on the first gate oxide layer by photolithography, and a polysilicon is deposited in the gate recess to form a first dummy gate structure in the first transistor. A dielectric material is deposited on sidewalls of the first dummy gate structure to form a first spacer in the first transistor. A portion of the first fin structure is etched to form a first source-drain recess. Source-drain epitaxial growth is performed in the first source-drain recess to form a first source-drain structure in the first transistor. A dielectric material is deposited on the first source-drain structure and the etched first shallow trench isolation structure to form a first interlayer dielectric layer in the first transistor and a fourth interlayer dielectric layer in the isolation device. It is noted that the first interlayer dielectric layer and the fourth interlayer dielectric layer have the same height as the first dummy gate structure. Next, the first dummy gate structure is removed to expose the gate recess, and a metal material is deposited in the gate recess to form a first gate structure in the first transistor. An insulating material is deposited on the first interlayer dielectric layer and the fourth interlayer dielectric layer to form a first contact layer. By photolithography, the first contact layer and the first interlayer dielectric layer are etched to form a first via on an upper surface of the first source-drain structure. A metal material is deposited in the first via to form a first source-drain metal. Finally, a back-end-of-line process is performed on the first contact layer to form a first metal interconnection layer in the first transistor and a front-side dielectric layer in the isolation device.

[0083] It is noted that, in the case where the lateral diffuser device is arranged side by side with the second transistor, no gate structure and source-drain structure are formed in the isolation device, and therefore, in the process of the back-end-of-line, only a dielectric layer (i.e., the front-side dielectric layer) needs to be formed, and no metal interconnection needs to be performed in the front-side dielectric layer.

[0084] In some embodiments, in the case where the lateral diffuser device is arranged side by side with the second transistor, the above-mentioned steps of forming the second transistor and the lateral diffuser device can include: based on the second fin structure, forming a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffuser device; etching a portion of the second fin structure to form a third source-drain recess and a second source-drain recess; performing source-drain epitaxial growth in the third source-drain recess and the second source-drain recess to form a third source-drain structure in the second transistor and a second source-drain structure in the lateral diffuser device; removing the third dummy gate structure and the second dummy gate structure, and forming a third gate structure in the second transistor and a second gate structure in the lateral diffuser device; forming a third source-drain metal in the second transistor and a second source-drain metal in the lateral diffuser device on the third source-drain structure and the second source-drain structure; and performing a back-end-of-line process on the third gate structure, the second gate structure, the third source-drain metal, and the second source-drain metal to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffuser device.

[0085] It can be understood that, in the case that the lateral diffusion device is arranged side by side with the second transistor, the same device in the second transistor and the lateral diffusion device is formed in the same process, for example, the third dummy gate structure and the second dummy gate structure are formed in the same process, and the third source-drain structure and the second source-drain structure are formed in the same process.

[0086] In an example, the second part of the first shallow trench isolation structure and the third part of the second shallow trench isolation structure are etched so that the second fin structure is exposed, and a shallow trench isolation layer is formed. An oxide with a preset height is deposited on the surface of the second fin structure to form a second gate oxide layer covering the surface of the second fin structure. Then, a gate recess is opened on the second gate oxide layer by lithography, and a polysilicon is deposited in the gate recess to form a third dummy gate structure in the second transistor and a second dummy gate structure in the lateral diffusion device; a dielectric material is deposited on the sidewall of the third dummy gate structure to form a third spacer in the second transistor, and a dielectric material is deposited on the sidewall of the second dummy gate structure to form a second spacer in the lateral diffusion device. A part of the second fin structure is etched to form a third source-drain recess and a second source-drain recess; source-drain epitaxial growth is performed in the third source-drain recess to form a third source-drain structure in the second transistor, and source-drain epitaxial growth is performed in the second source-drain recess to form a second source-drain structure in the lateral diffusion device. A dielectric material is deposited on the third source-drain structure, the second source-drain structure and the shallow trench isolation layer to form a third interlayer dielectric layer in the second transistor and a second interlayer dielectric layer in the lateral diffusion device. It should be noted that the height of the third interlayer dielectric layer and the second interlayer dielectric layer is the same as the height of the third dummy gate structure and the second dummy gate structure. Then, the third dummy gate structure and the second dummy gate structure are removed to expose the gate recess, and a metal material is deposited in the gate recess to form a third gate structure in the second transistor and a second gate structure in the lateral diffusion device. An insulating material is deposited on the third interlayer dielectric layer and the second interlayer dielectric layer to form a second contact layer. By lithography, the second contact layer, the third interlayer dielectric layer and the second interlayer dielectric layer are etched to form a third via hole located on the upper surface of the third source-drain structure and a second via hole located on the upper surface of the second source-drain structure. A metal material is deposited in the third via hole and the second via hole to form a third source-drain metal and a second source-drain metal. Finally, a post-process is performed on the second contact layer to form a third metal interconnection layer in the second transistor and a second metal interconnection layer in the lateral diffusion device.

[0087] In the following, the semiconductor structure provided by the embodiments of the present application will be described by taking the first transistor and the second transistor as fin-type field effect transistors as an example. Figure 2 The design layout of the semiconductor structure in the embodiments of the present application. Figure 2(a) is the design layout of the lateral diffusion device. It should be noted that, for ease of understanding, only the fin structure, gate structure, and source / drain structure are shown in the design layout; (b) is the design layout of the first transistor; (c) is the design layout of the isolation device; and (d) is the design layout of the second transistor. Figure 3 This is a schematic diagram of a semiconductor structure in one embodiment of this application. Figure 3 (a) is a cross-sectional view of the semiconductor structure taken along the AA' direction of the lateral diffusion region; (b) is a cross-sectional view of the semiconductor structure taken along the BB' direction of the lateral diffusion region; (c) is a cross-sectional view of the semiconductor structure taken along the A1-A1' direction of the core region; and (d) is a cross-sectional view of the semiconductor structure taken along the B1-B1' direction of the core region.

[0088] Figure 3 The semiconductor structure 10 shown has a lateral diffusion device and a first transistor arranged side by side. The first fin structure is subjected to a first fin cutting process with an etching depth of the full width. The second fin structure is not subjected to fin cutting.

[0089] The following section, in conjunction with the above preparation method, discusses... Figure 3 The fabrication process of the semiconductor structure 10 shown will be explained. Figure 3 The semiconductor structure 10 shown can be used to... Figures 4A to 4D The process shown is used for preparation. Figures 4A to 4D This is a schematic diagram of the first fabrication process of the semiconductor structure in the embodiments of this application.

[0090] In one example, the first fabrication process of the semiconductor structure 10 may include the following steps:

[0091] Step 1: Provide a Si substrate 21. Coat the Si substrate 21 with photoresist and perform two ion implantations in the lateral diffusion region to form a high-concentration P-type well region and a low-concentration N-type drift region (see...). Figure 4A (a) in the middle.

[0092] Step 2: Remove the photoresist on the Si substrate 21, coat the N-type drift region with photoresist to form a photoresist layer 24, and etch the substrate 21 under the masking effect of the photoresist layer 24 to form fin structures 22 in the core region and P-type well region. The fin structures 22 include a first fin structure 221 and a second fin structure 222. The unetched N-type drift region forms a planar block structure 25 (see...). Figure 4A (b) in the example. Figure 4A As shown in (b), this is a cross-sectional view of the AA' direction of the transverse diffusion region. The shape of the fin-like structure in the transverse diffusion region is shown by dashed lines. The fin-like structure is located in the P-type trap region.

[0093] It should be noted that, inFigures 4A to 4D The diagram showing one fin-like structure in the core area and two fin-like structures in the lateral diffusion area is for illustrative purposes only; the number of fin-like structures can be set according to actual needs and is not limited to the examples described above. Figures 4A to 4D The number of fin structures shown in this embodiment is not specifically limited.

[0094] Step 3: Perform a first fin cutting process on the first fin structure 221 to form a first fin cutting groove 231 (see...). Figure 4A (c) in the figure. The etching depth is the full width depth.

[0095] Step 4: Deposit oxide on substrate 21 and fin structure 22 to form a first shallow trench isolation structure 41. The first shallow trench isolation structure 41 encloses fin structure 22, covers substrate 21, and fills the first fin trench 231. Then, etch a first portion of the first shallow trench isolation structure 41 to expose the first fin structure 221. Deposit oxide on the surface of the first fin structure 221 to form a first gate oxide layer 261. Form a first dummy gate structure 311, a first spacer 111, a second dummy gate structure 312, and a second spacer 121 on the first gate oxide layer 261 (see...). Figure 4B (a) in the middle.

[0096] It should be noted that the first gate oxide layer 261 can be made of the same material as the first shallow trench isolation structure 41.

[0097] Step 5: Etch the first fin structure 221 to form the first source / drain groove and the second source / drain groove. Perform epitaxial growth of the source / drain in the first source / drain groove and the second source / drain groove to form the first source / drain structure 112 and the second source / drain structure 122 (see...). Figure 4B (b) in the middle.

[0098] Step 6: Deposit dielectric material on the etched first shallow trench isolation structure 41, first source / drain structure 112, and second source / drain structure 122 to form a first interlayer dielectric layer 113 and a second interlayer dielectric layer 123. Remove the first dummy gate structure 311 and the second dummy gate structure 312 to expose the gate trench, and deposit insulating material on the surface of the gate trench to form a first gate dielectric layer 114 and a second gate dielectric layer 124; then, deposit metal material in the gate trench to form a first gate structure 115 and a second gate structure 125. Deposit dielectric material on the first interlayer dielectric layer 113 and the second interlayer dielectric layer 123 to form a first contact layer 271. Perform photolithography on the first contact layer 271, the first interlayer dielectric layer 113, and the second interlayer dielectric layer 123 to form a first via and a second via; deposit metal material in the first via and the second via to form a first source / drain metal 116 and a second source / drain metal 126 (see...). Figure 4BThe first contact layer 271 is formed by depositing a metal layer on the exposed surface of the second gate oxide layer 262 and the second source / drain structure 222. The first contact layer 271 is then patterned by photolithography and etching. The first contact layer 271 is formed by depositing a metal layer on the exposed surface of the second gate oxide layer 262 and the second source / drain structure 222. The first contact layer 271 is then patterned by photolithography and etching.

[0099] It is noted that the first contact layer 271 can be made of the same material as the spacers (e.g. the first spacer 111 and the second spacer 121).

[0100] Step 7: After the first transistor 11 and the lateral diffused device 12 are formed, an insulating material is deposited on the first transistor 11 and the lateral diffused device 12 to form a first insulating layer 15. Then, a handle wafer 16 is bonded to the first insulating layer 15 (see Fig. 2 (a)). Figure 4C

[0101] Step 8: The first transistor 11 and the lateral diffused device 12 are flipped and the substrate 21 is removed so that the second fin structure 222 is placed upward (see Fig. 2 (b)). Figure 4C

[0102] Step 9: The second portion of the first shallow trench isolation structure 41 is removed by etching so that the second fin structure 222 is exposed and a shallow trench isolation layer 40 is formed. An oxide is deposited on the surface of the exposed second fin structure 222 to form a second gate oxide layer 262. A third dummy gate structure 313 and a third spacer 131 are formed on the second gate oxide layer 262 in the core region (see Fig. 2 (c)). Figure 4C

[0103] Step 10: The third source / drain structure 132 in the second transistor 13 is formed by referring to the steps in the above-mentioned Step 5 (see Fig. 2 (a)). Figure 4D

[0104] Step 11: The third ILD layer 133, the third gate dielectric layer 134, the third gate structure 135, the second contact layer 272, the third source / drain metal 136 in the second transistor 13 and the fourth ILD layer 143 in the isolation device 14 are formed by referring to the steps in the above-mentioned Step 6 (see Fig. 2 (b)). The third metal interconnect layer in the second transistor 13 and the backside dielectric layer in the isolation device 14 are also formed (not shown in the figure). Figure 4D

[0105] So far, the semiconductor structure 10 has been prepared according to the first preparation method.

[0106] ​​​​​In some embodiments, the first preparation method is only used for fin cutting the first fin structure (i.e., first fin cutting), and the fin cutting depth is full-width depth; based on the first preparation method, the second preparation method provided by the embodiments of the present application can be used for fin cutting the second fin structure (i.e., second fin cutting), and the fin cutting depth is full-width depth; the preparation methods of other structures (such as the first source / drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the second preparation method are the same as the first preparation method, which is not limited in the embodiments of the present application.

[0107] In some embodiments, the third preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the first transistor; in the preparation process, the first fin structure is subjected to first fin cutting, and the etching depth of the first fin cutting is half-width depth; the second fin structure is subjected to second fin cutting, and the etching depth of the second fin cutting is half-width depth. The preparation methods of other structures (such as the first source / drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the third preparation method are the same as the first preparation method, which is not limited in the embodiments of the present application.

[0108] In some embodiments, the fourth preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the first transistor; in the preparation process, the first fin structure is subjected to first fin cutting, and the etching depth of the first fin cutting is half-width depth; the second fin structure is subjected to second fin cutting, and the etching depth of the second fin cutting is full-width depth. Figure 5 For a schematic diagram of the fourth preparation process of the semiconductor structure in the embodiments of the present application, refer to FIG. 12. Figure 5 As shown in FIG. 12, after the second fin structure is subjected to the second fin cutting, the second fin cutting groove 232 is formed. The preparation methods of other structures (such as the first source / drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the fourth preparation method are the same as the first preparation method, which is not limited in the embodiments of the present application.

[0109] In some embodiments, the fifth preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; in the preparation process, only the first fin structure is subjected to first fin cutting, and the etching depth of the first fin cutting is full-width depth; the second fin structure is not subjected to fin cutting. Figure 6 For a schematic diagram of the fifth preparation process of the semiconductor structure in the embodiments of the present application, refer to FIG. 13. Figure 6As shown, in the case where the lateral diffusion device is arranged side by side with the second transistor, the ion implantation depth of the N-type drift region is deeper. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the fifth preparation method are the same as the first preparation method described above, which will not be limited herein.

[0110] In some embodiments, the sixth preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; during the preparation process, only the second fin cutting process is performed on the second fin-shaped structure, and the etching depth of the second fin cutting process is full-width depth, and the fin cutting process is not performed on the first fin-shaped structure. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the sixth preparation method are the same as the first preparation method described above, which will not be limited herein.

[0111] In some embodiments, the seventh preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; during the preparation process, the first fin cutting process is performed on the first fin-shaped structure, and the etching depth of the first fin cutting process is half-width depth, and the second fin cutting process is performed on the second fin-shaped structure, and the etching depth of the second fin cutting process is half-width depth. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the seventh preparation method are the same as the first preparation method described above, which will not be limited herein.

[0112] In some embodiments, the eighth preparation method of the semiconductor structure, the lateral diffusion device is arranged side by side with the second transistor; during the preparation process, the first fin cutting process is performed on the first fin-shaped structure, and the etching depth of the first fin cutting process is half-width depth, and the second fin cutting process is performed on the second fin-shaped structure, and the etching depth of the second fin cutting process is half-width depth. The preparation methods of other structures (such as the first source-drain structure, the first gate structure, etc.) in the semiconductor structure prepared based on the seventh preparation method are the same as the first preparation method described above, which will not be limited herein.

[0113] In the embodiments of the present application, by forming the fin-shaped structure and the planar block structure in the lateral diffusion region, the formed lateral diffusion device can withstand higher voltage while being fully compatible with the process of preparing the stacked transistor, thereby optimizing the preparation process of the semiconductor structure.

[0114] Further, since the lateral diffusion device can be arranged side by side with the first transistor or the second transistor, and the etching depth of the first fin cutting process and the second fin cutting process can be selected as full-width depth or half-width depth according to actual needs, the layout of the internal devices of the semiconductor structure is more flexible.

[0115] Further, the semiconductor structure provided by the embodiments of the present application can be detected by a detection analysis instrument, for example, a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscopy (STEM), and the like. Taking the TEM as an example, the semiconductor structure provided by the embodiments of the present application can be detected in a TEM slice mode, for example, the lateral diffuser device and the first transistor are arranged side by side or the lateral diffuser device and the second transistor are arranged side by side, and the lateral diffuser device includes a fin-type diffusion region and a planar diffusion region.

[0116] Further, the semiconductor structure provided by the embodiments of the present application can be detected by a detection analysis instrument, for example, a scanning electron microscope (SEM), a transmission electron microscope (TEM), a scanning transmission electron microscopy (STEM), and the like. Taking the TEM as an example, the semiconductor structure provided by the embodiments of the present application can be detected in a TEM slice mode, for example, the lateral diffuser device and the first transistor are arranged side by side or the lateral diffuser device and the second transistor are arranged side by side, and the lateral diffuser device includes a fin-type diffusion region and a planar diffusion region.

[0117] The embodiments of the present application provide a semiconductor device, including the semiconductor structure as described above. The specific limitation of the semiconductor structure can be referred to the semiconductor structure as described above, and will not be repeated here. Figure 3 The specific limitation of the semiconductor structure can be referred to the semiconductor structure as described above, and will not be repeated here.

[0118] The embodiments of the present application provide an electronic device, including a circuit board and the semiconductor device as described above, and the semiconductor device is arranged on the circuit board. The semiconductor device includes the semiconductor structure as described above. The specific limitation of the semiconductor structure can be referred to the semiconductor structure as described above, and will not be repeated here. Figure 3 The specific limitation of the semiconductor structure can be referred to the semiconductor structure as described above, and will not be repeated here. Figure 5 The specific limitation of the semiconductor structure can be referred to the semiconductor structure as described above, and will not be repeated here.

[0119] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the illustrative description of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0120] The above merely provides preferred embodiments of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the principles and technical scope of the present application shall fall into the scope of the present application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The semiconductor structure includes a lateral diffusion device and a core device. The core device includes a first transistor and a second transistor stacked along a first direction. The lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor. The method includes: A substrate is provided; the substrate includes a lateral diffusion region and a core region; the lateral diffusion region and the core region are disposed adjacent to each other in a second direction; the second direction is perpendicular to the first direction; Ion implantation is performed in the lateral diffusion region to form a P-type trap region and an N-type drift region; The P-type well region and the core region are etched to form a fin-like structure and a planar block structure; the fin-like structure includes a first fin-like structure and a second fin-like structure stacked along the first direction; the planar block structure is formed based on the unetched N-type drift region in the lateral diffusion region; the planar block structure includes a first planar block structure and a second planar block structure stacked along the first direction. The first transistor is formed based on the first fin structure; The wafer is then poured and the substrate is removed. The second transistor is formed based on the second fin structure; The method further includes: performing a first fin cutting process on the first fin structure to form a first fin cutting groove, and / or performing a second fin cutting process on the second fin structure to form a second fin cutting groove; the first fin cutting groove is perpendicular to the extension direction of the first fin structure, and the etching depth of the first fin cutting groove is half the height of the fin structure or equal to the height of the fin structure; the second fin cutting groove is perpendicular to the extension direction of the second fin structure, and the etching depth of the second fin cutting groove is half the height of the fin structure or equal to the height of the fin structure.

2. The method according to claim 1, characterized in that, The etching of the P-type well region and the core region to form fin-like structures and planar block structures includes: Photoresist is coated on the N-type drift region to form a photoresist layer; Under the masking action of the photoresist layer, the P-type well region and the core region are etched to form fin-like structures located in the P-type well region and the core region, as well as planar block-like structures located in the N-type drift region.

3. The method according to claim 1, characterized in that, Prior to forming the first transistor based on the first fin structure, the method further includes: An oxide is deposited on the substrate and the fin structure to form a first shallow trench isolation structure; the first shallow trench isolation structure encloses the fin structure; Remove a first portion of the first shallow trench isolation structure to expose the first fin structure.

4. The method according to claim 3, characterized in that, When the first fin structure is subjected to a first fin-cutting process; The deposition of oxide on the substrate and the fin structure to form a first shallow trench isolation structure includes: Oxides are deposited on the substrate and the fin structure, and oxides are deposited in the first fin trench to form a first shallow trench isolation structure; The first shallow trench isolation structure fills the first fin-cut groove.

5. The method according to claim 3, characterized in that, When the second fin structure is subjected to a second fin-cutting process; Prior to forming the second transistor based on the second fin structure, the method further includes: An oxide is deposited in the second fin groove to form a second shallow trench isolation structure; the second shallow trench isolation structure fills the second fin groove. Remove the second portion of the first shallow trench isolation structure and the third portion of the second shallow trench isolation structure to expose the second fin structure; the height of the second portion is the same as the height of the third portion.

6. The method according to claim 1, characterized in that, When the lateral diffusion device is arranged side by side with the first transistor... While forming the first transistor based on the first fin structure, the method further includes: forming the lateral diffusion device based on the first fin structure located in the lateral diffusion region and the first planar block structure; While forming the second transistor based on the second fin structure, the method further includes: forming an isolation device based on the second fin structure and the second planar block structure located in the lateral diffusion region; the isolation device and the lateral diffusion device are stacked along the first direction.

7. The method according to claim 1, characterized in that, When the lateral diffusion device and the second transistor are arranged side by side. While forming the first transistor based on the first fin structure, the method further includes: forming an isolation device based on the first fin structure located in the lateral diffusion region and the first planar block structure; While forming the second transistor based on the second fin structure, the method further includes: forming the lateral diffusion device based on the second fin structure and the second planar block structure located in the lateral diffusion region; the isolation device and the lateral diffusion device are stacked along the first direction.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method described in any one of claims 1 to 7, wherein the semiconductor structure comprises: Core components; the core components include a first transistor and a second transistor stacked along the first direction; Lateral diffusion device; the lateral diffusion device is arranged side by side with the first transistor or side by side with the second transistor; An isolation device; the isolation device and the lateral diffusion device are stacked in the first direction, and the isolation device is arranged side by side with the second transistor or side by side with the first transistor; The lateral diffusion device includes a fin structure and a planar block structure. The fin structure is formed by etching the P-type well region in the lateral diffusion device, and the planar block structure is the N-type drift region in the lateral diffusion device.

9. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

Images