Semiconductor device with epitaxial source / drain region with bottom dielectric

Abstract

The invention relates to a semiconductor device having an epitaxial source / drain region with a bottom dielectric. Embodiments of the present disclosure provide a gate all around FET device including a patterned or reduced bottom dielectric layer. The bottom dielectric layer prevents volume loss of the subsequently formed epitaxial source / drain region and induces compressive stress in the channel region to prevent stress loss and channel resistance degradation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device having an epitaxial source / drain region with a bottom dielectric and a method for manufacturing the same. Background Art

[0002] The semiconductor industry has experienced continued rapid growth due to the continuous improvement in the integration density of various electronic components. In large part, this improvement in integration density comes from the repeated reduction in minimum feature size, which allows more components to be integrated into a given chip area. As the minimum feature size decreases, side effects such as leakage, parasitic devices, resistance degradation, etc. may occur. Therefore, there is a need to solve the above problems. Summary of the invention

[0003] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor channel disposed above a top surface of a semiconductor substrate; an epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region comprises a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate; and a bottom dielectric layer in contact with the bottom surface of the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the bottom surface extending below the top surface of the semiconductor substrate.

[0004] According to one aspect of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; two or more semiconductor channel layers vertically stacked above the top surface of the semiconductor substrate; two or more internal spacers, alternately stacked with the two or more semiconductor channel layers; and an epitaxial source / drain region, comprising: a first epitaxial source / drain layer and a semiconductor surface, the first epitaxial source / drain layer grown from the two or more semiconductor channel layers, the semiconductor surface being arranged below the top surface of the semiconductor substrate; and a main epitaxial source / drain layer grown from the first epitaxial source / drain layer.

[0005] According to one aspect of the present disclosure, a method is provided, comprising: forming a semiconductor fin on a top surface of a semiconductor substrate, wherein the semiconductor fin comprises a first semiconductor layer and a second semiconductor layer arranged alternately; forming a recess passing through the semiconductor fin and entering the semiconductor substrate; forming a bottom dielectric layer in the recess, wherein the bottom dielectric layer partially covers a semiconductor surface below the top surface of the semiconductor substrate; and growing an epitaxial source / drain region on top of the bottom dielectric layer, wherein the epitaxial source / drain region contacts a portion of the semiconductor surface below the top surface of the semiconductor substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features may be arbitrarily increased or reduced.

[0007] Figures 1A to 1K A semiconductor device according to an embodiment of the present disclosure is schematically illustrated.

[0008] Figure 2 is a flow chart of a method for manufacturing a semiconductor substrate according to an embodiment of the present disclosure.

[0009] FIG. 3A to FIG. 3R Various stages of manufacturing a semiconductor device according to an embodiment of the present disclosure are schematically illustrated.

[0010] FIG. 4A to FIG. 4L Structural details of a semiconductor device according to an embodiment of the present disclosure are schematically shown.

[0011] FIG. 5A to FIG. 5L Structural details of a semiconductor device according to an embodiment of the present disclosure are schematically shown. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms (e.g., "below," "lower," "above," "over," "top," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0014] The foregoing generally summarizes some aspects of the embodiments described in the present disclosure. Although some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and / or other devices, such as planar FETs, fin FETs, horizontal all-around gate (HGAA) FETs, vertical all-around gate (VGAA) FETs, and other suitable devices. A person of ordinary skill in the art will readily appreciate that other modifications that may be made are considered within the scope of the present disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than described herein. In the present disclosure, source / drain regions refer to source and / or drain. Source and drain may be used interchangeably.

[0015] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, the double patterning process or multi-patterning process combines a photolithography process with a self-alignment process, thereby allowing the creation of patterns with a pitch that is smaller than that obtainable using a single direct photolithography process, for example.

[0016] Embodiments of the present disclosure relate to a device including a device having a reduced channel resistance (R ch ) of a semiconductor device having a nanosheet channel region. In particular, embodiments of the present disclosure provide a GAA semiconductor device with reduced channel resistance for source / drain epitaxial regions in a P-type FET. In particular, embodiments of the present disclosure provide a GAA device formed from a semiconductor stack, the semiconductor stack including a bottom dielectric film at the bottom surface of the source / drain region to prevent leakage current through parasitic devices. In some embodiments, the bottom dielectric film may be patterned or otherwise shaped to allow the source / drain region to grow below the lowermost layer of the semiconductor stack. Embodiments of the present disclosure provide improvements in AC performance and avoid R ch Severe DC performance loss due to degradation. For example, by patterning or shaping the bottom dielectric layer, the volume of the subsequently formed epitaxial source / drain regions is not lost, and compressive stress can be induced in the channel region to prevent stress loss and R ch Degeneration.

[0017] Figures 1A to 1E A semiconductor device 10 according to an embodiment of the present disclosure is schematically illustrated. Figures 1A to 1C is a cross-sectional view of a semiconductor device 10 according to the present disclosure. Figure 1A The semiconductor device 10 is Figure 1B Cross-sectional view along line 1A-1A in FIG. Figure 1B The semiconductor device 10 is Figure 1A Cross-sectional view along line 1B-1B in FIG. Figure 1C The semiconductor device 10 is Figure 1A Partial cross-sectional view along line 1C-1C in FIG.

[0018] The semiconductor device 10 is a GAA device including a semiconductor channel 16 formed between epitaxial source / drain regions 40. A gate structure 50 is formed over and around the semiconductor channel 16. The semiconductor device 10 is formed by patterning a semiconductor stack 18 on a substrate 12 into a semiconductor fin 20, forming a sacrificial gate structure over the semiconductor fin 20, recessing the semiconductor fin 20 outside the sacrificial gate structure to form the epitaxial source / drain regions 40, and replacing the sacrificial gate structure with the gate structure 50.

[0019] In some embodiments, the semiconductor device 10 includes a bottom dielectric layer 38 disposed between the epitaxial source / drain regions 40 and the bottom epitaxial layer 36. The bottom dielectric layer 38 provides isolation between the epitaxial source / drain regions 40 and the mesa regions 12M of the semiconductor substrate 12. The bottom epitaxial layer 36 may be an epitaxial semiconductor layer formed in a recess in the semiconductor substrate 12 between the mesa regions 12M. The bottom epitaxial layer 36 is formed in the space between the semiconductor fins 20. Figure 1B As shown, the bottom epitaxial layer 36 contacts the shallow trench isolation layer 22 and / or the sidewall spacer 30. In some embodiments, the bottom epitaxial layer 36 is an epitaxial semiconductor material formed from the semiconductor substrate 12. The bottom epitaxial layer 36 can be a transition layer between the crystal structure of the semiconductor substrate 12 and the epitaxial source / drain region 40. In some embodiments, the bottom epitaxial layer 36 can be used as an alignment feature for forming back source / drain contacts.

[0020] A bottom dielectric layer 38 is formed on and partially covers the bottom epitaxial layer 36. In some embodiments, an opening 39 is formed through the bottom dielectric layer 38, thereby exposing a portion of the bottom epitaxial layer 36. As a result, the bottom epitaxial layer 36, together with the semiconductor channel layer 16, serves as a seed layer for growing epitaxial source / drain regions 40. Figure 1A As shown, a semiconductor stack 18 is formed on a top surface 12f of a semiconductor substrate 12. The top surface 12f may also be referred to as a bottom. Because the epitaxial source / drain region 40 is formed from a portion of the bottom epitaxial layer 36, the epitaxial source / drain region 40 extends below the top surface 12f or bottom. In some embodiments, the bottom epitaxial layer 36 may be omitted, and a bottom dielectric layer 38 may be formed directly in a recess on the semiconductor substrate 12.

[0021] The epitaxial source / drain region 40 is formed to be in physical contact with the semiconductor channel layer 16. Using a portion of the bottom semiconductor layer 36 as a seed layer to grow the epitaxial source / drain region 40 increases the volume of the source / drain region 40. The increased volume of the epitaxial source / drain region 40 increases the compressive force F on the semiconductor channel layer 16. The increased compressive force F causes compressive stress in the semiconductor channel layer 16, thereby increasing the mobility of the channel region. The semiconductor channel 16 is separated by an internal spacer 32 and surrounded by a replacement gate 50. The replacement gate 50 can be a gate stack including an interface layer, a gate dielectric layer and an agate electrode layer. The gate electrode layer can also include one or more work function layers and one or more metal filling layers. A sidewall spacer 30 is set between the epitaxial source / drain region 40 and the gate structure 50.

[0022] The semiconductor device 10 may further include a source / drain contact 52 disposed on the epitaxial source / drain region 40. A silicide layer 54 may be formed between the source / drain contact 52 and the epitaxial source / drain region 40 to facilitate electrical connection therebetween. A contact etch stop layer (CESL) 42 is deposited over the epitaxial source / drain region 40 to protect the epitaxial source / drain region 40 during formation. An interlayer dielectric (ILD) 44 is deposited over the CESL 42 to provide electrical isolation to the S / D contacts 52 and the epitaxial source / drain region 40.

[0023] During operation, when a gate bias greater than a threshold voltage is applied to the gate structure 50, a conductive channel is formed in the semiconductor channel layer 16. If an appropriate bias is applied to the epitaxial source / drain regions 40 via the source / drain contacts 52, current flows between the epitaxial source / drain regions 40 through the channel formed in the semiconductor channel layer 16. During the above-mentioned operating conditions, a portion of the gate structure 50 closest to the mesa region 12M may form a parasitic FET. If the epitaxial source / drain regions 40 are in physical contact with the mesa region 12M, an undesirable leakage current may flow between the epitaxial source / drain regions 40 via the mesa portion 12M. The bottom dielectric layer 38 in the semiconductor device 10 provides sufficient electrical isolation and leakage current suppression from the epitaxial source / drain regions 40.

[0024] In some embodiments, the semiconductor device 10 is formed on a bulk semiconductor substrate 12, for example, different from an SOI substrate. In some embodiments, the semiconductor substrate 12 includes crystalline silicon (Si) or another basic semiconductor, such as germanium (Ge). Alternatively, the semiconductor substrate 12 may include (i) a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (ii) an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or (iv) a combination thereof.

[0025] The semiconductor stack 18 may include semiconductor channel layers 16 arranged alternately with sacrificial semiconductor layers (not shown). In some embodiments, the number of semiconductor channel layers 16 is between 1 and 6. The semiconductor channel layers 16 may be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor channel layers 16 may include the same material as the substrate 10. In some embodiments, the semiconductor channel layers 16 may include a different material from the substrate 10. In some embodiments, the semiconductor channel layers 16 and the sacrificial semiconductor layers are made of materials having different lattice constants. In some embodiments, the sacrificial semiconductor layers include epitaxially grown silicon germanium (SiGe) layers, and the semiconductor channel layers 16 include epitaxially grown silicon (Si) layers. Alternatively, in some embodiments, either the semiconductor channel layer 16 and the sacrificial layer may include other materials, such as Ge, compound semiconductors (e.g., SiC, GeAs, GaP, InP, InAs and / or InSb), alloy semiconductors (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof.

[0026] In some embodiments, each semiconductor channel layer 16 has a channel height H in the range between about 5 nm and about 15 nm along the z-direction. 16 In some embodiments, the semiconductor channel layer 16 in the semiconductor stack 18 has a channel height H 16 In some embodiments, the semiconductor channel layer 16 in the semiconductor stack 18 has a channel height H 16 In some embodiments, the semiconductor channel layer 16 has a channel width W in the y direction in a range between about 6 nm and about 80 nm. 16In some embodiments, the fin 20 or the epitaxial source / drain regions 40 have a spacing S40 in the y-direction in a range between about 6 nm and about 115 nm.

[0027] In some embodiments, for p-type devices, the epitaxial source / drain regions 40 may include boron-doped (B-doped) silicon germanium (SiGe), B-doped germanium (Ge), B-doped germanium tin (GeSn), or a combination thereof. In some embodiments, for n-type devices, the epitaxial source / drain regions 40 may include arsenic (As) or phosphorus (P)-doped silicon (Si), carbon-doped silicon (Si:C), or a combination thereof. In some embodiments, the epitaxial source / drain regions 40 may include two or more epitaxially grown layers, which will be discussed later, but for simplicity, are described in detail below. Figures 1A to 1C In some embodiments, epitaxial source / drain regions 40 are grown from exposed sidewall surfaces of semiconductor channel layer 16 and exposed portions of bottom epitaxial layer 36 .

[0028] In some embodiments, the epitaxial source / drain regions 40 have a width W in the x-direction in a range between about 9 nm and about 32 nm. 40 In some embodiments, the epitaxial source / drain regions 40 have a height H in the z-direction in a range between about 20 nm and about 105 nm. 40 Because the bottom portion of the epitaxial source / drain region 40 is grown from the bottom epitaxial layer 36, the height H 40 The bottom epitaxial layer 36 is located below the top surface 12f of the mesa portion 12M or the bottom of the semiconductor stack 18. In some embodiments, the epitaxial source / drain region 40 is lowered by a distance D 40 (which is defined by the distance between the top surface 12f of the mesa portion 12M and the bottom surface 40b of the epitaxial source / drain region 40) is in the range between 0 nm and about 80 nm.

[0029] In some embodiments, the bottom epitaxial layer 36 is an undoped semiconductor layer. For example, the bottom epitaxial layer 36 may include Si x Ge 1-x , where x is in the range between 0.1 and 1. In some embodiments, the bottom epitaxial layer 36 has a height H in the z direction in the range between about 0 nm and about 50 nm. 36 In some embodiments, the depth D of the bottom epitaxial layer 36 is 36 The distance between the top surface 12f of the mesa portion 12M and the bottom surface 36b of the bottom epitaxial layer 36 along the z-direction is in the range between about 3 nm and about 50 nm.

[0030] In some embodiments, bottom dielectric layer 38 may include any suitable dielectric material, such as an oxide (e.g., silicon oxide, germanium oxide), a nitride (e.g., silicon nitride), a carbide, or other suitable dielectric material. In some embodiments, bottom dielectric layer 38 may include one or more dielectric materials having a resistivity greater than about 1×10 10 In some embodiments, the bottom dielectric layer 38 has a thickness H in the z direction ranging between 0 nm and about 30 nm. 38 For example, the bottom dielectric layer 38 may have a thickness H between about 10 nm and about 20 nm. 38 .

[0031] The bottom dielectric layer 38 may be formed at a level close to the top surface 12f of the mesa portion 12M. Depending on the design, the top surface 38f of the bottom dielectric layer 38 may be formed below or above the top surface 12f of the mesa portion 12M. In some embodiments, the bottom dielectric layer 38 is lowered by a distance D 38 The positive drop distance D is defined by the distance between the top surface 12f of the mesa portion 12M and the lowest point of the bottom dielectric layer 38, and is in the range between -15 nm and about 15 nm. 38 = 1. The negative drop distance D indicates that the entire bottom dielectric layer 38 is above the top surface 12f of the mesa portion 12M. 38 The bottom surface 38b of the bottom dielectric layer 38 is shown below the top surface 12f of the mesa portion 12M. Figure 1A to Figure 1B shown.

[0032] exist Figure 1A and Figure 1B In the embodiment, the bottom dielectric layer 38 has a negative drop distance D 38 As a result, the mesa portion 12M is not exposed to the epitaxial source / drain region 40. The epitaxial source / drain region 40 in the semiconductor device 10 is partially electrically decoupled from the bottom epitaxial layer 36 and the mesa region 12M.

[0033] An opening 39 is formed through the bottom dielectric layer 38 to expose a portion of the bottom epitaxial layer 36 for the epitaxial source / drain region 40 to grow from an area below the top surface 12f of the mesa portion 12M. In some embodiments, the opening 39 is formed by patterning. The position and size of the opening 39 can be determined according to the circuit design. For example, the size and position of the opening 39 can be designed to achieve the shape and volume required for the initial growth of the epitaxial source / drain region 40.

[0034] Figure 1C The shape and position of the opening 39 according to one embodiment of the present disclosure are schematically shown. Figure 1CIn the embodiment of the present invention, an opening 39 is formed near the central region of the bottom dielectric layer 38. In some embodiments, the opening 39 may have a width W in the x-direction in a range between 0 nm and about 30 nm. 39 , and may have a length L in the y direction in a range between 0 nm and about 30 nm 39 In some embodiments, the opening 39 may be substantially circular. In other embodiments, the opening 39 may have a square shape and a shape that is symmetrical along the x-direction and the y-direction.

[0035] Alternatively, the opening 39 may have other shapes, such as a rectangular or asymmetrical shape. Figure 1D and Figure 1E Two alternative embodiments are schematically shown. Figure 1D In the embodiment, a rectangular opening 39 is formed through the bottom dielectric layer 38'. Figure 1D In the embodiment, the bottom dielectric layer 38' is still a continuous film. Figure 1E In the embodiment, a groove 39 is formed through the bottom dielectric layer 38''. The groove 39'' divides the bottom dielectric layer 38'' into two separate parts. Figure 1E , the bottom dielectric layer 38" is not a continuous film.

[0036] As described above, the gate structure 50 occupies the space between and above the semiconductor channel layers 16. The gate structure 50 may extend above the topmost semiconductor channel layer 16tm to a height H 50 The gate structure 50 may include an interface layer, a gate dielectric layer, and a gate electrode layer.

[0037] In some embodiments, the gate structure 50 occupies the middle portion of the semiconductor channel layer 16. The edge portion of the semiconductor channel layer 16 is covered by the inner spacer 32. The gate sidewall spacer 30 is disposed on both sides of the gate structure 50 (except between the semiconductor channel layers 16). In some embodiments, the height H of the gate structure 50 along the y direction is 100 Å. 50 In some embodiments, the sidewall spacers 30 and the inner spacers 32 may include nitrides such as silicon nitride (Si3N4 or "SiN"), silicon carbonitride (SiCN), and silicon carbon oxynitride (SiCON). In some embodiments, the width W of the sidewall spacers 30 along the x-direction is 30 In some embodiments, the width W of the inner spacer 32 along the x direction is about 100 nm. 32 Inner spacers 32 are inserted between the gate structure 50 and the epitaxial source / drain regions 40 to electrically isolate the gate structure 50 from the epitaxial source / drain regions 40 .

[0038] The silicide layer 54 inserted between the source / drain contact 52 and the epitaxial source / drain region 40 may include titanium silicide (TiSi), nickel silicide (NiSi), cobalt silicide (CoSi), platinum silicide (PtSi), or a suitable silicide material. As an example and not limitation, each silicide layer 54 may have a thickness between about 4 nm and about 8 nm. In some embodiments, the silicide layer reduces the contact resistance between the source / drain contact 52 and the epitaxial source / drain region 40.

[0039] In some embodiments, the ILD layer 44 includes one or more layers of dielectric material. In some embodiments, the ILD layer 44 is a silicon oxide-based dielectric with nitrogen, hydrogen, carbon, or a combination thereof. According to some embodiments, the ILD layer 44 provides electrical isolation and structural support for the gate structure 50, the source / drain contacts 52, and the epitaxial source / drain regions 40.

[0040] Figure 1F to Figure 1G A semiconductor device 10 ′ according to an embodiment of the present disclosure is schematically illustrated. Figure 1F to Figure 1G is a cross-sectional view of a semiconductor device 10 ′ according to the present disclosure. Figure 1F The semiconductor device 10' is Figure 1G Cross-sectional view along line 1F-1F in FIG. Figure 1G The semiconductor device 10' is Figure 1F Cross-sectional view along line 1G-1G in FIG.

[0041] The semiconductor device 10' is similar to the semiconductor device 10, except that the semiconductor device 10' includes a bottom dielectric layer 38a formed below the top surface 12f of the mesa portion 12M. In some embodiments, the bottom dielectric layer 38a is a continuous film deposited on the bottom epitaxial layer 36a. In some embodiments, the bottom dielectric layer 38a covers the top surface of the bottom epitaxial layer 36a. The mesa sidewall 12s of the mesa portion 12M is not covered by the bottom dielectric layer 36a. That is, the bottom dielectric layer 38a partially covers the semiconductor surface located below the top surface 12f in the recess 34, which includes the top surface 36t of the bottom epitaxial layer 36 and the sidewall 12s of the mesa region 12M. As a result, the mesa sidewall 12s also serves as a seed layer during the formation of the epitaxial source / drain region 40a. In some embodiments, the depression distance D of the epitaxial source / drain region 40a is 40a The bottom dielectric layer 38a has a negative step-down distance D 38As a result, the mesa portion 12M is exposed to the epitaxial source / drain region 40. The epitaxial source / drain region 40a in the semiconductor device 10' is partially electrically decoupled from the bottom epitaxial layer 36a and the mesa region 12M.

[0042] Figures 1H to 1K A semiconductor device 10 ″ according to an embodiment of the present disclosure is schematically shown. Figure 1H is a cross-sectional view of a semiconductor device 10 ″. Fig. 1I is a semiconductor device 10" along Figure 1H Partial cross-sectional view along line 1I-1I in FIG.

[0043] Semiconductor device 10″ is similar to semiconductor device 10, except that semiconductor device 10″ includes an air gap 60 disposed between bottom dielectric layer 38 and epitaxial source / drain regions 40. In some embodiments, air gap 60 may be open to inner spacer 32. Air gap 60 may be the result of a merger of an epitaxial portion grown from semiconductor channel layer 16 and an epitaxial portion grown from bottom epitaxial layer 36. In some embodiments, air gap 60 may be designed to increase isolation around epitaxial source / drain regions 40. Fig. 1I As shown, the air gap 60 may extend along the y-direction.

[0044] Figure 1J and Figure 1K Two alternative embodiments with a rectangular opening and a slotted opening are schematically shown. Figure 1J In FIG. 3 , an air gap 60 is formed through the bottom dielectric layer 38 ′ near the rectangular opening 39 ′. Figure 1K In the embodiment of the present invention, an air gap 60 is formed through the bottom dielectric layer 38" near the groove 39".

[0045] Figure 2 is a flow chart of a method 100 for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 3A to FIG. 3R Schematically illustrates various stages of manufacturing a semiconductor device 200 according to an embodiment of the present disclosure. The semiconductor device 200 is similar to the semiconductor device 10 and the semiconductor device 10a. Alternatively, the method 100 may be used to manufacture the semiconductor device 10 and the semiconductor device 10a.

[0046] The method 100 begins at operation 102 where a plurality of semiconductor fins 220 are formed over a substrate 210, such as Figure 3AAs shown. A substrate 210 is provided to form a semiconductor device 200 thereon. The substrate 210 may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Depending on the circuit design, the substrate 210 may include various doping configurations. For example, different doping profiles (e.g., n-well, p-well) may be formed in the substrate 210 in regions designed for different device types (e.g., n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs)). In some embodiments, the substrate 210 may be a silicon-on-insulator (SOI) substrate including an insulator structure (not shown) for enhancement.

[0047] The substrate 210 has a front surface 210f. A semiconductor stack 218 is then formed over the front surface 210f of the substrate 210. The semiconductor stack includes alternating semiconductor layers made of different materials to facilitate the formation of a nanosheet channel in a multi-gate device (e.g., a nanosheet channel FET). In some embodiments, the semiconductor stack includes a first semiconductor layer 214 inserted by a second semiconductor layer 216. The first semiconductor layer 214 and the second semiconductor layer 216 have different oxidation rates and / or etching selectivities. In some embodiments, the front surface 210f of the substrate 210 may have a (100) orientation or a (110) orientation. The orientation of the front surface 210f determines the orientation of the layers in the semiconductor stack 218 and epitaxial features, such as epitaxial source / drain regions formed from the semiconductor channel layer in the semiconductor stack 218.

[0048] In a subsequent manufacturing stage, portions of the second semiconductor layer 216 form nanosheet channels in a multi-gate device. Figure 3A As an example, three first semiconductor layers 214 and three second semiconductor layers 216 are arranged alternately. More or fewer semiconductor layers 214 and semiconductor layers 216 may be included in the semiconductor stack, depending on the number of channels desired in the semiconductor device to be formed. In some embodiments, the number of semiconductor layers 216 is between 1 and 6.

[0049] The semiconductor layer 214 and the semiconductor layer 216 may be formed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the semiconductor layer 216 includes the same material as the substrate 210. In some embodiments, the semiconductor layer 214 and the semiconductor layer 216 include a material different from the substrate 210. In some embodiments, the semiconductor layer 214 and the semiconductor layer 216 are made of materials with different lattice constants. In some embodiments, the first semiconductor layer 214 includes an epitaxially grown silicon germanium (SiGe) layer, and the second semiconductor layer 216 includes an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the semiconductor layer 214 and the semiconductor layer 216 may include other materials, such as Ge, a compound semiconductor (e.g., SiC, GeAs, GaP, InP, InAs, and / or InSb), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof.

[0050] The first semiconductor layer 214 in the channel region can be eventually removed and used to define the vertical distance between adjacent channels of the subsequently formed multi-gate device. In some embodiments, the thickness of the first semiconductor layer 214 is equal to or greater than the thickness of the second semiconductor layer 216. In some embodiments, each semiconductor layer 214 has a thickness in a range between about 3 nm and about 15 nm. In some embodiments, each second semiconductor layer 216 has a thickness in a range between about 3 nm and about 15 nm. In some embodiments, the thickness of the second semiconductor layer 216 in the semiconductor stack is uniform.

[0051] The semiconductor fins 220 are formed from a portion of the substrate 210 and the semiconductor stack. The semiconductor fins 220 may be formed by patterning a hard mask (not shown) formed on the semiconductor stack and one or more etching processes. Each semiconductor fin 220 has a channel portion 218 formed from the semiconductor layer 214, the semiconductor layer 216, and a well portion 212 formed from the substrate 210. The semiconductor fins 220 are formed along the X direction.

[0052] An isolation layer (not shown, but similar to Figure 1BThe isolation layer 22 in the substrate 210 is formed to cover the well portion 212 of the semiconductor fin 220. The isolation layer can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 222 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or a combination thereof. In some embodiments, an insulating layer is formed by a suitable deposition process (e.g., atomic layer deposition (ALD)) to cover the semiconductor fin 220, and then recessed etching is performed using a suitable anisotropic etching process to expose the channel portion 218 of the semiconductor fin 220.

[0053] In operation 104, a sacrificial gate structure 228 and a spacer layer 230 are then formed over the semiconductor fin 220, such as Figure 3A As shown. A sacrificial gate dielectric layer 224 is deposited over the exposed surface of the semiconductor device 200. The sacrificial gate dielectric layer 224 may be conformally formed over the semiconductor fins 220 and the isolation layer 222. In some embodiments, the sacrificial gate dielectric layer 224 may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable processes. The sacrificial gate dielectric layer 224 may include one or more layers of dielectric material, such as SiO2, SiN, a high-k dielectric material, and / or other suitable dielectric materials.

[0054] A sacrificial gate electrode layer 226 is deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 may be blanket deposited over the sacrificial gate dielectric layer 224. The sacrificial gate electrode layer 226 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the sacrificial gate electrode layer 226 is planarized. The sacrificial gate electrode layer 226 may be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes. A patterning operation is performed over the sacrificial gate dielectric layer 224 and the sacrificial gate electrode layer 226 to form a sacrificial gate structure 228, which covers a portion of the semiconductor fin 220 designed as a channel region.

[0055] A gate sidewall spacer 230 is then formed on the sidewalls of each sacrificial gate structure 228. After forming the sacrificial gate structure 228, the gate sidewall spacer 230 may be formed by blanket deposition of an insulating material followed by anisotropic etching to remove the insulating material from horizontal surfaces. The gate sidewall spacer 230 may have a thickness in a range between about 3 nm and about 8 nm. In some embodiments, the insulating material of the gate sidewall spacer 230 is a silicon nitride-based material such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. Figure 3A In the embodiment, the gate sidewall spacer 230 includes two layers. In other embodiments, the gate sidewall spacer 230 can be formed from fewer or more layers of dielectric material.

[0056] In operation 106, the semiconductor fins 220 on opposite sides of the sacrificial gate structures 228 are recessed etched to form source / drain recesses 234 between adjacent sacrificial gate structures 228, as shown in FIG. Figure 3B As shown. The first semiconductor layer 214 and the second semiconductor layer 216 in the semiconductor fin 220 are etched down on both sides of the sacrificial gate structure 228 using an etching operation. In some embodiments, all layers in the semiconductor stack of the semiconductor fin 220 and a portion of the well portion 212 of the semiconductor fin 220 are etched. In some embodiments, the first semiconductor layer 214, the second semiconductor layer 216, and the substrate 210 may be removed using appropriate dry etching and / or wet etching.

[0057] In some embodiments, the source / drain recess 234 is a deep trench formed below the top surface 210f of the substrate 210. In some embodiments, the source / drain recess 234 has a drop distance D 234 , the descending distance D 234 The distance D is defined by the distance between the top surface 210f of the substrate 210 and the bottom of the sheet to the bottom 234b of the source / drain recess 234. In some embodiments, the descending distance D 234 In the range between about 3 nm and about 50 nm.

[0058] In operation 108, an inner spacer 232 is formed on the exposed end of the first semiconductor layer 214 below the sacrificial gate structure 228, such as Figures 3C to 3E As shown. Figure 3CAs shown, the first semiconductor layer 214 exposed to the source / drain recess 234 is first horizontally etched along the X direction to form a spacer cavity. In some embodiments, the first semiconductor layer 214 can be selectively etched by using a wet etchant (for example, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution). In some embodiments, the etching amount of the first semiconductor layer 214 along the X direction is in a range between about 5 nm and about 10 nm.

[0059] After forming the spacer cavities at opposite ends of the first semiconductor layer 214, inner spacers 232 may be formed in the spacer cavities by conformally depositing an insulating layer, such as Figure 3D Then, the insulating layer is partially removed to form the inner spacer 232, as shown in FIG. Figure 3E As shown. The insulating layer may be formed by ALD or any other suitable method. A subsequent etching process removes most of the insulating layer (except for the portion located inside the cavity), resulting in an internal spacer 232. The internal spacer 232 includes two or more segments alternately stacked with the second semiconductor layer 216.

[0060] The inner spacer 232 may be formed from a single layer or multiple layers of dielectric material. In some embodiments, the inner spacer 232 may include one of silicon nitride (SiN) and silicon oxide (SiO2), SiONC, or a combination thereof. The inner spacer 232 may have a thickness in the range of about 5 nm to about 10 nm along the X direction.

[0061] In operation 110, a bottom epitaxial layer 236 is formed at the bottom of the source / drain recess 234, such as Figure 3F As shown. In some embodiments, the bottom epitaxial layer 236 fills the lower portion of the source / drain recess 234 to a level lower than the bottommost semiconductor layer 216L or the bottommost channel region. In some embodiments, the bottom epitaxial layer 236 fills the source / drain recess 234 to a level lower than the bottommost internal spacer 232L. In some embodiments, the front surface 236f may be at a level lower than the bottommost internal spacer 232L. In some embodiments, the front surface 236f is located below the top surface 210f of the substrate 210, and after the bottom epitaxial layer 236 is formed, a portion of the mesa sidewall 212s is exposed to the source / drain recess 234.

[0062] The material and shape of the bottom epitaxial layer 236 can be selected to achieve one or more purposes. For example, the bottom epitaxial layer 236 can provide a crystal transition from the substrate 210 to the subsequently formed source / drain region with improved adhesion. The bottom epitaxial layer 236 can define the bottom profile and crystal orientation of the subsequently formed source / drain region. In some embodiments, the bottom epitaxial layer 236 can also be used as an alignment feature for the back source / drain contact.

[0063] In some embodiments, the bottom epitaxial layer 236 can be formed from a material having an etch selectivity to the material of the substrate 210 (e.g., the material in the well portion 212 of the semiconductor fin 220). In some embodiments, the bottom epitaxial layer 236 can also have an etch selectivity to the insulating material in the isolation layer. In some embodiments, the bottom epitaxial layer 236 is formed from a semiconductor material having a high etch selectivity to Si. For example, the bottom epitaxial layer 236 is formed from SiGe.

[0064] The bottom epitaxial layer 236 may be formed by any suitable method, such as by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique. In some embodiments, the bottom epitaxial layer 236 is formed from undoped SiGe. In some embodiments, the bottom epitaxial layer 236 is formed from undoped SiGe including a Ge atomic concentration in a range between about 10% and about 100%. Alternatively, the bottom epitaxial layer 236 may include other materials, such as Ge, a compound semiconductor (e.g., SiC, GeAs, GaP, InP, InAs, and / or InSb), an alloy semiconductor (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof.

[0065] In operation 112, a bottom dielectric layer 238 is formed over the bottom epitaxial layer 236, such as Figure 3G to Figure 3H As shown. A bottom dielectric layer 238 is formed on the front surface 236f of the bottom epitaxial layer 236. The bottom dielectric layer 238 may also cover the exposed surface of the isolation layer. The bottom dielectric layer 238 may include one or more layers of dielectric material. During operation, the bottom dielectric layer 238 may provide electrical isolation between the well portion 212 and the source / drain region of the substrate 210.

[0066] The bottom dielectric layer 238 may be formed by a directional deposition process with bottom-up sidewall growth selectivity. For example, the bottom dielectric layer 238 may be formed by a directional PECVD process. In some embodiments, the bottom dielectric layer 238 may be formed by depositing a conformal dielectric layer, such as Figure 3GAs shown, the conformal dielectric layer is then selectively removed from the vertical and outer surfaces, leaving a portion on the bottom of the source / drain recess 234, as shown in FIG. Figure 3H In some embodiments, the bottom dielectric layer 238 may be formed from any suitable dielectric material, such as a silicon nitride-containing material (eg, SiN, SiON, SiOCN, SiOC, SiCN), a metal oxide (eg, AlOx, HfOx), or a combination thereof.

[0067] In some embodiments, the bottom dielectric layer 238 covers the top surface 236f of the bottom epitaxial layer 236. The vertical position of the bottom dielectric layer 238 depends on the shape and position of the bottom epitaxial layer 236. The bottom dielectric layer 238 can have a thickness above the bottom epitaxial layer 236. In some embodiments, the thickness is in a range between about 0 nm and about 30 nm. In some embodiments, the top surface 238t of the bottom dielectric layer 238 can intersect the bottommost inner spacer 232L so that the bottom dielectric layer 238 covers the well portion 212 of the substrate 210 while leaving the bottommost semiconductor layer 216 exposed. In other embodiments, as Fig. 3I As shown, the top surface 238t of the bottom dielectric layer 238 is below the top surface 210f of the substrate 210, so that a portion of the sidewall 212s remains exposed to the source / drain recess 234. The shape and position of the bottom dielectric layer 238 may vary depending on the design.

[0068] In operation 114, an opening 239 is formed through the bottom dielectric layer 238 to expose a portion of the bottom epitaxial layer 236, such as FIG. 3I to FIG. 3J Operation 114 may be omitted, depending on the design of the device. An opening 239 is formed so that a portion of the bottom epitaxial layer 236 may be used as a seed layer during the epitaxial growth of the source / drain regions.

[0069] In some embodiments, the opening 239 may be formed by forming a pattern using photolithography techniques and etching through the pattern using a suitable etching process. In other embodiments, the opening 239 may be formed by directional etching.

[0070] Figure 3J yes Figure 3H A partial enlarged view of area 3J in the middle. Figure 3J As shown, the opening 239 exposes a portion of the top surface 236t of the bottom epitaxial layer 236 to the source / drain recess 234. During subsequent epitaxial growth, the epitaxial layer can grow from the top surface 236t and fill the opening 239. Figure 3HIn the example, both sidewall portions of the sidewall 212s are also exposed to the source / drain recess 234, and epitaxial features can also grow from the sidewall 212s. After operation 114, the bottom dielectric layer 238 partially covers the semiconductor surface below the top surface 210f.

[0071] In operation 116, an optional channel-drive process is performed to etch back the edge region of the semiconductor layer 216 and the sidewall 212s of the well portion 212, such as Figure 3K to Figure 3L As shown. In some embodiments, the semiconductor layer 216 exposed to the source / drain recess 234 is horizontally etched along the x-direction to form a push-in cavity 216C. In some embodiments, the semiconductor layer 216 can be selectively etched by using a wet etchant (for example, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution). The push-in cavity 216C is formed under the sidewall spacer 230 and between the inner spacers 232. In some embodiments, the etching amount of the semiconductor layer 216 along the x-direction is in a range between about 1 nm and about 6 nm. In some embodiments, the semiconductor layer 216 is etched back by a certain amount without exposing the first semiconductor layer 216 behind the inner spacer 232.

[0072] In some embodiments, when the sidewall 212s of the well portion 212 is exposed to the source / drain recess 234, a portion of the well portion 212 may also be etched back during the channel driving process to form the well cavity 212C. The well cavity 212C is located below the lowermost inner spacer 232L and above the top surface 238t of the bottom dielectric layer 238.

[0073] Figure 3L yes Figure 3K A partial enlarged view of the middle area 3L. Figure 3L As shown, after the channel driving operation, the sidewall 232s, the top surface 232t and the bottom surface 232b are exposed to the source / drain recess 234. Figure 3L As shown, the cavity 216C may have a width W along the x-direction. 216C Width W 216C The width W may be defined by the distance between the sidewall 216s of the semiconductor layer 216 and the sidewall 232s of the inner spacer 232. In some embodiments, the width W 216C In the range between about 1 nm and about 6 nm.

[0074] The channel-driving operation enlarges the source / drain region recess 234, thereby providing increased volume for subsequently formed source / drain regions. Alternatively, the channel-driving operation may be omitted.

[0075] In operation 118, a first epitaxial source / drain layer 241 is formed in the source / drain region recess 234, such as Figure 3M As shown. In some embodiments, a pre-cleaning process may be performed before the epitaxial growth of the first epitaxial source / drain layer 241. The first epitaxial source / drain layer 241 is formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). The first epitaxial layer 241 is grown from the exposed semiconductor surface (i.e., the sidewall 216s of the semiconductor layer 216 and the top surface 236t of the bottom epitaxial layer 236). The first epitaxial source / drain layer 241 starts from the exposed semiconductor surface as a discrete portion. For example, the first epitaxial source / drain layer 241 includes a channel portion 241C grown from the sidewall 216s of the semiconductor layer 216, a sidewall portion 241S grown from the exposed sidewall, and a bottom portion 241B grown from the bottom epitaxial layer 236 via the opening 239. The channel portion 241C, the sidewall portion 241S and the bottom portion 241B are collectively referred to as the first epitaxial source / drain layer 241.

[0076] The first epitaxial source / drain layer 241 is grown to a desired thickness to achieve high quality crystal growth in the subsequent main epitaxial growth. After operation 118, the channel portion 241C, the sidewall portion 241S, and the bottom portion 241B may remain discrete or merged. For example, in Figure 3M In the embodiment, adjacent channel portions 241C may be merged, or the lowermost channel portion 241C may be merged with the sidewall portion 241S. Alternatively, the bottom portion 241B may be merged with the sidewall portion 241S.

[0077] Because of different surface orientations, materials, and / or locations of corresponding seed layers, the channel portion 241C, the sidewall portion 241S, and the bottom portion 241B may have different physical characteristics, such as thickness, shape, or surface orientation.

[0078] In some embodiments, the channel portion 241C may have a channel thickness t c , channel thickness t c The channel thickness t is defined by the distance from the thickest portion of the channel portion 241C to the sidewall 232s of the inner spacer 232. In some embodiments, the channel thickness t c In some embodiments, when a channel driving operation is performed, the channel portion 241C further includes a driving thickness t PH , advancement thickness t PH The driving thickness t is defined by the distance between the sidewall 232s of the inner spacer 232 and the sidewall 216s of the semiconductor layer 216. In some embodiments, the driving thickness t PHIn some embodiments, the top surface 241Ct of the channel portion 241C may be at an angle θ relative to a horizontal plane. S Angle θ S reflects the surface orientation as a result of the seed layer surface orientation and process parameters. In some embodiments, the angle θ S In the range between about 10° and about 80°.

[0079] In some embodiments, the bottom portion 241B may have a bottom thickness t B , bottom thickness t B The bottom thickness t is defined by the distance from the thickest portion of the bottom portion 241B to the top surface 236t of the bottom epitaxial layer 236. In some embodiments, the bottom thickness t B In some embodiments, the top surface 241Bt of the bottom portion 241B may be at an angle θ relative to the horizontal plane. B Angle θ B reflects the surface orientation as a result of the seed layer surface orientation and process parameters. In some embodiments, the angle θ B In the range between about 10° and about 80°.

[0080] The first epitaxial source / drain layer 241 may include one or more layers of Si, SiP, SiC, and SiCP for NFET or Si, SiGe, Ge for PFET. For PFET, a p-type dopant, such as boron (B), may also be included in the first epitaxial source / drain layer 241. For NFET, an n-type dopant, such as arsenic (As), phosphorus (P), or carbon (C), or a combination thereof, may also be included in the first epitaxial source / drain layer 241.

[0081] In some embodiments, semiconductor device 200 is a p-type device, and first epitaxial source / drain layer 241 includes Si or SiGe with a p-type dopant such as B or Ga. In some embodiments, first epitaxial source / drain layer 241 may be a SiGe layer with a Ge atomic concentration in a range between about 0% and about 40%. In some embodiments, first epitaxial source / drain layer 241 includes a p-type dopant with a concentration between about 1E20 and about 2E21.

[0082] In some embodiments, the first epitaxial source / drain layer 241 may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, the epitaxial deposition process may be performed in a temperature range between about 400° C. and about 750° C. (e.g., between about 520° C. and about 620° C.). In some embodiments, the epitaxial deposition process may be performed at a pressure between about 10 torr and about 300 torr (e.g., between about 20 torr and about 100 torr). In some embodiments, the epitaxial deposition process may use a precursor such as H2SiC l2 (DCS), SiH4, Si2H6, GeH4, GeCl4, HCl, Cl2. In some embodiments, p-type dopant precursors such as B2H6, BCl3, and Ga(CH3)3 may be used during deposition.

[0083] In operation 120, a bulk epitaxial source / drain layer 243 is formed on the first epitaxial source / drain layer 241, such as Figure 3N As shown. The main epitaxial source / drain layer 243 fills the source / drain recess 234. The first epitaxial source / drain layer 241 and the main epitaxial source / drain layer 243 form an epitaxial source / drain region 240. Figure 3N There is only one layer in the bulk epitaxial source / drain layer 243, but the bulk epitaxial source / drain layer 243 may also include two or more layers.

[0084] The bulk epitaxial source / drain layer 243 is epitaxially grown from the first epitaxial source / drain layer 241. The bulk epitaxial source / drain layer 243 has a higher dopant concentration than the first epitaxial source / drain layer 241. In some embodiments, the composition of the bulk epitaxial source / drain layer 243 is also different from that of the first epitaxial source / drain layer 241. The bulk epitaxial source / drain layer 243 and the first epitaxial source / drain layer 241 have different crystal structures. The bulk epitaxial source / drain layer 243 may include one or more layers of Si, SiP, SiC, and SiCP for NFETs or Si, SiGe, Ge for PFETs. For PFETs, p-type dopants, such as boron (B), are also included in the bulk epitaxial source / drain layer 243. For NFETs, n-type dopants, such as arsenic (As), phosphorus (P), or carbon (C), or a combination thereof, are included in the bulk epitaxial source / drain layer 243.

[0085] In some embodiments, semiconductor device 200 is a p-type device, and bulk epitaxial source / drain layer 243 includes Si or SiGe with a p-type dopant such as B or Ga. In some embodiments, bulk epitaxial source / drain layer 243 may be a SiGe layer with a Ge atomic concentration in a range between about 20% and about 70%. In some embodiments, bulk epitaxial source / drain layer 243 includes a p-type dopant in a concentration between about 1E20 and about 3E21.

[0086] In some embodiments, the bulk epitaxial source / drain layer 243 may be formed by an epitaxial growth method using CVD, ALD, or molecular beam epitaxy (MBE). In some embodiments, the epitaxial deposition process may be performed in a temperature range between about 400° C. and about 750° C. (e.g., between about 520° C. and about 620° C.). In some embodiments, the epitaxial deposition process may be performed at a pressure between about 10 torr and about 300 torr (e.g., between about 20 torr and about 100 torr). In some embodiments, the epitaxial deposition process may use a precursor such as H2SiC l2 (DCS), SiH4, Si2H6, GeH4, GeCl4, HCl, Cl2. In some embodiments, p-type dopant precursors such as B2H6, BCl3, and Ga(CH3)3 may be used during deposition.

[0087] like Figure 3N As shown, epitaxial source / drain regions 240 are grown through the topmost semiconductor channel, i.e., the second semiconductor layer 216 under the sacrificial gate structure 228, to contact the gate sidewall spacers 230. The first semiconductor layer 214 under the sacrificial gate structure 228 is separated from the epitaxial source / drain regions 240 by internal spacers 232.

[0088] As the epitaxial source / drain regions 240 are grown from the sidewalls 212s of the well portion 212 and / or the bottom epitaxial layer 236, the epitaxial source / drain regions 240 extend below the top surface 210f of the substrate 210 or extend beyond the lowermost layer in the semiconductor stack 218. The epitaxial source / drain regions 240 are in contact with the bottom dielectric layer 238, which in turn provides isolation between the epitaxial source / drain regions 240 and the well portion 212.

[0089] In operation 122, a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are formed over the exposed surface, such as Fig.3OCESL 242 is formed on the epitaxial source / drain regions 240 and the gate sidewall spacers 230. In some embodiments, CESL 242 has a thickness in a range between about 1 nm and about 15 nm. CESL 242 may include Si3N4, SiON, SiCN, or any other suitable material, and may be formed by CVD, PVD, or ALD.

[0090] An interlayer dielectric (ILD) layer 244 is formed over the contact etch stop layer (CESL) 242. The material of the ILD layer 244 includes a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. An organic material (e.g., a polymer) may be used for the ILD layer 244. After the ILD layer 244 is formed, a planarization operation (e.g., CMP) is performed to expose the sacrificial gate electrode layer 226 for subsequent removal of the sacrificial gate structure 228. During the removal of the sacrificial gate structure 228, the ILD layer 244 protects the epitaxial source / drain region 240.

[0091] In operation 124, a replacement gate structure 250 is formed to replace the sacrificial gate structure 228, such as Figure 3P , Figure 3Q and Figure 3R As shown. First, the sacrificial gate structure 228 is removed. In particular, the sacrificial gate electrode layer 226 and the sacrificial gate dielectric layer 224 are removed in sequence to expose the channel portion 218. The first semiconductor layer 214 and the second semiconductor layer 216 are exposed. The first semiconductor layer 214 is then selectively removed using an etchant having a higher etching rate for the first semiconductor layer 214 than for the second semiconductor layer 216. After the first semiconductor layer 214 is removed, the second semiconductor layer 216 is exposed, resulting in a semiconductor channel region including the second semiconductor layer 216 connected to the epitaxial source / drain region 240.

[0092] A replacement gate structure 250 is then formed around the channel region. A gate dielectric layer 246 is formed around each second semiconductor layer 216, and a gate electrode layer 248 is formed on the gate dielectric layer 246. The gate dielectric layer 246 and the gate electrode layer 248 may be referred to as a replacement gate structure 250.

[0093] The gate dielectric layer 246 may be formed by CVD, ALD, or any suitable method. In one embodiment, the gate dielectric layer 246 is formed using a highly conformal deposition process (e.g., ALD) to ensure that the gate dielectric layer 246 having a uniform thickness is formed around each second semiconductor layer 216. In some embodiments, the thickness of the gate dielectric layer 246 is in a range between about 1 nm and about 6 nm.

[0094] The gate dielectric layer 246 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-k dielectric materials, other suitable dielectric materials and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, other suitable high-K dielectric materials and / or combinations thereof. In some embodiments, an interfacial layer (not shown) is formed between the second semiconductor layer 216 and the gate dielectric layer 246. In some embodiments, one or more work function adjustment layers (not shown) are inserted between the gate dielectric layer 246 and the gate electrode layer 248.

[0095] A gate electrode layer 248 is formed on the gate dielectric layer 246 to surround each of the second semiconductor layer 216 (i.e., each channel) and the gate dielectric layer 246. The gate electrode layer 248 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 248 can be formed by CVD, ALD, electroplating, or other suitable methods.

[0096] After forming the gate electrode layer 248, a planarization process (e.g., a CMP process) is performed to remove excess deposited gate electrode material and expose the top surface of the ILD layer 244. In some embodiments, source / drain contacts 252 are formed in the ILD layer 244. Before forming the front side source / drain contacts 252, contact holes are formed in the ILD layer 244, the CESL 242, and a portion of the epitaxial source / drain region 240.

[0097] After forming the front side source / drain contacts 252, a front side interconnect structure (not shown) is formed by the middle end of the line process. The front side interconnect structure includes a plurality of dielectric layers in which metal lines and vias are formed. The metal lines and vias in the front side interconnect structure may be formed of copper or copper alloy using one or more damascene processes. The front side interconnect structure may include multiple sets of interlayer dielectric (ILD) layers and intermetallic dielectric (IMD) layers.

[0098] Figure 3Q is Figure 3P In the area marked with 3Q Figure 3P A partial enlarged view of . Figure 3R The semiconductor device 200 is along Figure 3P The cross-sectional view of the 3R-3R line in FIG. Figure 3Q and Figure 3PAs shown, the inner spacer 232 contacts the channel portion 241C of the first epitaxial layer 241 at the top surface 232t and the bottom surface 232b. The sidewall 232s of the inner spacer 232 contacts the epitaxial source / drain region 240, which can be the channel portion 241C or the bulk epitaxial source / drain layer 243.

[0099] The bottom dielectric layer (eg, bottom dielectric layer 238) according to the present disclosure may vary in shape and / or position to achieve various design effects. The bottom dielectric layer may be formed at different positions relative to the channel layer and / or have different shapes. FIG. 4A to FIG. 4L Various arrangements of the bottom dielectric layer according to embodiments of the present disclosure are included.

[0100] FIG. 4A to FIG. 4B A semiconductor device 10 a according to the present disclosure is schematically illustrated. Figure 4A is a schematic cross-sectional view of semiconductor device 10 a after operation 114 . Figure 4B is a corresponding top view of the semiconductor device 10a. Figure 4A In the embodiment of the present invention, the bottom epitaxial layer 36 has a substantially flat top surface 36t, resulting in a substantially flat bottom dielectric layer 38. The bottom dielectric layer 38 may have a thickness t in a range between about 1 nm and about 10 nm. DF The bottom dielectric layer 36 may be substantially located near the bottom or top surface 12f of the substrate 12. The relative position between the bottom dielectric layer 38 and the top surface 12f may be determined by the step-down distance h. DF Indicates that the falling distance h DF The lowering distance h is defined by the distance between the bottom surface 38b of the bottom dielectric layer 38 and the bottom or top surface 12f of the sheet. In some embodiments, the lowering distance h DF In the range between about -15 nm and about 15 nm. The positive drop distance h DF The bottom surface 38b of the bottom dielectric layer 38 is above the bottom or top surface 12f of the sheet, and the negative drop distance h DF 38b of the bottom dielectric layer 38 is shown below the bottom or top surface 12f of the sheet. Figure 4A In the middle, the descending distance h DF It is negative.

[0101] The opening 39 through the bottom dielectric film 39 is wide enough to allow epitaxial source / drain regions to grow from the bottom epitaxial layer 36 through the opening 39. Figure 4B As shown, the opening 39 extends through the bottom dielectric layer 38 along the y direction, dividing the bottom dielectric layer 38 into two discontinuous parts. In some embodiments, the width S of the opening 39 is DF In the range between about 1 nm and about 30 nm.

[0102] FIG. 4C to FIG. 4D A semiconductor device 10 b according to the present disclosure is schematically illustrated. The semiconductor device 10 b is similar to the semiconductor device 10 a except that the openings 39 are asymmetrically placed relative to the inner spacers 32 .

[0103] Figure 4E A semiconductor device 10c according to the present disclosure is schematically shown. The semiconductor device 10c is similar to the semiconductor device 10a, except that the bottom dielectric layer 38 in the semiconductor device 10c is lower along the z direction, ie, has a larger negative step-down distance h DF . Larger negative drop distance h DF As a result, a portion of the sidewall 12s of the mesa portion 12M is exposed to the source / drain recess 34. The exposed sidewall 12s is used as a seed layer during the subsequent growth of the source / drain region 40 to achieve a specific structure in the source / drain region. Lowering the bottom dielectric layer 38 also increases the volume of the source / drain region 40.

[0104] Figure 4F Schematically illustrates a semiconductor device 10d according to the present disclosure. Semiconductor device 10f is similar to semiconductor device 10a, except that sidewalls 38s of opening 38 are inclined. Sidewalls 38s and top surface 38t form an angle θ DF In some embodiments, the angle θ DF In the range between about 10° and about 150°, a suitable angle θ may be selected. DF to achieve the desired crystal structure.

[0105] Figure 4G A semiconductor device 10e according to the present disclosure is schematically shown. The semiconductor device 10f is similar to the semiconductor device 10a, except that the bottom dielectric layer 38 in the semiconductor device 10f is higher along the z direction, ie, has a positive step-down distance h DF . Positive descent distance h DF Improved isolation between mesa portion 12M and epitaxial source / drain regions 40 to be formed over bottom dielectric layer 38 results.

[0106] Figure 4H Schematically illustrates a semiconductor device 10f according to the present disclosure. The semiconductor device 10f is similar to the semiconductor device 10a, except that the bottom epitaxial layer 36 has a curved top surface 36t, resulting in a substantially curved bottom dielectric layer 38. The bottom dielectric layer 38 may have a vertical extension V DC , vertical extension V DC The vertical extension V is defined by the distance along the z direction between the highest point of the top surface 38t and the lowest point of the bottom surface 38b. DCIn the range between about 1 nm and about 30 nm. The bottom dielectric layer 38 may have a horizontal extension L DC , horizontal extension L DC The horizontal extension L is defined by the distance along the x-direction between the sidewall 32s of the inner spacer 32 and the sidewall 38s of the opening 39. DC In some embodiments, the bottom dielectric layer 38 and the xy plane may form an angle θ DC In some embodiments, the angle θ DC In the range between about 5° and about 90°. The relative position between the bottom dielectric layer 38 and the top surface 12f can be determined by the lowering distance h DC Indicates that the falling distance h DC The distance h is defined by the distance along the z direction between the lowest point of the bottom dielectric layer 38 and the bottom or top surface 12f of the sheet. In some embodiments, the descending distance h DC In the range between about -15 nm and about 15 nm. Figure 4H In the middle, the descending distance h DC is negative. Figure 4H , the top surface 36t of the bottom epitaxial layer 36 and the bottom dielectric layer 38 are both recessed.

[0107] The opening 39 through the bottom dielectric film 39 is wide enough to allow the epitaxial source / drain region to grow from the bottom epitaxial layer 36 through the opening 39. The opening 39 extends through the bottom dielectric layer 38 along the y-direction, dividing the bottom dielectric layer 38 into two discrete portions. In some embodiments, the width S of the opening 39 is DC In the range between about 1 nm and about 30 nm.

[0108] Fig. 4I The semiconductor device 10g according to the present disclosure is schematically shown. The semiconductor device 10g is similar to Figure 4H The semiconductor device 10f shown in FIG. 10 is a semiconductor device 10f in which the top surface 36t of the bottom epitaxial layer 36 and the bottom dielectric layer 38 are both raised and lowered by a distance h. DC is correct.

[0109] Figure 4J The semiconductor device 10h according to the present disclosure is schematically shown. The semiconductor device 10h is similar to Figure 4E The semiconductor device 10c shown in FIG. 1 is a semiconductor device 10c, except that the bottom dielectric layer 36 is a continuous layer without any openings. The exposed sidewalls 12s are used as seed layers when forming the epitaxial source / drain regions 40. The bottom dielectric layer 38 may have a thickness t in the range between about 1 nm and about 10 nm. CFThe bottom dielectric layer 36 may be substantially located near the bottom or top surface 12f of the substrate 12. The relative position between the bottom dielectric layer 38 and the top surface 12f may be determined by the step-down distance h. CF Indicates that the falling distance h CF The lowering distance h is defined by the distance between the bottom surface 38b of the bottom dielectric layer 38 and the bottom or top surface 12f of the sheet. In some embodiments, the lowering distance h CF In the range between about -20 nm and about 20 nm.

[0110] Figure 4K The semiconductor device 10i according to the present disclosure is schematically shown. The semiconductor device 10i is similar to Figure 4J The semiconductor device 10h is shown in FIG. 1, except that the bottom epitaxial layer 36 has a curved top surface 36t, resulting in a substantially curved bottom dielectric layer 38. The bottom dielectric layer 38 is a continuous curved film.

[0111] The bottom dielectric layer 38 may have a vertical extension V CC , vertical extension V CC The vertical extension V is defined by the distance along the z direction between the highest point of the top surface 38t and the lowest point of the bottom surface 38b. CC In some embodiments, the bottom dielectric layer 38 and the xy plane may form an angle θ CC In some embodiments, the angle θ CC In the range between about 5° and about 90°. The relative position between the bottom dielectric layer 38 and the top surface 12f can be determined by the lowering distance h CC Indicates that the falling distance h CC The distance h is defined by the distance along the z direction between the lowest point of the bottom dielectric layer 38 and the bottom or top surface 12f of the sheet. In some embodiments, the descending distance h CC In the range between about -20 nm and about 20 nm.

[0112] Figure 4L The semiconductor device 10j according to the present disclosure is schematically shown. The semiconductor device 10j is similar to Figure 4L The semiconductor device 10 i is shown in that all but the top surface 36 t of the bottom epitaxial layer 36 and the bottom dielectric layer 38 are raised.

[0113] According to embodiments of the present disclosure, the source / drain regions may be designed to achieve different shapes and / or layer compositions of the source / drain regions. For example, by changing the shape and / or position of the bottom dielectric layer, forming or omitting an opening through the bottom dielectric layer, selecting the shape and position of the opening, using or not using a channel push process, etc. FIG. 5A to FIG. 5LVarious designs of source / drain regions according to embodiments of the present disclosure are schematically shown.

[0114] Figure 5A A semiconductor device 200 a according to an embodiment of the present disclosure is schematically illustrated. Figure 5A The semiconductor device 200a is schematically shown after forming the epitaxial source / drain regions 240 (e.g., after operation 120). The semiconductor device 200a is similar to the semiconductor device 200 described above, except that the channel-driving operation 116 is omitted when manufacturing the semiconductor device 200a. Instead, the bottom dielectric layer 238 contacts the lowermost inner spacer 232, and the sidewalls 212s of the well portion 212 do not contact the epitaxial source / drain regions 240. In other words, the bottom dielectric layer 238 isolates the epitaxial source / drain regions 240 from the well portion 212 or mesa region of the substrate 210.

[0115] In the semiconductor device 200a, the first epitaxial source / drain layer 241 includes various discrete portions, namely, a channel portion 241C and a bottom portion 241B that do not merge with each other. The channel portion 241C extends from the sidewall 232s of the inner spacer 232 along the x direction by a distance t S In some embodiments, the distance t S The bottom portion 241B extends from the top surface 236t along the z direction by a distance t B In some embodiments, the distance t B The bulk epitaxial source / drain layer 243 contacts at least a portion of the sidewall 232s of the inner spacer 232 . The bulk epitaxial source / drain layer 243 also contacts the bottom dielectric layer 238 .

[0116] Figure 5B A semiconductor device 200b according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200b is similar to the semiconductor device 200a described above, except that some channel portions 241C of the first epitaxial source / drain layer 241 are merged with each other while other channel portions 241 remain unmerged. The epitaxial source / drain region 240 has an EPI height M, which can be defined as the distance along the z-direction between the top surface 240t and the bottom surface 240b of the epitaxial source / drain region 240. In some embodiments, the EPI height is in a range between about 20 nm and about 105 nm. In some embodiments, the channel portion 241C can be at a merge height h M Merge at the height h M The merge height h may be defined as the distance between the top surface 240t of the epitaxial source / drain region 240 and the merge point along the z direction. In some embodiments, the merge height hM In the range between 0 and the EPI height M. Figure 5B As shown, in semiconductor device 200 b, bulk epitaxial source / drain layer 243 contacts some of inner spacers 232 , but a portion of inner spacers 232 may be covered by first epitaxial source / drain layer 241 . Bulk epitaxial source / drain layer 243 also contacts bottom dielectric layer 238 .

[0117] Figure 5C A semiconductor device 200c according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200c is similar to the semiconductor device 200a described above, except that the lowermost channel portion 241C and the bottom portion 241B of the first epitaxial source / drain layer 241 are merged together while the upper channel portion 241 remains unmerged. Figure 5C As shown, in the semiconductor device 200 c , the bulk epitaxial source / drain layer 243 contacts the upper inner spacer 232 , but the lowermost inner spacer 232 and the bottom dielectric layer 238 are covered by the first epitaxial source / drain layer 241 .

[0118] Figure 5D A semiconductor device 200d according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200d is similar to the semiconductor device 200c described above, except that some of the upper channel portions 241 are merged with each other. Figure 5D As shown, in the semiconductor device 200 d , the bulk epitaxial source / drain layer 243 contacts some of the upper inner spacers 232 , but the lowermost inner spacers 232 and the bottom dielectric layer 238 are covered by the first epitaxial source / drain layer 241 .

[0119] Figure 5E A semiconductor device 200e according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200e is similar to the semiconductor device 200a described above, except that a channel push operation is performed during the manufacture of the semiconductor device 200e. As a result, the epitaxial source / drain region 240 extends into the semiconductor layer 216 or the channel layer beyond the sidewall 232s of the inner spacer 232. The first epitaxial source / drain layer 241 may extend from the sidewall 232s of the inner spacer 232 by a length t PH In some embodiments, the length t PH In the range between about 1 nm and about 6 nm. As described above, the channel portion 241C of the first epitaxial source / drain layer 241 may extend from the sidewall 232s of the inner spacer 232 by a distance t S In some embodiments, the total thickness t of the channel portion 241C of the first epitaxial source / drain layer 241 is S +t PHIn the range between about 1 nm and about 14 nm.

[0120] In an embodiment, the bottom epitaxial layer 236 is also etched back during the channel driving operation. As a result, the epitaxial source / drain regions 240 extend through the bottom dielectric layer 238 and into the bottom epitaxial layer 236. In some embodiments, the epitaxial source / drain regions 240 may extend from the top surface 236t by a length t PV into the bottom epitaxial layer 236. In some embodiments, the length t PV In the range between about 1 nm and about 10 nm. As described above, the bottom portion 241B of the first epitaxial source / drain layer 241 may extend from the top surface 236t by a distance t B In some embodiments, the total thickness t of the bottom portion 241B of the first epitaxial source / drain layer 241 is B +t PV In the range between about 1 nm and about 22 nm.

[0121] Fig. 5F A semiconductor device 200f according to an embodiment of the present disclosure is schematically illustrated. The semiconductor device 200f is similar to the semiconductor device 200 described above, except that the channel driving operation 116 is omitted when manufacturing the semiconductor device 200f. Alternatively, the bottom dielectric layer 238 is a continuous layer without an opening 239. In some embodiments, the sidewall 212s of the well portion 212 contacts the epitaxial source / drain region 240 for a vertical length K. In some embodiments, the vertical length K is in a range between about 0 nm and about 50 nm. In the semiconductor device 200f, the first epitaxial source / drain layer 241 includes various discrete portions, namely, a channel portion 241C and a sidewall portion 241S that do not merge with each other. The sidewall portion 241S is grown from the exposed sidewall 212s. In some embodiments, the top surface 241 of the sidewall portion 241S is St The angle θ is formed with the xy plane DB In some embodiments, the angle θ DB In the range between about 10° and about 80°, the bulk epitaxial source / drain layer 243 contacts at least a portion of the sidewall 232s of the inner spacer 232 . The bulk epitaxial source / drain layer 243 also contacts the bottom dielectric layer 238 .

[0122] Figure 5GA semiconductor device 200g according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200g is similar to the semiconductor device 200 described above, except that the channel push operation 116 is omitted when manufacturing the semiconductor device 200g. Alternatively, the bottom dielectric layer 238 is a continuous layer without an opening 239. The first epitaxial source / drain layer 241 covers the sidewalls 232s of some of the inner spacers 232. The main epitaxial source / drain layer 243 contacts at least a portion of the sidewalls 232s of the inner spacers 232. The main epitaxial source / drain layer 243 also contacts the bottom dielectric layer 238.

[0123] Figure 5H A semiconductor device 200h according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200h is similar to the semiconductor device 200g described above, except that the sidewall portions 241S of the first epitaxial source / drain layer 241 are merged together while the channel portion 241 remains unmerged. Figure 5H As shown, in the semiconductor device 200 h , the bulk epitaxial source / drain layer 243 contacts the inner spacer 232 , but the bottom dielectric layer 238 is covered by the first epitaxial source / drain layer 241 .

[0124] Fig.5I A semiconductor device 200i according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200i is similar to the semiconductor device 200h described above, except that the sidewall portions 241S of the first epitaxial source / drain layer 241 are merged together and merged with the lowermost channel portion 241C. Some of the upper channel portions 241 remain unmerged. Fig.5I As shown, in the semiconductor device 200 i , the bulk epitaxial source / drain layer 243 contacts some of the upper inner spacers 232 , but the lowermost inner spacers 232 and the bottom dielectric layer 238 are covered by the first epitaxial source / drain layer 241 .

[0125] Figure 5J The semiconductor device 200j according to an embodiment of the present disclosure is schematically shown. The semiconductor device 200j is similar to Fig. 5F The semiconductor device 200f described above, except that the channel push operation 116 is performed during the manufacturing of the semiconductor device 200j. As a result, the epitaxial source / drain region 240 extends into the semiconductor layer 216 or the channel layer beyond the sidewall 232s of the inner spacer 232. The first epitaxial source / drain layer 241 may extend from the sidewall 232s of the inner spacer 232 by a length t PH In some embodiments, the length t PHIn the range between about 1 nm and about 6 nm. As described above, the channel portion 241C of the first epitaxial source / drain layer 241 may extend from the sidewall 232s of the inner spacer 232 by a distance t S In some embodiments, the total thickness t of the channel portion 241C of the first epitaxial source / drain layer 241 is S +t PH In a range between about 1 nm and about 14 nm. In an embodiment, the well portion 212 is also etched back during the channel driving operation. As a result, the sidewall portion 241S of the first epitaxial source / drain layer 241 extends beyond the sidewall 232s of the inner spacer 232 .

[0126] Figure 5K Various profiles of the interface between the epitaxial source / drain region 240 and the semiconductor layer 216 or channel layer are schematically shown. The profile can be convex, flat, concave, or inclined. Different profiles can be achieved by controlling the etch-back process during the channel push operation (e.g., operation 116). The interface forms an angle θ with the yz plane. C In some embodiments, the angle θ C In the range between about -80° and about 80°.

[0127] Figure 5L Various profiles of the interface between the epitaxial source / drain region 240 and the internal spacer 232 are schematically shown. The profile can be convex, flat, or concave. The different profiles can be achieved by controlling the etch-back process when forming the internal spacer 232. The interface forms an angle θ with the yz plane. SP In some embodiments, the angle θ SP In the range between about -80° and about 80°.

[0128] Various embodiments or examples described herein provide several advantages over the prior art. A semiconductor device according to the present disclosure has a reduced channel resistance (R ch ), improved AC performance and minimized R ch Degraded DC performance loss.

[0129] It is understood that not all advantages are necessarily discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide different advantages.

[0130] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a semiconductor channel disposed above a top surface of a semiconductor substrate; an epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below the top surface of the semiconductor substrate; and a bottom dielectric layer in contact with the bottom surface of the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the bottom surface extending below the top surface of the semiconductor substrate.

[0131] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a semiconductor substrate; two or more semiconductor channel layers vertically stacked above the top surface of the semiconductor substrate; two or more internal spacers alternately stacked with the two or more semiconductor channel layers; and an epitaxial source / drain region, including: a first epitaxial source / drain layer grown from the two or more semiconductor channel layers and a semiconductor surface disposed below the top surface of the semiconductor substrate; and a main epitaxial source / drain layer grown from the first epitaxial source / drain layer.

[0132] Some embodiments provide a method for forming a semiconductor device. The method includes: forming a semiconductor fin on a top surface of a semiconductor substrate, wherein the semiconductor fin includes a first semiconductor layer and a second semiconductor layer arranged alternately; forming a recess through the semiconductor fin and into the semiconductor substrate; forming a bottom dielectric layer in the recess, wherein the bottom dielectric layer partially covers a semiconductor surface below the top surface of the semiconductor substrate; and growing an epitaxial source / drain region on the bottom dielectric layer, wherein the epitaxial source / drain region contacts a portion of the semiconductor surface below the top surface of the semiconductor substrate.

[0133] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0134] Example 1. A semiconductor device comprising:

[0135] A semiconductor channel is disposed above a top surface of the semiconductor substrate;

[0136] an epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below a top surface of the semiconductor substrate; and

[0137] A bottom dielectric layer contacts a bottom surface of the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the bottom surface extending below the top surface of the semiconductor substrate.

[0138] Example 2. The semiconductor device of Example 1, wherein the semiconductor channel includes two or more semiconductor channel layers stacked over a top surface of the semiconductor substrate.

[0139] Example 3. The semiconductor device of Example 2 further includes: a bottom epitaxial layer disposed below the bottom dielectric layer, and a bottom portion of the epitaxial source / drain region is formed above the bottom epitaxial layer.

[0140] Example 4. The semiconductor device of Example 3, wherein the bottom dielectric layer includes an opening, and a bottom portion of the epitaxial source / drain region extends through the opening below the bottom dielectric layer to contact the bottom epitaxial layer.

[0141] Example 5. The semiconductor device of Example 4, wherein the bottom dielectric layer is a continuous layer in which the opening is formed.

[0142] Example 6. The semiconductor device of Example 4, wherein the bottom dielectric layer is a discontinuous layer, and the opening is a trench formed across the bottom dielectric layer.

[0143] Example 7. The semiconductor device of Example 4, wherein a bottom portion of the epitaxial source / drain region extends into the bottom epitaxial layer.

[0144] Example 8. A semiconductor device according to Example 3, wherein the bottom dielectric layer is disposed below the top surface of the semiconductor substrate, and the epitaxial source / drain region contacts the semiconductor substrate on a side wall located below the top surface of the semiconductor substrate and above the bottom dielectric layer.

[0145] Example 9. The semiconductor device according to Example 2 further includes: an internal spacer disposed between the two or more semiconductor channel layers, wherein a top surface, a bottom surface and a sidewall of the internal spacer are in contact with the epitaxial source / drain region.

[0146] Example 10. A semiconductor device comprising:

[0147] Semiconductor substrate;

[0148] two or more semiconductor channel layers vertically stacked above the top surface of the semiconductor substrate;

[0149] Two or more internal spacers are alternately stacked with the two or more semiconductor channel layers; and

[0150] Epitaxial source / drain regions, including:

[0151] a first epitaxial source / drain layer grown from the two or more semiconductor channel layers and a semiconductor surface disposed below a top surface of the semiconductor substrate; and

[0152] A bulk epitaxial source / drain layer is grown from the first epitaxial source / drain layer.

[0153] Example 11. The semiconductor device of Example 10, wherein the first epitaxial source / drain layer comprises:

[0154] two or more channel portions grown from the two or more semiconductor channel layers; and

[0155] A bottom portion grows from the semiconductor surface disposed below the top surface of the semiconductor substrate.

[0156] Example 12. The semiconductor device of Example 11 further comprises: a bottom dielectric layer disposed between the semiconductor surface and the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the semiconductor surface.

[0157] Example 13. The semiconductor device of Example 12, wherein the bottom dielectric layer has an opening and the bottom portion grows from the semiconductor surface through the opening.

[0158] Example 14. The semiconductor device of Example 13, wherein the bottom portion extends below the bottom dielectric layer and into the semiconductor surface.

[0159] Example 15. The semiconductor device of Example 12, wherein the bottom dielectric layer is disposed below a top surface of the semiconductor substrate, and the bottom portion grows from a sidewall of the semiconductor substrate below the top surface and above the bottom dielectric layer.

[0160] Example 16. A method comprising:

[0161] forming a semiconductor fin on a top surface of the semiconductor substrate, wherein the semiconductor fin comprises a first semiconductor layer and a second semiconductor layer arranged alternately;

[0162] forming a recess through the semiconductor fin and into the semiconductor substrate;

[0163] forming a bottom dielectric layer in the recess, wherein the bottom dielectric layer partially covers a semiconductor surface below a top surface of the semiconductor substrate; and

[0164] Epitaxial source / drain regions are grown over the bottom dielectric layer, wherein the epitaxial source / drain regions contact a portion of the semiconductor surface below a top surface of the semiconductor substrate.

[0165] Example 17. The method according to Example 16, further comprising:

[0166] A bottom epitaxial layer is grown in the recess, wherein the bottom dielectric layer is formed on the bottom epitaxial layer.

[0167] Example 18. The method of Example 17, wherein forming the bottom dielectric layer comprises:

[0168] depositing a continuous dielectric layer; and

[0169] An opening is formed through the continuous dielectric layer to expose a portion of the bottom epitaxial layer, wherein a portion of the epitaxial source / drain region is grown from the bottom epitaxial layer through the opening.

[0170] Example 19. The method according to Example 18, further comprising:

[0171] selectively etching back the first semiconductor layer to form an inner spacer between the second semiconductor layers; and

[0172] Prior to forming the epitaxial source / drain regions, the second semiconductor layer is etched back from the inner spacers.

[0173] Example 20. The method of Example 17, wherein a top surface of the bottom epitaxial layer is below a top surface of the semiconductor substrate, and a sidewall of the recess is exposed between the bottom dielectric layer and the top surface of the semiconductor substrate, and growing epitaxial source / drain regions comprises:

[0174] A first source / drain layer is grown from the sidewalls of the recess.

Claims

1. A semiconductor device, comprising: A semiconductor channel is disposed above a top surface of the semiconductor substrate; an epitaxial source / drain region connected to the semiconductor channel, wherein the epitaxial source / drain region includes a sidewall connected to the semiconductor channel and a bottom surface extending below a top surface of the semiconductor substrate; and A bottom dielectric layer contacts a bottom surface of the epitaxial source / drain region, wherein the bottom dielectric layer partially covers the bottom surface extending below the top surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The semiconductor channel includes two or more semiconductor channel layers stacked over a top surface of the semiconductor substrate.

3. The semiconductor device according to claim 2, further comprising: A bottom epitaxial layer is disposed below the bottom dielectric layer, and a bottom portion of the epitaxial source / drain region is formed on the bottom epitaxial layer.

4. The semiconductor device according to claim 3, wherein: The bottom dielectric layer includes an opening, and a bottom portion of the epitaxial source / drain region extends beneath the bottom dielectric layer through the opening to contact the bottom epitaxial layer.

5. The semiconductor device according to claim 4, wherein: The bottom dielectric layer is a continuous layer in which the openings are formed.

6. The semiconductor device according to claim 4, wherein: The bottom dielectric layer is a discontinuous layer, and the opening is a trench formed across the bottom dielectric layer.

7. The semiconductor device according to claim 4, wherein: A bottom portion of the epitaxial source / drain region extends into the bottom epitaxial layer.

8. The semiconductor device according to claim 3, wherein: The bottom dielectric layer is disposed below a top surface of the semiconductor substrate, and the epitaxial source / drain regions contact the semiconductor substrate on sidewalls below the top surface of the semiconductor substrate and above the bottom dielectric layer.

9. A semiconductor device comprising: Semiconductor substrate; two or more semiconductor channel layers vertically stacked above the top surface of the semiconductor substrate; Two or more internal spacers are alternately stacked with the two or more semiconductor channel layers; as well as Epitaxial source / drain regions, including: a first epitaxial source / drain layer and a semiconductor surface, the first epitaxial source / drain layer grown from the two or more semiconductor channel layers, the semiconductor surface being disposed below a top surface of the semiconductor substrate; as well as A bulk epitaxial source / drain layer is grown from the first epitaxial source / drain layer.

10. A method comprising: forming a semiconductor fin on a top surface of the semiconductor substrate, wherein the semiconductor fin comprises a first semiconductor layer and a second semiconductor layer arranged alternately; forming a recess through the semiconductor fin and into the semiconductor substrate; forming a bottom dielectric layer in the recess, wherein the bottom dielectric layer partially covers a semiconductor surface below a top surface of the semiconductor substrate; and Epitaxial source / drain regions are grown over the bottom dielectric layer, wherein the epitaxial source / drain regions contact a portion of the semiconductor surface below a top surface of the semiconductor substrate.

Images