Semiconductor device

Abstract

The semiconductor device includes: a first electrode; a second electrode disposed at a position facing the first electrode; and a semiconductor section provided between the first electrode and the second electrode and including a first semiconductor layer of a first conductivity type. The semiconductor section further includes a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first electrode, and a third semiconductor layer of the second conductivity type selectively provided in the first semiconductor layer and disposed at a position separated from the second semiconductor layer. The first electrode has an extension portion electrically connected to the second semiconductor layer, extending through the second semiconductor layer in a first direction toward the second electrode, and connected to the third semiconductor layer.

Description

[0001] This application is a divisional application of the invention patent application with Chinese patent application number 201910022345.X and invention name “Semiconductor Device” filed by the present applicant on January 10, 2019.

[0002] Related Application

[0003] This application claims priority based on Japanese Patent Application No. 2018-172650 (filing date: September 14, 2018). This application includes all the contents of the basic application by reference. Technical Field

[0004] Embodiments relate to a semiconductor device. Background Art

[0005] In a semiconductor device for power control, it is required to reduce the forward voltage and switching loss. The forward voltage can be reduced by increasing the carrier concentration in the semiconductor. On the other hand, the switching loss is reduced by shortening the time for the carriers in the semiconductor to be pulled to the electrode when the semiconductor device is turned off. Therefore, it is difficult to reduce both the forward voltage and the switching loss. Summary of the invention

[0006] Embodiments provide a semiconductor device capable of reducing switching loss.

[0007] The semiconductor device according to the embodiment comprises: a first electrode; a second electrode arranged at a position opposite to the first electrode; and a semiconductor portion provided between the first electrode and the second electrode and including a first semiconductor layer of a first conductivity type. The semiconductor portion further comprises: a second semiconductor layer of a second conductivity type provided between the first semiconductor layer and the first electrode; and a third semiconductor layer of a second conductivity type selectively provided in the first semiconductor layer and arranged at a position separated from the second semiconductor layer. The first electrode has an extension portion, the extension portion being electrically connected to the second semiconductor layer, extending in a first direction toward the second electrode through the second semiconductor layer, and being connected to the third semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic cross-sectional view showing the semiconductor device according to the first embodiment.

[0009] Figure 2A and Figure 2B It is a schematic plan view showing the semiconductor device according to the first embodiment.

[0010] Figure 3A and Figure 3BThis is a schematic diagram showing the flow of carriers in the semiconductor device according to the first embodiment.

[0011] Figure 4 It is a schematic cross-sectional view showing a semiconductor device according to a modification of the first embodiment.

[0012] Figure 5A and Figure 5B This is a schematic diagram showing the flow of carriers in a semiconductor device according to a modification of the first embodiment.

[0013] Figure 6 This is a schematic cross-sectional view showing a semiconductor device according to another modified example of the first embodiment.

[0014] Fig. 7A and Figure 7B This is a schematic diagram showing the flow of carriers in a semiconductor device according to another modification of the first embodiment.

[0015] Figure 8 It is a schematic cross-sectional view showing a semiconductor device according to a second embodiment.

[0016] Fig.9A and Fig. 9B This is a schematic diagram showing the flow of carriers in the semiconductor device according to the second embodiment.

[0017] Fig.10 It is a schematic cross-sectional view showing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same parts in the drawings are marked with the same numbers, and their detailed descriptions are appropriately omitted, and different parts are described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc., are not necessarily the same as in reality. In addition, even when representing the same part, there is a case where the size and ratio of each other are different according to the drawings.

[0019] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, there is a case where the Z direction is regarded as the upper direction and the opposite direction is regarded as the lower direction.

[0020] (First embodiment)

[0021] Figure 11 is a schematic cross-sectional view showing a semiconductor device 1 according to the first embodiment. The semiconductor device 1 is, for example, a PIN diode, and is used together with an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or the like to constitute a power converter or the like.

[0022] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor portion 10, an anode electrode 20, and a cathode electrode 30. The semiconductor device 1 is a vertical element, and the cathode electrode 30 is arranged at a position facing the anode electrode 20. The semiconductor portion 10 is provided between the anode electrode 20 and the cathode electrode 30.

[0023] The semiconductor portion 10 includes an n-type semiconductor layer 11, a p-type anode layer 13, an n-type cathode layer 15, and a p-type semiconductor layer 17. The p-type anode layer 13 is disposed between the n-type semiconductor layer 11 and the anode electrode 20. The n-type cathode layer 15 is disposed between the n-type semiconductor layer 11 and the cathode electrode 30.

[0024] The p-type semiconductor layer 17 is selectively provided in the n-type semiconductor layer 11. The p-type semiconductor layer 17 is arranged at a position separated from the p-type anode layer 13.

[0025] The anode electrode 20 is electrically connected to the p-type anode layer 13. The cathode electrode 30 is electrically connected to the n-type cathode layer 15. Here, the term "electrical connection" means both direct contact and contact through another conductive layer. This also applies to the following description.

[0026] The anode electrode 20 has an extension portion 21 extending in a direction toward the cathode electrode 30 (i.e., the opposite direction of the Z direction, hereinafter, the -Z direction) through the p-type anode layer 13. The extension portion 21 is provided to be connected to the p-type semiconductor layer 17. In addition, the extension portion 21 includes a contact portion CP located between the p-type anode layer 13 and the p-type semiconductor layer 17. The contact portion CP is in contact with the n-type semiconductor layer 11.

[0027] The n-type semiconductor layer 11 and the n-type cathode layer 15 are, for example, n-type silicon layers. The n-type cathode layer 15 includes n-type impurities at a higher concentration than the n-type impurities included in the n-type semiconductor layer 11. The n-type cathode layer 15 can be provided integrally with the n-type semiconductor layer 11. That is, a high concentration of n-type impurities can be introduced into the back side of the n-type semiconductor layer 11, for example, by ion implantation. The p-type anode layer 13 is formed, for example, by ion implanting p-type impurities into the n-type semiconductor layer 11.

[0028] The extension portion 21 of the anode electrode 20 is formed by burying a metal layer inside a groove TR having a depth penetrating the p-type anode layer 13. The extension portion 21 includes a metal that is in Schottky contact with the n-type semiconductor layer 11 at least in the portion in contact with the n-type semiconductor layer 11. The extension portion 21 may be formed of the same material as the main body of the anode electrode 20, or may be formed using a different material. For example, the extension portion 21 includes one of aluminum (Al), tantalum (Ta), silver (Ag), molybdenum (Mo), tungsten (W), cobalt (Co), chromium (Cr), ruthenium (Ru), gold (Au), palladium (Pd), nickel (Ni), and platinum (Pt) at least in the portion in contact with the n-type semiconductor layer 11.

[0029] The p-type semiconductor layer 17 is formed, for example, by ion implanting p-type impurities into the bottom surface of the trench TR. The p-type semiconductor layer 17 may be formed simultaneously with the p-type anode layer 13 or may be formed in another process. The p-type semiconductor layer 17 is provided, for example, in contact with the metal layer (i.e., the extension 21) buried in the trench TR.

[0030] Figure 2A and Figure 2B It is a schematic plan view showing the semiconductor device 1 according to the first embodiment. Figure 2A and Figure 2B For example, the top surface of the semiconductor device 1 is shown, and the arrangement of the extending portion 21 in the XY plane is shown. The arrangement of the extending portion 21 shown here is an example, and the embodiment is not limited to this.

[0031] like Figure 2A As shown, the extension portion 21 of the anode electrode 20 extends in the Y direction. In addition, a plurality of extension portions 21 are provided and arranged in parallel in the X direction.

[0032] like Figure 2B As shown, the extension portion 21 may be provided in a cylindrical shape, for example. A plurality of extension portions 21 are arranged in the X direction and the Y direction, for example, and are spaced apart from each other.

[0033] Figure 3A and Figure 3B It is a schematic diagram showing the flow of carriers in the n-type semiconductor layer 11 of the semiconductor device 1 according to the first embodiment. Figure 3A The semiconductor device 1 is shown in a forward biased state (on state). Figure 3B The flow of carriers during a transition period when the bias of the semiconductor device 1 is switched from the forward direction to the reverse direction (off state) is shown.

[0034] exist Figure 3AIn the on state shown, electrons in the n-type semiconductor layer 11 flow toward the p-type anode layer 13. Meanwhile, holes are injected from the p-type anode layer 13 into the n-type semiconductor layer 11, and the amount of electrons and holes in the n-type semiconductor layer 11 is balanced.

[0035] The paths of electrons flowing from the n-type semiconductor layer 11 to the anode electrode 20 include, for example, a path through the pn junction between the n-type semiconductor layer 11 and the p-type anode layer 13, and a path through the contact portion CP in the extension portion 21 of the anode electrode 20. In addition, the potential that hinders the flow of electrons is lower in the path through the Schottky junction of the contact portion CP than in the path through the pn junction. Therefore, the electrons in the n-type semiconductor layer 11 mainly flow to the anode electrode 20 through the contact portion CP.

[0036] Figure 3B Indicates the flow of carriers during the transition period from the on state to the off state. Electrons in the n-type semiconductor layer 11 are discharged to the cathode electrode 30 via the n-type cathode layer 15. On the other hand, holes are discharged through the p-type anode layer 13 to the anode electrode 20 and through the p-type semiconductor layer 17 and the extension 21 located in the n-type semiconductor layer 11 to the anode electrode 20. In this example, most of the holes in the n-type semiconductor layer 11 are discharged through the p-type semiconductor layer 17 and the extension 21.

[0037] In the on-state of the semiconductor device 1, the electrons in the n-type semiconductor layer 11 flow toward the anode electrode 20 via the contact portion CP of the extension portion 21. For this reason, the electrons flow toward the anode electrode 20 more quickly than in a structure without the extension portion 21. Therefore, the amount of electrons in the n-type semiconductor layer 11 decreases, and the amount of holes that balance them also decreases. That is, in the semiconductor device 1, the amount of carriers in the n-type semiconductor layer 11 in the on-state decreases.

[0038] On the other hand, during the transition period to the off state, holes in the n-type semiconductor layer 11 are discharged to the anode electrode 20 via the p-type semiconductor layer 17. Therefore, compared with a structure without the p-type semiconductor layer 17, holes are discharged to the anode electrode 20 more quickly.

[0039] For example, the length of the transition period from the on state to the off state depends on the discharge time of the holes. Therefore, in the semiconductor device 1, the discharge of holes is promoted by providing the p-type semiconductor layer 17, thereby shortening the transition period. Furthermore, in the semiconductor device 1, the amount of carriers in the n-type semiconductor layer 11 in the on state can be reduced. Thus, the time required for the discharge of carriers can be further shortened. As a result, the transition period for the discharge of carriers from the n-type semiconductor layer 11 is shortened, and the switching loss can be reduced.

[0040] Figure 41 is a schematic cross-sectional view showing a semiconductor device 2 according to a modification of the first embodiment. In the semiconductor device 2, the p-type anode layer 13 has a protruding portion 19 provided between the extending portions 21 adjacent to each other in the X direction, for example.

[0041] The protrusion 19 includes p-type impurities having a higher concentration than the n-type impurities of the n-type semiconductor layer 11, and extends in the direction (-Z direction) from the p-type anode layer 13 toward the cathode electrode 30. The front end of the protrusion 19 is formed to be located at approximately the same level as the lower end of the p-type semiconductor layer 17 in the Z direction, for example.

[0042] Furthermore, a p may be provided between the protrusion 19 and the anode electrode 20. + Type contact layer 14. + The p-type contact layer 14 is selectively provided between the p-type anode layer 13 and the anode electrode 20 and includes a p-type impurity having a higher concentration than the p-type impurity of the p-type anode layer 13. + The contact layer 14 is electrically connected to the anode electrode 20 .

[0043] Figure 5A and Figure 5B It is a schematic diagram showing the flow of carriers in the n-type semiconductor layer 11 of the semiconductor device 2 according to the modification of the first embodiment. Figure 5A The case where the semiconductor device 2 is forward biased (on state) is shown. Figure 5B 2 represents the flow of carriers during the transition period when the bias of the semiconductor device 2 is switched from the forward direction to the reverse direction (off state). In the semiconductor device 2, the interval in the X direction of the extension 21 of the anode electrode 20 is, for example, Figure 1 In the semiconductor device 1 shown, the intervals between the extending portions 21 in the X direction are wide.

[0044] exist Figure 5A In the on-state shown, the electrons in the n-type semiconductor layer 11 flow mainly to the anode electrode 20 via the contact portion CP of the extension portion 21. In this example, the interval in the X direction of the extension portion 21 is wide, so the number of electrons flowing to the anode electrode 20 via the contact portion CP is reduced compared to the semiconductor device 1. As a result, the amount of electrons in the n-type semiconductor layer 11 increases, and in order to balance it, the amount of holes injected from the p-type anode layer 13 also increases.

[0045] Figure 5B The flow of carriers during the transition from the on state to the off state is shown. Holes in the n-type semiconductor layer 11 are discharged to the anode electrode 20 via the p-type semiconductor layer 17 and the extension 21, and are discharged to the anode electrode 20 via the protrusion 19 of the p-type anode layer 13. +The p-type contact layer 14 facilitates the movement of holes from the p-type anode layer 13 to the anode electrode 20. This can improve avalanche resistance.

[0046] In the semiconductor device 2, the number of carriers in the n-type semiconductor layer 11 increases in the on state, so the forward voltage can be reduced compared to the semiconductor device 1. That is, the switching loss increases compared to the semiconductor device 1, but the forward voltage can be reduced.

[0047] In this embodiment, for example, the forward voltage and the switching loss can be controlled by changing the interval in the X direction of the extension portion 21 of the anode electrode 20. For example, by narrowing the interval in the X direction of the extension portion 21, the switching loss can be reduced. On the other hand, when the interval in the X direction of the extension portion 21 is widened, the forward voltage is reduced. Therefore, the desired forward voltage and switching characteristics can be achieved by appropriately adjusting the interval in the X direction of the extension portion 21.

[0048] In addition, in the semiconductor devices 1 and 2, holes are rapidly discharged from the n-type semiconductor layer 11 via the p-type semiconductor layer 17 and the extension 21 when the semiconductor device 1 and 2 are turned off. For this reason, in the semiconductor devices 1 and 2, the avalanche resistance can be improved compared with the structure without the extension 21. On the other hand, the avalanche resistance of the semiconductor device 1 depends on the spacing of the extension 21 in the X direction, and the avalanche resistance decreases as the spacing of the extension 21 in the X direction becomes wider. Therefore, in the semiconductor device 2, the discharge of holes can be promoted and the reduction of the avalanche resistance can be prevented by providing the protrusion 19 of the p-type anode layer 13 between the adjacent extensions 21 in the X direction.

[0049] Figure 6 1 is a schematic cross-sectional view showing a semiconductor device 3 according to another modified example of the first embodiment. In the semiconductor device 3, the p-type semiconductor layer 17 is not provided inside the n-type semiconductor layer 11. That is, one end of the extension portion 21 of the anode electrode 20 is located in the n-type semiconductor layer 11. In addition, the portion of the extension portion 21 located in the n-type semiconductor layer 11 is in Schottky contact with the n-type semiconductor layer 11.

[0050] Fig. 7A and Figure 7B It is a schematic diagram showing the flow of carriers in the n-type semiconductor layer 11 of the semiconductor device 3 . Fig. 7A The case where the semiconductor device 3 is forward biased (on state) is shown. Figure 7B The flow of carriers in a transition period when the bias of the semiconductor device 3 is switched from the forward direction to the reverse direction (off state) is shown.

[0051] exist Fig. 7AIn the on-state shown, the electrons in the n-type semiconductor layer 11 flow mainly toward the anode electrode 20 via the extension portion 21. The electrons in the n-type semiconductor layer 11 flow efficiently toward the anode electrode 20 via the extension portion 21. For this reason, the amount of electrons in the n-type semiconductor layer 11 decreases, and to balance this, the amount of holes injected from the p-type anode layer 13 also decreases.

[0052] Figure 7B The flow of carriers during the transition period from the on state to the off state is shown. The holes in the n-type semiconductor layer 11 are rapidly discharged to the anode electrode 20 via the extension portion 21 .

[0053] In the semiconductor device 3, the carrier amount in the n-type semiconductor layer 11 is reduced, and holes in the n-type semiconductor layer 11 are quickly discharged to the anode electrode 20 via the extension portion 21. Therefore, the transition period from the on state to the off state during shutdown can be shortened, and the switching loss can be further reduced.

[0054] (Second embodiment)

[0055] Figure 8 2 is a schematic cross-sectional view showing a semiconductor device 4 according to the second embodiment. Figure 8 As shown, the semiconductor device 4 includes a metal layer 23 located in the p-type semiconductor layer 17. The metal layer 23 is arranged to be connected to the extension 21 of the anode electrode 20. The metal layer 23 is arranged not to be in contact with the n-type semiconductor layer 11, for example.

[0056] The metal layer 23 is provided to be in Schottky contact with the p-type semiconductor layer 17. For example, the metal layer 23 includes a metal having a work function smaller than the work function of the metal included in the portion of the extension 21 that contacts the n-type semiconductor layer 11, at least in the portion that contacts the p-type semiconductor layer 17. For example, the metal layer 23 includes one of titanium (Ti), tantalum (Ta) and molybdenum (Mo) at least in the portion that contacts the p-type semiconductor layer 17.

[0057] Fig.9A and Fig. 9B It is a schematic diagram showing the flow of carriers in the n-type semiconductor layer 11 of the semiconductor device 4 according to the second embodiment. Fig.9A The case where the semiconductor device 4 is forward biased (on state) is shown. Fig. 9B The flow of carriers in a transition period when the bias of the semiconductor device 4 is switched from the forward direction to the reverse direction (off state) is shown.

[0058] exist Fig.9AIn the on-state shown, electrons in the n-type semiconductor layer 11 flow toward the anode electrode 20 via the contact portion CP of the extension portion 21. For this reason, the amount of electrons in the n-type semiconductor layer 11 can be reduced. Correspondingly, the amount of holes injected from the p-type anode layer 13 to the n-type semiconductor layer 11 is also reduced. Furthermore, the Schottky junction formed between the metal layer 23 and the p-type semiconductor layer 17 suppresses the injection of holes from the p-type semiconductor layer 17 to the n-type semiconductor layer 11.

[0059] Fig. 9B Indicates the flow of carriers during the transition period from the on state to the off state. The holes in the n-type semiconductor layer 11 are mainly discharged to the anode electrode 20 via the p-type anode layer 13. The amount of holes discharged to the anode electrode 20 via the p-type semiconductor layer 17 is reduced by the metal layer 23. In addition, the electrons in the n-type semiconductor layer 11 are discharged to the cathode electrode 30 via the n-type cathode layer 15.

[0060] In the semiconductor device 4, by reducing the amount of carriers in the n-type semiconductor layer 11 in the on state, the switching loss during the transition period from the on state to the off state can be reduced. In addition, by suppressing the hole injection from the p-type semiconductor layer 17 to the n-type semiconductor layer 11, current concentration can be avoided, and the withstand voltage of the semiconductor device 4 can be improved.

[0061] (Third embodiment)

[0062] Fig.10 1 is a schematic cross-sectional view showing a semiconductor device 5 according to a third embodiment. The semiconductor device 5 is, for example, an IGBT, and includes a portion that functions as an IGBT (IGBT region) and a portion that functions as an FRD (Fast Recovery Diode) (FRD region).

[0063] like Fig.10 As shown, the semiconductor device 5 includes a semiconductor portion 50, an emitter electrode 60, a collector electrode 70, and a gate electrode 80. The semiconductor portion 50 is provided between the emitter electrode 60 and the collector electrode 70. The gate electrode 80 is arranged in the IGBT region, for example, in the gate trench GT provided on the surface of the semiconductor portion 50 on the emitter electrode 60 side. For example, a plurality of gate electrodes 80 are provided and arranged along the surface of the semiconductor portion 50.

[0064] In addition, the gate electrode 80 may be configured to include, for example, a plurality of portions arranged along the surface of the semiconductor portion 50. That is, the gate electrode 80 may be an integrated electrode connected via portions not shown.

[0065] The semiconductor portion 50 includes an n-type base layer 51 , a p-type base layer 53 , an n-type emitter layer 55 , a p-type contact layer 56 , an n-type buffer layer 57 , and a p-type collector layer 59 .

[0066] The p-type base layer 53 is provided between the n-type base layer 51 and the emitter electrode 60. The n-type emitter layer 55 is selectively provided between the p-type base layer 53 and the emitter electrode 60. The p-type contact layer 56 is selectively provided between the p-type base layer 53 and the emitter electrode 60. The n-type emitter layer 55 and the p-type contact layer 56 are arranged along the surface of the semiconductor portion 50.

[0067] The n-type emitter layer 55 and the p-type contact layer 56 are arranged in the IGBT region and provided between gate electrodes 80 adjacent to each other in the direction along the surface of the semiconductor portion 50 . The p-type contact layer 56 includes p-type impurities having a higher concentration than that of the p-type base layer 53 .

[0068] The emitter electrode 60 covers the surface of the semiconductor portion 50 and is in contact with the n-type emitter layer 55 and the p-type contact layer 56. The emitter electrode 60 is electrically connected to the p-type base layer 53 via the n-type emitter layer 55 and the p-type contact layer 56.

[0069] The gate electrode 80 is disposed opposite to the n-type base layer 51 , the p-type base layer 53 , and the n-type emitter layer 55 via the gate insulating film 83 . The gate electrode 80 is electrically insulated from the emitter electrode 60 by the interlayer insulating film 85 .

[0070] The emitter electrode 60 has an extension portion 61 provided in the FRD region. The extension portion 61 extends in a direction (−Z direction) toward the collector electrode 70 while penetrating the p-type base layer 53 .

[0071] The semiconductor portion 50 further includes a p-type semiconductor layer 63 provided in the n-type base layer 51. The p-type semiconductor layer 63 is arranged at a position separated from the p-type base layer 53 in the FRD region.

[0072] The extension 61 of the emitter electrode 60 is provided to be connected to the p-type semiconductor layer 63. The extension 61 includes a contact portion CP contacting the n-type base layer 51 between the p-type base layer 53 and the p-type semiconductor layer 63. The extension 61 includes a material in Schottky contact with the n-type base layer 51 at the contact portion CP.

[0073] The n-type buffer layer 57 is provided between the n-type base layer 51 and the collector electrode 70. The n-type buffer layer 57 includes n-type impurities at a higher concentration than the n-type impurities of the n-type base layer 51. The n-type buffer layer 57 is provided, for example, in contact with the collector electrode 70 in the FRD region. In addition, an n-type buffer layer 57 may be provided between the n-type buffer layer 57 and the collector electrode 70. + Type contact layer 58.+ The n-type contact layer 58 includes an n-type impurity having a higher concentration than the n-type impurity of the n-type buffer layer 57 , and is electrically connected to the collector electrode 70 .

[0074] P-type collector layer 59 is provided between n-type buffer layer 57 and collector electrode 70 in the IGBT region. P-type collector layer 59 includes p-type impurities having a higher concentration than p-type impurities of p-type base layer 53. P-type collector layer 59 is provided in contact with collector electrode 70, for example.

[0075] The semiconductor device 5 according to this embodiment can discharge holes in the n-type base layer 51 to the emitter electrode 60 via the p-type semiconductor layer 63 and the extension 61 during the transition period when the FRD portion switches from the on state to the off state. This can reduce switching loss in the semiconductor device 5 .

[0076] Here, including Figure 1 The IGBT of the structure shown in FIG. is described as an example, but the implementation is not limited to this. For example, it is possible to apply Figure 4 , Figure 6 and Figure 8 The structure shown can also be combined with MOSFET.

[0077] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: 1st electrode; a second electrode disposed at a position opposing the first electrode; and The semiconductor portion is provided between the first electrode and the second electrode and includes a first semiconductor layer of a first conductivity type. The above-mentioned Semiconductor Division also includes: A second semiconductor layer of a second conductivity type, provided between the first semiconductor layer and the first electrode; and a third semiconductor layer of the second conductivity type, which is selectively provided in the first semiconductor layer and is arranged at a position separated from the second semiconductor layer, The first electrode has an extension portion, the extension portion is electrically connected to the second semiconductor layer, extends in a first direction toward the second electrode so as to penetrate the second semiconductor layer, and is connected to the third semiconductor layer. The extension portion of the first electrode includes a first portion located in the third semiconductor layer and a second portion in contact with the first semiconductor layer. The first portion includes a first metal, and the second portion includes a second metal having a larger work function than the first metal.

2. The semiconductor device according to claim 1, wherein The first electrode is in contact with and electrically connected to the second semiconductor layer.

3. The semiconductor device according to claim 1, wherein The extension portion is in Schottky contact with the first semiconductor layer at a portion located between the second semiconductor layer and the third semiconductor layer.

4. The semiconductor device according to claim 1, wherein The semiconductor portion further includes a first conductivity type fourth semiconductor layer provided between the first semiconductor layer and the second electrode and including first conductivity type impurities having a higher concentration than the first conductivity type impurities of the first semiconductor layer.

5. The semiconductor device according to claim 4, wherein: The second electrode is in contact with and electrically connected to the fourth semiconductor layer.

6. The semiconductor device according to claim 1, wherein The second portion is in Schottky contact with the first semiconductor layer.

7. The semiconductor device according to claim 1, wherein The extension portion of the first electrode and the third semiconductor layer are respectively provided in plurality. The extension portions are arranged in a second direction along a boundary between the first semiconductor layer and the second semiconductor layer and are connected to the third semiconductor layer, respectively. The second semiconductor layer has a protruding portion extending in the first direction, and the protruding portion is provided between two extending portions arranged at adjacent positions in the second direction.

8. The semiconductor device according to claim 7, wherein: The semiconductor portion further includes a fifth semiconductor layer, the fifth semiconductor layer being selectively provided between the first electrode and the second semiconductor layer and including a second conductivity type impurity having a higher concentration than a second conductivity type impurity of the second semiconductor layer. The fifth semiconductor layer is located between the first electrode and the protrusion.

9. The semiconductor device according to claim 8, wherein: The first electrode is in contact with and electrically connected to the fifth semiconductor layer.

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