Semiconductor device structure and forming method thereof

Abstract

A semiconductor device structure and a method of forming the same are described. The structure includes a first semiconductor material disposed over a substrate and a dielectric layer disposed on the first semiconductor material. The dielectric layer includes a dopant. The structure further includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes a dopant.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of connected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be manufactured using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] Therefore, there is a need for improvements in the processing and manufacturing of ICs. Summary of the invention

[0004] According to one aspect of the present application, a semiconductor device structure is provided, comprising: a first semiconductor material, disposed on a substrate; a dielectric layer, disposed on the first semiconductor material, wherein the dielectric layer comprises a dopant; a second semiconductor material, disposed on the dielectric layer; the first semiconductor layer, in contact with the second semiconductor material; and a first dielectric spacer, in contact with the first semiconductor layer, wherein the first dielectric spacer comprises a dopant.

[0005] In some implementations, the dopant includes Si, F, or B.

[0006] In some implementations, a dopant concentration of the first dielectric spacer decreases in a direction away from the second semiconductor material.

[0007] In some implementations, the dopant concentration of the dielectric layer increases in a direction away from the first semiconductor material.

[0008] In some implementations, the semiconductor device structure further includes a second semiconductor layer in contact with the second semiconductor material, wherein the second semiconductor layer is disposed over the first semiconductor layer, and the first dielectric spacer is disposed between the first semiconductor layer and the second semiconductor layer.

[0009] In some implementations, the semiconductor device structure further includes a second dielectric spacer in contact with the second semiconductor layer, wherein the second dielectric spacer and the first and second semiconductor layers are doped with a dopant.

[0010] In some implementations, the thickness of the dielectric layer is 50% to 80% of the thickness of the first dielectric spacer, and a top surface of the dielectric layer is located lower than a bottom surface of the first semiconductor layer.

[0011] According to one aspect of the present application, a method is provided, comprising: forming a sacrificial gate stack over a portion of a fin structure; removing an exposed portion of the fin structure to expose a portion of a substrate and a surface of a semiconductor layer of the fin structure; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a bottom portion disposed on the first semiconductor material and a sidewall portion disposed on the surface of the semiconductor layer; removing the sidewall portion of the dielectric layer; performing an implantation process to implant dopants into the bottom portion of the dielectric layer; performing an annealing process on the bottom portion of the dielectric layer; and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0012] In some implementations, the dopant concentration of the dielectric layer is between 5×10 20 cm -3 Up to 1×10 21 cm -3 within the range.

[0013] In some implementations, the implant process implants dopants into gate spacers formed along sidewalls of the sacrificial gate stack.

[0014] In some implementations, the annealing process includes flash lamp annealing FLA, laser spike annealing LSA, or rapid thermal annealing RTA.

[0015] In some implementations, the annealing process includes FLA or LSA, the annealing temperature is in a range of 1050 degrees Celsius to 1200 degrees Celsius, and the dwell time of the annealing process is in a range of 0.1 ms to 40 ms.

[0016] In some implementations, the annealing process includes RTA, the annealing temperature ranges from 600 degrees Celsius to 1000 degrees Celsius, and the dwell time of the annealing process ranges from 1 second to 20 seconds.

[0017] In some implementations, the bottom portion of the dielectric layer has a center portion and an edge portion, the center portion has a first thickness, and the edge portion has a second thickness that is substantially less than the first thickness.

[0018] In some implementations, the method further includes a wet cleaning process after the annealing process and before forming the second semiconductor material, wherein after the wet cleaning process, a thickness of a bottom portion of the dielectric layer is in a range of 2 nm to 5 nm.

[0019] According to one aspect of the present application, a method is provided, comprising: forming a fin structure from a substrate, wherein the fin structure includes a first plurality of semiconductor layers and a second plurality of semiconductor layers; forming a sacrificial gate stack above the fin structure; depositing a gate spacer on the sacrificial gate stack; removing a portion of the fin structure to expose a portion of the substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a sidewall portion in contact with the gate spacer, the first plurality of semiconductor layers and the dielectric spacer, and a bottom portion in contact with the first semiconductor material; removing the sidewall portion of the dielectric layer; performing an implantation process to implant dopants into the bottom portion of the dielectric layer; performing an annealing process on the bottom portion of the dielectric layer; and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0020] In some implementations, removing a sidewall portion of the dielectric layer includes: depositing a mask layer on the dielectric layer; recessing the mask layer to expose a portion of the sidewall portion of the dielectric layer; removing the exposed portion of the sidewall portion of the dielectric layer; recessing the remaining sidewall portion of the dielectric layer; removing the mask layer; and removing the remaining sidewall portion.

[0021] In some implementations, the method further includes a wet cleaning process after the annealing process and before forming the second semiconductor material.

[0022] In some implementations, the wet etch rate of the dielectric layer is reduced by the implantation process.

[0023] In some implementations, the second semiconductor material is grown from the first plurality of semiconductor layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0025] Figure 1-Figure 5 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0026] Figure 6-Figure 18 According to some embodiments, Figure 5 Line AA captures cross-sectional side views of various stages in the fabrication of a semiconductor device structure. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0028] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "above," "top," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0029] Embodiments of the present disclosure provide a semiconductor device structure having a dielectric layer, which is disposed between two semiconductor materials in a source / drain region. Prior to a wet cleaning process, an implantation process and an annealing process are performed on the dielectric layer. Therefore, a wet etch rate (WER) of the dielectric layer is reduced, and the thickness of the dielectric layer is increased. A thicker dielectric layer can reduce current leakage.

[0030] Although embodiments of the present disclosure are discussed with respect to nanostructured channel FETs (e.g., gate allaround (GAA) FETs, such as horizontal gate allaround (HGAA) FETs or vertical gate allaround (VGAA) FETs), implementations of some aspects of the present disclosure may be used for other processes and / or other devices, such as planar FETs, Fin-FETs, and other suitable devices. A person of ordinary skill in the art will readily appreciate other modifications that may be made within the scope of the present disclosure. In the case of a gate allaround (GAA) transistor structure, the GAA transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes (including a double patterning process or a multi-patterning process). Typically, a double patterning process or a multi-patterning process combines a photolithography process with a self-alignment process, allowing the creation of a pattern having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A spacer is formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer may be used to pattern the GAA structure.

[0031] Figure 1-Figure 18 FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It will be understood that Figure 1-Figure 18 Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated for other embodiments of the method. The order of the operations / processes is not limiting and may be interchanged.

[0032] Figure 1-Figure 5 1 is a perspective view of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. Figure 1 As shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhancement. In one aspect, the insulating layer is an oxygen-containing layer.

[0033] The substrate 101 may include various regions doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopant may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0034] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructured channels in multi-gate devices (e.g., nanostructured channel FETs). In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si and the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, any one of the semiconductor layers 106, 108 may be or may include other materials, for example, Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0035] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the layers of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0036] The first semiconductor layer 106 or a portion thereof may form (one or more) nanostructure channels of the semiconductor device structure 100 in a later manufacturing stage. The term nanostructure is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Therefore, the term refers to both elongated material portions of circular and substantially circular cross-sections, and beam-shaped or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. (One or more) nanostructure channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate all around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0037] The thickness of each first semiconductor layer 106 may be in a range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 is in a range between about 2 nm and about 50 nm. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and does not limit the contents specifically described in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100. In some embodiments, the semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes four first semiconductor layers 106.

[0038] like Figure 2 As shown, the fin structure 112 is formed by the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108, and a well portion 116 formed by the substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including a photolithography process and an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including a photoresist layer. In some embodiments, patterning the photoresist layer to form a masking element can be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 in the unprotected areas, through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend along the X direction. The trenches 114 may be etched using dry etching (e.g., RIE), wet etching, and / or a combination thereof.

[0039] like Figure 3As shown, after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation is performed, for example, a chemical mechanical polishing (CMP) method and / or an etch-back method, so that the top of the fin structure 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, for example, low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD).

[0040] like Figure 4 As shown, the insulating material 118 is recessed to form an isolation region 120. The recessing of the insulating material 118 exposes some portions of the fin structure 112, for example, the semiconductor layer stack 104. The recessing of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process, for example, a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 that contacts the well portion 116 formed from the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI) region.

[0041] like Figure 5 As shown, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed as follows: a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 is deposited in sequence, and then the layers are patterned into the sacrificial gate structure 130. Although one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the X direction. In some embodiments, as Figure 11-Figure 15 As shown, three sacrificial gate structures 130 are arranged along the X direction.

[0042] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0043] Figure 6-Figure 18 According to some embodiments, Figure 5 The cross-sectional side views of various stages of manufacturing the semiconductor device structure 100 are obtained along the line AA. Figure 6 As shown, the first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120 and the sacrificial gate structure 130. The first gate spacer 138 can be made of a dielectric material, for example, silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON and / or a combination thereof. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed by a conformal process (e.g., an atomic layer deposition (ALD) process).

[0044] like Figure 7 As shown, the second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, for example, SiOx, SiON, SiN, SiCON or SiCO. The thickness of the second gate spacer 139 may be in the range of about 0.5nm to about 5nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited by CVD, PECVD or electron cyclotron resonance CVD (ECR-CVD).

[0045] like Figure 8 As shown, horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed by an anisotropic etching process. The anisotropic etching process may be a selective etching process that does not substantially affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120.

[0046] like Fig. 9As shown, portions of the fin structure 112 that are not covered by the sacrificial gate structure 130, and the first gate spacer 138 and the second gate spacer 139 are recessed to a level above, located at, or below the top surface of the isolation region 120. The recessing of these portions of the fin structure 112 can be accomplished by an etching process. The etching process can be a dry etch (e.g., RIE, NBE, etc.) or a wet etch (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). Fig. 9 As shown, the well portion 116 is exposed on an opposite side of the sacrificial gate structure 130 .

[0047] like Fig.10 As shown, the edge portion of each second semiconductor layer 108 of the semiconductor layer stack 104 is horizontally removed along the X direction. The edge portion of the second semiconductor layer 108 is removed to form a cavity. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant (such as but not limited to ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP) or potassium hydroxide (KOH) solution) can be used to selectively etch the second semiconductor layer 108.

[0048] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-K dielectric material, for example, SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 may be formed as follows: a conformal dielectric layer is first formed using a conformal deposition process (e.g., ALD), and then anisotropic etching is performed to remove the portion of the conformal dielectric layer other than the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0049] like Fig.11As shown, trenches 151 are formed between adjacent semiconductor layer stacks and between adjacent sacrificial gate structures 130. As described above, in some embodiments, the mask layer 136 includes an oxide layer 133 and a nitride layer 135. A first semiconductor material 150 is formed on the exposed well portion 116 at the bottom of the trench 151. In some embodiments, the first semiconductor material 150 includes undoped silicon or undoped SiGe. The first semiconductor material 150 may first be formed on a semiconductor surface, for example, on the exposed well portion 116 and on the first semiconductor layer 106, by epitaxy. A subsequent etching process is performed to remove a portion of the first semiconductor material 150 formed on the first semiconductor layer 106. As a result of the etching process, the first semiconductor material 150 formed on the exposed well portion 116 may form a concave top surface. In some embodiments, the thickness of the first semiconductor material 150 along the Z direction is in a range of about 5 nm to about 50 nm.

[0050] Next, if Fig.11 As shown, a dielectric layer 152 is formed on the semiconductor device structure 100. The dielectric layer 152 is formed in the trench 151 and is formed on the sacrificial gate structure 130 and the first gate spacer 138 and the second gate spacer 139. The dielectric layer 152 may include any suitable dielectric material. In some embodiments, the dielectric layer 152 includes SiN. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by CVD. The portion of the dielectric layer 152 formed on the vertical surface may have a first thickness T1, and the portion of the dielectric layer 152 formed on the horizontal surface may have a second thickness T2, and the second thickness T2 is significantly greater than the first thickness T1. In some embodiments, the dielectric layer 152 includes a sidewall portion disposed on the vertical surface inside each trench 151 and a bottom portion disposed on the first semiconductor material 150. For example, as Fig.11As shown, the sidewall portion of the dielectric layer 152 can be formed on the vertical surfaces of the dielectric spacer 144, the first semiconductor layer 106, and the first gate spacer 138 and the second gate spacer 139. In some embodiments, the sidewall portion of the dielectric layer 152 has a thickness T1, and the bottom portion of the dielectric layer 152 has a thickness T2, and the thickness T2 is significantly greater than the first thickness T1. In some embodiments, the width of the trench 151 in the X direction is in the range of about 22nm to about 26nm, and the thickness T2 can be greater than about 5nm and less than about 10nm. If the thickness T2 is greater than about 10nm, the dielectric layer 152 can be connected at the top of the trench 151. In other words, the dielectric layer 152 can seal the trench 151 and form a gap therein. The bottom portion of the dielectric layer 152 can be used as an isolation layer to prevent current leakage through the portion of the well portion 116 located below the bottommost second semiconductor layer 108. Therefore, if the thickness T2 is less than about 5 nm, the bottom portion of the dielectric layer 152 may be too thin to fully function as an isolation layer.

[0051] like Fig.12 As shown, a mask layer 154 is formed on the dielectric layer 152 and partially fills the trench 151. The mask layer 154 may be a bottom anti-reflective coating (BARC) layer. The mask layer 154 may be formed as follows: first, a layer that completely fills the trench 151 and is above the sacrificial gate structure 130 is formed, and then the layer is recessed to form the mask layer 154. In some embodiments, the mask layer 154 may be recessed by a selective etching process that does not significantly affect the dielectric layer 152. The selective etching process may be dry etching, wet etching, or a combination thereof. In some embodiments, the selective etching process is wet etching. The mask layer 154 contacts a first portion of the sidewall portion of the dielectric layer 152 in the trench 151, and a second portion of the sidewall portion of the dielectric layer 152 in the trench 151 is exposed. In some embodiments, as Fig.12 As shown, the top surface of the mask layer 154 in the trench 151 is located at a level between the top surface and the bottom surface of the sacrificial gate electrode layer 134. In some embodiments, the top surface of the mask layer 154 in the trench 151 is located at a level below the bottom surface of the sacrificial gate electrode layer 134, for example, a level below the topmost first semiconductor layer 106, such as between the top surface and the bottom surface of the second first semiconductor layer 106 from the bottom. The sidewall portion of the dielectric layer 152 will be removed in a subsequent process, and the bottom portion of the dielectric layer 152 will remain. Therefore, the mask layer 154 protects the bottom portion of the dielectric layer 152 during the subsequent removal of the second portion of the sidewall portion of the dielectric layer 152 and the subsequent recessing of the first portion of the sidewall portion of the dielectric layer 152.

[0052] like Fig.13As shown, the exposed second portions of the sidewall portions of the dielectric layer 152 in each trench 151, and the portions of the dielectric layer 152 located above the sacrificial gate structure 130 and the first and second gate spacers 138 and 139 are removed. These portions of the dielectric layer 152 may be removed by a selective etching process, such as dry etching, wet etching, or a combination thereof. The selective etching process removes the exposed second portions of the sidewall portions of the dielectric layer 152, but does not significantly affect the mask layer 154, the first and second gate spacers 138 and 139, and the mask layer 136. The remaining first portions of the sidewall portions of the dielectric layer 152 located in the trenches 151 may include a top surface that is substantially coplanar with a top surface of the mask layer 154, as shown in FIG. Fig.13 shown.

[0053] like Fig.14 As shown, the mask layer 154 and the first portion of the sidewall portion of the dielectric layer 152 are removed. The mask layer 154 and the sidewall portion of the dielectric layer 152 can be removed by any suitable process. In some embodiments, the first portion of the sidewall portion of the dielectric layer 152 is first recessed by a selective etching process, and the top surface of the recessed dielectric layer 152 is substantially below the top surface of the mask layer 154. The selective etching process recesses the dielectric layer 152 but does not significantly affect the mask layer 136, the first gate spacer 138 and the second gate spacer 139, and the mask layer 154. In some embodiments, the top surface of the recessed dielectric layer 152 is located between the top surface and the bottom surface of the bottommost first semiconductor layer 106. In some embodiments, the selective etching process for recessing the first portion of the sidewall portion of the dielectric layer 152 and the selective etching process for removing the exposed second portion of the sidewall portion of the dielectric layer 152 are the same selective etching process. In other words, a single selective etching process is performed to remove the exposed second portion of the sidewall portion of the dielectric layer 152 and to recess the first portion of the sidewall portion of the dielectric layer 152 .

[0054] Next, the mask layer 154 is removed. The mask layer 154 can be removed by a selective process. In some embodiments, the mask layer 154 is removed using a stripping process, for example, using a solvent or an oxygen plasma. The selective process for removing the mask layer 154 does not significantly affect the mask layer 136, the first gate spacer 138 and the second gate spacer 139, the first semiconductor layer 106, the dielectric spacer 144, and the dielectric layer 152. After removing the mask layer 154, the dielectric layer 152 includes a sidewall portion (which is a first portion of the sidewall portion that is recessed) and a bottom portion. As described above, the top surface of the sidewall portion of the dielectric layer 152 can be located at a level between the top surface and the bottom surface of the bottommost first semiconductor layer 106.

[0055] Next, an etching process is performed to remove the sidewall portion of the dielectric layer 152, while the bottom portion of the dielectric layer 152 remains. As described above, the sidewall portion of the dielectric layer 152 has a thickness T1, which is significantly less than the thickness T2 of the bottom portion of the dielectric layer 152. Therefore, the etching process completely removes the sidewall portion of the dielectric layer 152 while reducing the thickness T2 of the bottom portion of the dielectric layer 152. In some embodiments, after removing the sidewall portion of the dielectric layer 152, the thickness T2 of the bottom portion of the dielectric layer 152 is in a range of about 5 nm to about 8 nm. The etching process may be any suitable etching process, for example, a dry etching process, a wet etching process, or a combination thereof.

[0056] After the etching process to remove the sidewall portion of the dielectric layer 152, the dielectric layer 152 (the remaining bottom portion) is disposed on the first semiconductor material 150, such as Fig.14 As shown. Next, an implantation process is performed on the dielectric layer 152, followed by an annealing process to reduce the WER of the dielectric layer 152. In some embodiments, the implantation process includes implanting dopants in the dielectric layer 152. For example, the dielectric layer 152 includes SiN, and the dopant may include Si, F, B, or any suitable dopant. Doping gases, such as silicon-containing gas, fluorine-containing gas, or boron-containing gas, may be used during the implantation process. The implantation energy of the implantation process is in the range of about 0.2 keV to about 5 keV, the implantation temperature is in the range of about -60 degrees Celsius to about 450 degrees Celsius, the implantation tilt angle is in the range of about 0 degrees to about 15 degrees, and the substrate rotation is in the range of about 0 degrees to about 360 degrees. The dopant concentration may be in the range of about 5×10 20 cm -3 About 1×10 21 cm -3 As described above, the implantation process reduces the WER of the dielectric layer 152. Therefore, if the dopant concentration of the dielectric layer 152 is less than about 5×10 20 cm -3 , the WER of the dielectric layer 152 will not be reduced, and the thickness of the dielectric layer 152 will be significantly reduced during the subsequent wet cleaning process. On the other hand, if the dopant concentration of the dielectric layer 152 is greater than about 1×10 21 cm -3 , the quality of the subsequently formed second semiconductor material 156 may be negatively affected. In some embodiments, the dopant concentration of the dielectric layer 152 increases in a direction away from the first semiconductor material 150 .

[0057] In some embodiments, prior to the implantation process, dielectric layer 152 has a first silicon concentration. The first silicon concentration may be substantially uniform in dielectric layer 152. After the implantation process, in embodiments where the dopant is silicon, dielectric layer 152 has a second silicon concentration that is significantly greater than the first silicon concentration. In some embodiments, the dopant is B or F, and prior to the implantation process, dielectric layer 152 is substantially free of the dopant. After the implantation process, the concentration profile of the dopant increases from the bottom surface of dielectric layer 152 to the top surface of dielectric layer 152.

[0058] In some embodiments, the exposed layers (e.g., the first gate spacers 138 and the second gate spacers 139, the first semiconductor layer 106, and the dielectric spacers 144) may also be doped with dopants from the implantation process. Therefore, in some embodiments, the first gate spacers 138 and the second gate spacers 139, the first semiconductor layer 106, and the dielectric spacers 144 include dopants located at the respective surfaces exposed in the trench 151. In some embodiments, the dopant is Si, and the silicon concentration of the first gate spacers 138 and the second gate spacers 139, the first semiconductor layer 106, and the dielectric spacers 144 at and near the respective surfaces exposed in the trench 151 is significantly greater than the silicon concentration in other areas of the first gate spacers 138 and the second gate spacers 139, the first semiconductor layer 106, and the dielectric spacers 144. In other words, the dopant concentration of the first gate spacers 138 and the second gate spacers 139, the first semiconductor layer 106, and the dielectric spacers 144 decreases in a direction away from the trench 151. In some embodiments, the dopant passes through the dielectric layer 152 and diffuses into the first semiconductor material 150. Thus, the first semiconductor material 150 may include the dopant near the interface between the first semiconductor material 150 and the dielectric layer 152.

[0059] After the implantation process, an annealing process is performed to drive off hydrogen to densify the dielectric layer 152. The annealing process may be any suitable annealing process. In some embodiments, the annealing process may be a flash lamp annealing (FLA), a laser spike annealing (LSA), or a rapid thermal annealing (RTA). The annealing temperature may be in the range of about 1050 degrees Celsius to about 1200 degrees Celsius for FLA or LSA, and in the range of about 600 degrees Celsius to about 1000 degrees Celsius for RTA. The dwell time of the annealing process may be in the range of about 0.1 ms to about 40 ms for FLA or LSA, and in the range of about 1 s to about 20 s for RTA. During the annealing process, the chamber pressure may be in the range of about 1 torr to about 760 torr.

[0060] As a result of the implantation process and annealing process, Fig.14The dielectric layer 152 shown has a reduced WER. In some embodiments, the WER is improved by 75%. Fig.14 The dielectric layer 152 shown is not previously subjected to an implantation process and an annealing process. In other words, the implantation process and the annealing process are performed after the sidewall portion of the dielectric layer 152 is removed. For example, if the implantation process and the annealing process are performed before the sidewall portion of the dielectric layer 152 is removed, the sidewall portion of the dielectric layer 152 is removed. Fig.11 If performed after depositing dielectric layer 152 as shown, the dopants in dielectric layer 152 may cause sidewall portions of dielectric layer 152 to be more difficult to remove.

[0061] After the implantation process and the annealing process, a wet cleaning process is performed to remove native oxide and other contaminants from the semiconductor device structure 100. The wet cleaning process may use any suitable solution, for example, deionized water (DI), SC1 (DI, NH4OH and / or H2O2), SC2 (DI, HCl and / or H2O2), ozone deionized water (DIWO3), SPM (H2SO4 and / or H2O2), SOM (H2SO4 and / or O3), SPOM, H3PO4, dilute hydrofluoric acid (DHF), HF, HF / ethylene glycol (EG), HF / HNO3, NH4OH, or tetramethylammonium hydroxide (TMAH). Since the implantation process and the annealing process reduce the WER, the dielectric layer 152 is substantially unaffected by the wet cleaning process. Without the implantation process and the annealing process, the thickness of the dielectric layer 152 may be significantly reduced by the wet cleaning process, which may cause current leakage. In some embodiments, if the implantation process and the annealing process are not performed on the dielectric layer 152, the wet cleaning process may reduce the thickness of the dielectric layer 152 by 1 nm or more. In some embodiments, after the wet cleaning process, the thickness T2 of the dielectric layer 152 is in the range of about 2 nm to about 5 nm. In some embodiments, the bottom surface of the dielectric layer 152 may be located at the same level as the bottom surface of the dielectric spacer 144, and the thickness T2 of the dielectric layer 152 may be about 50% to about 80% of the thickness of the dielectric spacer 144. If the thickness T2 of the dielectric layer 152 is less than about 50% of the thickness of the dielectric spacer 144, the dielectric layer 152 may be too thin to prevent current leakage. On the other hand, if the thickness T2 of the dielectric layer 152 is greater than about 80% of the thickness of the dielectric spacer 144, the quality of the second semiconductor material 156 may be negatively affected because the dielectric layer 152 is too close to the first semiconductor layer 106. In some embodiments, the dielectric layer 152 has a varying thickness due to the wet cleaning process. For example, edge portions of the dielectric layer 152 adjacent to the dielectric spacer 144 may be thinner than a central portion of the dielectric layer 152. In some embodiments, the thickness of the edge portions of the dielectric layer 152 is in a range of about 1.5 nm to about 2.5 nm, and the thickness of the central portion of the dielectric layer 152 is in a range of about 3 nm to about 4 nm.

[0062] In some embodiments, the distance along the Z direction from the bottom surface of the bottommost first semiconductor layer 106 to the top surface of the topmost first semiconductor layer 106 is in the range of about 30nm to about 60nm, and the distance from the top surface of the topmost first semiconductor layer 106 to the top surface of the nitride layer 135 can be in the range of about 120nm to about 150nm.

[0063] like Fig.15As shown, a second semiconductor material 156 is formed in the trench 151, and the second semiconductor material 156 can be epitaxially grown from the first semiconductor layer 106. The second semiconductor material 156 can grow in both horizontal and vertical directions to form facets, which can correspond to the crystal planes of the material used for the first semiconductor layer 106. The second semiconductor material 156 can be a source / drain (S / D) region. In the present disclosure, the source region and the drain region are used interchangeably, and their structures are basically the same. In addition, (one or more) source / drain regions can refer to the source or drain individually or collectively, depending on the context. The second semiconductor material 156 can be made of one or more layers of Si, SiP, SiC and SiCP for n-channel FETs, or can be made of Si, SiGe, Ge for p-channel FETs. For p-channel FETs, the second semiconductor material 156 can also include p-type dopants, such as boron (B). The second semiconductor material 156 can be formed by an epitaxial growth method using CVD, ALD or MBE.

[0064] like Fig.16 As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 120, and the second semiconductor material 156. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL 162 is a single layer, such as Fig.16 As shown. In some embodiments, CESL 162 includes two or more layers. Next, an interlayer dielectric (ILD) layer 164 is formed on CESL 162. The material of ILD layer 164 may include a compound containing Si, O, C and / or H, for example, silicon oxide, SiCOH or SiOC. Organic materials (for example, polymers) may also be used for ILD layer 164. ILD layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming ILD layer 164, semiconductor device structure 100 may be thermally treated to anneal ILD layer 164.

[0065] After forming the ILD layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. Fig.16 shown.

[0066] like Fig.17As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening between the first gate spacers 138 and between the first semiconductor layer 106. During the removal process, the ILD layer 164 protects the second semiconductor material 156. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be first removed by any suitable process such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 is removed, which can also be performed by any suitable process such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.

[0067] The second semiconductor layer 108 can be removed using a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemistry used in the selective wet etching process removes SiGe without significantly affecting the dielectric material of Si, the first gate spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0068] like Fig.18As shown, after forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the exposed surface of the first semiconductor layer 106 and the gate dielectric layer 170. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride or high-K dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-K dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, other suitable high-K dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD or any suitable deposition technique. The gate electrode layer 172 may include one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or any combination thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed on the ILD layer 164 are then removed by using, for example, CMP until the upper surface of the ILD layer 164 is exposed.

[0069] It is understood that the semiconductor device structure 100 can be further processed to form a conductive contact in the ILD layer 164 to electrically connect to the second semiconductor material 156, and to form a conductive contact to electrically connect to the gate electrode layer 172. An interconnect structure can be formed over the semiconductor device structure 100 to provide an electrical path for devices formed on the substrate 101.

[0070] Embodiments of the present disclosure provide a semiconductor device structure including a dielectric layer 152 disposed between a first semiconductor material 150 and a second semiconductor material 156. An implantation process is performed to implant dopants into the dielectric layer 152, and the implantation process may also implant dopants into the first gate spacer 138, the dielectric spacer 144, and the first semiconductor layer 106. Some embodiments may achieve advantages. For example, the dielectric layer 152 including the dopant has a reduced WER. Therefore, the thickness of the dielectric layer 152 is not significantly affected by the wet cleaning process, which in turn prevents current leakage.

[0071] One embodiment is a semiconductor device structure. The structure includes a first semiconductor material disposed on a substrate and a dielectric layer disposed on the first semiconductor material. The dielectric layer includes a dopant. The structure also includes a second semiconductor material disposed on the dielectric layer, a first semiconductor layer in contact with the second semiconductor material, and a first dielectric spacer in contact with the first semiconductor layer, wherein the first dielectric spacer includes a dopant.

[0072] Another embodiment is a method. The method includes forming a sacrificial gate stack over a portion of a fin structure, removing an exposed portion of the fin structure to expose a portion of a substrate and a surface of a semiconductor layer of the fin structure, depositing a first semiconductor material on the exposed portion of the substrate, and depositing a dielectric layer. The dielectric layer includes a bottom portion disposed on the first semiconductor material and a sidewall portion disposed on the surface of the semiconductor layer. The method also includes removing the sidewall portion of the dielectric layer, performing an implantation process to implant a dopant into the bottom portion of the dielectric layer, then performing an annealing process on the bottom portion of the dielectric layer, and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0073] Another embodiment is a method. The method includes forming a fin structure from a substrate, the fin structure including a first plurality of semiconductor layers and a second plurality of semiconductor layers. The method also includes forming a sacrificial gate stack above the fin structure, depositing a gate spacer on the sacrificial gate stack, removing a portion of the fin structure to expose a portion of the substrate, recessing the second plurality of semiconductor layers to form a cavity, forming a dielectric spacer in the cavity, depositing a first semiconductor material on the exposed portion of the substrate, and depositing a dielectric layer. The dielectric layer includes a sidewall portion in contact with the gate spacer, the first plurality of semiconductor layers, and the dielectric spacer, and a bottom portion in contact with the first semiconductor material. The method also includes removing a sidewall portion of the dielectric layer, performing an implantation process to implant a dopant into a bottom portion of the dielectric layer, then performing an annealing process on the bottom portion of the dielectric layer, and forming a second semiconductor material on the bottom portion of the dielectric layer.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device structure, comprising: A first semiconductor material is disposed on a substrate; a dielectric layer disposed on the first semiconductor material, wherein the dielectric layer includes a dopant; a second semiconductor material disposed on the dielectric layer; A first semiconductor layer in contact with the second semiconductor material; and A first dielectric spacer is in contact with the first semiconductor layer, wherein the first dielectric spacer includes the dopant.

2. The semiconductor device structure according to claim 1, wherein: The dopant includes Si, F or B.

3. The semiconductor device structure according to claim 1, wherein: The dopant concentration of the first dielectric spacer decreases in a direction away from the second semiconductor material.

4. The semiconductor device structure according to claim 3, wherein: The dopant concentration of the dielectric layer increases in a direction away from the first semiconductor material.

5. The semiconductor device structure according to claim 1, further comprising a second semiconductor layer in contact with the second semiconductor material, wherein: The second semiconductor layer is disposed over the first semiconductor layer, and the first dielectric spacer is disposed between the first semiconductor layer and the second semiconductor layer.

6. The semiconductor device structure according to claim 5, further comprising a second dielectric spacer in contact with the second semiconductor layer, wherein: The second dielectric spacer and the first and second semiconductor layers are doped with the dopant.

7. The semiconductor device structure according to claim 1, wherein: The thickness of the dielectric layer is 50% to 80% of the thickness of the first dielectric spacer, and a top surface of the dielectric layer is located lower than a bottom surface of the first semiconductor layer.

8. A method comprising: forming a sacrificial gate stack over a portion of the fin structure; removing the exposed portion of the fin structure to expose a portion of the substrate and a surface of the semiconductor layer of the fin structure; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes a bottom portion disposed on the first semiconductor material and a sidewall portion disposed on a surface of the semiconductor layer; removing a sidewall portion of the dielectric layer; performing an implantation process to implant dopants into a bottom portion of the dielectric layer; performing an annealing process on a bottom portion of the dielectric layer; and A second semiconductor material is formed on a bottom portion of the dielectric layer.

9. The method according to claim 8, wherein: The dopant concentration of the dielectric layer is 5×10 20 cm -3 Up to 1×10 21 cm -3 within the range.

10. A method comprising: forming a fin structure from a substrate, wherein the fin structure comprises a first plurality of semiconductor layers and a second plurality of semiconductor layers; forming a sacrificial gate stack over the fin structure; depositing a gate spacer on the sacrificial gate stack; removing a portion of the fin structure to expose a portion of the substrate; recessing the second plurality of semiconductor layers to form a cavity; forming a dielectric spacer in the cavity; depositing a first semiconductor material on the exposed portion of the substrate; depositing a dielectric layer, wherein the dielectric layer includes sidewall portions in contact with the gate spacers, the first plurality of semiconductor layers, and the dielectric spacers, and a bottom portion in contact with the first semiconductor material; removing a sidewall portion of the dielectric layer; performing an implantation process to implant dopants into a bottom portion of the dielectric layer; performing an annealing process on a bottom portion of the dielectric layer; and A second semiconductor material is formed on a bottom portion of the dielectric layer.

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