Semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device. The present disclosure provides a technique capable of ensuring high-level ESD resistance and protecting a semiconductor device by a small-area ESD protector. The semiconductor device includes an input / output unit, a core logic circuit, a first power supply unit, a second power supply unit, a third power supply unit, and a fourth power supply unit. Each power supply unit comprises a protection circuit and a bidirectional diode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The entire contents of Japanese Patent Application No. 2023-112739 filed on July 10, 2023, including specification, drawings and abstract, are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and to an effective technology applied to a semiconductor device having an electrostatic protection circuit. Background Art

[0004] There is a semiconductor device in which a signal input to an input / output pad electrode from the outside of the semiconductor device is sequentially transmitted to an input / output unit and an input / output logic circuit including an electrostatic discharge (ESD) protective device (protective circuit), and an internal circuit (core logic circuit) through a level conversion circuit. In addition, there is a semiconductor device in which an input / output unit and a power supply unit are placed in an IO area provided along an edge portion of the periphery of a semiconductor chip, and an internal circuit is provided in a center area surrounded by the IO area of ​​the semiconductor chip.

[0005] As an ESD test of a device, there is a CDM test. The CDM test is a target charging model (CDM method: charged device model), and is a test that simulates a situation where a semiconductor device to be tested is charged and static electricity has been discharged from the semiconductor device to be tested.

[0006] The disclosed techniques are listed below.

[0007] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-161721

[0008] [Patent Document 2] International Publication No. 2016 / 203648 Summary of the invention

[0009] In a CDM test for semiconductor devices, an input-logic circuit or an internal circuit may be more easily damaged by a potential difference before an ESD protection circuit.

[0010] An object of the present disclosure is to provide a technology capable of ensuring high resistance ESD and protecting a semiconductor device by a small-area ESD protector.

[0011] Other objects and novel features will be apparent from the specification and the accompanying drawings.An overview of representative parts of the present disclosure will be briefly described below.

[0012] According to one embodiment, a semiconductor device includes: an input / output unit connected between a first power wiring and a first ground wiring, a core logic circuit connected between a second power wiring and a second ground wiring, a first power supply unit and a second power supply unit connected between the first power wiring and the first ground wiring, and a third power supply unit and a fourth power supply unit connected between the second power wiring and the second ground wiring. Each of the first power supply unit, the second power supply unit, the third power supply unit, and the fourth power supply unit includes a protection circuit connected between a corresponding power line and a corresponding ground line, and a bidirectional diode connected between the first ground line and the second ground line.

[0013] According to the semiconductor device of the above-described embodiment, the semiconductor device can be protected by the ESD protector having a small area while ensuring a high level of ESD resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is an overall layout diagram of the semiconductor device according to the first embodiment.

[0015] Figure 2 is a schematic block diagram of a semiconductor device according to a first embodiment.

[0016] Figure 3 yes Figure 2 Schematic diagram of the schematic layout placement of semiconductor devices.

[0017] Figure 4 is a schematic diagram for explaining the effects of the semiconductor device according to the first embodiment.

[0018] Figure 5 is a schematic block diagram of a semiconductor device according to a second embodiment.

[0019] Figure 6 yes Figure 5 Schematic diagram of the schematic layout placement of semiconductor devices.

[0020] Figure 7 is a schematic block diagram of a semiconductor device according to Comparative Example 1.

[0021] Figure 8 2 is a schematic diagram showing the layout of a semiconductor device according to Comparative Example 1.

[0022] Fig. 9 is a schematic block diagram of a semiconductor device according to Comparative Example 2.

[0023] Fig.10 3 is a schematic diagram showing the layout of a semiconductor device according to Comparative Example 2.

[0024] Fig.11is a schematic diagram for explaining a problem of the semiconductor device according to Comparative Example 1.

[0025] Fig.12 is a schematic diagram for explaining another problem of the semiconductor device according to Comparative Example 1.

[0026] Fig.13 is a schematic diagram for explaining a problem of the semiconductor device according to Comparative Example 2.

[0027] Fig.14 is a schematic diagram for explaining another problem of the semiconductor device according to Comparative Example 2. DETAILED DESCRIPTION

[0028] Embodiments are described below with reference to the accompanying drawings. However, in the following description, the same components are indicated by the same reference numerals, and repeated descriptions thereof may be omitted. It should be noted that for the sake of clear explanation, the pictures may be schematically represented in comparison with the actual embodiments, but are merely examples and do not limit the interpretation of the present invention.

[0029] First embodiment

[0030] The semiconductor device 10 according to the first embodiment will refer to Figures 1 to 3 to describe. Figure 1 FIG. 1 is a schematic diagram showing the overall layout of the semiconductor device according to the first embodiment. Figure 2 is a schematic block diagram of a semiconductor device according to a first embodiment. Figure 3 yes Figure 2 Schematic diagram of the layout placement of semiconductor devices. Figure 3 It is shown in Figure 1 The layout is placed in the area indicated by the dotted line V.

[0031] like Figure 1 As shown in , the semiconductor device 10 includes an input / output unit (IOC) 11, a first power supply unit (IO power supply unit IOPC) 12 (IO power supply unit 12A, IO power supply unit 12B), and a second power supply unit (core power supply unit CPC) 13 (core power supply unit 13A, core power supply unit 13B) at the peripheral portion of a rectangular semiconductor chip 101 such as single crystal silicon. The IO power supply unit 12A may be referred to as a first power supply unit, the IO power supply unit 12B may be referred to as a second power supply unit, the core power supply unit 13A may be referred to as a third power supply unit, and the core power supply unit 13B may be referred to as a fourth power supply unit.

[0032] The region where the input / output unit 11, the first power supply unit 12, and the second power supply unit 13 are disposed is referred to as an IO region IOR. The IO region IOR is disposed along four sides 21, 22, 23, and 24 of the chip end (edge) of the semiconductor chip 101 in a plan view. The four sides 21, 22, 23, and 24 include a first side 21, a third side 23 disposed opposite to the first side 21, a second side 22 disposed between the first side 21 and the third side 23, and a fourth side 24 disposed opposite to the second side 22.

[0033] The device 10 also includes an internal circuit 14 as a core logic circuit (CORE-LOG). A core logic region (also referred to as a central region and a second region) CER is provided in the central portion of the semiconductor chip 101 and is a region surrounded by the IO region, and the internal circuit 14 is arranged in the core logic region.

[0034] The input / output unit 11 is a formation area of ​​an input / output circuit connected to an input / output pad. The power supply unit 12 and the power supply unit 13 are ESD protective circuits (CESD, ESD) for protecting the device 10 from electrostatic discharge (ESD) and noise, and for providing power supply potential (VDDIO, VDD) or ground potential (VSSIO, VSS) to the inside of the chip.

[0035] Since it is necessary to uniformly reduce the impedance of the power supply, the power supply unit 12 and the power supply unit 13 are placed in a distributed manner for each input / output unit 11 and are placed adjacent to each other between the input / output units 11 and the input / output units 11 .

[0036] The power supply potential (VDDIO, VDD) includes a first power supply potential VDDIO of the input / output unit 11 and a second power supply potential VDD of the internal circuit 14. Similarly, the ground potential (VSSIO, VSS) includes a first ground potential VSSIO of the input / output unit 11 and a second ground potential VSS of the internal circuit 14. The first power supply potential VDDIO may be a potential greater than the second power supply potential VDD (VDDIO>VDD). The first power supply potential VDDIO, the first ground potential VSSIO, the second power supply potential VDD, and the second ground potential VSS are provided to the input / output unit 11 via a power supply line. The second power supply potential VDD and the second ground potential VSS are provided to the internal circuit 14 via a power supply line.

[0037] The IO power supply unit 12A includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first power supply potential VDDIO to a power supply wiring (first power supply wiring L1). The IO power supply unit 12B includes an ESD protection circuit (ESD) and a bridge circuit 15, and supplies a first ground potential VSSIO to a power supply wiring (L2: also referred to as a first ground wiring). The ESD protector (ESD) may include an NMOS transistor NM.

[0038] The core power supply unit 13A includes an ESD protection circuit (CESD) and a bridge circuit 15, and provides a second power supply potential VDD to a power supply wiring (a second power supply wiring L3). The core power supply unit 13B includes an ESD protection circuit (CESD) and a bridge circuit 15, and provides a second ground potential VSS to a power supply wiring (L4: also referred to as a second ground wiring). The ESD protector (CESD) may include an NMOS transistor NM.

[0039] The ESD protection circuit (ESD) (i.e., the source-gate path of the NMOS transistor NM constituting the ESD protection circuit (ESD)) is connected between a power line provided with a first power supply potential VDDIO and a power line provided with a first ground potential VSSIO. The ESD protection circuit (CESD) (i.e., the source-drain path of the NMOS transistor NM constituting the ESD protection circuit (CESD)) is connected between a power wiring provided with a second power supply potential VDD and a power wiring provided with a second ground potential VSS.

[0040] The bridge 15 includes a pair of bidirectional diodes connected between a power supply wiring provided with a first ground potential VSSIO and a power supply wiring provided with a second ground potential VSS, and connected between the power supply wiring provided with the first ground potential VSSIO and the power supply wiring provided with the second ground potential VSS. The anode of one of the diodes is connected to the power supply wiring provided with the first ground potential VSSIO, and the cathode is connected to the power supply wiring provided with the second ground potential VSS. The anode of the other diode is connected to the power supply wiring provided with the second ground potential VSS, and the cathode is connected to the power supply wiring provided with the first ground potential VSSIO. The bridge 15 may also be referred to as a bidirectional diode 15.

[0041] The input / output unit 11 includes an input / output circuit connected to an input / output terminal (TIO). The input / output terminal TIO, power terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are arranged on the input / output unit 11, the IO power supply unit 12, and the core power supply unit 13, respectively, but may be arranged separately from the input / output unit 11, the IO power supply unit 12, and the core power supply unit 13, respectively. The input / output terminal TIO, power terminals TVDD, TVDDIO, and ground terminals TVSS, TVSSIO are connected to bonding wires, etc., and are also referred to as input / output pads, power pads, and ground pads, respectively.

[0042] The input / output circuit constituting the input / output unit 11 includes a diode D1, a diode D2 constituting an ESD protection circuit, and an output circuit including a P-channel transistor Q1 and an N-channel transistor Q2 which are output transistors for transmitting an output signal to a signal line connected to the input / output terminal TIO. A level shifter circuit and an input / output logic circuit IOL including a CMOS inverter are provided, and the CMOS inverter receives an output signal output from the input / output terminal TIO through the signal line. The input / output circuit also receives an input signal which is input from the input / output terminal TIO via the signal line, output to the level shifter circuit LSC via the input / output logic circuit IOL, and is level-converted by the level shifter circuit LSC and supplied to the internal circuit 14. On the other hand, a signal output from the internal circuit 14 is input to the level shifter circuit LSC, level-converted, supplied to the input / output logic circuit IOL, and output as an output signal from the output circuit including the P-channel transistor Q1 and the N-channel transistor Q2 to the input / output terminal TIO. The P-channel transistor Q1 and the N-channel transistor Q2 may be formed of MOS transistors.

[0043] The source-drain path of the P-channel transistor Q1 is connected between the power line of the first power supply potential VDDIO and the signal line from the input / output terminal TIO, and the source-drain path of the N-channel transistor Q2 is connected between the signal line and the ground line of the first ground potential VSSIO. The anode of the diode D1 is connected to the signal line from the input / output terminal TIO, and its cathode is connected to the power wiring of the first power supply potential VDDIO. The anode of the diode D2 is connected to the ground wiring of the first ground potential VSSIO, and its cathode is connected to the signal wiring from the input / output terminal TIO. The diode D1 supplies a surge current from the input / output terminal TIO to the power terminal VDDIO via the signal wiring and the power wiring of the first power supply potential VDDIO, and the diode D2 supplies a surge current from the ground terminal TVDDIO to the input / output terminal TIO via the ground wiring and the signal wiring of the first ground potential VSSIO. The output circuit may be a so-called open-drain type without the P-channel transistor Q1. In addition, the input / output circuit may not include any one of the output circuit and the input circuit.

[0044] The input / output logic IOL is connected between a power supply line of the first power supply potential VDDIO and a ground line of the first ground potential VSSIO. The level shifter LSC is connected between a circuit power supply line of the first power supply potential VDDIO, a power supply line supplied with a second power supply potential VDD, and a power supply line supplied with a second ground potential VSS.

[0045] The power supply units 12A and 13A include ESD protection circuits (CESD and ESD) corresponding to the power supply terminals (TVDDIO and TVDD), and the power supply units 12B and 13B include ESD protection circuits (CESD and ESD) corresponding to the ground terminals (TVSSIO and TVSS).

[0046] The first power supply potential VDDIO is, for example, 1.8 V (or 3.3 V), and the second power supply potential VDD is, for example, 0.8 V. The ground terminals (TVSSIO, TVSS) are, for example, 0.0 V.

[0047] For example, when the first power supply potential VDDIO is 1.8V and the second power supply potential VDD is 0.8V, 1) the transistor Q1, the transistor Q2 and the input / output logic circuit IOL of the output circuit are configured only by MOSFET (1.8V-MOS has a breakdown voltage of 1.8V); 2) the internal circuit 14 is composed only of MOSFET (also called core MOS) with a withstand voltage of 0.8V; 3) the level shifter LSC includes 1.8V-MOS and core MOS; 4) the core power supply unit 13A, the core power supply unit 13B protects the core MOS of the internal circuit 14 and the core MOS of the level shifter circuit LSC; 5) the IO power supply unit 12A, the IO power supply unit 12B protects the transistor Q1, the transistor Q2 and the 1.8V-MOS of the input / output logic circuit IOL of the output circuit.

[0048] Figure 3 The IO power supply unit 12A and IO power supply unit 12B placed in the IO region IOR, the input / output unit 11 and the core power supply unit 13A and core power supply unit 13B, and the internal circuit 14 placed in the core logic region are shown. Figure 3 As shown in the figure, in the IO area IOR, the IO power supply unit 12A, the IO power supply unit 12B, the input / output unit 11, and the core power supply unit 13A, the core power supply unit 13B are placed in sequence, and the internal circuit 14 is placed adjacent to the IO area IOR in the core logic area CER located above the IO area.

[0049] Figure 4 1 is a schematic diagram for explaining the effect of the semiconductor device according to the first embodiment. Here, in the CDM test which is one of the electrostatic tests, the situation where a current flows into the capacitance component Cpkg parasitic to the power supply wiring provided with the second ground potential VSS is checked. Figure 4 In FIG. 1 , a first CDM test on the input / output terminal TIO and a second CDM test on the power supply terminal TVDD are assumed.

[0050] 1) In the first CDM test, as described below, there are a first charging path PT1 and a second charging path PT2. First charging path PT1: TIO->D1->power supply wiring of the first power supply potential VDDIO->ESD of 12B->power supply wiring provided with the first ground potential VSSIO->15 of 12B->power supply wiring provided with the second ground potential VSS->Cpkg. Second charging path PT2: TIO->D1->power supply wiring of the first power supply potential VDDIO->ESD of 12A->power supply wiring provided with the first ground potential VSSIO->15 of 12A->power supply wiring provided with the second ground potential VSS->Cpkg.

[0051] 2) In the second CDM, as described below, there are a third charging path PT3 and a fourth charging path PT4. The third charging path PT3: TVDD->power supply wiring supplied with the second power supply potential VDD->CESD of 13A->power supply wiring supplied with the second ground potential VSS->Cpkg. The fourth charging path PT4: TVDD->power supply wiring supplied with the second power supply potential VDD->CESD of 13B->power supply wiring supplied with the second ground potential VSS->Cpkg.

[0052] That is, the semiconductor device 10 of the first embodiment has the following features.

[0053] 1) A bidirectional diode 15 between a power line supplied with the first ground potential VSSIO and a power line supplied with the second ground potential VSS is provided in each of the IO power supply unit 12A, 12B and the core power supply unit 13A, 13B.

[0054] 2) In the first TIO test for the input / output terminal, in the first CDM test, a discharge path (PT1, PT2) from the input / output terminal TIO to the second ground potential VSS provided on the parasitic capacitance component Cpkg can be easily formed without relying on the layout placement of the input / output unit 11 and the core power supply unit 13B.

[0055] 3) According to the above 2, even in the case where the CDM current flows through the power wiring provided with the second ground potential VSS, the input / output terminal TIO makes it difficult for the input / output terminal to be affected by the parasitic resistance VSS of the power wiring provided with the first power potential VDDIO and the parasitic resistance Rvss of the power wiring provided with the second ground potential VSS, and thus it is possible to avoid breakdown due to the potential difference of the input / output logic circuit IOL.

[0056] 4) An ESD protection circuit (CESD) is arranged in each of the core power supply unit 13A and the core power supply unit 13B, and can ensure a sufficient discharge path (PATH3, PATH4) from the power terminal TVDD to the power line of the second ground potential VSS provided with a parasitic capacitance component Cpkg in the second CDM test for the power port TVDD.

[0057] 5) According to the above 4, breakdown due to the potential difference of the internal circuit 14 can also be avoided.

[0058] 6) In Figure 3The bidirectional diode 15 of the IO power supply unit 12A and the IO power supply unit 12B shown in FIG. 1 is arranged on the IO power supply unit 12A and the IO power supply unit 12B (in Figure 3 On the other hand, the bidirectional diode 15 of the core power supply unit 13A and the core power supply unit 13B is not arranged on the side of the core power supply unit 13A and the core power supply unit 13B facing the internal circuit 14, but is arranged on the side facing the core power supply unit 13A and the core power supply unit 13B (at the top end). Figure 3 The upper side of the chip edge side of the semiconductor chip 101 ( Figure 1 These bidirectional diodes 15 are placed at positions that have less influence of parasitic resistance in a discharge path formed between a power supply wiring supplied with the first ground potential VSSIO and a power supply wiring supplied with the second ground potential VSS.

[0059] Second embodiment

[0060] Thereafter, reference will be made to Figure 1 and Figure 6 10S according to the second embodiment will be described. Figure 5 is a schematic block diagram of a semiconductor device according to a second embodiment. Figure 6 yes Figure 5 Schematic diagram of the layout placement of semiconductor devices.

[0061] According to Figure 5 The semiconductor device 10S of the second embodiment shown in FIG. Figure 2 The semiconductor device 10 of the first embodiment shown in FIG. 1 is different in that: (1) the power supply wiring (L1) of the first power supply potential VDDIO is separated and used to provide the power supply potential VDDIOL (also referred to as the fourth power supply wiring (L5)) of the input / output logic circuit IOL. The power supply line of the first power supply potential VDDIO can be referred to as the third power supply line (L1). (2) The power supply potential VDDIOL is connected to the power supply terminal TVDDIOL, and (3) the IO power supply unit 12C (fifth power supply unit) as the power supply unit IOPC for IO is connected between the power supply potential VDDIOL and the power supply line provided with the second ground potential VSS.

[0062] Here, the basic configuration of the IO power supply unit 12C is the same as that of the IO power supply unit 12A and the IO power supply unit 12B.

[0063] In addition, if Figure 6As shown in FIG. 1 , in the IO region 12C, the power supply unit for IOR is arranged in the region between the IO power supply unit 12B and the input / output unit 11. A bidirectional diode 15 is also placed in the added IO power supply unit 12C, and helps form a discharge path that escapes from the power supply line provided with the second ground potential VSS.

[0064] In the input / output unit 11 , a power supply line supplied with a power supply potential VDDIOL is laid out in an upper half of the input / output unit 11 according to the input / output logic IOL.

[0065] In the IO power supply unit 12C, a power supply line supplied with the power supply potential VDDIOL and a power supply line supplied with the second ground potential VSS are vertically laid out.

[0066] Therefore, the bidirectional diode 15 in the IO power supply unit 12C is arranged on the chip edge side ( Figure 1 Therefore, the bidirectional diode 15 in the IO power supply unit 12C is placed in the most efficient layout to form a discharge path between the power supply wiring provided with the first ground potential VSSIO and the power supply line provided with the second ground potential VSS, which is the same as the placement of the bidirectional diode 15 in the core power supply unit 13A and the core power supply unit 13B.

[0067] By this configuration, the same effects as those of the first embodiment can be obtained. In addition, since the noise of the power supply line of the first power supply potential VDDIO can be reduced by propagating to the input / output logic circuit IOL, the performance of the input / output logic circuit IOL can be improved (speed increase).

[0068] Figure 7 is a schematic block diagram of a semiconductor device according to Comparative Example 1. Figure 8 2 is a schematic diagram showing the layout of a semiconductor device according to Comparative Example 1. Fig. 9 is a schematic block diagram of a semiconductor device according to Comparative Example 2. Fig.10 2 is a schematic diagram showing the layout of a semiconductor device according to Comparative Example 2.

[0069] like Figure 7 and Figure 8 As shown in FIG. 1 , in the semiconductor device 10r of the comparative example 1, relative to Figure 2The semiconductor device 10 of the embodiment of the present invention does not provide the bidirectional diode 15 in the IO power supply unit 12A, the IO power supply unit 12B, and the core power supply unit 13A. In addition, in the core power supply unit 13A of the semiconductor device 10r, the ESD protector (CESD) is connected between the power supply line provided with the second power supply potential VDD and the power supply line provided with the first ground potential VSSIO. In the core power supply unit 13B of the semiconductor device 10r, the ESD protector (CESD) is connected between the power supply line provided with the first power supply potential VDDIO and the power supply line provided with the second ground potential VSS.

[0070] like Fig. 9 and Fig.10 As shown in FIG. 1 , in the semiconductor device 10r1 of the comparative example 2, the ESD protective circuit (CESD) of the core power supply unit 13A is connected between the power supply wiring provided with the second power supply potential VDD and the power supply wiring provided with the second ground potential VSS, relative to the semiconductor device 10r of the comparative example 1. The core power supply unit 13B of the semiconductor device 10r1 is not provided with the ESD protector (CESD).

[0071] Fig.11 is a schematic diagram for explaining a problem of the semiconductor device according to Comparative Example 1. Fig.12 is a schematic diagram for explaining another problem of the semiconductor device according to Comparative Example 1.

[0072] like Fig.11 As shown in, in the CDM test which is one of the electrostatic tests, the current flows from the input / output terminal TIO to the discharge path (PT1r, PT2r) of the power line of the second ground potential VSS parasitized with the capacitance component Cpkg. When the protected circuit becomes fragile due to the miniaturization of the structure of the semiconductor device, the parasitic resistance Rvddio of the power wiring provided with the first ground potential VSSIO, the parasitic resistance Rvssio of the power wiring provided with the first ground potential VSSIO, and the parasitic resistance Rvss of the power wiring provided with the second ground potential VSS are affected, and the problem that the input / output logic circuit IOL is damaged by the potential difference dV1 has been found in the CDM test. In order to overcome this problem in Comparative Example 1, it is necessary to reduce the parasitic resistance 13B of the power line provided with the second ground potential VSS by increasing the cell width of the power supply unit Rvss for the core, and it is also necessary to reduce the parasitic resistance Rvssio of the power line provided with the first ground potential VSSIO by providing a strict placement constraint between the unit of the input / output unit 11 and the power supply unit for the core. It was found that the size of the semiconductor device 10r was increased and the degree of freedom in design was hindered.

[0073] like Fig.12 As described in the foregoing, the ESD protection circuit (CESD) in the core power supply unit 13A is connected between the power supply wiring provided with the second ground power supply potential VDD and the power supply wiring provided with the first ground potential VSSIO. Therefore, in the CDM test of the power supply terminal TVDD, the current flows from the power supply terminal TVDD through the bidirectional diode 15 to the capacitor component Cpkg parasitic on the power supply line provided with the second ground potential VSS, as shown in the discharge route PT3. In addition, the potential difference dV2 generated by the bidirectional diode 15 also causes pressure on the internal circuit 14, and the internal circuit 14 is easily damaged by the potential difference dV2. Specifically, since a plurality of thin-film MOS transistors having relatively thin gate oxide films are used in the internal circuit 14, they are susceptible to the pressure of the potential difference.

[0074] Fig.13 is a schematic diagram for explaining a problem of a semiconductor device according to Comparative Example 2. Fig.14 is a schematic diagram for explaining another problem of the semiconductor device according to Comparative Example 2.

[0075] like Fig.13 As shown in FIG. 2 , in Comparative Example 2, since the discharge path PT2r is connected to Fig.11 Although the input / output logic IOL is formed in the same manner as in Comparative Example 1, there is a problem that the input / output logic IOL is damaged by the potential difference dV1 in the CDM test in the same manner as in Comparative Example 1. Fig.14 As shown in , also in Comparative Example 2, in the CDM test of the power supply terminal TVDD, a discharge path PT4r is formed from the power supply terminal TVDD to the capacitor component Cpkg. In the semiconductor device 10r1 of Comparative Example 2, only the core power supply unit 13A is provided with an ESD protection circuit (CESD), and there is no ESD protection circuit (CESD) in the core power supply unit 13B. Therefore, Fig.13 As shown in , in the CDM test of the power supply terminal TVDD, the discharge performance of the ESD protection circuit (CESD) becomes insufficient, and when the protected circuit becomes fragile due to the miniaturization of the semiconductor device structure, the internal circuit 14 is easily damaged by the potential difference dV3. When the number of ESD protective circuits (CESD) in the core power supply unit 13A is small, it is also easily affected by the parasitic resistance Rvss of the vertical wiring provided in the vertical direction between the ESD protective circuit (CESD) and the power supply wiring provided with the second ground potential VSS.

[0076] According to the first and second embodiments, the problem described in Comparative Example 1 and the problem described in Comparative Example 2 can be avoided, and thus it is possible to ensure high-level ESD resistance and protect the device by a small-area ESD protector.

[0077] Although the present disclosure has been described in detail based on the embodiments, it is needless to say that the present disclosure is not limited to the above-described embodiments and can be variously modified.

Claims

1. A semiconductor device comprising: a first power supply wiring configured to provide a first power supply voltage; a second power supply wiring configured to provide a second power supply voltage; A first ground wiring configured to provide a first ground voltage; a second ground wiring configured to provide a second ground voltage; An I / O unit connected between the first power wiring and the first ground wiring; a core logic circuit connected between the second power wiring and the second ground wiring; A first power supply unit and a second power supply unit connected between the first power supply wiring and the first ground wiring; as well as A third power supply unit and a fourth power supply unit are connected between the second power supply wiring and the second ground wiring, Each of the first power supply unit, the second power supply unit, the third power supply unit and the fourth power supply unit comprises: a protection circuit connected between the corresponding power wiring and the corresponding ground wiring; as well as A bidirectional diode is connected between the first ground wiring and the second ground wiring.

2. The semiconductor device according to claim 1, wherein each bidirectional diode of the first power supply unit and the second power supply unit is arranged between the core logic circuit and the protection circuit in a plan view, and Each of the bidirectional diodes of the third power supply unit and the fourth power supply unit is arranged at the chip side, so that the protection circuit is arranged between the core logic circuit and the bidirectional diode in a plan view.

3. The semiconductor device according to claim 2, The I / O unit includes an output transistor and an IO logic circuit. The first power supply wiring comprises: a third power supply wiring connected to the output transistor; as well as a fourth power supply wiring connected to the IO logic circuit and separated from the third power supply wiring, wherein the IO logic circuit is connected between the fourth power wiring and the first ground wiring, wherein the semiconductor device further includes a fifth power supply unit connected between the fourth power supply wiring and the first ground wiring, The fifth power supply unit comprises: a protection circuit connected between the fourth power wiring and the first ground wiring; as well as A bidirectional diode is connected between the first ground wiring and the second ground wiring.

4. The semiconductor device according to claim 3, The bidirectional diode of the fifth power supply unit is arranged at a chip side so that the protection circuit of the fifth power supply unit is arranged between the core logic circuit and the bidirectional diode in a plan view.

5. The semiconductor device according to claim 3, The circuit is placed between the core logic circuit and the chip side in the order of the first power supply unit, the second power supply unit, the IO unit, the third power supply unit and the fourth power supply unit.

6. The semiconductor device according to claim 4, The circuit is placed between the core logic circuit and the chip side in the order of the first power supply unit, the second power supply unit, the fifth power supply unit, the IO unit, the third power supply unit and the fourth power supply unit.

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