Error correction method of calculation SSD (Solid State Disk) for supporting rapid file semantic search

Abstract

Disclosed herein are devices and methods for implementing semantic search on an SSD by a compute SSD system that distributes computations to each NAND flash memory die of the SSD while an SSD controller utilizes new on-die compute logic circuitry to handle result aggregation to provide on-device file semantic search. The compute SSD system may read file feature vectors from multiple dies to the SSD controller, and if desired, the feature vectors may be buffered in the DRAM and the controller handles distance calculations. A local on-die AI / ML processing unit may perform, for example, compute and compare operations and communicate processing scores and results to the SSD controller. The SSD controller aggregates the results from all the dies and returns the results to the host. Feature vector storage size, the number of circuits, and on-die AI / ML processing units may be configured on demand to accommodate different tasks, system constraints, and / or feature vector size.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 18 / 449,165, entitled “Error Correction Methods for Computational SSDs supporting Rapid File Semantic Search,” filed in the U.S. Patent and Trademark Office on August 14, 2023, and is incorporated herein by reference in its entirety for all purposes, which U.S. non-provisional application claims priority to U.S. Provisional Application No. 63 / 476,666, filed on December 22, 2022. Technical Field

[0003] The present disclosure relates to storage systems. More specifically, the present disclosure relates to utilizing storage systems to perform machine learning processes. Background Art

[0004] Storage devices are ubiquitous within computing systems. Recently, solid-state storage devices (SSDs) have become increasingly common. These non-volatile storage devices can communicate and utilize a variety of protocols, including Non-Volatile Memory Express (NVMe) and Peripheral Component Interconnect Express (PCIe), to reduce processing overhead and improve efficiency.

[0005] As they evolve, SSDs have become more power efficient compared to traditional hard disk drives (HDDs), thus making SSDs advantageous in consumer and commercial markets. Over the years, many users have accumulated thousands of files to record their lives, experiences, travels, and interests. In order to find specific media files based on the content of specific media files, users often spend a lot of time navigating, organizing, and searching albums and folders to find specific photos, videos, and other media. Generally speaking, user media is stored on various storage and computing devices, and users have limited methods for contextual search of photos, videos, and other media to find desired media files. In fact, users are limited to traditional search methods, such as vocabulary searches for finding media on storage systems, which are limited to searching for recent files or files with specific file names or attributes. In addition, the lack of a large amount of stored media files and contextual search methods makes it difficult for users to find specific media on their storage and computing devices.

[0006] With the development of artificial intelligence (AI) and machine learning (ML), accurate semantic search has become possible, allowing users to find relevant content within media files stored on their storage devices. However, conventional implementations of AI / ML semantic search for storage devices have some problems that make them inefficient and limited. One problem in conventional AI / ML implementations of semantic search is that data is repeatedly moved between the host processor, main memory, and storage devices, causing a large waste of bandwidth and energy from data movement. Another problem in conventional AI / ML implementations of semantic search is preparing data for AI / ML processing for host computing, that is, reading data from multiple dies to a storage device controller and buffering the data in memory for the controller to handle AI / ML processing, and then performing AI / ML processing. This causes a bottleneck in the storage device controller because the controller must handle both I / O and computing operations, and such calculations require additional memory buffers to store data for AI / ML processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of several embodiments of the present disclosure will become more apparent from the following description presented in conjunction with the following several drawings of the accompanying drawings.

[0008] Figure 1 is a schematic block diagram of an exemplary host computing device having a storage system suitable for use in a computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0009] Figure 2 is a schematic block diagram of an exemplary storage device suitable for a computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0010] Figure 3 is a conceptual illustration of a page of memory cells being sensed or programmed in parallel, organized, for example, in a NAND configuration, according to an embodiment of the present disclosure;

[0011] Figure 4 is a schematic block diagram of an exemplary computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0012] Figure 5 is a schematic block diagram of an exemplary machine learning processing unit of a computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0013] Figure 6 is a schematic block diagram of an exemplary machine learning processing unit of a computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0014] Figure 7is a flow chart depicting a process for utilizing an exemplary compute SSD system supporting semantic search according to an embodiment of the present disclosure;

[0015] Figure 8 is a flow chart depicting a process for utilizing an exemplary compute SSD system supporting semantic search according to an embodiment of the present disclosure;

[0016] Fig. 9 is a schematic block diagram of an exemplary machine learning process according to an embodiment of the present disclosure;

[0017] Fig. 10A is a schematic block diagram of an exemplary error correction system according to an embodiment of the present disclosure;

[0018] Fig. 10B According to the embodiments of the present disclosure Fig. 10A A diagram of an exemplary error correction system;

[0019] Fig. 10C According to the embodiments of the present disclosure Fig. 10A A table of exemplary error correction systems;

[0020] Fig.11A is a schematic block diagram of an exemplary error correction system according to an embodiment of the present disclosure;

[0021] Fig. 11B According to the embodiments of the present disclosure Fig.11A A diagram of an exemplary error correction system;

[0022] Fig. 11C According to the embodiments of the present disclosure Fig.11A A table of exemplary error correction systems;

[0023] Fig.12 is a schematic block diagram of an exemplary error correction mode and storage mode of a computing SSD system supporting semantic search with an error correction system according to an embodiment of the present disclosure; and

[0024] Fig.13 is a schematic block diagram of another exemplary error correction mode and storage mode of a computing SSD system supporting semantic search with an error correction system according to an embodiment of the present disclosure;

[0025] Fig.14 is a flow chart depicting a process for utilizing an exemplary error correction method in a computing SSD system supporting semantic search according to an embodiment of the present disclosure;

[0026] Fig.15 is a flow chart depicting a process for utilizing an exemplary error correction method in a computing SSD system supporting semantic search according to an embodiment of the present disclosure.

[0027] In the several figures throughout the drawings, corresponding reference numerals indicate corresponding parts. The elements in the several figures are shown for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be emphasized relative to other elements to facilitate understanding of the various embodiments currently disclosed. In addition, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not shown to facilitate less obstructed viewing of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] In response to the above problems, this article discusses a device and method for implementing semantic search on an SSD by a computing SSD system, which distributes the calculation to each NAND flash die of the SSD, while the SSD controller uses a new on-die computing logic circuit to handle the result aggregation to provide semantic search of files on the device. Specifically, many embodiments utilize a computing SSD system that reads file feature vectors from multiple dies to the SSD controller. If there are millions of feature vectors to be compared, these feature vectors can be buffered in DRAM and the controller handles the distance calculation. The AI / ML processing unit on the local die can perform, for example, calculation and comparison operations and pass the processing score and results to the SSD controller. The SSD controller aggregates the results from all dies and returns the results to the host. In some embodiments, the feature vector storage size of each AI / ML processing unit on the die can be configured as needed to accommodate different tasks and / or feature vector sizes. Based on this, the circuits of the AI / ML processing unit and the number of AI / ML processing units on the die can be configured and distributed as needed to provide increased computing speed or meet specific die area constraints. Additional embodiments are discussed in more detail below.

[0029] These solutions can help reduce the significant waste of bandwidth and energy from data movement between host processors, main memory, and storage devices. In addition, these solutions can help reduce the bottleneck of storage device controllers in AI / ML processing, where storage device controllers need to handle both I / O and computational operations in AI / ML operations, which requires reading feature vectors from multiple dies to the controller and buffering the feature vectors in memory to perform AI / ML calculations and processing.

[0030] Aspects of the present disclosure may be embodied as devices, systems, methods or computer program products. Therefore, aspects of the present disclosure may take the form of a completely hardware implementation, a completely software implementation (including firmware, resident software, microcode, etc.) or an implementation combining software and hardware aspects, which may all be collectively referred to herein as "functions", "modules", "devices" or "systems". In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transient computer-readable storage media storing computer-readable program code and / or computer-executable program code. Many of the functional units described in this specification have been labeled as functions in order to more specifically emphasize the implementation independence of these functional units. For example, a function may be implemented as a hardware circuit including a custom VLSI circuit or gate array, a ready-made semiconductor such as a logic chip, a transistor or other discrete component. Functions may also be implemented in programmable hardware devices such as via field programmable gate arrays, programmable array logic components, programmable logic devices, etc.

[0031] Functions may also be implemented at least in part in software for execution by various types of processors. An identified executable code function may, for example, include one or more physical or logical blocks of computer instructions, which may, for example, be organized as objects, procedures, or functions. However, the executable files of the identified functions need not be physically located together, but may include different instructions stored in different locations, which when logically joined together include the function and achieve the purpose described for the function.

[0032] In practice, executable code functions may include a single instruction or many instructions, and may even be distributed over several different code fragments, between different programs, across several storage devices, etc. When functions or parts of functions are implemented in software, these software parts may be stored on one or more computer-readable storage media and / or computer-executable storage media. Any combination of one or more computer-readable storage media may be utilized. For example, computer-readable storage media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing, but does not include propagating signals. In the context of this document, computer-readable storage media and / or computer-executable storage media may be any tangible and / or non-transient medium that may contain or store programs for use by or in conjunction with an instruction execution system, device, processor, or device.

[0033] Computer program code for performing operations of various aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Python, Java, Smalltalk, C++, C#, Objective C, etc., conventional procedural programming languages ​​such as the "C" programming language, scripting programming languages, and / or other similar programming languages. The program code may be executed partially or completely on one or more users' computers and / or on a remote computer or server over a data network, etc.

[0034] As used herein, a component includes a tangible, physical, non-transient device. For example, a component may be implemented as: a hardware logic circuit including a custom VLSI circuit, a gate array, or other integrated circuit; an off-the-shelf semiconductor, such as a logic chip, a transistor, or other discrete device; and / or other mechanical or electrical device. Components may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic components, programmable logic devices, and the like. Components may include one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices that are electrically connected to one or more other components via wires of a printed circuit board (PCB), etc. In certain embodiments, each of the functions and / or modules described herein may alternatively be embodied or implemented as a component.

[0035] As used herein, a circuit includes a group of one or more electrical components and / or electronic components that provide one or more paths for electric current. In some embodiments, a circuit may include a return path for electric current, so that the circuit is a closed loop. However, in another embodiment, a group of components that may not include a return path for electric current may be referred to as a circuit (e.g., an open loop). For example, whether an integrated circuit is grounded (as a return path for electric current) or not, the integrated circuit may be referred to as a circuit. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a group of integrated circuits, a group of non-integrated electrical components and / or electronic components with or without integrated circuit devices, etc. In one embodiment, a circuit may include: a custom VLSI circuit, a gate array, a logic circuit, or other integrated circuit; an off-the-shelf semiconductor, such as a logic chip, a transistor, or other discrete device; and / or other mechanical devices or electrical devices. The circuit may also be implemented as a synthetic circuit in a programmable hardware device, such as a field programmable gate array, a programmable array logic unit, a programmable logic device, etc. (e.g., as firmware, a netlist, etc.). A circuit may include one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices that are electrically connected to one or more other components via wires of a printed circuit board (PCB), etc. In some embodiments, each of the functions and / or modules described herein may be embodied or implemented as a circuit.

[0036] "One embodiment", "embodiment" or similar language mentioned throughout this specification means that the specific features, structures or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment", "in an embodiment" and similar language appearing throughout this specification may but do not necessarily all refer to the same embodiment, but to "one or more but not all embodiments", unless otherwise explicitly stated. The terms "including", "comprising", "having" and their variations mean "including but not limited to", unless otherwise explicitly stated. An enumerated list of items may not mean that any or all of the items in the items are mutually exclusive and / or mutually inclusive, unless otherwise explicitly stated. The terms "one", "an" and "the" also mean "one or more", unless otherwise explicitly stated.

[0037] Furthermore, as used herein, references to reading, writing, storing, buffering, and / or transmitting data may include the entire data, a portion of the data, a data set, and / or a subset of the data. Likewise, references to reading, writing, storing, buffering, and / or transmitting non-host data may include the entire non-host data, a portion of the non-host data, a non-host data set, and / or a subset of the non-host data.

[0038] Finally, as used herein, the terms "or" and "and / or" should be interpreted as inclusive or meaning any one or any combination. Thus, "A, B, or C" or "A, B, and / or C" means "any of: A; B; C; A and B; A and C; B and C; A, B, and C". An exception to this definition will only occur if a combination of elements, functions, steps, or actions are inherently mutually exclusive in some way.

[0039] Aspects of the present disclosure are described below with reference to the schematic flow chart and / or schematic block diagram of the method, device, system and computer program product according to the embodiments of the present disclosure. It should be understood that each frame of the schematic flow chart and / or schematic block diagram, and the combination of frames in the schematic flow chart and / or schematic block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor or other programmable data processing equipment of the computer to produce a machine, so that the instructions executed via the processor or other programmable data processing equipment create a device for implementing the function and / or action specified in one or more frames of the schematic flow chart and / or schematic block diagram.

[0040] It should also be noted that in some alternative implementations, the functions shown in the frame may not occur in the order shown in the figure. For example, in fact, the two frames shown in succession may be performed substantially simultaneously, or these frames may sometimes be performed in reverse order, depending on the functionality involved. It is conceivable that other steps and methods that are equivalent to one or more frames or parts thereof of the accompanying drawings shown in function, logic or effect. Although various arrow types and line types can be adopted in flow charts and / or block diagrams, it should be understood that these arrow types and line types do not limit the scope of the corresponding embodiments. For example, an arrow may indicate a waiting or monitoring period of unspecified duration between the steps of the enumeration of the depicted embodiment.

[0041] In the following detailed description, reference is made to the accompanying drawings that form a part of the detailed description. The foregoing summary of the invention is merely illustrative and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, other aspects, embodiments and features will become apparent by reference to the accompanying drawings and the following detailed description. The description of the elements in each figure may refer to the elements of the previous figures. Similar numbers may refer to similar elements in the drawings, including alternative embodiments of similar elements.

[0042] refer to Figure 1, a schematic block diagram of an exemplary host computing device 110 having a storage system 102 suitable for a computing SSD system supporting semantic search according to an embodiment of the present disclosure is shown. The computing SSD system 100 includes one or more storage devices 120 of the storage system 102 within the host computing device 110 that communicate via a controller 126. The host computing device 110 may include a processor 111, a volatile memory 112, and a communication interface 113. The processor 111 may include one or more central processing units, one or more general-purpose processors, one or more special-purpose processors, one or more virtual processors (for example, the host computing device 110 may be a virtual machine operating within a host), one or more processor cores, etc. The communication interface 113 may include one or more network interfaces configured to communicatively couple the controller 126 of the host computing device 110 and / or the storage device 120 to a communication network 115, such as an Internet Protocol (IP) network, a storage area network (SAN), a wireless network, a wired network, etc.

[0043] In various embodiments, the storage device 120 may be disposed at one or more different locations relative to the host computing device 110. In one embodiment, the storage device 120 includes one or more non-volatile memory devices 123, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, storage housings, and / or other mechanical support structures and / or electrical support structures. For example, the storage device 120 may include one or more direct-insertion memory modules (DIMM) cards, one or more expansion cards and / or daughter cards, solid-state drives (SSDs) or other hard drive devices, and / or may have another memory and / or storage form factor. The storage device 120 may be integrated with and / or mounted on a motherboard of the host computing device 110, mounted in a port and / or slot of the host computing device 110, mounted on a different host computing device 110, and / or on a dedicated storage device on the network 115, communicate with the host computing device 110 via an external bus (e.g., an external hard drive), etc.

[0044] In one embodiment, the storage device 120 may be disposed on a memory bus of the processor 111 (e.g., on the same memory bus as the volatile memory 112, on a different memory bus than the volatile memory 112, in place of the volatile memory 112, etc.). In another embodiment, the storage device 120 may be disposed on a peripheral bus of the host computing device 110, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus (such as, but not limited to, an NVM Express (NVMe) interface), a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switch (PCIe-AS) bus, etc. In another embodiment, the storage device 120 may be disposed on a communication network 115, such as an Ethernet network, an Infiniband network, SCSI RDMA over the network 115, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 115, etc.

[0045] The host computing device 110 may also include a computer-readable storage medium 114. The computer-readable storage medium 114 may include executable instructions configured to cause the host computing device 110 (e.g., the processor 111) to perform the steps of one or more methods disclosed herein. Additionally or alternatively, the buffer component 150 may be embodied as one or more computer-readable instructions stored on the computer-readable storage medium 114.

[0046] In certain embodiments, the device driver and / or controller 126 may present a logical address space 134 to the host client 116. As used herein, a logical address space 134 refers to a logical representation of a memory resource. The logical address space 134 may include a plurality (e.g., a range) of logical addresses. As used herein, a logical address refers to any identifier used to reference a memory resource (e.g., data), including, but not limited to: a logical block address (LBA), a cylinder / head / segment portion (CHS) address, a file name, an object identifier, an inode, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, an extent, etc.

[0047] The device driver for the storage device 120 may maintain metadata 135, such as a logical to physical address mapping structure, to map logical addresses of the logical address space 134 to media storage locations on the storage device 120. The device driver may be configured to provide storage services to one or more host clients 116. The host clients 116 may include local clients operating on the host computing device 110 and / or remote clients 117 accessible via the network 115 and / or the communication interface 113. The host clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0048] In many embodiments, the host computing device 110 may include multiple virtual machines that may be instantiated or otherwise created based on user requests. As will be appreciated by those skilled in the art, the host computing device 110 may create multiple virtual machines configured as virtual hosts that are limited to available computing resources and / or requirements. A hypervisor may be used to create, run, and otherwise manage multiple virtual machines. Each virtual machine may include multiple virtual host clients, similar to the host client 116 that may utilize the storage system 102 to store and access data.

[0049] The device driver may also be communicatively coupled to one or more storage systems 102, which may include storage devices 120 of different types and configurations, including but not limited to solid-state storage devices, semiconductor storage devices, SAN storage resources, etc. The one or more storage devices 120 may include one or more corresponding controllers 126 and non-volatile memory channels 122. The device driver may provide access to the one or more storage devices 120 via any compatible protocol or interface 133, such as but not limited to SATA and PCIe. Metadata 135 may be used to manage and / or track data operations performed through the protocol or interface 133. The logical address space 134 may include a plurality of logical addresses, each logical address corresponding to a corresponding media location of the one or more storage devices 120. The device driver may maintain metadata 135, which includes any-to-any mappings between logical addresses and media locations.

[0050] The device driver may also include and / or communicate with a storage device interface 139 configured to transmit data, commands, and / or queries to the one or more storage devices 120 via a bus 125, which may include, but is not limited to, a memory bus of the processor 111, a peripheral component interconnect express (PCI Express or PCIe) bus, a serial advanced technology attachment (ATA) bus, a parallel ATA bus, a small computer system interface (SCSI), FireWire, Fibre Channel, a universal serial bus (USB), a PCIe advanced switch (PCIe-AS) bus, a network 115, Infiniband, SCSI RDMA, etc. The storage device interface 139 may communicate with the one or more storage devices 120 using input-output control (IO-CTL) commands, IO-CTL command extensions, remote direct memory access, etc.

[0051] Communication interface 113 may include one or more network interfaces configured to communicatively couple host computing device 110 and / or controller 126 to network 115 and / or to one or more remote clients 117 (which may serve as additional hosts). Controller 126 may be part of and / or in communication with one or more storage devices 120. Figure 1 A single storage device 120 is shown, but the present disclosure is not limited in this regard and may be adapted to incorporate any number of storage devices 120 .

[0052] The storage device 120 may include one or more non-volatile memory devices 123 of the non-volatile memory channel 122, which may include, but are not limited to: ReRAM, memristor memory, programmable metallization cell memory, phase change memory (PCM, PCME, PRAM, PCRAM, bidirectional unified memory, chalcogenide RAM or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nm process memory, graphene memory, silicon oxide nitride oxide silicon (SONOS), programmable metallization cell (PMC), conductive bridge RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic storage media (e.g., hard disk, tape), optical storage media, etc. In some embodiments, the one or more non-volatile memory devices 123 of the non-volatile memory channel 122 include storage class memory (SCM) (e.g., write-in-place memory, etc.).

[0053] Although the nonvolatile memory channel 122 may be referred to herein as a "memory medium," in various embodiments, the nonvolatile memory channel 122 may more generally include one or more nonvolatile recording media capable of recording data, which may be referred to as nonvolatile memory media, nonvolatile memory devices, etc. In addition, in various embodiments, the storage device 120 may include a nonvolatile recording device, a nonvolatile memory array 129, a plurality of interconnected storage devices in an array, etc.

[0054] The non-volatile memory channel 122 may include one or more non-volatile memory devices 123, which may include, but are not limited to, chips, packages, planes, dies, etc. The controller 126 may be configured to manage data operations on the non-volatile memory channel 122, and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the controller 126 may be configured to store data on the non-volatile memory channel 122 and / or read data from the non-volatile memory channel, to transfer data to / from the storage device 120, etc.

[0055] The controller 126 may be communicatively coupled to the nonvolatile memory channel 122 via a bus 127. The bus 127 may include an I / O bus for transferring data to / from the nonvolatile memory devices 123. The bus 127 may also include a control bus for transferring addressing and other command and control information to the nonvolatile memory devices 123. In some embodiments, the bus 127 may communicatively couple the nonvolatile memory devices 123 to the controller 126 in parallel. This parallel access may allow the nonvolatile memory devices 123 to be managed as a group, thereby forming a nonvolatile memory array 129. The nonvolatile memory devices 123 may be divided into corresponding logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks). The logical memory units may be formed by logically combining the physical memory units of each nonvolatile memory device 123.

[0056] In some embodiments, the controller 126 may use the addresses of the word lines to organize blocks of word lines within the nonvolatile memory device 123 so that the word lines can be logically organized into a monotonically increasing sequence (e.g., decoding and / or converting the addresses of the word lines into a monotonically increasing sequence, etc.). In another embodiment, the word lines of a block within the nonvolatile memory device 123 can be physically arranged in a monotonically increasing sequence of word line addresses, where consecutively addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2, . . . WLN).

[0057] Controller 126 may include and / or communicate with a device driver executing on host computing device 110. The device driver may provide storage services to host client 116 via one or more interfaces 133. The device driver may also include a storage device interface 139 configured to transmit data, commands, and / or queries to controller 126 via bus 125, as described above.

[0058] refer to Figure 2 , a schematic block diagram of an exemplary storage device 120 suitable for a computing SSD system supporting semantic search according to an embodiment of the present disclosure. The controller 126 may include a front-end module 208 that interacts with a host via multiple high priority and low priority communication channels, a back-end module 210 that interacts with a non-volatile memory device 123, and various other modules that perform various functions of the storage device 120. In some examples, each module may be only a portion of a memory that includes instructions that can be executed by a processor to implement the features of the corresponding module, and the module does not include any other hardware. Because each module includes at least some hardware, each module may be interchangeably referred to as a hardware module even when the included hardware includes software.

[0059] The controller 126 may include a buffer management / bus control module 214 that manages buffers in a random access memory (RAM) 216 and controls internal bus arbitration to communicate on an internal communication bus 217 of the controller 126. A read-only memory (ROM) 218 ​​may store and / or access system boot code. Figure 2 218 can be located within the controller 126. In some implementations, the controller 126, RAM 216, and ROM 218 can be located on separate semiconductor dies. As discussed below, in one implementation, the submission queue and the completion queue can be stored in a controller memory buffer that can be accommodated in the RAM 216.

[0060] In addition, the front-end module 208 may include a host interface 220 and a physical layer interface 222 that provide an electrical interface with a host or a next-level storage controller. The selection of the type of host interface 220 may depend on the type of memory used. Exemplary types of host interface 220 may include, but are not limited to, SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 may generally facilitate the transmission of data, control signals, and timing signals.

[0061] The back-end module 210 may include an error correction engine 224 that encodes data bytes received from the host and decodes and corrects data bytes read from the non-volatile memory device 123 using an error correction code (ECC). The back-end module 210 may also include a command sequencer 226 that generates command sequences, such as a program command sequence, a read command sequence, and an erase command sequence, for transmission to the non-volatile memory device 123. In addition, the back-end module 210 may include a RAID (Redundant Array of Independent Drives) module 228 that manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the storage device 120. In some cases, the RAID module 228 can be part of the error correction engine 224. The memory interface 230 provides the command sequence to the non-volatile memory device 123 and receives status information from the non-volatile memory device 123. Data to be programmed into and read from the nonvolatile memory device 123 may be transferred along with command sequences and status information through the memory interface 230. The flash control layer 232 may control the overall operation of the backend module 210.

[0062] Figure 2 Additional modules of the storage device 120 shown in FIG. 1 may include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory device 123. The storage device 120 may also include other discrete components 240, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that may interact with the controller 126. In alternative embodiments, one or more of the RAID module 228, the media management layer 238, and the buffer management / bus control module 214 may be optional components that may not be required in the controller 126.

[0063] Finally, the controller 126 may also include a smart memory array logic component 234. In many embodiments, the smart memory array logic component 234 may be configured to receive a query, extract context data from the received query, and determine a machine learning model for processing the query based on the extracted context data. The determination of the machine learning model for further processing the query may be performed by the controller 126. In some embodiments, the controller 126 may determine one or more suitable machine learning models for further processing the query. The smart memory array logic component 234 may be provided by hardware, firmware, software, circuits and / or components or any combination thereof for receiving data (e.g., a query) and performing a machine learning process, calculation, comparison, operation or other processing to obtain and / or extract context data from the received query, thereby generating one or more query vectors, and then determining one or more suitable machine learning models for further processing the one or more query vectors. This may include accessing control data stored in the storage device 120, scanning the non-volatile memory devices 123 for relevant pages and determining relevant non-volatile memory devices 123 associated with the generated query vector, and passing the query vector to one or more determined relevant non-volatile memory devices 123.

[0064] Each of the non-volatile memory devices 123 may include feature data and feature vector storage associated with one or more machine learning models and processes. The feature data may be evenly distributed in each of the one or more non-volatile memory devices 123. In some embodiments, the non-volatile memory devices 123 may be grouped into a plurality of sets, wherein each set of non-volatile memory devices 123 provides a specific machine learning model and performs a machine learning process based on the specific machine learning model. In addition, each set of non-volatile memory devices 123 may include the same or different feature data and feature vector storage. The controller 126 may then pass the query vector to one or more relevant non-volatile memory devices 123.

[0065] Each of the non-volatile memory devices 123 of the memory array 129 may also include one or more machine learning processing units configured to process a query vector obtained from the controller 126 as a first input. Feature data within the one or more non-volatile memory devices 123 may be used as a second input, and the query vector and feature data may be buffered in the memory device before being processed by the one or more machine learning processing units. For example, the first input and the second input are processed to generate a comparison value. The one or more non-volatile memory devices 123 may be grouped into one or more memory sets based on similarities in the machine learning processing unit or similarities in the feature data. As a result of processing the first input and the second input from the one or more non-volatile memory devices 123, the controller 126 may obtain a comparison value or output data. In some embodiments, one or more sets of non-volatile memory devices 123 may be grouped together based on a specific machine learning model or process, similarities in the machine learning processing unit, or similarities in the feature data.

[0066] refer to Figure 3 , a conceptual illustration of a page of memory cells being sensed or programmed in parallel, organized, for example, in a NAND configuration, according to an embodiment of the present disclosure. Figure 3 Conceptually show Figure 1 A 'page' such as page 360 ​​is a group of memory cells that can be sensed or programmed in parallel. This is achieved in the peripheral circuitry by a corresponding page of sense amplifiers 310. The sensed results can be utilized in latches within a corresponding set of data latches 320. Each sense amplifier can be coupled to a NAND string such as NAND string 350 via a bit line 336. For example, page 360 ​​can be sensed along a row and by a sense voltage applied to the control gates of the cells of the page that are commonly connected to word line WL3. Along each column, each memory cell such as memory cell 311 can be accessed by a sense amplifier via a bit line 336. The data in the data latches 320 can be transferred from or to the memory controller 126 via a data I / O bus 331.

[0067] The NAND string 350 may be a series of memory cells, such as memory cell 311, connected in a daisy-chain manner by their sources and drains to form source and drain terminals at their ends, respectively. A pair of select transistors S1, S2 may control the connection of the memory cell chain to an external source via the source and drain terminals of the NAND string, respectively. In the memory array, when the source select transistor S1 is turned on, the source terminal is coupled to the source line 334. Similarly, when the drain select transistor S2 is turned on, the drain terminal of the NAND string is coupled to the bit line 336 of the memory array. Each memory cell 311 in the chain is used to store charge. The memory cell has a charge storage element to store a given amount of charge so as to represent an expected memory state. In many embodiments, a control gate within each memory cell may allow control of read and write operations. Typically, the control gates of the corresponding memory cells of each row within a plurality of NAND strings may all be connected to the same word line (such as, WL0, WL1...WLn 342). Similarly, the control gate of each of the select transistors S1, S2 (accessed via select lines 344SGS and SGD, respectively) provides control access to the NAND string via its source and drain terminals, respectively.

[0068] Although the exemplary memory devices mentioned above include physical pages of memory cells that store a single bit of data, in most embodiments, each cell stores multiple bits of data, and each physical page may have multiple pages of data. Additionally, in another embodiment, a physical page may store one or more logical sectors of data. Typically, a host computing device 110 (see FIG. 1 ) operating with a disk operating system Figure 1) manages the storage of files by organizing the contents of the files in units of logical sector portions, which are typically in units of one or more 512 bytes. In some embodiments, a physical page may have 16kB of memory cells sensed in parallel by a corresponding 16kB sense amplifier via a 16kB bit line. An exemplary logical sector portion allocated by the host has a data size of 2kB. Therefore, if the cells are each configured to store 1 bit of data (SLC), then a physical page can store 8 sector portions. For MLC, TLC, and QLC and other density-increasing structures, each cell can store 2, 3, 4, or more bits of data, and each physical page can store 16, 32, 64, or more logical sector portions, depending on the structure utilized. For feature vector sizes and allocations in a computing SSD system that supports semantic search, the machine learning processing unit of the non-volatile memory device 123 can be configured to accommodate different feature vector sizes. As an example, a media file (e.g., an image, a document, a video, etc.) can be represented by any number of feature vectors. In some embodiments, the feature vector of the media file may be 128 to 1024 features, and the size of the feature vector may be 256B to 2KB. Then for a 16KB NAND flash memory page, reading one page will obtain 8 to 64 feature vectors.

[0069] A unique difference between flash memory and other types of memory is that the memory cell must be programmed from an erased state associated with no charge in the memory cell. This requires that the charge of the floating gate must first be cleared before programming. Programming adds the required amount of charge back to the floating gate. It may not support removing a portion of the charge from the floating to change from a more programmed state to a less programmed state. Therefore, new data cannot overwrite existing data and must be written to a location that was not previously written or erased. In addition, erasing all charges from the floating gate may usually take a considerable amount of time. For this reason, erasing cell by cell or even page by page will be cumbersome and inefficient. Therefore, in most embodiments, the memory cell array is divided into a large number of blocks. It is common for many flash-based memory systems that blocks are erased units. That is, each block contains the minimum number of memory cells erased in one action. This, combined with the limited life of the memory cells in the flash memory, increases the expectation of limiting the amount of erasure and programming that occurs in the storage device.

[0070] refer to Figure 4, a schematic block diagram of an exemplary computing SSD system supporting semantic search according to an embodiment of the present disclosure. As described above, the controller 426 includes an intelligent memory array logic component 434 and a result aggregation unit 412. The controller 426 receives a semantic search query 401 and passes the query 401 to the intelligent memory array logic component 434 for processing. In some embodiments, the controller 426 may receive data (e.g., a query) and perform a machine learning process, calculation, comparison, operation, or other processing to obtain and / or extract context data from the received query 401 and prepare the query 401 for the intelligent memory array logic component 434. The content of the query 401 may include one or more of text, documents, images, audio, or other media. Upon receiving the query 401, the controller 426 processes the query 401 and extracts context data from the query 401. In addition to extracting context data from the query 401, other relevant context information for constructing context data can be obtained by comparing the query 401 and / or context data with one or more dictionaries, libraries, or databases, or a combination thereof. Relevant contextual information may be added to the query 401 or contextual data extracted from the query 401 for further processing. In addition, the contextual information may be stored locally on the controller 426 or may be remotely accessed by the controller 426 and the smart memory array logic component 434. The controller 426 passes the contextual data to the smart memory array logic component 434, and the smart memory array logic component 434 determines a machine learning model for processing the query 401 based on the contextual data provided by the controller 426.

[0071] In some embodiments, the controller 426 may determine one or more suitable machine learning models or machine learning processes within the smart memory array logic component 434 for further processing the query 401. The smart memory array logic component 434 may receive data (e.g., a query) and perform machine learning processes, calculations, comparisons, operations, or other processing to obtain and / or extract context data from the received query 401.

[0072] The smart memory array logic component 434 processes the query 401 and / or contextual data from the query 401 and generates a query vector 403 based on the received query 401, the contextual data from the query 401, or a combination thereof. In addition, the query vector 403 may be generated in part or in whole based on the determined machine learning model. The smart memory array logic component 434 may determine one or more relevant non-volatile memory devices 423 or a set of non-volatile memory devices 423 for processing the generated query vector 403. The determination may be based on the query 401, the contextual data from the query 401, the relevant contextual information from the query 401, or the determined machine learning model, or any combination thereof. The smart memory array logic component 434 then passes the generated query vector 403 to one or more relevant non-volatile memory devices 423.

[0073] As discussed above, each of the one or more non-volatile memory devices 423 includes feature data and one or more machine learning processing units 421aa, 421ab, ... 421an, 421ba, 421bb, ... 421bn, 421na, 421nb, ... 421nn, etc. (hereinafter referred to as "machine learning processing units 421"), wherein each machine learning processing unit 421 may include hardware, firmware, software, circuits and / or components or any combination thereof for performing machine learning procedures, calculations, comparisons, operations or other processing to obtain results and / or values ​​based on inputs from the feature data stored on the non-volatile memory device 423 and inputs provided by the smart memory array logic component 434. Each of the one or more machine learning processing units 421 can be configured to process the passed query vector 403 as a first input and utilize the stored feature data as a second input. The one or more machine learning processing units 421 may then process the first input and the second input to generate a result and / or value (e.g., a comparison value) as an output 405 to the controller 426. The smart memory array logic component 434 may add feature metadata to the output 405 for further processing by the controller 426.

[0074] In some embodiments, the query vector 403 and the feature data may be buffered in a memory device before being processed by the one or more machine learning processing units 421. In addition, the feature data may be evenly distributed within the one or more non-volatile memory devices 423. In some embodiments, each of the one or more non-volatile memory devices 423 may be grouped into one or more memory sets based on similarity in the machine learning processing unit or similarity in the feature data.

[0075] The result aggregation unit 412 obtains the results and / or values ​​from all the machine learning processing units 421 as output 405, and performs machine learning processes, calculations, comparisons, operations, or other processing on the output 405, such as, for example, searching, collecting, and presenting the results from the output 405 in summary, report-based, or table form as results 470. The results 470 may be passed to the host 110 for further processing.

[0076] refer to Figure 5 , a schematic block diagram of an exemplary machine learning processing unit of a computing SSD system supporting semantic search according to an embodiment of the present disclosure. In some embodiments, the machine learning processing unit 421 may be configured to trade area for speed in a speed-constrained situation, thereby resulting in less hardware reuse or parallel processing with lower area efficiency. As an example, the machine learning processing unit 500 may be configured for higher speeds. The machine learning processing unit 500 may include hardware, firmware, software, circuits and / or components or any combination thereof for performing machine learning processes, calculations, comparisons, operations or other processing. The machine learning processing unit 500 includes: a module 571, which determines a query vector V q One or more distance calculation units 573a ... 573n (hereinafter referred to as "distance calculation unit 573"), which calculates the distance between two input vectors (eg, V q 、V f(i) ) between (e.g., Euclidean / Hamming distance); a control unit 574, which receives the query vector V from module 571; q The extracted feature sizes are then compared to the feature vector sizes by, for example, comparing the number of distance comparisons to the feature vector size and selecting the correct one as the input feature vector V for all input features. f(i)... V f(i+n) The final similarity score is used to adapt to the changed feature vector size. In addition, the machine learning processing unit 500 includes a module 575 having one or more machine learning operators, functions, or registers to perform machine learning processing, for example, comparing two distance inputs from the distance calculation unit 573 and outputting the smaller distance to a register. The register of the module 575 can then provide the result, score, or value to the non-volatile memory device 423 and / or the controller 426.

[0077] refer to Figure 6, a schematic block diagram of an exemplary machine learning processing unit of a computing SSD system supporting semantic search according to an embodiment of the present disclosure. In some embodiments, the machine learning processing unit 421 may be configured to trade speed for area in an area-constrained situation, thereby resulting in hardware reuse or serial processing with lower speed. As an example, the machine learning processing unit 600 may be configured for high area efficiency. The machine learning processing unit 600 may include hardware, firmware, software, circuits and / or components or any combination thereof for performing machine learning processes, calculations, comparisons, operations or other processing. The machine learning processing unit 600 includes: a module 671, which determines a query vector V q The feature vector size; a distance calculation unit 673, which is used to calculate two input vectors (eg, V q 、V f ) between (e.g., Euclidean / Hamming distance); a control unit 674, which receives the query vector V from module 671; q The extracted feature sizes are then compared to the feature vector sizes by, for example, comparing the number of distance comparisons to the feature vector size and selecting the correct one as the input feature vector V for all input features. f The final similarity score is used to adapt to the changed feature vector size. In addition, the machine learning processing unit 600 includes a module 675 having one or more machine learning operators, functions, or registers to perform machine learning processing, for example, comparing two distance inputs from the distance calculation unit 673 and outputting the smaller distance to a register. The register of the module 675 can then provide the result, score, or value to the non-volatile memory device 423 and / or the controller 426.

[0078] refer to Figure 7 , depicting a flow diagram of a process 700 for utilizing an exemplary computing SSD system supporting semantic search according to an embodiment of the present disclosure. Process 700 may begin by receiving a query (block 710). In many embodiments, when this occurs, a host or SSD controller receives a query for a semantic search. In some embodiments, a user provides a semantic search request that is passed to the host or SSD controller. In response, various embodiments of the controller may direct multiple processes (such as controller 426 for a computing SSD system supporting semantic search (see Figure 4 ) within those processes) perform the semantic search process 700.

[0079] Process 700 may extract context data from the received query (block 715). In some embodiments, the context data may be obtained directly from the query. As described above, in some embodiments, context information relevant to the query may be obtained from other resources to help construct context data for the query. Relevant context information for constructing context data may be obtained by comparing the query and / or context data with one or more machine learning processes that access a dictionary, library, or database, or a combination thereof.

[0080] Process 700 may determine a machine learning model based on the extracted context data (block 720). As is known in the art, various machine learning models may be used to extract and process features from the query, such as convolutional neural networks (CNNs), computer vision, supervised learning, semi-supervised learning, unsupervised learning, reinforcement learning (RL), deep learning (DL), artificial neural networks (ANNs), computer vision, speech recognition, natural language processing, machine translation, and others as needed.

[0081] After determining the machine learning model based on the extracted context data, process 700 can utilize the machine learning model to process the query (block 725). By way of example and not limitation, when processing a query, various features can be obtained from the machine learning model, which can be processed to create vectors and prepared for machine learning processes such as similarity search.

[0082] Based on the features obtained from the received query and the determined machine learning model, the process 700 may generate a query vector (block 730) and determine one or more relevant non-volatile memory devices associated with the generated query vector (block 735). As discussed above, the non-volatile memory device 123 may be part of any suitable storage device 120 that may have a variety of different types of memory devices. By way of example and not limitation, the storage device may include a plurality of non-volatile NAND memory devices including single-level cell NAND memory and quad-level cell NAND memory.

[0083] The process 700 may pass a query vector to one or more determined relevant non-volatile memory devices (block 740). The process 700 may process the passed query vector as a first input (block 745) and utilize feature data on the one or more related non-volatile memory devices as a second input (block 750). As described above, the one or more determined relevant non-volatile memory devices have a machine learning processing unit that processes the query vector as a first input and the feature data stored on the one or more non-volatile memory devices as a second input.

[0084] The process 700 may process the first input and the second input to generate a comparison value (block 755). In certain embodiments, the process 700 may utilize a hyperdimensional vector / vector symbol architecture to implement on-die computation without error correction code (ECC). In this way, features may be stored as hyperdimensional vectors rather than dense feature vectors that may be noise resilient.

[0085] refer to Figure 8 , depicting a flow diagram of a process 800 for utilizing an exemplary computing SSD system supporting semantic search according to an embodiment of the present disclosure. Process 800 may begin by processing a query using a machine learning model (block 810). In many embodiments, when this occurs, a host or SSD controller receives a query for a semantic search. In some embodiments, a user provides a semantic search request that may be passed to the host or SSD controller. In response, various embodiments of the controller may direct multiple processes (such as controller 426 for a computing SSD system supporting semantic search (see Figure 4 ) within those processes) perform the semantic search process 800.

[0086] Process 800 may generate a query vector (block 815). In generating the query vector, contextual data may be obtained directly from the query and the processing of the query by the machine learning model. By way of example and not limitation, in processing the query, various features may be obtained from the machine learning model, which may be processed to create a vector and prepared for a machine learning process such as a similarity search. As is known in the art, various machine learning models may be used to extract and process features from the query, such as convolutional neural networks (CNNs), computer vision, supervised learning, semi-supervised learning, unsupervised learning, reinforcement learning (RL), deep learning (DL), artificial neural networks (ANNs), computer vision, speech recognition, natural language processing, machine translation, and others as needed.

[0087] The process 800 may pass the query vector to one or more machine learning processing units as a first unit (block 820), which further utilizes feature data stored on one or more associated non-volatile memory devices as a second input (block 825). The process 800 may utilize the one or more machine learning processing units to process the first input and the second input to determine output data to be retrieved from the one or more non-volatile memory devices (block 830). The process 800 may assign feature metadata to the output data using smart memory array logic components (block 835). In certain embodiments, the process 800 may utilize a hyperdimensional vector / vector symbol architecture to implement on-die computation without error correction code (ECC). In this way, features may be stored as hyperdimensional vectors rather than dense feature vectors that may be noise resilient.

[0088] refer to Figures 7 and 8,Hyperdimensional computing is used to calculate similarities between data and can be implemented by, for example, three operations including addition, multiplication, and permutation.,Hyperdimensional computing can be inherently robust because information is evenly distributed across each bit of a supervector and provides fast learning capability, high energy efficiency, and acceptable accuracy in learning and classification tasks.

[0089] refer to Fig. 9 , a schematic block diagram of an exemplary machine learning process according to an embodiment of the present disclosure. As shown, the input of the machine learning system 900 may include a semantic search request through one or more queries 901. The query 901 may include text, images, documents, audio, or other media. The query 901 may be passed to the smart memory array logic component 934, which performs machine learning processes, calculations, comparisons, operations, or other processing to obtain and / or extract context data from the received query 901. The smart memory array logic component 934 determines the context data from the query 901 and assigns features to the query 901 to form a query vector 903 as a first input to the machine learning processing unit (MPLU) 921 of the machine learning system 900.

[0090] The second input of the machine learning system 900 includes data stored on the SSD device, such as one or more media files 902. The media files 902 may include text, images, documents, audio, or other media. The stored media files 902 may be assigned feature data 904 by the smart memory array logic component 934, and each media file 902 may be stored on one or more non-volatile memory devices 123. The feature data 904 may be scanned from the one or more non-volatile memory devices 123 by the MPLU 921 as a second input for comparison with the query vector 903.

[0091] The MPLU 921 follows an iterative process of retrieving, extracting, calculating, and comparing the feature data 904 of the stored media file 902 with the query vector 903 to obtain output data 905. The output data 905 may be provided as a result of one or more operations of the MPLU 921. In some embodiments, the output data 905 may be a similarity score of a comparison between the query vector 903 and one or more sets of feature data 904. The output data 905 may then be passed to the controller 126 for further processing.

[0092] In some embodiments, the controller 426 may determine one or more suitable machine learning models or machine learning processes within the smart memory array logic component 934 for further processing the query 401. The smart memory array logic component 934 may receive data (e.g., a query) and perform machine learning processes, calculations, comparisons, operations, or other processing to obtain and / or extract context data from the received query 901.

[0093] As discussed above, each machine learning processing unit 921 may include hardware, firmware, software, circuits and / or components, or any combination thereof, for performing machine learning processes, calculations, comparisons, operations, or other processing to obtain results and / or values ​​based on inputs from feature data stored on the non-volatile memory device 123 and inputs provided by the smart memory array logic component 934.

[0094] In some embodiments, the query vector 903 and the feature data 904 may be buffered in a memory device before being processed by the one or more machine learning processing units 921. In addition, the feature data 904 may be evenly distributed within the one or more non-volatile memory devices 123. In some embodiments, each of the one or more non-volatile memory devices 123 may be grouped into one or more memory sets based on similarity in the machine learning processing unit or similarity in the feature data.

[0095] refer to Fig. 10A , a schematic block diagram of an exemplary error correction system according to an embodiment of the present disclosure. As shown in the figure, the error correction system 1000 is used to integrate the ECC function for encoding and decoding dense feature vectors.

[0096] The exemplary error correction system 1000 may include a host 1010, an SSD controller 1026, a NAND flash memory array 1029, and a volatile memory 1016 (e.g., DRAM). The error correction system 1000 may also include a host interface 1020, an embedded processor 1011, an ECC memory module 1024 having at least one encoding 1024a and decoding 1024b circuit and process, and a flash memory interface 1032 partially or entirely included within or otherwise communicating with or integrated within the SSD controller 1026. The embedded processor 1011 may communicate with the volatile memory 1016. The volatile memory 1016 may be integrated within the SSD controller 1026 and / or communicate with the embedded processor 1011.

[0097] The NAND flash memory array 1029 may include a plurality of NAND dies 1023, each having memory circuits and logic components 1027 including an ECC memory module 1028 and a machine learning processing unit 1021. In some embodiments, the exemplary error correction system 1000 may operate in a storage mode, wherein the SSD controller 1026 receives file data and one or more instructions from the host 1010 to store the data on the NAND die 1023. Additionally, in the storage mode, the SSD controller 1026 may receive one or more instructions from the host 1010 to access the same or different file data stored on the NAND die 1023. As shown, in a write operation, the ECC memory module 1024 may encode an error correction code within the file data to facilitate storage, retrieval, and processing of error-free file data on the NAND die 1023. Furthermore, in order to retrieve error-free file data to send to the host 1010, in a read operation, the ECC memory module 1024 may use the encoded error correction code for the file data to process and / or remove file data errors received from the file data stored on the NAND die 1023. In some embodiments, file data errors in storage mode may be introduced at any file data processing stage from receiving file data and / or instructions by the host 1010 to storing the file data and / or instructions on the NAND flash memory array 1029, for example, but not limited to, at the flash interface 1032 or within the SSD controller 1026.

[0098] In some embodiments, the exemplary error correction system 1000 can operate in a computing mode, where the NAND flash memory array 1029 utilizes a memory circuit and logic component 1027 with an ECC memory module 1028 to encode, decode, verify error-free feature data (e.g., a dense feature vector) and provide the error-free feature data to the machine learning processing unit 1021 for comparison with a query vector to obtain a score. Therefore, each NAND die 1023 includes an ECC function for encoding and decoding feature data error correction codes to provide error-free feature data or error-free dense feature vectors. Therefore, the NAND die 1023 stores at least two types of data: original file data and feature data (e.g., feature vectors) corresponding to the file. The memory circuit and logic component 1027 can perform feature data management to maximize feature data processing efficiency, such as parallel processing on feature data and die. In some embodiments, similar to the machine learning processing unit 1021 being disposed in each NAND die 1023, the memory circuit and logic component 1027 may also be distributed in the NAND flash memory array 1029 as a single unit of each NAND die 1023 to handle the file data and feature data stored on the corresponding NAND die 1023. Furthermore, in some embodiments, the feature data may be equally divided and distributed on each NAND die 1023 of the NAND flash memory array 1029. Furthermore, the feature vector may be relocated within the same NAND die 1023 during storage management operations such as, for example, garbage collection.

[0099] Fig. 10B According to the embodiments of the present disclosure Fig. 10A . A diagram of an exemplary error correction system of FIG. 1 . To ensure data integrity, data scrubbing may be performed on feature vectors (e.g., using FV scrubbing) and file data (e.g., using conventional data scrubbing). As shown, the number of bit flips per time for FV data scrubbing of feature data may be performed at a higher frequency than conventional data scrubbing of file data, or at a fraction of the frequency of conventional data scrubbing, such as 1 / 6, 1 / 4, 1 / 3, 1 / 2, 2 / 3 of the conventional scrubbing time. In addition, once a predetermined threshold of bit flips is reached, FV scrubbing and conventional scrubbing may be triggered. For example, when the FV threshold is reached, FV scrubbing may be performed, and when the conventional threshold is reached, conventional scrubbing may be performed. In some embodiments, a combination of time / frequency and threshold may be used to perform at least one of FV scrubbing or conventional scrubbing. As shown, FV data scrubbing may be performed at 2 / 3 of the time of conventional scrubbing of file data.

[0100] Fig. 10C According to the embodiments of the present disclosure Fig. 10ATable of an exemplary error correction system of FIG. As described above, file data and feature data error correction are shown. File data and feature data may also undergo data scrubbing to reduce the possibility of a single correctable error accumulating into multiple uncorrectable errors. As shown, an error correction engine may be used to verify file data, and conventional data scrubbing may be used to perform wear leveling to maintain data integrity of file data in storage mode. Conventional data scrubbing may include error correction techniques that use one or more background tasks to periodically check for errors in a main memory or storage device, and then use redundant data in the form of different checksums or data copies to correct the detected errors. File data is cleaned by a process of detecting and correcting damaged or inaccurate records from a record set, table, or database, and identifying incomplete, incorrect, inaccurate, or irrelevant portions of the data, and then replacing, modifying, or deleting erroneous, damaged, or rough data.

[0101] As an example, when the exemplary error correction system 1000 is in a computation mode for feature vector data (e.g., a compact feature vector), on-die ECC is required. In some embodiments, in order to reduce the area and delay overhead of the on-die ECC, a weaker ECC, such as Bose–Chaudhuri–Hocquenghem (BCH), can be used. In some embodiments, other types of on-die ECC, such as low-density parity check (LDPC), can be used. In addition, on-die ECC can also be further used for file data error correction. In some embodiments, feature vector data (e.g., a compact feature vector) can be stored in its own memory block separately from file data for easier data management. In some embodiments, feature vector data (e.g., a compact feature vector) can be stored in the same memory block with related file data for faster computation time and data access. Data scrubbing of file data can use the above-mentioned conventional data scrubbing, while feature data can use an independent data scrubbing algorithm to, for example, remove erroneous, incorrect, incomplete, empty, or duplicate feature vector data.

[0102] In some embodiments, when the SSD storage device 120 is operating in semantic search mode, requests from the host 1010 to service read / write requests may be ignored, delayed and executed after some semantic search operations have been completed, or queued to be executed after all semantic search operations have been completed, or any combination thereof. Thus, the volatile memory 1016 may be used to load feature data associated with data management data structures, rather than logical to physical (L2P) tables for file data access.

[0103] Regarding feature vector data management, the application needs to maintain at least one database in the SSD storage device 120 for performing fast semantic searches, for example, the database may contain attributes: file name, hash value, and feature vector data. In addition, at least one file may contain attribute file name and hash value to be loaded into the application when the application is started. In some embodiments, the information of hash value and feature vector data may be contained in one or more data structures (e.g., table X) to index one or more feature vectors. In some embodiments, table X may be stored in the SSD storage device 120 firmware, and table X may contain attributes of Addr, hash value, and feature vector data. In addition, based on the hash value returned from the semantic search, the application can retrieve the file name from the search results. In some embodiments, the size of table X may be proportional to the number of files stored in the SSD storage device 120. In addition, in some embodiments, Addr may be in the form of [die, plane, block, page, fragment], where the number of bits represents the fragment.

[0104]

[0105] In some embodiments, the hash value feature vector may be a cascade of a hash value and its feature vector to simplify data management. In addition, when the SSD storage device 120 receives a search request (e.g., a query), the SSD controller 1026 needs to generate a special search command and send it to each NAND flash die 1023. The SSD controller 1026 can inform the NAND flash die 1023 which block contains the feature vector data, and the NAND flash die 1023 should perform calculations accordingly. In addition, each NAND flash die 1023 can execute the function top_k hashvalue=Loop(search(query_vec,plane#,block#,last_page#,last segment#)).

[0106] Fig.11A11 is a schematic block diagram of an exemplary error correction system according to an embodiment of the present disclosure. As shown, the error correction system 1100 is used to integrate ECC functions for encoding and decoding hyperdimensional vectors (HDV) or vector symbol architectures (VSA), where on-die ECC can be optional. In the present disclosure, HDV and VSA are used interchangeably, however, HDV will be used hereinafter. In some embodiments, it may be too expensive to integrate ECC logic components, circuits, or processing in each NAND die 1123. For example, incorporating an ECC memory module 1128 into each NAND die 1123 may be very expensive, or occupy too much area on the NAND flash memory array 1129. Instead, HDV / VSA can be stored for each file, where such context / semantic representations can be robust to noise, thereby preserving similarity, and can be read from the NAND flash die 1123 and calculated without error correction.

[0107] An exemplary error correction system 1100 may include a host 1110, an SSD controller 1126, a NAND flash memory array 1129, and a volatile memory 1116 (e.g., DRAM). The error correction system 1100 may also include a host interface 1120, an embedded processor 1111, an ECC memory module 1124 having at least one encoding 1124a and decoding 1124b circuit and process, and a flash memory interface 1132 partially or entirely included in or otherwise communicating with or integrated within the SSD controller 1126. The embedded processor 1111 may communicate with the volatile memory 1116. The volatile memory 1116 may be integrated within the SSD controller 1126 and / or communicate with the embedded processor 1111.

[0108] The NAND flash memory array 1129 may include a plurality of NAND dies 1123, each having memory circuits and logic components 1127 including a machine learning processing unit 1121. In some embodiments, the exemplary error correction system 1100 may operate in a storage mode, wherein the SSD controller 1126 receives file data and one or more instructions from the host 1110 to store the data on the NAND die 1123. Additionally, in the storage mode, the SSD controller 1126 may receive one or more instructions from the host 1110 to access the same or different file data stored on the NAND die 1123. As shown, in a write operation, the ECC memory module 1124 may encode an error correction code within the file data to facilitate storage, retrieval, and processing of error-free file data on the NAND die 1123. Furthermore, in order to retrieve error-free file data to send to the host 1110, in a read operation, the ECC memory module 1124 may use the encoded error correction code for the file data to process and / or remove file data errors received from the file data stored on the NAND die 1123. In some embodiments, file data errors in storage mode may be introduced at any file data processing stage from receiving file data and / or instructions by the host 1110 to storing the file data and / or instructions on the NAND flash memory array 1129, for example, but not limited to, at the flash interface 1132 or within the SSD controller 1126.

[0109] In some embodiments, the exemplary error correction system 1100 may operate in a computational mode, wherein the NAND flash memory array 1129 utilizes the memory circuit and logic component 1127 and the ECC memory module 1128 of the SSD controller 1126 to encode, decode, verify, and provide error-free feature data (e.g., HDV / VSA vectors) to the machine learning processing unit 1121 for comparison with the query vector to obtain a score. Each NAND die 1123 utilizes two copies of the HDV vector, the ECC function from the ECC memory module 1128, and the exemplary error correction scheme described below to encode and decode feature data error correction codes to provide error-free feature data, such as error-free HDV vectors.

[0110] In the exemplary error correction system 1100, the NAND die 1123 stores at least two types of data: raw file data and HDV / VSA vectors. Feature data corresponding to the file data (e.g., HDV vectors) can be very robust to noise, preserve similarity, and can be read from the NAND die 1123 and calculated without error correction. In some embodiments, two copies of the HDV vector can be stored on each NAND die 1123 corresponding to the file data; a first copy, the HDV without ECC decoding, and a second copy, the HDV with SSD controller 1026 ECC encoding. As shown, the first copy of the HDV vector without ECC decoding can be used by the machine learning processing unit 1121. However, due to the limitations on its resilience, the blocks storing the HDV vectors also need wear leveling.

[0111] The second copy of the HDV vector with ECC decoding may be used to correct errors in the first copy of the HDV vector. When the scrubbing algorithm finds that the bit error rate of the HDV copy with ECC decoding exceeds a predefined threshold, the corrected HDV without ECC decoding may be stored on the memory circuit and logic component 1127, and the HDV copy with ECC decoding may be relocated to the memory circuit and logic component 1127. In some embodiments, depending on the application, when the VSA vector is very long and ultra-robust, an independent scrubbing algorithm for the second copy of the HDV vector with ECC decoding may not be needed, otherwise, an independent scrubbing algorithm may be performed on the HDV vector with ECC decoding.

[0112] The memory circuit and logic unit 1127 may perform feature data management to maximize feature data processing efficiency, such as parallel processing of feature data and on-die. In some embodiments, the memory circuit and logic unit 1127 may also be distributed in the NAND flash memory array 1129 as a single unit for each NAND die 1123 to handle file data and HDV vector data stored on the corresponding NAND die 1123. In addition, in some embodiments, the feature data may be equally divided and distributed on each NAND die 1123 in the NAND flash memory array 1129. In addition, the feature vector data may be relocated within the same NAND die 1123 during storage management operations such as, for example, garbage collection.

[0113] Fig. 11B According to the embodiments of the present disclosure Fig.11A. A diagram of an exemplary error correction system of FIG. 4 . To ensure data integrity, data scrubbing may be performed on HDV vectors (e.g., using HDV scrubbing) and file data (e.g., using conventional data scrubbing). As shown, the number of bit flips per time for HDV data scrubbing of feature data may be performed at a higher frequency than conventional data scrubbing of file data, or at a fraction of the frequency of conventional data scrubbing, such as 1 / 6, 1 / 4, 1 / 3, 1 / 2, 2 / 3 of the conventional scrubbing time. In addition, once a predetermined threshold of bit flips is reached, the HDV scrubbing and conventional scrubbing may be triggered. For example, when the HDV threshold is reached, the HDV scrubbing may be performed, and when the conventional threshold is reached, the conventional scrubbing may be performed. In some embodiments, a combination of time / frequency and threshold may be used to perform at least one of the HDV scrubbing or the conventional scrubbing. As shown, the HDV data scrubbing may be performed at 2 / 3 of the time of the conventional scrubbing of the file data.

[0114] Fig. 11C According to the embodiments of the present disclosure Fig.11A Table of an exemplary error correction system. As described above, file data and feature data error correction are shown. File data and feature data may also undergo data scrubbing to reduce the possibility of a single correctable error accumulating into multiple uncorrectable errors. As shown, the SSD controller 1126ECC may be used to verify file data, and conventional data scrubbing (e.g., low-density parity check (LDPC) for wear leveling) may be used to maintain data integrity of file data in storage mode. Conventional data scrubbing may include error correction techniques that use one or more background tasks to periodically check errors in the main memory or storage device, and then use redundant data in the form of different checksums or data copies to correct the detected errors. File data may be cleaned by detecting and correcting damaged or inaccurate records from a record set, table, or database, and identifying incomplete, incorrect, inaccurate, or irrelevant portions of the data, and then replacing, modifying, or deleting the erroneous, damaged, or rough data.

[0115] As an example, when the exemplary error correction system 1100 is in the computation mode, conventional data scrubbing may not be required for the first copy of the HDV vector (i.e., HDV, HDV vector without ECC decoding). In some embodiments, conventional data scrubbing may be used as needed for the first copy of the HDV vector to maintain data integrity of feature data of the first copy of the HDV vector without ECC decoding. In addition, in the computation mode, the SSD controller 1126 ECC may be used to verify feature data of the second copy of the HDV vector (i.e., HDV copy, HDV vector with ECC decoding) using, for example, a low density parity check (LDPC). In addition, at least one of conventional data scrubbing or HDV scrubbing using a feature data scrubbing algorithm may be used, for example, to clear erroneous, incorrect, incomplete, empty, or duplicate feature vector data.

[0116] In some embodiments, when the SSD storage device 120 is operating in a semantic search mode, requests from the host 1110 to service read / write requests may be ignored, delayed, and executed after some semantic search operations have been completed, or queued to be executed after all semantic search operations have been completed, or any combination thereof. Thus, the volatile memory 1116 may be used to load feature data associated with data management data structures other than the logical to physical (L2P) table for file data access. In addition, HDV vector data management may be performed as described above.

[0117] In some embodiments, the hash value feature vector may be a cascade of a hash value and its feature vector to simplify data management. In addition, when the SSD storage device 120 receives a search request (e.g., a query), the SSD controller 1126 needs to generate a special search command and send it to each NAND flash die 1123. The SSD controller 1126 can inform the NAND flash die 1123 which block contains the feature vector data, and the NAND flash die 1123 should perform calculations accordingly. In addition, each NAND flash die 1123 can execute the function top_k hashvalue=Loop(search(query_vec,plane#,block#,last_page#,last segment#)).

[0118] Fig.12It is a schematic block diagram of an exemplary error correction mode and storage mode of a computing SSD system 1200 supporting semantic search with an error correction system according to an embodiment of the present disclosure. As shown in the figure, the exemplary computing SSD system 1200 supports semantic search in computing mode and raw file data processing in storage mode, wherein the host 1210 provides corresponding instructions and file data or feature data to the SSD storage device 1220. In some embodiments where the non-volatile memory 1316 is limited, the SSD storage device 1320 can switch between computing mode and storage mode to achieve result file retrieval. In addition, requests from the host 1310 to serve read / write requests can be ignored, delayed and executed after some semantic search operations have been completed, or queued to be executed after all semantic search operations have been completed, or any combination thereof. Therefore, the volatile memory 1116 can be used to load feature data associated with the data management data structure, rather than the logical to physical (L2P) table for file data access.

[0119] In step 1: compute mode, table X may use non-volatile memory 1216 (e.g., DRAM), query 1201 may be sent to SSD storage device 1220, processed (e.g., machine learning processing unit 1021 / 1121), and then the result or hash 1203 is returned to host 1210 for semantic search request.

[0120] In step 2: storage mode, non-volatile memory 1216 (e.g., DRAM) may be used for L2P table mapping, a data request 1205 may be sent to the SSD storage device 1220, processed (e.g., by the SSD controller 1026 / 1126), and then the file data 1207 is returned to the host 1210 for the file search / read / write / access request.

[0121] Fig.13 1 is a schematic block diagram of another exemplary error correction mode and storage mode of a computing SSD system 1300 supporting semantic search with an error correction system according to an embodiment of the present disclosure. In some embodiments where non-volatile memory 1316 may be sufficient for both storage mode and computing mode, storage operations and computing operations may be performed simultaneously or in parallel without requiring separate modes.

[0122] For example, table X may use non-volatile memory 1316 (e.g., DRAM), query 1301 may be sent to SSD storage device 1320, processed (e.g., machine learning processing unit 1021 / 1121), and then the result or hash 1303 is returned to host 1310 for semantic search requests. In addition, in parallel, non-volatile memory 1316 (e.g., DRAM) may be used for L2P table mapping, data request 1305 may be sent to SSD storage device 1320, processed (e.g., processed by SSD controller 1026 / 1126), and then file data 1307 is returned to host 1310 for file search / read / write / access requests. In addition, in some embodiments using hyperscale or storage arrays, semantic search and file data may be performed in parallel, and file data may be retrieved from a regular SSD using a copy of the file from SSD storage device 1320.

[0123] refer to Fig.14 , depicting a flow chart of a process 1400 for utilizing an exemplary error correction method in a computing SSD system supporting semantic search according to an embodiment of the present disclosure. Process 1400 may begin by storing original file data in one or more memory structures (box 1410). Process 1400 may store feature data corresponding to the original file data in the corresponding one or more memory structures (box 1415). Process 1400 may load feature data from at least one of the one or more memory structures, the feature data comprising at least one of the following: a dense feature vector or a hyperdimensional vector (box 1420). Process 1400 may generate one or more databases from the feature data (box 1425). Process 1400 may load original file data from at least one of the one or more memory structures (box 1430). Process 1400 may utilize an error correction algorithm to store and access the feature data (box 1435).

[0124] refer to Fig.15 , depicting a flow chart of a process 1500 for utilizing an exemplary error correction method in a computing SSD system supporting semantic search according to an embodiment of the present disclosure. Process 1500 may begin by processing a query using a machine learning model to retrieve raw file data stored on one or more memory structures (box 1510). Process 1500 may generate one or more databases from feature data stored in one or more memory structures, the feature data comprising at least one of the following: a dense feature vector or a hyperdimensional vector (box 1515). Process 1500 may load one or more databases and raw file data from one or more memory structures (box 1525). Process 1500 may process the raw file data and one or more databases to obtain a response to the query (box 1525).

[0125] The information shown and described in detail herein is fully capable of achieving the above-mentioned purpose of the present disclosure (the currently preferred embodiment of the present disclosure), and therefore represents the subject matter broadly contemplated by the present disclosure. The scope of the present disclosure fully encompasses other embodiments that may become apparent to those skilled in the art, and therefore will not be subject to any other restrictions except for the appended claims. Unless explicitly stated, any reference to an element in the singular form is not intended to mean "one and only one", but to mean "one or more". All structural and functional equivalents of the elements of the above-mentioned preferred embodiments and other embodiments considered by those of ordinary skill in the art are hereby expressly incorporated by reference, and are intended to be covered by the present claims.

[0126] Furthermore, it is not necessary for a system or method to solve every problem that the present disclosure seeks to solve, nor is it necessary for the present claims to cover solutions to such problems. In addition, no element, component, or method step of the present disclosure is intended to be dedicated to the public, regardless of whether the element, component, or method step is explicitly stated in the claims. It will be apparent to one of ordinary skill in the art that various changes and modifications in form, materials, workpieces, and manufacturing material details may be made and covered by the present disclosure without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A device, comprising: processor; a memory array comprising a plurality of memory devices; and a controller communicatively coupled to the memory array; one or more memory structures configured to store raw file data and feature data corresponding to the raw file data; wherein the feature data comprises at least one of the following: a dense feature vector or a hyperdimensional vector; wherein each of the one or more memory structures utilizes an error correction algorithm to store and access the characteristic data; and Each of the one or more memory structures includes one or more machine learning processing units configured to process the feature data.

2. The apparatus of claim 1, wherein the feature data comprises a dense feature vector based on error-free data.

3. The apparatus of claim 2, wherein the dense feature vector is stored in a block separate from the original file data. 4 . The apparatus of claim 1 , wherein the characteristic data is evenly distributed within the one or more memory structures.

5. The apparatus of claim 1, wherein the error correction algorithm is implemented as an on-die error correction code (ECC), wherein each of the one or more memory structures has an ECC.

6. The apparatus of claim 1 , wherein the feature data comprises a superdimensional vector, and at least two copies of the superdimensional vector are stored on each of the one or more memory structures, a first copy of the superdimensional vector being stored without using an error correction algorithm, and a second copy being stored using an error correction algorithm.

7. The apparatus of claim 6, wherein the first copy of the superdimensional vector is provided to the machine learning processing unit, and the second copy of the superdimensional vector is provided for correcting errors in the first copy.

8. A method comprising: storing raw file data in one or more memory structures; storing feature data corresponding to the original file data in the corresponding one or more memory structures; loading characteristic data from at least one memory structure of the one or more memory structures; wherein the feature data comprises at least one of the following: a dense feature vector or a hyperdimensional vector; generating one or more databases from the feature data; loading the original file data from at least one memory structure of the one or more memory structures; as well as The characteristic data is stored and accessed using an error correction algorithm.

9. The method of claim 8, wherein the feature data comprises a dense feature vector based on error-free data.

10. The method of claim 9, wherein storing feature data comprises storing the dense feature vector in a block separate from the original file data.

11. The method of claim 8, further comprising evenly distributing the characteristic data within the one or more memory structures.

12. The method of claim 8, wherein the error correction algorithm is implemented as an on-die error correction code (ECC), wherein each of the one or more memory structures has an ECC.

13. The method of claim 8, wherein the feature data comprises a hyperdimensional vector, and storing the feature data comprises: At least two copies of the superdimensional vector are stored on each of the one or more memory structures, a first copy of the superdimensional vector being stored without an error correction algorithm and a second copy being stored with an error correction algorithm.

14. A method according to claim 8, wherein each of the one or more memory structures includes a machine learning processing unit, and wherein the first copy of the superdimensional vector is provided to the machine learning processing unit, and the second copy of the superdimensional vector is provided for correcting errors in the first copy.

15. A method comprising: processing queries using a machine learning model to retrieve raw file data stored on one or more storage structures; generating one or more databases from the feature data stored in the one or more memory structures; wherein the feature data comprises at least one of the following: a dense feature vector or a hyperdimensional vector; loading the one or more databases and raw file data from the one or more memory structures; and The raw document data and one or more databases are processed to obtain a response to the query.

16. The method of claim 15, wherein a controller switches between a computation mode for processing the query to obtain the response and a storage mode for retrieving one or more files from the one or more memory structures.

17. The method of claim 16, wherein the controller utilizes a compute mapping table having a volatile memory configured for table X in the compute mode and a storage mapping table having a volatile memory configured for a logical-to-physical (L2P) table in the storage mode.

18. The method of claim 15, wherein an error correction algorithm is used to process the raw file data and the one or more databases to obtain the response to the query.

19. The method of claim 15, wherein the controller determines which blocks on the one or more memory structures contain the characteristic data and whether they should be processed to obtain a response to the query.

20. The method of claim 15, wherein each of the one or more memory structures comprises a machine learning processing unit for processing the raw file data and one or more databases to obtain a response to the query.

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